2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.35 2008/05/14 11:59:19 sephe Exp $
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/syslog.h>
50 #include <sys/module.h>
53 #include <sys/thread2.h>
55 #include <net/ethernet.h>
57 #include <net/ifq_var.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_mib.h>
61 #include <net/if_media.h>
64 #include <dev/netif/mii_layer/mii.h>
65 #include <dev/netif/mii_layer/miivar.h>
70 #include <machine/md_var.h>
75 devclass_t ed_devclass
;
77 static void ed_init (void *);
78 static int ed_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
79 static void ed_start (struct ifnet
*);
80 static void ed_reset (struct ifnet
*);
81 static void ed_watchdog (struct ifnet
*);
83 static void ed_tick (void *);
86 static void ds_getmcaf (struct ed_softc
*, u_int32_t
*);
88 static void ed_get_packet (struct ed_softc
*, char *, u_short
);
90 static __inline
void ed_rint (struct ed_softc
*);
91 static __inline
void ed_xmit (struct ed_softc
*);
92 static __inline
char * ed_ring_copy (struct ed_softc
*, char *, char *,
94 static void ed_hpp_set_physical_link (struct ed_softc
*);
95 static void ed_hpp_readmem (struct ed_softc
*, u_short
, u_char
*, u_short
);
96 static void ed_hpp_writemem (struct ed_softc
*, u_char
*, u_short
, u_short
);
97 static u_short
ed_hpp_write_mbufs (struct ed_softc
*, struct mbuf
*, int);
99 static u_short
ed_pio_write_mbufs (struct ed_softc
*, struct mbuf
*, int);
101 static void ed_setrcr (struct ed_softc
*);
103 static uint32_t ds_mchash (const uint8_t *);
105 DECLARE_DUMMY_MODULE(if_ed
);
108 * Interrupt conversion table for WD/SMC ASIC/83C584
110 static u_short ed_intr_val
[] = {
122 * Interrupt conversion table for 83C790
124 static u_short ed_790_intr_val
[] = {
136 * Interrupt conversion table for the HP PC LAN+
139 static u_short ed_hpp_intr_val
[] = {
159 * Generic probe routine for testing for the existance of a DS8390.
160 * Must be called after the NIC has just been reset. This routine
161 * works by looking at certain register values that are guaranteed
162 * to be initialized a certain way after power-up or reset. Seems
163 * not to currently work on the 83C690.
167 * Register reset bits set bits
168 * Command Register (CR) TXP, STA RD2, STP
169 * Interrupt Status (ISR) RST
170 * Interrupt Mask (IMR) All bits
171 * Data Control (DCR) LAS
172 * Transmit Config. (TCR) LB1, LB0
174 * We only look at the CR and ISR registers, however, because looking at
175 * the others would require changing register pages (which would be
176 * intrusive if this isn't an 8390).
178 * Return 1 if 8390 was found, 0 if not.
182 ed_probe_generic8390(struct ed_softc
*sc
)
184 if ((ed_nic_inb(sc
, ED_P0_CR
) &
185 (ED_CR_RD2
| ED_CR_TXP
| ED_CR_STA
| ED_CR_STP
)) !=
186 (ED_CR_RD2
| ED_CR_STP
))
188 if ((ed_nic_inb(sc
, ED_P0_ISR
) & ED_ISR_RST
) != ED_ISR_RST
)
195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
198 ed_probe_WD80x3_generic(device_t dev
, int flags
, u_short
*intr_vals
[])
200 struct ed_softc
*sc
= device_get_softc(dev
);
203 u_int memsize
, maddr
;
204 u_char iptr
, isa16bit
, sum
, totalsum
;
205 u_long conf_maddr
, conf_msize
, irq
, junk
;
207 sc
->chip_type
= ED_CHIP_TYPE_DP8390
;
209 if (ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_TOSH_ETHER
) {
210 totalsum
= ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER
;
211 ed_asic_outb(sc
, ED_WD_MSR
, ED_WD_MSR_POW
);
215 totalsum
= ED_WD_ROM_CHECKSUM_TOTAL
;
218 * Attempt to do a checksum over the station address PROM. If it
219 * fails, it's probably not a SMC/WD board. There is a problem with
220 * this, though: some clone WD boards don't pass the checksum test.
221 * Danpex boards for one.
223 for (sum
= 0, i
= 0; i
< 8; ++i
)
224 sum
+= ed_asic_inb(sc
, ED_WD_PROM
+ i
);
226 if (sum
!= totalsum
) {
229 * Checksum is invalid. This often happens with cheap WD8003E
230 * clones. In this case, the checksum byte (the eighth byte)
231 * seems to always be zero.
233 if (ed_asic_inb(sc
, ED_WD_CARD_ID
) != ED_TYPE_WD8003E
||
234 ed_asic_inb(sc
, ED_WD_PROM
+ 7) != 0)
237 /* reset card to force it into a known state. */
238 if (ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_TOSH_ETHER
)
239 ed_asic_outb(sc
, ED_WD_MSR
, ED_WD_MSR_RST
| ED_WD_MSR_POW
);
241 ed_asic_outb(sc
, ED_WD_MSR
, ED_WD_MSR_RST
);
244 ed_asic_outb(sc
, ED_WD_MSR
, ed_asic_inb(sc
, ED_WD_MSR
) & ~ED_WD_MSR_RST
);
245 /* wait in the case this card is reading its EEROM */
248 sc
->vendor
= ED_VENDOR_WD_SMC
;
249 sc
->type
= ed_asic_inb(sc
, ED_WD_CARD_ID
);
252 * Set initial values for width/size.
257 case ED_TYPE_WD8003S
:
258 sc
->type_str
= "WD8003S";
260 case ED_TYPE_WD8003E
:
261 sc
->type_str
= "WD8003E";
263 case ED_TYPE_WD8003EB
:
264 sc
->type_str
= "WD8003EB";
266 case ED_TYPE_WD8003W
:
267 sc
->type_str
= "WD8003W";
269 case ED_TYPE_WD8013EBT
:
270 sc
->type_str
= "WD8013EBT";
274 case ED_TYPE_WD8013W
:
275 sc
->type_str
= "WD8013W";
279 case ED_TYPE_WD8013EP
: /* also WD8003EP */
280 if (ed_asic_inb(sc
, ED_WD_ICR
) & ED_WD_ICR_16BIT
) {
283 sc
->type_str
= "WD8013EP";
285 sc
->type_str
= "WD8003EP";
288 case ED_TYPE_WD8013WC
:
289 sc
->type_str
= "WD8013WC";
293 case ED_TYPE_WD8013EBP
:
294 sc
->type_str
= "WD8013EBP";
298 case ED_TYPE_WD8013EPC
:
299 sc
->type_str
= "WD8013EPC";
303 case ED_TYPE_SMC8216C
: /* 8216 has 16K shared mem -- 8416 has 8K */
304 case ED_TYPE_SMC8216T
:
305 if (sc
->type
== ED_TYPE_SMC8216C
) {
306 sc
->type_str
= "SMC8216/SMC8216C";
308 sc
->type_str
= "SMC8216T";
311 ed_asic_outb(sc
, ED_WD790_HWR
,
312 ed_asic_inb(sc
, ED_WD790_HWR
) | ED_WD790_HWR_SWH
);
313 switch (ed_asic_inb(sc
, ED_WD790_RAR
) & ED_WD790_RAR_SZ64
) {
314 case ED_WD790_RAR_SZ64
:
317 case ED_WD790_RAR_SZ32
:
320 case ED_WD790_RAR_SZ16
:
323 case ED_WD790_RAR_SZ8
:
324 /* 8216 has 16K shared mem -- 8416 has 8K */
325 if (sc
->type
== ED_TYPE_SMC8216C
) {
326 sc
->type_str
= "SMC8416C/SMC8416BT";
328 sc
->type_str
= "SMC8416T";
333 ed_asic_outb(sc
, ED_WD790_HWR
,
334 ed_asic_inb(sc
, ED_WD790_HWR
) & ~ED_WD790_HWR_SWH
);
337 sc
->chip_type
= ED_CHIP_TYPE_WD790
;
339 case ED_TYPE_TOSHIBA1
:
340 sc
->type_str
= "Toshiba1";
344 case ED_TYPE_TOSHIBA4
:
345 sc
->type_str
= "Toshiba4";
355 * Make some adjustments to initial values depending on what is found
358 if (isa16bit
&& (sc
->type
!= ED_TYPE_WD8013EBT
)
359 && (sc
->type
!= ED_TYPE_TOSHIBA1
) && (sc
->type
!= ED_TYPE_TOSHIBA4
)
360 && ((ed_asic_inb(sc
, ED_WD_ICR
) & ED_WD_ICR_16BIT
) == 0)) {
365 error
= bus_get_resource(dev
, SYS_RES_MEMORY
, 0,
366 &conf_maddr
, &conf_msize
);
371 kprintf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
372 sc
->type
, sc
->type_str
, isa16bit
, memsize
, conf_msize
);
373 for (i
= 0; i
< 8; i
++)
374 kprintf("%x -> %x\n", i
, ed_asic_inb(sc
, i
));
378 * Allow the user to override the autoconfiguration
381 memsize
= conf_msize
;
384 if (maddr
< 0xa0000 || maddr
+ memsize
> 0x1000000) {
385 device_printf(dev
, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
386 maddr
, maddr
+ memsize
);
391 * (note that if the user specifies both of the following flags that
392 * '8bit' mode intentionally has precedence)
394 if (flags
& ED_FLAGS_FORCE_16BIT_MODE
)
396 if (flags
& ED_FLAGS_FORCE_8BIT_MODE
)
400 * If possible, get the assigned interrupt number from the card and
403 if ((sc
->type
& ED_WD_SOFTCONFIG
) &&
404 (sc
->chip_type
!= ED_CHIP_TYPE_WD790
)) {
407 * Assemble together the encoded interrupt number.
409 iptr
= (ed_asic_inb(sc
, ED_WD_ICR
) & ED_WD_ICR_IR2
) |
410 ((ed_asic_inb(sc
, ED_WD_IRR
) &
411 (ED_WD_IRR_IR0
| ED_WD_IRR_IR1
)) >> 5);
414 * If no interrupt specified (or "?"), use what the board tells us.
416 error
= bus_get_resource(dev
, SYS_RES_IRQ
, 0,
418 if (error
&& intr_vals
[0] != NULL
) {
419 error
= bus_set_resource(dev
, SYS_RES_IRQ
, 0,
420 intr_vals
[0][iptr
], 1);
426 * Enable the interrupt.
428 ed_asic_outb(sc
, ED_WD_IRR
,
429 ed_asic_inb(sc
, ED_WD_IRR
) | ED_WD_IRR_IEN
);
431 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
432 ed_asic_outb(sc
, ED_WD790_HWR
,
433 ed_asic_inb(sc
, ED_WD790_HWR
) | ED_WD790_HWR_SWH
);
434 iptr
= (((ed_asic_inb(sc
, ED_WD790_GCR
) & ED_WD790_GCR_IR2
) >> 4) |
435 (ed_asic_inb(sc
, ED_WD790_GCR
) &
436 (ED_WD790_GCR_IR1
| ED_WD790_GCR_IR0
)) >> 2);
437 ed_asic_outb(sc
, ED_WD790_HWR
,
438 ed_asic_inb(sc
, ED_WD790_HWR
) & ~ED_WD790_HWR_SWH
);
441 * If no interrupt specified (or "?"), use what the board tells us.
443 error
= bus_get_resource(dev
, SYS_RES_IRQ
, 0,
445 if (error
&& intr_vals
[1] != NULL
) {
446 error
= bus_set_resource(dev
, SYS_RES_IRQ
, 0,
447 intr_vals
[1][iptr
], 1);
455 ed_asic_outb(sc
, ED_WD790_ICR
,
456 ed_asic_inb(sc
, ED_WD790_ICR
) | ED_WD790_ICR_EIL
);
458 error
= bus_get_resource(dev
, SYS_RES_IRQ
, 0,
461 device_printf(dev
, "%s cards don't support auto-detected/assigned interrupts.\n",
465 sc
->isa16bit
= isa16bit
;
468 error
= ed_alloc_memory(dev
, 0, memsize
);
470 kprintf("*** ed_alloc_memory() failed! (%d)\n", error
);
473 sc
->mem_start
= (caddr_t
) rman_get_virtual(sc
->mem_res
);
476 * allocate one xmit buffer if < 16k, two buffers otherwise
478 if ((memsize
< 16384) ||
479 (flags
& ED_FLAGS_NO_MULTI_BUFFERING
)) {
484 sc
->tx_page_start
= ED_WD_PAGE_OFFSET
;
485 sc
->rec_page_start
= ED_WD_PAGE_OFFSET
+ ED_TXBUF_SIZE
* sc
->txb_cnt
;
486 sc
->rec_page_stop
= ED_WD_PAGE_OFFSET
+ memsize
/ ED_PAGE_SIZE
;
487 sc
->mem_ring
= sc
->mem_start
+ (ED_PAGE_SIZE
* sc
->rec_page_start
);
488 sc
->mem_size
= memsize
;
489 sc
->mem_end
= sc
->mem_start
+ memsize
;
492 * Get station address from on-board ROM
494 for (i
= 0; i
< ETHER_ADDR_LEN
; ++i
)
495 sc
->arpcom
.ac_enaddr
[i
] = ed_asic_inb(sc
, ED_WD_PROM
+ i
);
498 * Set upper address bits and 8/16 bit access to shared memory.
501 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
502 sc
->wd_laar_proto
= ed_asic_inb(sc
, ED_WD_LAAR
);
504 sc
->wd_laar_proto
= ED_WD_LAAR_L16EN
|
505 ((kvtop(sc
->mem_start
) >> 19) & ED_WD_LAAR_ADDRHI
);
508 * Enable 16bit access
510 ed_asic_outb(sc
, ED_WD_LAAR
, sc
->wd_laar_proto
|
513 if (((sc
->type
& ED_WD_SOFTCONFIG
) ||
514 (sc
->type
== ED_TYPE_TOSHIBA1
) ||
515 (sc
->type
== ED_TYPE_TOSHIBA4
) ||
516 (sc
->type
== ED_TYPE_WD8013EBT
)) &&
517 (sc
->chip_type
!= ED_CHIP_TYPE_WD790
)) {
518 sc
->wd_laar_proto
= (kvtop(sc
->mem_start
) >> 19) &
520 ed_asic_outb(sc
, ED_WD_LAAR
, sc
->wd_laar_proto
);
525 * Set address and enable interface shared memory.
527 if (sc
->chip_type
!= ED_CHIP_TYPE_WD790
) {
528 if (ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_TOSH_ETHER
) {
529 ed_asic_outb(sc
, ED_WD_MSR
+ 1,
530 ((kvtop(sc
->mem_start
) >> 8) & 0xe0) | 4);
531 ed_asic_outb(sc
, ED_WD_MSR
+ 2,
532 ((kvtop(sc
->mem_start
) >> 16) & 0x0f));
533 ed_asic_outb(sc
, ED_WD_MSR
,
534 ED_WD_MSR_MENB
| ED_WD_MSR_POW
);
536 ed_asic_outb(sc
, ED_WD_MSR
,
537 ((kvtop(sc
->mem_start
) >> 13) &
538 ED_WD_MSR_ADDR
) | ED_WD_MSR_MENB
);
540 sc
->cr_proto
= ED_CR_RD2
;
542 ed_asic_outb(sc
, ED_WD_MSR
, ED_WD_MSR_MENB
);
543 ed_asic_outb(sc
, ED_WD790_HWR
, (ed_asic_inb(sc
, ED_WD790_HWR
) | ED_WD790_HWR_SWH
));
544 ed_asic_outb(sc
, ED_WD790_RAR
, ((kvtop(sc
->mem_start
) >> 13) & 0x0f) |
545 ((kvtop(sc
->mem_start
) >> 11) & 0x40) |
546 (ed_asic_inb(sc
, ED_WD790_RAR
) & 0xb0));
547 ed_asic_outb(sc
, ED_WD790_HWR
, (ed_asic_inb(sc
, ED_WD790_HWR
) & ~ED_WD790_HWR_SWH
));
552 kprintf("starting memory performance test at 0x%x, size %d...\n",
553 sc
->mem_start
, memsize
*16384);
554 for (i
= 0; i
< 16384; i
++)
555 bzero(sc
->mem_start
, memsize
);
556 kprintf("***DONE***\n");
560 * Now zero memory and verify that it is clear
562 bzero(sc
->mem_start
, memsize
);
564 for (i
= 0; i
< memsize
; ++i
) {
565 if (sc
->mem_start
[i
]) {
566 device_printf(dev
, "failed to clear shared memory at %llx - check configuration\n",
567 (long long)kvtop(sc
->mem_start
+ i
));
570 * Disable 16 bit access to shared memory
573 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
574 ed_asic_outb(sc
, ED_WD_MSR
, 0x00);
576 ed_asic_outb(sc
, ED_WD_LAAR
, sc
->wd_laar_proto
&
584 * Disable 16bit access to shared memory - we leave it
585 * disabled so that 1) machines reboot properly when the board
586 * is set 16 bit mode and there are conflicting 8bit
587 * devices/ROMS in the same 128k address space as this boards
588 * shared memory. and 2) so that other 8 bit devices with
589 * shared memory can be used in this 128k region, too.
592 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
593 ed_asic_outb(sc
, ED_WD_MSR
, 0x00);
595 ed_asic_outb(sc
, ED_WD_LAAR
, sc
->wd_laar_proto
&
602 ed_probe_WD80x3(device_t dev
, int port_rid
, int flags
)
604 struct ed_softc
*sc
= device_get_softc(dev
);
606 static u_short
*intr_vals
[] = {ed_intr_val
, ed_790_intr_val
};
608 error
= ed_alloc_port(dev
, port_rid
, ED_WD_IO_PORTS
);
612 sc
->asic_offset
= ED_WD_ASIC_OFFSET
;
613 sc
->nic_offset
= ED_WD_NIC_OFFSET
;
615 return ed_probe_WD80x3_generic(dev
, flags
, intr_vals
);
619 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
622 ed_probe_3Com(device_t dev
, int port_rid
, int flags
)
624 struct ed_softc
*sc
= device_get_softc(dev
);
629 u_long conf_maddr
, conf_msize
, irq
, junk
;
631 error
= ed_alloc_port(dev
, 0, ED_3COM_IO_PORTS
);
635 sc
->asic_offset
= ED_3COM_ASIC_OFFSET
;
636 sc
->nic_offset
= ED_3COM_NIC_OFFSET
;
639 * Verify that the kernel configured I/O address matches the board
642 switch (ed_asic_inb(sc
, ED_3COM_BCFR
)) {
643 case ED_3COM_BCFR_300
:
644 if (rman_get_start(sc
->port_res
) != 0x300)
647 case ED_3COM_BCFR_310
:
648 if (rman_get_start(sc
->port_res
) != 0x310)
651 case ED_3COM_BCFR_330
:
652 if (rman_get_start(sc
->port_res
) != 0x330)
655 case ED_3COM_BCFR_350
:
656 if (rman_get_start(sc
->port_res
) != 0x350)
659 case ED_3COM_BCFR_250
:
660 if (rman_get_start(sc
->port_res
) != 0x250)
663 case ED_3COM_BCFR_280
:
664 if (rman_get_start(sc
->port_res
) != 0x280)
667 case ED_3COM_BCFR_2A0
:
668 if (rman_get_start(sc
->port_res
) != 0x2a0)
671 case ED_3COM_BCFR_2E0
:
672 if (rman_get_start(sc
->port_res
) != 0x2e0)
679 error
= bus_get_resource(dev
, SYS_RES_MEMORY
, 0,
680 &conf_maddr
, &conf_msize
);
685 * Verify that the kernel shared memory address matches the board
686 * configured address.
688 switch (ed_asic_inb(sc
, ED_3COM_PCFR
)) {
689 case ED_3COM_PCFR_DC000
:
690 if (conf_maddr
!= 0xdc000)
693 case ED_3COM_PCFR_D8000
:
694 if (conf_maddr
!= 0xd8000)
697 case ED_3COM_PCFR_CC000
:
698 if (conf_maddr
!= 0xcc000)
701 case ED_3COM_PCFR_C8000
:
702 if (conf_maddr
!= 0xc8000)
711 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
712 * sequence because it'll lock up if the cable isn't connected if we
715 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_RST
| ED_3COM_CR_XSEL
);
718 * Wait for a while, then un-reset it
723 * The 3Com ASIC defaults to rather strange settings for the CR after
724 * a reset - it's important to set it again after the following outb
725 * (this is done when we map the PROM below).
727 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_XSEL
);
730 * Wait a bit for the NIC to recover from the reset
734 sc
->vendor
= ED_VENDOR_3COM
;
735 sc
->type_str
= "3c503";
737 sc
->cr_proto
= ED_CR_RD2
;
740 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
746 * Get station address from on-board ROM
750 * First, map ethernet address PROM over the top of where the NIC
751 * registers normally appear.
753 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_EALO
| ED_3COM_CR_XSEL
);
755 for (i
= 0; i
< ETHER_ADDR_LEN
; ++i
)
756 sc
->arpcom
.ac_enaddr
[i
] = ed_nic_inb(sc
, i
);
759 * Unmap PROM - select NIC registers. The proper setting of the
760 * tranceiver is set in ed_init so that the attach code is given a
761 * chance to set the default based on a compile-time config option
763 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_XSEL
);
766 * Determine if this is an 8bit or 16bit board
770 * select page 0 registers
772 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD2
| ED_CR_STP
);
775 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
778 ed_nic_outb(sc
, ED_P0_DCR
, 0);
781 * select page 2 registers
783 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_PAGE_2
| ED_CR_RD2
| ED_CR_STP
);
786 * The 3c503 forces the WTS bit to a one if this is a 16bit board
788 if (ed_nic_inb(sc
, ED_P2_DCR
) & ED_DCR_WTS
)
794 * select page 0 registers
796 ed_nic_outb(sc
, ED_P2_CR
, ED_CR_RD2
| ED_CR_STP
);
798 error
= ed_alloc_memory(dev
, 0, memsize
);
802 sc
->mem_start
= (caddr_t
) rman_get_virtual(sc
->mem_res
);
803 sc
->mem_size
= memsize
;
804 sc
->mem_end
= sc
->mem_start
+ memsize
;
807 * We have an entire 8k window to put the transmit buffers on the
808 * 16bit boards. But since the 16bit 3c503's shared memory is only
809 * fast enough to overlap the loading of one full-size packet, trying
810 * to load more than 2 buffers can actually leave the transmitter idle
811 * during the load. So 2 seems the best value. (Although a mix of
812 * variable-sized packets might change this assumption. Nonetheless,
813 * we optimize for linear transfers of same-size packets.)
816 if (flags
& ED_FLAGS_NO_MULTI_BUFFERING
)
821 sc
->tx_page_start
= ED_3COM_TX_PAGE_OFFSET_16BIT
;
822 sc
->rec_page_start
= ED_3COM_RX_PAGE_OFFSET_16BIT
;
823 sc
->rec_page_stop
= memsize
/ ED_PAGE_SIZE
+
824 ED_3COM_RX_PAGE_OFFSET_16BIT
;
825 sc
->mem_ring
= sc
->mem_start
;
828 sc
->tx_page_start
= ED_3COM_TX_PAGE_OFFSET_8BIT
;
829 sc
->rec_page_start
= ED_TXBUF_SIZE
+ ED_3COM_TX_PAGE_OFFSET_8BIT
;
830 sc
->rec_page_stop
= memsize
/ ED_PAGE_SIZE
+
831 ED_3COM_TX_PAGE_OFFSET_8BIT
;
832 sc
->mem_ring
= sc
->mem_start
+ (ED_PAGE_SIZE
* ED_TXBUF_SIZE
);
835 sc
->isa16bit
= isa16bit
;
838 * Initialize GA page start/stop registers. Probably only needed if
839 * doing DMA, but what the hell.
841 ed_asic_outb(sc
, ED_3COM_PSTR
, sc
->rec_page_start
);
842 ed_asic_outb(sc
, ED_3COM_PSPR
, sc
->rec_page_stop
);
845 * Set IRQ. 3c503 only allows a choice of irq 2-5.
847 error
= bus_get_resource(dev
, SYS_RES_IRQ
, 0, &irq
, &junk
);
854 ed_asic_outb(sc
, ED_3COM_IDCFR
, ED_3COM_IDCFR_IRQ2
);
857 ed_asic_outb(sc
, ED_3COM_IDCFR
, ED_3COM_IDCFR_IRQ3
);
860 ed_asic_outb(sc
, ED_3COM_IDCFR
, ED_3COM_IDCFR_IRQ4
);
863 ed_asic_outb(sc
, ED_3COM_IDCFR
, ED_3COM_IDCFR_IRQ5
);
866 device_printf(dev
, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
872 * Initialize GA configuration register. Set bank and enable shared
875 ed_asic_outb(sc
, ED_3COM_GACFR
, ED_3COM_GACFR_RSEL
|
879 * Initialize "Vector Pointer" registers. These gawd-awful things are
880 * compared to 20 bits of the address on ISA, and if they match, the
881 * shared memory is disabled. We set them to 0xffff0...allegedly the
884 ed_asic_outb(sc
, ED_3COM_VPTR2
, 0xff);
885 ed_asic_outb(sc
, ED_3COM_VPTR1
, 0xff);
886 ed_asic_outb(sc
, ED_3COM_VPTR0
, 0x00);
889 * Zero memory and verify that it is clear
891 bzero(sc
->mem_start
, memsize
);
893 for (i
= 0; i
< memsize
; ++i
)
894 if (sc
->mem_start
[i
]) {
895 device_printf(dev
, "failed to clear shared memory "
896 "at %llx - check configuration\n",
897 (unsigned long long)kvtop(sc
->mem_start
+ i
));
904 * Probe and vendor-specific initialization routine for SIC boards
907 ed_probe_SIC(device_t dev
, int port_rid
, int flags
)
909 struct ed_softc
*sc
= device_get_softc(dev
);
913 u_long conf_maddr
, conf_msize
;
916 error
= ed_alloc_port(dev
, 0, ED_SIC_IO_PORTS
);
920 sc
->asic_offset
= ED_SIC_ASIC_OFFSET
;
921 sc
->nic_offset
= ED_SIC_NIC_OFFSET
;
923 error
= bus_get_resource(dev
, SYS_RES_MEMORY
, 0,
924 &conf_maddr
, &conf_msize
);
930 memsize
= conf_msize
;
932 error
= ed_alloc_memory(dev
, 0, memsize
);
936 sc
->mem_start
= (caddr_t
) rman_get_virtual(sc
->mem_res
);
937 sc
->mem_size
= memsize
;
939 /* Reset card to force it into a known state. */
940 ed_asic_outb(sc
, 0, 0x00);
944 * Here we check the card ROM, if the checksum passes, and the
945 * type code and ethernet address check out, then we know we have
948 ed_asic_outb(sc
, 0, 0x81);
951 sum
= sc
->mem_start
[6];
952 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++) {
953 sum
^= (sc
->arpcom
.ac_enaddr
[i
] = sc
->mem_start
[i
]);
956 device_printf(dev
, "ed_probe_sic: got address %6D\n",
957 sc
->arpcom
.ac_enaddr
, ":");
962 if ((sc
->arpcom
.ac_enaddr
[0] | sc
->arpcom
.ac_enaddr
[1] |
963 sc
->arpcom
.ac_enaddr
[2]) == 0) {
967 sc
->vendor
= ED_VENDOR_SIC
;
968 sc
->type_str
= "SIC";
973 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
975 ed_asic_outb(sc
, 0, 0x80);
979 * Now zero memory and verify that it is clear
981 bzero(sc
->mem_start
, sc
->mem_size
);
983 for (i
= 0; i
< sc
->mem_size
; i
++) {
984 if (sc
->mem_start
[i
]) {
985 device_printf(dev
, "failed to clear shared memory "
986 "at %llx - check configuration\n",
987 (long long)kvtop(sc
->mem_start
+ i
));
994 sc
->mem_end
= sc
->mem_start
+ sc
->mem_size
;
997 * allocate one xmit buffer if < 16k, two buffers otherwise
999 if ((sc
->mem_size
< 16384) || (flags
& ED_FLAGS_NO_MULTI_BUFFERING
)) {
1004 sc
->tx_page_start
= 0;
1006 sc
->rec_page_start
= sc
->tx_page_start
+ ED_TXBUF_SIZE
* sc
->txb_cnt
;
1007 sc
->rec_page_stop
= sc
->tx_page_start
+ sc
->mem_size
/ ED_PAGE_SIZE
;
1009 sc
->mem_ring
= sc
->mem_start
+ sc
->txb_cnt
* ED_PAGE_SIZE
* ED_TXBUF_SIZE
;
1015 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1018 ed_probe_Novell_generic(device_t dev
, int flags
)
1020 struct ed_softc
*sc
= device_get_softc(dev
);
1022 u_char romdata
[16], tmp
;
1023 static char test_pattern
[32] = "THIS is A memory TEST pattern";
1024 char test_buffer
[32];
1026 /* XXX - do Novell-specific probe here */
1028 /* Reset the board */
1029 if (ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_GWETHER
) {
1030 ed_asic_outb(sc
, ED_NOVELL_RESET
, 0);
1033 tmp
= ed_asic_inb(sc
, ED_NOVELL_RESET
);
1036 * I don't know if this is necessary; probably cruft leftover from
1037 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1038 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1039 * non-invasive...but some boards don't seem to reset and I don't have
1040 * complete documentation on what the 'right' thing to do is...so we
1041 * do the invasive thing for now. Yuck.]
1043 ed_asic_outb(sc
, ED_NOVELL_RESET
, tmp
);
1047 * This is needed because some NE clones apparently don't reset the
1048 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1049 * - this makes the probe invasive! ...Done against my better
1052 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD2
| ED_CR_STP
);
1056 /* Make sure that we really have an 8390 based board */
1057 if (!ed_probe_generic8390(sc
))
1060 sc
->vendor
= ED_VENDOR_NOVELL
;
1062 sc
->cr_proto
= ED_CR_RD2
;
1065 * Test the ability to read and write to the NIC memory. This has the
1066 * side affect of determining if this is an NE1000 or an NE2000.
1070 * This prevents packets from being stored in the NIC memory when the
1071 * readmem routine turns on the start bit in the CR.
1073 ed_nic_outb(sc
, ED_P0_RCR
, ED_RCR_MON
);
1075 /* Temporarily initialize DCR for byte operations */
1076 ed_nic_outb(sc
, ED_P0_DCR
, ED_DCR_FT1
| ED_DCR_LS
);
1078 ed_nic_outb(sc
, ED_P0_PSTART
, 8192 / ED_PAGE_SIZE
);
1079 ed_nic_outb(sc
, ED_P0_PSTOP
, 16384 / ED_PAGE_SIZE
);
1084 * Write a test pattern in byte mode. If this fails, then there
1085 * probably isn't any memory at 8k - which likely means that the board
1088 ed_pio_writemem(sc
, test_pattern
, 8192, sizeof(test_pattern
));
1089 ed_pio_readmem(sc
, 8192, test_buffer
, sizeof(test_pattern
));
1091 if (bcmp(test_pattern
, test_buffer
, sizeof(test_pattern
)) == 0) {
1092 sc
->type
= ED_TYPE_NE1000
;
1093 sc
->type_str
= "NE1000";
1096 /* neither an NE1000 nor a Linksys - try NE2000 */
1097 ed_nic_outb(sc
, ED_P0_DCR
, ED_DCR_WTS
| ED_DCR_FT1
| ED_DCR_LS
);
1098 ed_nic_outb(sc
, ED_P0_PSTART
, 16384 / ED_PAGE_SIZE
);
1099 ed_nic_outb(sc
, ED_P0_PSTOP
, 32768 / ED_PAGE_SIZE
);
1104 * Write a test pattern in word mode. If this also fails, then
1105 * we don't know what this board is.
1107 ed_pio_writemem(sc
, test_pattern
, 16384, sizeof(test_pattern
));
1108 ed_pio_readmem(sc
, 16384, test_buffer
, sizeof(test_pattern
));
1109 if (bcmp(test_pattern
, test_buffer
, sizeof(test_pattern
)) == 0) {
1110 sc
->type
= ED_TYPE_NE2000
;
1111 sc
->type_str
= "NE2000";
1118 /* 8k of memory plus an additional 8k if 16bit */
1119 memsize
= 8192 + sc
->isa16bit
* 8192;
1121 #if 0 /* probably not useful - NE boards only come two ways */
1122 /* allow kernel config file overrides */
1123 if (isa_dev
->id_msize
)
1124 memsize
= isa_dev
->id_msize
;
1127 sc
->mem_size
= memsize
;
1129 /* NIC memory doesn't start at zero on an NE board */
1130 /* The start address is tied to the bus width */
1131 sc
->mem_start
= (char *) 8192 + sc
->isa16bit
* 8192;
1132 sc
->mem_end
= sc
->mem_start
+ memsize
;
1133 sc
->tx_page_start
= memsize
/ ED_PAGE_SIZE
;
1135 if (ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_GWETHER
) {
1136 int x
, i
, mstart
= 0, msize
= 0;
1137 char pbuf0
[ED_PAGE_SIZE
], pbuf
[ED_PAGE_SIZE
], tbuf
[ED_PAGE_SIZE
];
1139 for (i
= 0; i
< ED_PAGE_SIZE
; i
++)
1142 /* Clear all the memory. */
1143 for (x
= 1; x
< 256; x
++)
1144 ed_pio_writemem(sc
, pbuf0
, x
* 256, ED_PAGE_SIZE
);
1146 /* Search for the start of RAM. */
1147 for (x
= 1; x
< 256; x
++) {
1148 ed_pio_readmem(sc
, x
* 256, tbuf
, ED_PAGE_SIZE
);
1149 if (bcmp(pbuf0
, tbuf
, ED_PAGE_SIZE
) == 0) {
1150 for (i
= 0; i
< ED_PAGE_SIZE
; i
++)
1152 ed_pio_writemem(sc
, pbuf
, x
* 256, ED_PAGE_SIZE
);
1153 ed_pio_readmem(sc
, x
* 256, tbuf
, ED_PAGE_SIZE
);
1154 if (bcmp(pbuf
, tbuf
, ED_PAGE_SIZE
) == 0) {
1155 mstart
= x
* ED_PAGE_SIZE
;
1156 msize
= ED_PAGE_SIZE
;
1163 device_printf(dev
, "Cannot find start of RAM.\n");
1166 /* Search for the start of RAM. */
1167 for (x
= (mstart
/ ED_PAGE_SIZE
) + 1; x
< 256; x
++) {
1168 ed_pio_readmem(sc
, x
* 256, tbuf
, ED_PAGE_SIZE
);
1169 if (bcmp(pbuf0
, tbuf
, ED_PAGE_SIZE
) == 0) {
1170 for (i
= 0; i
< ED_PAGE_SIZE
; i
++)
1172 ed_pio_writemem(sc
, pbuf
, x
* 256, ED_PAGE_SIZE
);
1173 ed_pio_readmem(sc
, x
* 256, tbuf
, ED_PAGE_SIZE
);
1174 if (bcmp(pbuf
, tbuf
, ED_PAGE_SIZE
) == 0)
1175 msize
+= ED_PAGE_SIZE
;
1185 device_printf(dev
, "Cannot find any RAM, start : %d, x = %d.\n", mstart
, x
);
1188 device_printf(dev
, "RAM start at %d, size : %d.\n", mstart
, msize
);
1190 sc
->mem_size
= msize
;
1191 sc
->mem_start
= (caddr_t
) mstart
;
1192 sc
->mem_end
= (caddr_t
) (msize
+ mstart
);
1193 sc
->tx_page_start
= mstart
/ ED_PAGE_SIZE
;
1197 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1200 if ((memsize
< 16384) || (flags
& ED_FLAGS_NO_MULTI_BUFFERING
))
1205 sc
->rec_page_start
= sc
->tx_page_start
+ sc
->txb_cnt
* ED_TXBUF_SIZE
;
1206 sc
->rec_page_stop
= sc
->tx_page_start
+ memsize
/ ED_PAGE_SIZE
;
1208 sc
->mem_ring
= sc
->mem_start
+ sc
->txb_cnt
* ED_PAGE_SIZE
* ED_TXBUF_SIZE
;
1210 ed_pio_readmem(sc
, 0, romdata
, 16);
1211 for (n
= 0; n
< ETHER_ADDR_LEN
; n
++)
1212 sc
->arpcom
.ac_enaddr
[n
] = romdata
[n
* (sc
->isa16bit
+ 1)];
1214 if ((ED_FLAGS_GETTYPE(flags
) == ED_FLAGS_GWETHER
) &&
1215 (sc
->arpcom
.ac_enaddr
[2] == 0x86)) {
1216 sc
->type_str
= "Gateway AT";
1219 /* clear any pending interrupts that might have occurred above */
1220 ed_nic_outb(sc
, ED_P0_ISR
, 0xff);
1226 ed_probe_Novell(device_t dev
, int port_rid
, int flags
)
1228 struct ed_softc
*sc
= device_get_softc(dev
);
1231 error
= ed_alloc_port(dev
, port_rid
, ED_NOVELL_IO_PORTS
);
1235 sc
->asic_offset
= ED_NOVELL_ASIC_OFFSET
;
1236 sc
->nic_offset
= ED_NOVELL_NIC_OFFSET
;
1238 return ed_probe_Novell_generic(dev
, flags
);
1241 #define ED_HPP_TEST_SIZE 16
1244 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1245 * (HP Part nos: 27247B and 27252A).
1247 * The card has an asic wrapper around a DS8390 core. The asic handles
1248 * host accesses and offers both standard register IO and memory mapped
1249 * IO. Memory mapped I/O allows better performance at the expense of greater
1250 * chance of an incompatibility with existing ISA cards.
1252 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1253 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1254 * don't allow 32 bit accesses; these are indicated by a bit in the software
1255 * ID register (see if_edreg.h).
1257 * Other caveats are: we should read the MAC address only when the card
1260 * For more information; please consult the CRYNWR packet driver.
1262 * The AUI port is turned on using the "link2" option on the ifconfig
1266 ed_probe_HP_pclanp(device_t dev
, int port_rid
, int flags
)
1268 struct ed_softc
*sc
= device_get_softc(dev
);
1270 int n
; /* temp var */
1271 int memsize
; /* mem on board */
1272 u_char checksum
; /* checksum of board address */
1273 u_char irq
; /* board configured IRQ */
1274 char test_pattern
[ED_HPP_TEST_SIZE
]; /* read/write areas for */
1275 char test_buffer
[ED_HPP_TEST_SIZE
]; /* probing card */
1276 u_long conf_maddr
, conf_msize
, conf_irq
, junk
;
1278 error
= ed_alloc_port(dev
, 0, ED_HPP_IO_PORTS
);
1282 /* Fill in basic information */
1283 sc
->asic_offset
= ED_HPP_ASIC_OFFSET
;
1284 sc
->nic_offset
= ED_HPP_NIC_OFFSET
;
1286 sc
->chip_type
= ED_CHIP_TYPE_DP8390
;
1287 sc
->isa16bit
= 0; /* the 8390 core needs to be in byte mode */
1290 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1293 if ((ed_asic_inb(sc
, ED_HPP_ID
) != 0x50) ||
1294 (ed_asic_inb(sc
, ED_HPP_ID
+ 1) != 0x48) ||
1295 ((ed_asic_inb(sc
, ED_HPP_ID
+ 2) & 0xF0) != 0) ||
1296 (ed_asic_inb(sc
, ED_HPP_ID
+ 3) != 0x53))
1300 * Read the MAC address and verify checksum on the address.
1303 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_MAC
);
1304 for (n
= 0, checksum
= 0; n
< ETHER_ADDR_LEN
; n
++)
1305 checksum
+= (sc
->arpcom
.ac_enaddr
[n
] =
1306 ed_asic_inb(sc
, ED_HPP_MAC_ADDR
+ n
));
1308 checksum
+= ed_asic_inb(sc
, ED_HPP_MAC_ADDR
+ ETHER_ADDR_LEN
);
1310 if (checksum
!= 0xFF)
1314 * Verify that the software model number is 0.
1317 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_ID
);
1318 if (((sc
->hpp_id
= ed_asic_inw(sc
, ED_HPP_PAGE_4
)) &
1319 ED_HPP_ID_SOFT_MODEL_MASK
) != 0x0000)
1323 * Read in and save the current options configured on card.
1326 sc
->hpp_options
= ed_asic_inw(sc
, ED_HPP_OPTION
);
1328 sc
->hpp_options
|= (ED_HPP_OPTION_NIC_RESET
|
1329 ED_HPP_OPTION_CHIP_RESET
|
1330 ED_HPP_OPTION_ENABLE_IRQ
);
1333 * Reset the chip. This requires writing to the option register
1334 * so take care to preserve the other bits.
1337 ed_asic_outw(sc
, ED_HPP_OPTION
,
1338 (sc
->hpp_options
& ~(ED_HPP_OPTION_NIC_RESET
|
1339 ED_HPP_OPTION_CHIP_RESET
)));
1341 DELAY(5000); /* wait for chip reset to complete */
1343 ed_asic_outw(sc
, ED_HPP_OPTION
,
1344 (sc
->hpp_options
| (ED_HPP_OPTION_NIC_RESET
|
1345 ED_HPP_OPTION_CHIP_RESET
|
1346 ED_HPP_OPTION_ENABLE_IRQ
)));
1350 if (!(ed_nic_inb(sc
, ED_P0_ISR
) & ED_ISR_RST
))
1351 return ENXIO
; /* reset did not complete */
1354 * Read out configuration information.
1357 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_HW
);
1359 irq
= ed_asic_inb(sc
, ED_HPP_HW_IRQ
);
1362 * Check for impossible IRQ.
1365 if (irq
>= (sizeof(ed_hpp_intr_val
) / sizeof(ed_hpp_intr_val
[0])))
1369 * If the kernel IRQ was specified with a '?' use the cards idea
1370 * of the IRQ. If the kernel IRQ was explicitly specified, it
1371 * should match that of the hardware.
1373 error
= bus_get_resource(dev
, SYS_RES_IRQ
, 0,
1376 bus_set_resource(dev
, SYS_RES_IRQ
, 0,
1377 ed_hpp_intr_val
[irq
], 1);
1379 if (conf_irq
!= ed_hpp_intr_val
[irq
])
1384 * Fill in softconfig info.
1387 sc
->vendor
= ED_VENDOR_HP
;
1388 sc
->type
= ED_TYPE_HP_PCLANPLUS
;
1389 sc
->type_str
= "HP-PCLAN+";
1391 sc
->mem_shared
= 0; /* we DON'T have dual ported RAM */
1392 sc
->mem_start
= 0; /* we use offsets inside the card RAM */
1394 sc
->hpp_mem_start
= NULL
;/* no memory mapped I/O by default */
1397 * The board has 32KB of memory. Is there a way to determine
1398 * this programmatically?
1404 * Check if memory mapping of the I/O registers possible.
1407 if (sc
->hpp_options
& ED_HPP_OPTION_MEM_ENABLE
)
1412 * determine the memory address from the board.
1415 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_HW
);
1416 mem_addr
= (ed_asic_inw(sc
, ED_HPP_HW_MEM_MAP
) << 8);
1419 * Check that the kernel specified start of memory and
1420 * hardware's idea of it match.
1422 error
= bus_get_resource(dev
, SYS_RES_MEMORY
, 0,
1423 &conf_maddr
, &conf_msize
);
1427 if (mem_addr
!= conf_maddr
)
1430 error
= ed_alloc_memory(dev
, 0, memsize
);
1434 sc
->hpp_mem_start
= rman_get_virtual(sc
->mem_res
);
1438 * Fill in the rest of the soft config structure.
1442 * The transmit page index.
1445 sc
->tx_page_start
= ED_HPP_TX_PAGE_OFFSET
;
1447 if (device_get_flags(dev
) & ED_FLAGS_NO_MULTI_BUFFERING
)
1453 * Memory description
1456 sc
->mem_size
= memsize
;
1457 sc
->mem_ring
= sc
->mem_start
+
1458 (sc
->txb_cnt
* ED_PAGE_SIZE
* ED_TXBUF_SIZE
);
1459 sc
->mem_end
= sc
->mem_start
+ sc
->mem_size
;
1462 * Receive area starts after the transmit area and
1463 * continues till the end of memory.
1466 sc
->rec_page_start
= sc
->tx_page_start
+
1467 (sc
->txb_cnt
* ED_TXBUF_SIZE
);
1468 sc
->rec_page_stop
= (sc
->mem_size
/ ED_PAGE_SIZE
);
1471 sc
->cr_proto
= 0; /* value works */
1474 * Set the wrap registers for string I/O reads.
1477 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_HW
);
1478 ed_asic_outw(sc
, ED_HPP_HW_WRAP
,
1479 ((sc
->rec_page_start
/ ED_PAGE_SIZE
) |
1480 (((sc
->rec_page_stop
/ ED_PAGE_SIZE
) - 1) << 8)));
1483 * Reset the register page to normal operation.
1486 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_PERF
);
1489 * Verify that we can read/write from adapter memory.
1490 * Create test pattern.
1493 for (n
= 0; n
< ED_HPP_TEST_SIZE
; n
++)
1495 test_pattern
[n
] = (n
*n
) ^ ~n
;
1498 #undef ED_HPP_TEST_SIZE
1501 * Check that the memory is accessible thru the I/O ports.
1502 * Write out the contents of "test_pattern", read back
1503 * into "test_buffer" and compare the two for any
1507 for (n
= 0; n
< (32768 / ED_PAGE_SIZE
); n
++) {
1509 ed_hpp_writemem(sc
, test_pattern
, (n
* ED_PAGE_SIZE
),
1510 sizeof(test_pattern
));
1511 ed_hpp_readmem(sc
, (n
* ED_PAGE_SIZE
),
1512 test_buffer
, sizeof(test_pattern
));
1514 if (bcmp(test_pattern
, test_buffer
,
1515 sizeof(test_pattern
)))
1524 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1528 ed_hpp_set_physical_link(struct ed_softc
*sc
)
1530 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1533 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_LAN
);
1534 lan_page
= ed_asic_inw(sc
, ED_HPP_PAGE_0
);
1536 if (ifp
->if_flags
& IFF_ALTPHYS
) {
1542 lan_page
|= ED_HPP_LAN_AUI
;
1544 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_LAN
);
1545 ed_asic_outw(sc
, ED_HPP_PAGE_0
, lan_page
);
1551 * Use the ThinLan interface
1554 lan_page
&= ~ED_HPP_LAN_AUI
;
1556 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_LAN
);
1557 ed_asic_outw(sc
, ED_HPP_PAGE_0
, lan_page
);
1562 * Wait for the lan card to re-initialize itself
1565 DELAY(150000); /* wait 150 ms */
1568 * Restore normal pages.
1571 ed_asic_outw(sc
, ED_HPP_PAGING
, ED_HPP_PAGE_PERF
);
1576 * Allocate a port resource with the given resource id.
1579 ed_alloc_port(device_t dev
, int rid
, int size
)
1581 struct ed_softc
*sc
= device_get_softc(dev
);
1582 struct resource
*res
;
1584 res
= bus_alloc_resource(dev
, SYS_RES_IOPORT
, &rid
,
1585 0ul, ~0ul, size
, RF_ACTIVE
);
1589 sc
->port_used
= size
;
1597 * Allocate a memory resource with the given resource id.
1600 ed_alloc_memory(device_t dev
, int rid
, int size
)
1602 struct ed_softc
*sc
= device_get_softc(dev
);
1603 struct resource
*res
;
1605 res
= bus_alloc_resource(dev
, SYS_RES_MEMORY
, &rid
,
1606 0ul, ~0ul, size
, RF_ACTIVE
);
1610 sc
->mem_used
= size
;
1618 * Allocate an irq resource with the given resource id.
1621 ed_alloc_irq(device_t dev
, int rid
, int flags
)
1623 struct ed_softc
*sc
= device_get_softc(dev
);
1624 struct resource
*res
;
1626 res
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
1627 (RF_ACTIVE
| flags
));
1638 * Release all resources
1641 ed_release_resources(device_t dev
)
1643 struct ed_softc
*sc
= device_get_softc(dev
);
1646 bus_deactivate_resource(dev
, SYS_RES_IOPORT
,
1647 sc
->port_rid
, sc
->port_res
);
1648 bus_release_resource(dev
, SYS_RES_IOPORT
,
1649 sc
->port_rid
, sc
->port_res
);
1653 bus_deactivate_resource(dev
, SYS_RES_MEMORY
,
1654 sc
->mem_rid
, sc
->mem_res
);
1655 bus_release_resource(dev
, SYS_RES_MEMORY
,
1656 sc
->mem_rid
, sc
->mem_res
);
1660 bus_deactivate_resource(dev
, SYS_RES_IRQ
,
1661 sc
->irq_rid
, sc
->irq_res
);
1662 bus_release_resource(dev
, SYS_RES_IRQ
,
1663 sc
->irq_rid
, sc
->irq_res
);
1669 * Install interface into kernel networking data structures
1672 ed_attach(device_t dev
)
1674 struct ed_softc
*sc
= device_get_softc(dev
);
1675 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1677 callout_init(&sc
->ed_timer
);
1679 * Set interface to stopped condition (reset)
1684 * Initialize ifnet structure
1687 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
1688 ifp
->if_mtu
= ETHERMTU
;
1689 ifp
->if_start
= ed_start
;
1690 ifp
->if_ioctl
= ed_ioctl
;
1691 ifp
->if_watchdog
= ed_watchdog
;
1692 ifp
->if_init
= ed_init
;
1693 ifq_set_maxlen(&ifp
->if_snd
, IFQ_MAXLEN
);
1694 ifq_set_ready(&ifp
->if_snd
);
1695 ifp
->if_linkmib
= &sc
->mibdata
;
1696 ifp
->if_linkmiblen
= sizeof sc
->mibdata
;
1697 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1699 * XXX - should do a better job.
1701 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
)
1702 sc
->mibdata
.dot3StatsEtherChipSet
=
1703 DOT3CHIPSET(dot3VendorWesternDigital
,
1704 dot3ChipSetWesternDigital83C790
);
1706 sc
->mibdata
.dot3StatsEtherChipSet
=
1707 DOT3CHIPSET(dot3VendorNational
,
1708 dot3ChipSetNational8390
);
1709 sc
->mibdata
.dot3Compliance
= DOT3COMPLIANCE_COLLS
;
1712 * Set default state for ALTPHYS flag (used to disable the
1713 * tranceiver for AUI operation), based on compile-time
1716 if (device_get_flags(dev
) & ED_FLAGS_DISABLE_TRANCEIVER
)
1717 ifp
->if_flags
|= IFF_ALTPHYS
;
1720 * Attach the interface
1722 ether_ifattach(ifp
, sc
->arpcom
.ac_enaddr
, NULL
);
1724 /* device attach does transition from UNCONFIGURED to IDLE state */
1726 if (sc
->type_str
&& (*sc
->type_str
!= 0))
1727 kprintf("type %s ", sc
->type_str
);
1729 kprintf("type unknown (0x%x) ", sc
->type
);
1731 if (sc
->vendor
== ED_VENDOR_HP
)
1732 kprintf("(%s %s IO)", (sc
->hpp_id
& ED_HPP_ID_16_BIT_ACCESS
) ?
1733 "16-bit" : "32-bit",
1734 sc
->hpp_mem_start
? "memory mapped" : "regular");
1736 kprintf("%s ", sc
->isa16bit
? "(16 bit)" : "(8 bit)");
1738 kprintf("%s\n", (((sc
->vendor
== ED_VENDOR_3COM
) ||
1739 (sc
->vendor
== ED_VENDOR_HP
)) &&
1740 (ifp
->if_flags
& IFF_ALTPHYS
)) ? " transceiver disabled" : "");
1749 ed_reset(struct ifnet
*ifp
)
1751 struct ed_softc
*sc
= ifp
->if_softc
;
1761 * Stop interface and re-initialize.
1770 * Take interface offline.
1773 ed_stop(struct ed_softc
*sc
)
1777 #ifndef ED_NO_MIIBUS
1778 callout_stop(&sc
->ed_timer
);
1783 * Stop everything on the interface, and select page 0 registers.
1785 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STP
);
1788 * Wait for interface to enter stopped state, but limit # of checks to
1789 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1790 * just in case it's an old one.
1792 if (sc
->chip_type
!= ED_CHIP_TYPE_AX88190
)
1793 while (((ed_nic_inb(sc
, ED_P0_ISR
) & ED_ISR_RST
) == 0) && --n
);
1797 * Device timeout/watchdog routine. Entered if the device neglects to
1798 * generate an interrupt after a transmit has been started on it.
1801 ed_watchdog(struct ifnet
*ifp
)
1803 struct ed_softc
*sc
= ifp
->if_softc
;
1807 log(LOG_ERR
, "%s: device timeout\n", ifp
->if_xname
);
1813 #ifndef ED_NO_MIIBUS
1817 struct ed_softc
*sc
= arg
;
1818 struct mii_data
*mii
;
1821 ifp
= &sc
->arpcom
.ac_if
;
1822 lwkt_serialize_enter(ifp
->if_serializer
);
1829 if (sc
->miibus
!= NULL
) {
1830 mii
= device_get_softc(sc
->miibus
);
1834 callout_reset(&sc
->ed_timer
, hz
, ed_tick
, sc
);
1835 lwkt_serialize_exit(ifp
->if_serializer
);
1840 * Initialize device.
1845 struct ed_softc
*sc
= xsc
;
1846 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1857 * Initialize the NIC in the exact order outlined in the NS manual.
1858 * This init procedure is "mandatory"...don't change what or when
1862 /* reset transmitter flags */
1868 sc
->txb_next_tx
= 0;
1870 /* This variable is used below - don't move this assignment */
1871 sc
->next_packet
= sc
->rec_page_start
+ 1;
1874 * Set interface for page 0, Remote DMA complete, Stopped
1876 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STP
);
1881 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1882 * order=80x86, word-wide DMA xfers,
1884 ed_nic_outb(sc
, ED_P0_DCR
, ED_DCR_FT1
| ED_DCR_WTS
| ED_DCR_LS
);
1888 * Same as above, but byte-wide DMA xfers
1890 ed_nic_outb(sc
, ED_P0_DCR
, ED_DCR_FT1
| ED_DCR_LS
);
1894 * Clear Remote Byte Count Registers
1896 ed_nic_outb(sc
, ED_P0_RBCR0
, 0);
1897 ed_nic_outb(sc
, ED_P0_RBCR1
, 0);
1900 * For the moment, don't store incoming packets in memory.
1902 ed_nic_outb(sc
, ED_P0_RCR
, ED_RCR_MON
);
1905 * Place NIC in internal loopback mode
1907 ed_nic_outb(sc
, ED_P0_TCR
, ED_TCR_LB0
);
1910 * Initialize transmit/receive (ring-buffer) Page Start
1912 ed_nic_outb(sc
, ED_P0_TPSR
, sc
->tx_page_start
);
1913 ed_nic_outb(sc
, ED_P0_PSTART
, sc
->rec_page_start
);
1914 /* Set lower bits of byte addressable framing to 0 */
1915 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
)
1916 ed_nic_outb(sc
, 0x09, 0);
1919 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1921 ed_nic_outb(sc
, ED_P0_PSTOP
, sc
->rec_page_stop
);
1922 ed_nic_outb(sc
, ED_P0_BNRY
, sc
->rec_page_start
);
1925 * Clear all interrupts. A '1' in each bit position clears the
1926 * corresponding flag.
1928 ed_nic_outb(sc
, ED_P0_ISR
, 0xff);
1931 * Enable the following interrupts: receive/transmit complete,
1932 * receive/transmit error, and Receiver OverWrite.
1934 * Counter overflow and Remote DMA complete are *not* enabled.
1936 ed_nic_outb(sc
, ED_P0_IMR
,
1937 ED_IMR_PRXE
| ED_IMR_PTXE
| ED_IMR_RXEE
| ED_IMR_TXEE
| ED_IMR_OVWE
);
1940 * Program Command Register for page 1
1942 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_PAGE_1
| ED_CR_STP
);
1945 * Copy out our station address
1947 for (i
= 0; i
< ETHER_ADDR_LEN
; ++i
)
1948 ed_nic_outb(sc
, ED_P1_PAR(i
), sc
->arpcom
.ac_enaddr
[i
]);
1951 * Set Current Page pointer to next_packet (initialized above)
1953 ed_nic_outb(sc
, ED_P1_CURR
, sc
->next_packet
);
1956 * Program Receiver Configuration Register and multicast filter. CR is
1957 * set to page 0 on return.
1962 * Take interface out of loopback
1964 ed_nic_outb(sc
, ED_P0_TCR
, 0);
1967 * If this is a 3Com board, the tranceiver must be software enabled
1968 * (there is no settable hardware default).
1970 if (sc
->vendor
== ED_VENDOR_3COM
) {
1971 if (ifp
->if_flags
& IFF_ALTPHYS
) {
1972 ed_asic_outb(sc
, ED_3COM_CR
, 0);
1974 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_XSEL
);
1978 #ifndef ED_NO_MIIBUS
1979 if (sc
->miibus
!= NULL
) {
1980 struct mii_data
*mii
;
1981 mii
= device_get_softc(sc
->miibus
);
1986 * Set 'running' flag, and clear output active flag.
1988 ifp
->if_flags
|= IFF_RUNNING
;
1989 ifp
->if_flags
&= ~IFF_OACTIVE
;
1992 * ...and attempt to start output
1996 #ifndef ED_NO_MIIBUS
1997 callout_reset(&sc
->ed_timer
, hz
, ed_tick
, sc
);
2004 * This routine actually starts the transmission on the interface
2006 static __inline
void
2007 ed_xmit(struct ed_softc
*sc
)
2009 struct ifnet
*ifp
= (struct ifnet
*)sc
;
2014 len
= sc
->txb_len
[sc
->txb_next_tx
];
2017 * Set NIC for page 0 register access
2019 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
2022 * Set TX buffer start page
2024 ed_nic_outb(sc
, ED_P0_TPSR
, sc
->tx_page_start
+
2025 sc
->txb_next_tx
* ED_TXBUF_SIZE
);
2030 ed_nic_outb(sc
, ED_P0_TBCR0
, len
);
2031 ed_nic_outb(sc
, ED_P0_TBCR1
, len
>> 8);
2034 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2036 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_TXP
| ED_CR_STA
);
2040 * Point to next transmit buffer slot and wrap if necessary.
2043 if (sc
->txb_next_tx
== sc
->txb_cnt
)
2044 sc
->txb_next_tx
= 0;
2047 * Set a timer just in case we never hear from the board again
2053 * Start output on interface.
2054 * We make two assumptions here:
2055 * 1) that the current priority is set to splimp _before_ this code
2056 * is called *and* is returned to the appropriate priority after
2058 * 2) that the IFF_OACTIVE flag is checked before this code is called
2059 * (i.e. that the output part of the interface is idle)
2062 ed_start(struct ifnet
*ifp
)
2064 struct ed_softc
*sc
= ifp
->if_softc
;
2065 struct mbuf
*m0
, *m
;
2070 kprintf("ed_start(%p) GONE\n",ifp
);
2071 ifq_purge(&ifp
->if_snd
);
2077 * First, see if there are buffered packets and an idle transmitter -
2078 * should never happen at this point.
2080 if (sc
->txb_inuse
&& (sc
->xmit_busy
== 0)) {
2081 kprintf("ed: packets buffered, but transmitter idle\n");
2086 * See if there is room to put another packet in the buffer.
2088 if (sc
->txb_inuse
== sc
->txb_cnt
) {
2091 * No room. Indicate this to the outside world and exit.
2093 ifp
->if_flags
|= IFF_OACTIVE
;
2096 m
= ifq_dequeue(&ifp
->if_snd
, NULL
);
2100 * We are using the !OACTIVE flag to indicate to the outside
2101 * world that we can accept an additional packet rather than
2102 * that the transmitter is _actually_ active. Indeed, the
2103 * transmitter may be active, but if we haven't filled all the
2104 * buffers with data then we still want to accept more.
2106 ifp
->if_flags
&= ~IFF_OACTIVE
;
2111 * Copy the mbuf chain into the transmit buffer
2116 /* txb_new points to next open buffer slot */
2117 buffer
= sc
->mem_start
+ (sc
->txb_new
* ED_TXBUF_SIZE
* ED_PAGE_SIZE
);
2119 if (sc
->mem_shared
) {
2122 * Special case setup for 16 bit boards...
2125 switch (sc
->vendor
) {
2128 * For 16bit 3Com boards (which have 16k of
2129 * memory), we have the xmit buffers in a
2130 * different page of memory ('page 0') - so
2133 case ED_VENDOR_3COM
:
2134 ed_asic_outb(sc
, ED_3COM_GACFR
,
2135 ED_3COM_GACFR_RSEL
);
2139 * Enable 16bit access to shared memory on
2142 case ED_VENDOR_WD_SMC
:
2143 ed_asic_outb(sc
, ED_WD_LAAR
,
2144 sc
->wd_laar_proto
| ED_WD_LAAR_M16EN
);
2145 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
2146 ed_asic_outb(sc
, ED_WD_MSR
, ED_WD_MSR_MENB
);
2151 for (len
= 0; m
!= 0; m
= m
->m_next
) {
2152 bcopy(mtod(m
, caddr_t
), buffer
, m
->m_len
);
2158 * Restore previous shared memory access
2161 switch (sc
->vendor
) {
2162 case ED_VENDOR_3COM
:
2163 ed_asic_outb(sc
, ED_3COM_GACFR
,
2164 ED_3COM_GACFR_RSEL
| ED_3COM_GACFR_MBS0
);
2166 case ED_VENDOR_WD_SMC
:
2167 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
2168 ed_asic_outb(sc
, ED_WD_MSR
, 0x00);
2170 ed_asic_outb(sc
, ED_WD_LAAR
,
2171 sc
->wd_laar_proto
& ~ED_WD_LAAR_M16EN
);
2176 len
= ed_pio_write_mbufs(sc
, m
, (int)buffer
);
2183 sc
->txb_len
[sc
->txb_new
] = max(len
, (ETHER_MIN_LEN
-ETHER_CRC_LEN
));
2188 * Point to next buffer slot and wrap if necessary.
2191 if (sc
->txb_new
== sc
->txb_cnt
)
2194 if (sc
->xmit_busy
== 0)
2202 * Loop back to the top to possibly buffer more packets
2208 * Ethernet interface receiver interrupt.
2210 static __inline
void
2211 ed_rint(struct ed_softc
*sc
)
2213 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2216 struct ed_ring packet_hdr
;
2223 * Set NIC to page 1 registers to get 'current' pointer
2225 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_PAGE_1
| ED_CR_STA
);
2228 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2229 * i.e. it points to where new data has been buffered. The 'CURR'
2230 * (current) register points to the logical end of the ring-buffer -
2231 * i.e. it points to where additional new data will be added. We loop
2232 * here until the logical beginning equals the logical end (or in
2233 * other words, until the ring-buffer is empty).
2235 while (sc
->next_packet
!= ed_nic_inb(sc
, ED_P1_CURR
)) {
2237 /* get pointer to this buffer's header structure */
2238 packet_ptr
= sc
->mem_ring
+
2239 (sc
->next_packet
- sc
->rec_page_start
) * ED_PAGE_SIZE
;
2242 * The byte count includes a 4 byte header that was added by
2246 packet_hdr
= *(struct ed_ring
*) packet_ptr
;
2248 ed_pio_readmem(sc
, (int)packet_ptr
, (char *) &packet_hdr
,
2249 sizeof(packet_hdr
));
2250 len
= packet_hdr
.count
;
2251 if (len
> (ETHER_MAX_LEN
- ETHER_CRC_LEN
+ sizeof(struct ed_ring
)) ||
2252 len
< (ETHER_MIN_LEN
- ETHER_CRC_LEN
+ sizeof(struct ed_ring
))) {
2254 * Length is a wild value. There's a good chance that
2255 * this was caused by the NIC being old and buggy.
2256 * The bug is that the length low byte is duplicated in
2257 * the high byte. Try to recalculate the length based on
2258 * the pointer to the next packet.
2261 * NOTE: sc->next_packet is pointing at the current packet.
2263 len
&= ED_PAGE_SIZE
- 1; /* preserve offset into page */
2264 if (packet_hdr
.next_packet
>= sc
->next_packet
) {
2265 len
+= (packet_hdr
.next_packet
- sc
->next_packet
) * ED_PAGE_SIZE
;
2267 len
+= ((packet_hdr
.next_packet
- sc
->rec_page_start
) +
2268 (sc
->rec_page_stop
- sc
->next_packet
)) * ED_PAGE_SIZE
;
2271 * because buffers are aligned on 256-byte boundary,
2272 * the length computed above is off by 256 in almost
2273 * all cases. Fix it...
2277 if (len
> (ETHER_MAX_LEN
- ETHER_CRC_LEN
2278 + sizeof(struct ed_ring
)))
2279 sc
->mibdata
.dot3StatsFrameTooLongs
++;
2282 * Be fairly liberal about what we allow as a "reasonable" length
2283 * so that a [crufty] packet will make it to BPF (and can thus
2284 * be analyzed). Note that all that is really important is that
2285 * we have a length that will fit into one mbuf cluster or less;
2286 * the upper layer protocols can then figure out the length from
2287 * their own length field(s).
2288 * But make sure that we have at least a full ethernet header
2289 * or we would be unable to call ether_input() later.
2291 if ((len
>= sizeof(struct ed_ring
) + ETHER_HDR_LEN
) &&
2292 (len
<= MCLBYTES
) &&
2293 (packet_hdr
.next_packet
>= sc
->rec_page_start
) &&
2294 (packet_hdr
.next_packet
< sc
->rec_page_stop
)) {
2298 ed_get_packet(sc
, packet_ptr
+ sizeof(struct ed_ring
),
2299 len
- sizeof(struct ed_ring
));
2303 * Really BAD. The ring pointers are corrupted.
2306 "%s: NIC memory corrupt - invalid packet length %d\n",
2307 ifp
->if_xname
, len
);
2314 * Update next packet pointer
2316 sc
->next_packet
= packet_hdr
.next_packet
;
2319 * Update NIC boundry pointer - being careful to keep it one
2320 * buffer behind. (as recommended by NS databook)
2322 boundry
= sc
->next_packet
- 1;
2323 if (boundry
< sc
->rec_page_start
)
2324 boundry
= sc
->rec_page_stop
- 1;
2327 * Set NIC to page 0 registers to update boundry register
2329 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
2331 ed_nic_outb(sc
, ED_P0_BNRY
, boundry
);
2334 * Set NIC to page 1 registers before looping to top (prepare
2335 * to get 'CURR' current pointer)
2337 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_PAGE_1
| ED_CR_STA
);
2342 * Ethernet interface interrupt processor
2347 struct ed_softc
*sc
= (struct ed_softc
*) arg
;
2348 struct ifnet
*ifp
= (struct ifnet
*)sc
;
2355 * Set NIC to page 0 registers
2357 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
2360 * loop until there are no more new interrupts. When the card
2361 * goes away, the hardware will read back 0xff. Looking at
2362 * the interrupts, it would appear that 0xff is impossible,
2363 * or at least extremely unlikely.
2365 while ((isr
= ed_nic_inb(sc
, ED_P0_ISR
)) != 0 && isr
!= 0xff) {
2368 * reset all the bits that we are 'acknowledging' by writing a
2369 * '1' to each bit position that was set (writing a '1'
2372 ed_nic_outb(sc
, ED_P0_ISR
, isr
);
2375 * XXX workaround for AX88190
2376 * We limit this to 5000 iterations. At 1us per inb/outb,
2377 * this translates to about 15ms, which should be plenty
2378 * of time, and also gives protection in the card eject
2381 if (sc
->chip_type
== ED_CHIP_TYPE_AX88190
) {
2382 count
= 5000; /* 15ms */
2383 while (count
-- && (ed_nic_inb(sc
, ED_P0_ISR
) & isr
)) {
2384 ed_nic_outb(sc
, ED_P0_ISR
,0);
2385 ed_nic_outb(sc
, ED_P0_ISR
,isr
);
2392 * Handle transmitter interrupts. Handle these first because
2393 * the receiver will reset the board under some conditions.
2395 if (isr
& (ED_ISR_PTX
| ED_ISR_TXE
)) {
2396 u_char collisions
= ed_nic_inb(sc
, ED_P0_NCR
) & 0x0f;
2399 * Check for transmit error. If a TX completed with an
2400 * error, we end up throwing the packet away. Really
2401 * the only error that is possible is excessive
2402 * collisions, and in this case it is best to allow
2403 * the automatic mechanisms of TCP to backoff the
2404 * flow. Of course, with UDP we're screwed, but this
2405 * is expected when a network is heavily loaded.
2407 ed_nic_inb(sc
, ED_P0_TSR
);
2408 if (isr
& ED_ISR_TXE
) {
2412 * Excessive collisions (16)
2414 tsr
= ed_nic_inb(sc
, ED_P0_TSR
);
2415 if ((tsr
& ED_TSR_ABT
)
2416 && (collisions
== 0)) {
2419 * When collisions total 16, the
2420 * P0_NCR will indicate 0, and the
2424 sc
->mibdata
.dot3StatsExcessiveCollisions
++;
2425 sc
->mibdata
.dot3StatsCollFrequencies
[15]++;
2427 if (tsr
& ED_TSR_OWC
)
2428 sc
->mibdata
.dot3StatsLateCollisions
++;
2429 if (tsr
& ED_TSR_CDH
)
2430 sc
->mibdata
.dot3StatsSQETestErrors
++;
2431 if (tsr
& ED_TSR_CRS
)
2432 sc
->mibdata
.dot3StatsCarrierSenseErrors
++;
2433 if (tsr
& ED_TSR_FU
)
2434 sc
->mibdata
.dot3StatsInternalMacTransmitErrors
++;
2437 * update output errors counter
2443 * Update total number of successfully
2444 * transmitted packets.
2450 * reset tx busy and output active flags
2453 ifp
->if_flags
&= ~IFF_OACTIVE
;
2456 * clear watchdog timer
2461 * Add in total number of collisions on last
2464 ifp
->if_collisions
+= collisions
;
2465 switch(collisions
) {
2470 sc
->mibdata
.dot3StatsSingleCollisionFrames
++;
2471 sc
->mibdata
.dot3StatsCollFrequencies
[0]++;
2474 sc
->mibdata
.dot3StatsMultipleCollisionFrames
++;
2476 dot3StatsCollFrequencies
[collisions
-1]
2482 * Decrement buffer in-use count if not zero (can only
2483 * be zero if a transmitter interrupt occured while
2484 * not actually transmitting). If data is ready to
2485 * transmit, start it transmitting, otherwise defer
2486 * until after handling receiver
2488 if (sc
->txb_inuse
&& --sc
->txb_inuse
)
2493 * Handle receiver interrupts
2495 if (isr
& (ED_ISR_PRX
| ED_ISR_RXE
| ED_ISR_OVW
)) {
2498 * Overwrite warning. In order to make sure that a
2499 * lockup of the local DMA hasn't occurred, we reset
2500 * and re-init the NIC. The NSC manual suggests only a
2501 * partial reset/re-init is necessary - but some chips
2502 * seem to want more. The DMA lockup has been seen
2503 * only with early rev chips - Methinks this bug was
2504 * fixed in later revs. -DG
2506 if (isr
& ED_ISR_OVW
) {
2510 "%s: warning - receiver ring buffer overrun\n",
2515 * Stop/reset/re-init NIC
2521 * Receiver Error. One or more of: CRC error,
2522 * frame alignment error FIFO overrun, or
2525 if (isr
& ED_ISR_RXE
) {
2527 rsr
= ed_nic_inb(sc
, ED_P0_RSR
);
2528 if (rsr
& ED_RSR_CRC
)
2529 sc
->mibdata
.dot3StatsFCSErrors
++;
2530 if (rsr
& ED_RSR_FAE
)
2531 sc
->mibdata
.dot3StatsAlignmentErrors
++;
2532 if (rsr
& ED_RSR_FO
)
2533 sc
->mibdata
.dot3StatsInternalMacReceiveErrors
++;
2536 if_printf("receive error %x\n",
2537 ed_nic_inb(sc
, ED_P0_RSR
));
2542 * Go get the packet(s) XXX - Doing this on an
2543 * error is dubious because there shouldn't be
2544 * any data to get (we've configured the
2545 * interface to not accept packets with
2550 * Enable 16bit access to shared memory first
2554 (sc
->vendor
== ED_VENDOR_WD_SMC
)) {
2556 ed_asic_outb(sc
, ED_WD_LAAR
,
2557 sc
->wd_laar_proto
| ED_WD_LAAR_M16EN
);
2558 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
2559 ed_asic_outb(sc
, ED_WD_MSR
,
2565 /* disable 16bit access */
2567 (sc
->vendor
== ED_VENDOR_WD_SMC
)) {
2569 if (sc
->chip_type
== ED_CHIP_TYPE_WD790
) {
2570 ed_asic_outb(sc
, ED_WD_MSR
, 0x00);
2572 ed_asic_outb(sc
, ED_WD_LAAR
,
2573 sc
->wd_laar_proto
& ~ED_WD_LAAR_M16EN
);
2579 * If it looks like the transmitter can take more data,
2580 * attempt to start output on the interface. This is done
2581 * after handling the receiver to give the receiver priority.
2583 if ((ifp
->if_flags
& IFF_OACTIVE
) == 0)
2587 * return NIC CR to standard state: page 0, remote DMA
2588 * complete, start (toggling the TXP bit off, even if was just
2589 * set in the transmit routine, is *okay* - it is 'edge'
2590 * triggered from low to high)
2592 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
2595 * If the Network Talley Counters overflow, read them to reset
2596 * them. It appears that old 8390's won't clear the ISR flag
2597 * otherwise - resulting in an infinite loop.
2599 if (isr
& ED_ISR_CNT
) {
2600 ed_nic_inb(sc
, ED_P0_CNTR0
);
2601 ed_nic_inb(sc
, ED_P0_CNTR1
);
2602 ed_nic_inb(sc
, ED_P0_CNTR2
);
2608 * Process an ioctl request. This code needs some work - it looks
2612 ed_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
2614 struct ed_softc
*sc
= ifp
->if_softc
;
2615 #ifndef ED_NO_MIIBUS
2616 struct ifreq
*ifr
= (struct ifreq
*)data
;
2617 struct mii_data
*mii
;
2623 if (sc
== NULL
|| sc
->gone
) {
2624 ifp
->if_flags
&= ~IFF_RUNNING
;
2633 * If the interface is marked up and stopped, then start it.
2634 * If it is marked down and running, then stop it.
2636 if (ifp
->if_flags
& IFF_UP
) {
2637 if ((ifp
->if_flags
& IFF_RUNNING
) == 0)
2640 if (ifp
->if_flags
& IFF_RUNNING
) {
2642 ifp
->if_flags
&= ~IFF_RUNNING
;
2647 * Promiscuous flag may have changed, so reprogram the RCR.
2652 * An unfortunate hack to provide the (required) software
2653 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2654 * disables the tranceiver if set.
2656 if (sc
->vendor
== ED_VENDOR_3COM
) {
2657 if (ifp
->if_flags
& IFF_ALTPHYS
) {
2658 ed_asic_outb(sc
, ED_3COM_CR
, 0);
2660 ed_asic_outb(sc
, ED_3COM_CR
, ED_3COM_CR_XSEL
);
2662 } else if (sc
->vendor
== ED_VENDOR_HP
)
2663 ed_hpp_set_physical_link(sc
);
2669 * Multicast list has changed; set the hardware filter
2676 #ifndef ED_NO_MIIBUS
2679 if (sc
->miibus
== NULL
) {
2683 mii
= device_get_softc(sc
->miibus
);
2684 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
2689 error
= ether_ioctl(ifp
, command
, data
);
2699 * Given a source and destination address, copy 'amount' of a packet from
2700 * the ring buffer into a linear destination buffer. Takes into account
2703 static __inline
char *
2704 ed_ring_copy(struct ed_softc
*sc
, char *src
, char *dst
, u_short amount
)
2708 /* does copy wrap to lower addr in ring buffer? */
2709 if (src
+ amount
> sc
->mem_end
) {
2710 tmp_amount
= sc
->mem_end
- src
;
2712 /* copy amount up to end of NIC memory */
2714 bcopy(src
, dst
, tmp_amount
);
2716 ed_pio_readmem(sc
, (int)src
, dst
, tmp_amount
);
2718 amount
-= tmp_amount
;
2723 bcopy(src
, dst
, amount
);
2725 ed_pio_readmem(sc
, (int)src
, dst
, amount
);
2727 return (src
+ amount
);
2731 * Retreive packet from shared memory and send to the next level up via
2735 ed_get_packet(struct ed_softc
*sc
, char *buf
, u_short len
)
2737 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2738 struct ether_header
*eh
;
2742 * Allocate a header mbuf.
2743 * We always put the received packet in a single buffer -
2744 * either with just an mbuf header or in a cluster attached
2745 * to the header. The +2 is to compensate for the alignment
2748 m
= m_getl(len
+ 2, MB_DONTWAIT
, MT_DATA
, M_PKTHDR
, NULL
);
2751 m
->m_pkthdr
.rcvif
= ifp
;
2752 m
->m_pkthdr
.len
= m
->m_len
= len
;
2755 * The +2 is to longword align the start of the real packet.
2756 * This is important for NFS.
2759 eh
= mtod(m
, struct ether_header
*);
2762 * Get packet, including link layer address, from interface.
2764 ed_ring_copy(sc
, buf
, (char *)eh
, len
);
2766 m
->m_pkthdr
.len
= m
->m_len
= len
;
2768 ifp
->if_input(ifp
, m
);
2772 * Supporting routines
2776 * Given a NIC memory source address and a host memory destination
2777 * address, copy 'amount' from NIC to host using Programmed I/O.
2778 * The 'amount' is rounded up to a word - okay as long as mbufs
2780 * This routine is currently Novell-specific.
2783 ed_pio_readmem(struct ed_softc
*sc
, int src
, u_char
*dst
, u_short amount
)
2785 /* HP PC Lan+ cards need special handling */
2786 if (sc
->vendor
== ED_VENDOR_HP
&& sc
->type
== ED_TYPE_HP_PCLANPLUS
) {
2787 ed_hpp_readmem(sc
, src
, dst
, amount
);
2791 /* Regular Novell cards */
2792 /* select page 0 registers */
2793 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD2
| ED_CR_STA
);
2795 /* round up to a word */
2799 /* set up DMA byte count */
2800 ed_nic_outb(sc
, ED_P0_RBCR0
, amount
);
2801 ed_nic_outb(sc
, ED_P0_RBCR1
, amount
>> 8);
2803 /* set up source address in NIC mem */
2804 ed_nic_outb(sc
, ED_P0_RSAR0
, src
);
2805 ed_nic_outb(sc
, ED_P0_RSAR1
, src
>> 8);
2807 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD0
| ED_CR_STA
);
2810 ed_asic_insw(sc
, ED_NOVELL_DATA
, dst
, amount
/ 2);
2812 ed_asic_insb(sc
, ED_NOVELL_DATA
, dst
, amount
);
2817 * Stripped down routine for writing a linear buffer to NIC memory.
2818 * Only used in the probe routine to test the memory. 'len' must
2822 ed_pio_writemem(struct ed_softc
*sc
, char *src
, u_short dst
, u_short len
)
2824 int maxwait
= 200; /* about 240us */
2826 /* select page 0 registers */
2827 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD2
| ED_CR_STA
);
2829 /* reset remote DMA complete flag */
2830 ed_nic_outb(sc
, ED_P0_ISR
, ED_ISR_RDC
);
2832 /* set up DMA byte count */
2833 ed_nic_outb(sc
, ED_P0_RBCR0
, len
);
2834 ed_nic_outb(sc
, ED_P0_RBCR1
, len
>> 8);
2836 /* set up destination address in NIC mem */
2837 ed_nic_outb(sc
, ED_P0_RSAR0
, dst
);
2838 ed_nic_outb(sc
, ED_P0_RSAR1
, dst
>> 8);
2840 /* set remote DMA write */
2841 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD1
| ED_CR_STA
);
2844 ed_asic_outsw(sc
, ED_NOVELL_DATA
, src
, len
/ 2);
2846 ed_asic_outsb(sc
, ED_NOVELL_DATA
, src
, len
);
2850 * Wait for remote DMA complete. This is necessary because on the
2851 * transmit side, data is handled internally by the NIC in bursts and
2852 * we can't start another remote DMA until this one completes. Not
2853 * waiting causes really bad things to happen - like the NIC
2854 * irrecoverably jamming the ISA bus.
2856 while (((ed_nic_inb(sc
, ED_P0_ISR
) & ED_ISR_RDC
) != ED_ISR_RDC
) && --maxwait
);
2860 * Write an mbuf chain to the destination NIC memory address using
2864 ed_pio_write_mbufs(struct ed_softc
*sc
, struct mbuf
*m
, int dst
)
2866 struct ifnet
*ifp
= (struct ifnet
*)sc
;
2867 u_short total_len
, dma_len
;
2869 int maxwait
= 200; /* about 240us */
2871 /* HP PC Lan+ cards need special handling */
2872 if (sc
->vendor
== ED_VENDOR_HP
&& sc
->type
== ED_TYPE_HP_PCLANPLUS
) {
2873 return ed_hpp_write_mbufs(sc
, m
, dst
);
2876 /* Regular Novell cards */
2877 /* First, count up the total number of bytes to copy */
2878 for (total_len
= 0, mp
= m
; mp
; mp
= mp
->m_next
)
2879 total_len
+= mp
->m_len
;
2881 dma_len
= total_len
;
2882 if (sc
->isa16bit
&& (dma_len
& 1))
2885 /* select page 0 registers */
2886 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD2
| ED_CR_STA
);
2888 /* reset remote DMA complete flag */
2889 ed_nic_outb(sc
, ED_P0_ISR
, ED_ISR_RDC
);
2891 /* set up DMA byte count */
2892 ed_nic_outb(sc
, ED_P0_RBCR0
, dma_len
);
2893 ed_nic_outb(sc
, ED_P0_RBCR1
, dma_len
>> 8);
2895 /* set up destination address in NIC mem */
2896 ed_nic_outb(sc
, ED_P0_RSAR0
, dst
);
2897 ed_nic_outb(sc
, ED_P0_RSAR1
, dst
>> 8);
2899 /* set remote DMA write */
2900 ed_nic_outb(sc
, ED_P0_CR
, ED_CR_RD1
| ED_CR_STA
);
2903 * Transfer the mbuf chain to the NIC memory.
2904 * 16-bit cards require that data be transferred as words, and only words.
2905 * So that case requires some extra code to patch over odd-length mbufs.
2908 if (!sc
->isa16bit
) {
2909 /* NE1000s are easy */
2912 ed_asic_outsb(sc
, ED_NOVELL_DATA
,
2913 m
->m_data
, m
->m_len
);
2918 /* NE2000s are a pain */
2928 data
= mtod(m
, caddr_t
);
2929 /* finish the last word */
2931 savebyte
[1] = *data
;
2932 ed_asic_outw(sc
, ED_NOVELL_DATA
,
2933 *(u_short
*)savebyte
);
2938 /* output contiguous words */
2940 ed_asic_outsw(sc
, ED_NOVELL_DATA
,
2945 /* save last byte, if necessary */
2947 savebyte
[0] = *data
;
2953 /* spit last byte */
2955 ed_asic_outw(sc
, ED_NOVELL_DATA
, *(u_short
*)savebyte
);
2960 * Wait for remote DMA complete. This is necessary because on the
2961 * transmit side, data is handled internally by the NIC in bursts and
2962 * we can't start another remote DMA until this one completes. Not
2963 * waiting causes really bad things to happen - like the NIC
2964 * irrecoverably jamming the ISA bus.
2966 while (((ed_nic_inb(sc
, ED_P0_ISR
) & ED_ISR_RDC
) != ED_ISR_RDC
) && --maxwait
);
2969 log(LOG_WARNING
, "%s: remote transmit DMA failed to complete\n",
2978 * Support routines to handle the HP PC Lan+ card.
2982 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2987 ed_hpp_readmem(struct ed_softc
*sc
, u_short src
, u_char
*dst
, u_short amount
)
2990 int use_32bit_access
= !(sc
->hpp_id
& ED_HPP_ID_16_BIT_ACCESS
);
2993 /* Program the source address in RAM */
2994 ed_asic_outw(sc
, ED_HPP_PAGE_2
, src
);
2997 * The HP PC Lan+ card supports word reads as well as
2998 * a memory mapped i/o port that is aliased to every
2999 * even address on the board.
3002 if (sc
->hpp_mem_start
) {
3004 /* Enable memory mapped access. */
3005 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
&
3006 ~(ED_HPP_OPTION_MEM_DISABLE
|
3007 ED_HPP_OPTION_BOOT_ROM_ENB
));
3009 if (use_32bit_access
&& (amount
> 3)) {
3010 u_int32_t
*dl
= (u_int32_t
*) dst
;
3011 volatile u_int32_t
*const sl
=
3012 (u_int32_t
*) sc
->hpp_mem_start
;
3013 u_int32_t
*const fence
= dl
+ (amount
>> 2);
3015 /* Copy out NIC data. We could probably write this
3016 as a `movsl'. The currently generated code is lousy.
3022 dst
+= (amount
& ~3);
3027 /* Finish off any words left, as a series of short reads */
3029 u_short
*d
= (u_short
*) dst
;
3030 volatile u_short
*const s
=
3031 (u_short
*) sc
->hpp_mem_start
;
3032 u_short
*const fence
= d
+ (amount
>> 1);
3034 /* Copy out NIC data. */
3039 dst
+= (amount
& ~1);
3044 * read in a byte; however we need to always read 16 bits
3045 * at a time or the hardware gets into a funny state
3049 /* need to read in a short and copy LSB */
3050 volatile u_short
*const s
=
3051 (volatile u_short
*) sc
->hpp_mem_start
;
3056 /* Restore Boot ROM access. */
3058 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
);
3062 /* Read in data using the I/O port */
3063 if (use_32bit_access
&& (amount
> 3)) {
3064 ed_asic_insl(sc
, ED_HPP_PAGE_4
, dst
, amount
>> 2);
3065 dst
+= (amount
& ~3);
3069 ed_asic_insw(sc
, ED_HPP_PAGE_4
, dst
, amount
>> 1);
3070 dst
+= (amount
& ~1);
3073 if (amount
== 1) { /* read in a short and keep the LSB */
3074 *dst
= ed_asic_inw(sc
, ED_HPP_PAGE_4
) & 0xFF;
3080 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3082 * Only used in the probe routine to test the memory. 'len' must
3086 ed_hpp_writemem(struct ed_softc
*sc
, u_char
*src
, u_short dst
, u_short len
)
3088 /* reset remote DMA complete flag */
3089 ed_nic_outb(sc
, ED_P0_ISR
, ED_ISR_RDC
);
3091 /* program the write address in RAM */
3092 ed_asic_outw(sc
, ED_HPP_PAGE_0
, dst
);
3094 if (sc
->hpp_mem_start
) {
3095 u_short
*s
= (u_short
*) src
;
3096 volatile u_short
*d
= (u_short
*) sc
->hpp_mem_start
;
3097 u_short
*const fence
= s
+ (len
>> 1);
3100 * Enable memory mapped access.
3103 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
&
3104 ~(ED_HPP_OPTION_MEM_DISABLE
|
3105 ED_HPP_OPTION_BOOT_ROM_ENB
));
3108 * Copy to NIC memory.
3115 * Restore Boot ROM access.
3118 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
);
3121 /* write data using I/O writes */
3122 ed_asic_outsw(sc
, ED_HPP_PAGE_4
, src
, len
/ 2);
3127 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3128 * outsw() or via the memory mapped interface to the same register.
3129 * Writes have to be in word units; byte accesses won't work and may cause
3130 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3135 ed_hpp_write_mbufs(struct ed_softc
*sc
, struct mbuf
*m
, int dst
)
3140 volatile u_short
* const d
=
3141 (volatile u_short
*) sc
->hpp_mem_start
;
3142 int use_32bit_accesses
= !(sc
->hpp_id
& ED_HPP_ID_16_BIT_ACCESS
);
3144 /* select page 0 registers */
3145 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
3147 /* reset remote DMA complete flag */
3148 ed_nic_outb(sc
, ED_P0_ISR
, ED_ISR_RDC
);
3150 /* program the write address in RAM */
3151 ed_asic_outw(sc
, ED_HPP_PAGE_0
, dst
);
3153 if (sc
->hpp_mem_start
) /* enable memory mapped I/O */
3154 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
&
3155 ~(ED_HPP_OPTION_MEM_DISABLE
|
3156 ED_HPP_OPTION_BOOT_ROM_ENB
));
3161 if (sc
->hpp_mem_start
) { /* Memory mapped I/O port */
3163 total_len
+= (len
= m
->m_len
);
3165 caddr_t data
= mtod(m
, caddr_t
);
3166 /* finish the last word of the previous mbuf */
3168 savebyte
[1] = *data
;
3169 *d
= *((u_short
*) savebyte
);
3170 data
++; len
--; wantbyte
= 0;
3172 /* output contiguous words */
3173 if ((len
> 3) && (use_32bit_accesses
)) {
3174 volatile u_int32_t
*const dl
=
3175 (volatile u_int32_t
*) d
;
3176 u_int32_t
*sl
= (u_int32_t
*) data
;
3177 u_int32_t
*fence
= sl
+ (len
>> 2);
3185 /* finish off remain 16 bit writes */
3187 u_short
*s
= (u_short
*) data
;
3188 u_short
*fence
= s
+ (len
>> 1);
3196 /* save last byte if needed */
3197 if ((wantbyte
= (len
== 1)) != 0)
3198 savebyte
[0] = *data
;
3200 m
= m
->m_next
; /* to next mbuf */
3202 if (wantbyte
) /* write last byte */
3203 *d
= *((u_short
*) savebyte
);
3205 /* use programmed I/O */
3207 total_len
+= (len
= m
->m_len
);
3209 caddr_t data
= mtod(m
, caddr_t
);
3210 /* finish the last word of the previous mbuf */
3212 savebyte
[1] = *data
;
3213 ed_asic_outw(sc
, ED_HPP_PAGE_4
,
3214 *((u_short
*)savebyte
));
3219 /* output contiguous words */
3220 if ((len
> 3) && use_32bit_accesses
) {
3221 ed_asic_outsl(sc
, ED_HPP_PAGE_4
,
3226 /* finish off remaining 16 bit accesses */
3228 ed_asic_outsw(sc
, ED_HPP_PAGE_4
,
3233 if ((wantbyte
= (len
== 1)) != 0)
3234 savebyte
[0] = *data
;
3239 if (wantbyte
) /* spit last byte */
3240 ed_asic_outw(sc
, ED_HPP_PAGE_4
, *(u_short
*)savebyte
);
3244 if (sc
->hpp_mem_start
) /* turn off memory mapped i/o */
3245 ed_asic_outw(sc
, ED_HPP_OPTION
, sc
->hpp_options
);
3250 #ifndef ED_NO_MIIBUS
3252 * MII bus support routines.
3255 ed_miibus_readreg(device_t dev
, int phy
, int reg
)
3257 struct ed_softc
*sc
= device_get_softc(dev
);
3267 (*sc
->mii_writebits
)(sc
, 0xffffffff, 32);
3268 (*sc
->mii_writebits
)(sc
, ED_MII_STARTDELIM
, ED_MII_STARTDELIM_BITS
);
3269 (*sc
->mii_writebits
)(sc
, ED_MII_READOP
, ED_MII_OP_BITS
);
3270 (*sc
->mii_writebits
)(sc
, phy
, ED_MII_PHY_BITS
);
3271 (*sc
->mii_writebits
)(sc
, reg
, ED_MII_REG_BITS
);
3273 failed
= (*sc
->mii_readbits
)(sc
, ED_MII_ACK_BITS
);
3274 val
= (*sc
->mii_readbits
)(sc
, ED_MII_DATA_BITS
);
3275 (*sc
->mii_writebits
)(sc
, ED_MII_IDLE
, ED_MII_IDLE_BITS
);
3279 return (failed
? 0 : val
);
3283 ed_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
3285 struct ed_softc
*sc
= device_get_softc(dev
);
3294 (*sc
->mii_writebits
)(sc
, 0xffffffff, 32);
3295 (*sc
->mii_writebits
)(sc
, ED_MII_STARTDELIM
, ED_MII_STARTDELIM_BITS
);
3296 (*sc
->mii_writebits
)(sc
, ED_MII_WRITEOP
, ED_MII_OP_BITS
);
3297 (*sc
->mii_writebits
)(sc
, phy
, ED_MII_PHY_BITS
);
3298 (*sc
->mii_writebits
)(sc
, reg
, ED_MII_REG_BITS
);
3299 (*sc
->mii_writebits
)(sc
, ED_MII_TURNAROUND
, ED_MII_TURNAROUND_BITS
);
3300 (*sc
->mii_writebits
)(sc
, data
, ED_MII_DATA_BITS
);
3301 (*sc
->mii_writebits
)(sc
, ED_MII_IDLE
, ED_MII_IDLE_BITS
);
3307 ed_ifmedia_upd(struct ifnet
*ifp
)
3309 struct ed_softc
*sc
;
3310 struct mii_data
*mii
;
3313 if (sc
->gone
|| sc
->miibus
== NULL
)
3316 mii
= device_get_softc(sc
->miibus
);
3317 return mii_mediachg(mii
);
3321 ed_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
3323 struct ed_softc
*sc
;
3324 struct mii_data
*mii
;
3327 if (sc
->gone
|| sc
->miibus
== NULL
)
3330 mii
= device_get_softc(sc
->miibus
);
3332 ifmr
->ifm_active
= mii
->mii_media_active
;
3333 ifmr
->ifm_status
= mii
->mii_media_status
;
3337 ed_child_detached(device_t dev
, device_t child
)
3339 struct ed_softc
*sc
;
3341 sc
= device_get_softc(dev
);
3342 if (child
== sc
->miibus
)
3348 ed_setrcr(struct ed_softc
*sc
)
3350 struct ifnet
*ifp
= (struct ifnet
*)sc
;
3354 /* Bit 6 in AX88190 RCR register must be set. */
3355 if (sc
->chip_type
== ED_CHIP_TYPE_AX88190
)
3360 /* set page 1 registers */
3361 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_PAGE_1
| ED_CR_STP
);
3363 if (ifp
->if_flags
& IFF_PROMISC
) {
3366 * Reconfigure the multicast filter.
3368 for (i
= 0; i
< 8; i
++)
3369 ed_nic_outb(sc
, ED_P1_MAR(i
), 0xff);
3372 * And turn on promiscuous mode. Also enable reception of
3373 * runts and packets with CRC & alignment errors.
3375 /* Set page 0 registers */
3376 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STP
);
3378 ed_nic_outb(sc
, ED_P0_RCR
, ED_RCR_PRO
| ED_RCR_AM
|
3379 ED_RCR_AB
| ED_RCR_AR
| ED_RCR_SEP
| reg1
);
3381 /* set up multicast addresses and filter modes */
3382 if (ifp
->if_flags
& IFF_MULTICAST
) {
3385 if (ifp
->if_flags
& IFF_ALLMULTI
) {
3386 mcaf
[0] = 0xffffffff;
3387 mcaf
[1] = 0xffffffff;
3389 ds_getmcaf(sc
, mcaf
);
3392 * Set multicast filter on chip.
3394 for (i
= 0; i
< 8; i
++)
3395 ed_nic_outb(sc
, ED_P1_MAR(i
), ((u_char
*) mcaf
)[i
]);
3397 /* Set page 0 registers */
3398 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STP
);
3400 ed_nic_outb(sc
, ED_P0_RCR
, ED_RCR_AM
| ED_RCR_AB
| reg1
);
3404 * Initialize multicast address hashing registers to
3405 * not accept multicasts.
3407 for (i
= 0; i
< 8; ++i
)
3408 ed_nic_outb(sc
, ED_P1_MAR(i
), 0x00);
3410 /* Set page 0 registers */
3411 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STP
);
3413 ed_nic_outb(sc
, ED_P0_RCR
, ED_RCR_AB
| reg1
);
3420 ed_nic_outb(sc
, ED_P0_CR
, sc
->cr_proto
| ED_CR_STA
);
3424 * Compute crc for ethernet address
3427 ds_mchash(const uint8_t *addr
)
3429 #define ED_POLYNOMIAL 0x04c11db6
3430 uint32_t crc
= 0xffffffff;
3431 int carry
, idx
, bit
;
3434 for (idx
= 6; --idx
>= 0;) {
3435 for (data
= *addr
++, bit
= 8; --bit
>= 0; data
>>=1 ) {
3436 carry
= ((crc
& 0x80000000) ? 1 : 0) ^ (data
& 0x01);
3439 crc
= (crc
^ ED_POLYNOMIAL
) | carry
;
3447 * Compute the multicast address filter from the
3448 * list of multicast addresses we need to listen to.
3451 ds_getmcaf(struct ed_softc
*sc
, u_int32_t
*mcaf
)
3454 u_char
*af
= (u_char
*) mcaf
;
3455 struct ifmultiaddr
*ifma
;
3460 LIST_FOREACH(ifma
, &sc
->arpcom
.ac_if
.if_multiaddrs
, ifma_link
) {
3461 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
3463 index
= ds_mchash(LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
))
3465 af
[index
>> 3] |= 1 << (index
& 7);