2 * Copyright (c) 1999,2000,2001 Jonathan Lemon
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/dev/gx/if_gxvar.h,v 1.1.2.1 2001/11/15 03:09:23 jlemon Exp $
30 * $DragonFly: src/sys/dev/netif/gx/Attic/if_gxvar.h,v 1.6 2005/06/14 16:47:38 joerg Exp $
33 #ifndef PCIM_CMD_MWIEN
34 #define PCIM_CMD_MWIEN 0x0010
39 /* CSR_WRITE_8 assumes the register is in low/high order */
40 #define CSR_WRITE_8(gx, reg, val) do { \
41 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val & 0xffffffff); \
42 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg + 4, val >> 32); \
44 #define CSR_WRITE_4(gx, reg, val) \
45 bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val)
46 #define CSR_WRITE_2(gx, reg, val) \
47 bus_space_write_2(gx->gx_btag, gx->gx_bhandle, reg, val)
48 #define CSR_WRITE_1(gx, reg, val) \
49 bus_space_write_1(gx->gx_btag, gx->gx_bhandle, reg, val)
51 #define CSR_READ_4(gx, reg) \
52 bus_space_read_4(gx->gx_btag, gx->gx_bhandle, reg)
53 #define CSR_READ_2(gx, reg) \
54 bus_space_read_2(gx->gx_btag, gx->gx_bhandle, reg)
55 #define CSR_READ_1(gx, reg) \
56 bus_space_read_1(gx->gx_btag, gx->gx_bhandle, reg)
58 #define GX_SETBIT(gx, reg, x) \
59 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x)))
60 #define GX_CLRBIT(gx, reg, x) \
61 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) & ~(x)))
64 * In theory, these can go up to 64K each, but due to chip bugs,
65 * they are limited to 256 max. Descriptor counts should be a
68 #define GX_TX_RING_CNT 256
69 #define GX_RX_RING_CNT 256
71 #define GX_INC(x, y) (x) = (x + 1) % y
72 #define GX_PREV(x, y) (x == 0 ? y - 1 : x - 1)
74 #define GX_MAX_MTU (16 * 1024)
77 struct gx_rx_desc gx_rx_ring
[GX_RX_RING_CNT
];
78 struct gx_tx_desc gx_tx_ring
[GX_TX_RING_CNT
];
81 struct gx_chain_data
{
82 struct mbuf
*gx_rx_chain
[GX_RX_RING_CNT
];
83 struct mbuf
*gx_tx_chain
[GX_TX_RING_CNT
];
103 struct arpcom arpcom
; /* interface info */
104 struct ifmedia gx_media
; /* media info */
105 bus_space_handle_t gx_bhandle
; /* bus space handle */
106 bus_space_tag_t gx_btag
; /* bus space tag */
107 void *gx_intrhand
; /* irq handler handle */
108 struct resource
*gx_irq
; /* IRQ resource handle */
109 struct resource
*gx_res
; /* I/O or shared mem handle */
112 u_int8_t gx_unit
; /* controller number */
113 u_int8_t gx_tbimode
; /* transceiver flag */
114 int gx_vflags
; /* version-specific flags */
115 u_int32_t gx_ipg
; /* version-specific IPG */
116 struct gx_ring_data
*gx_rdata
;
117 struct gx_chain_data gx_cdata
;
119 struct mbuf
*gx_pkthdr
;
120 struct mbuf
**gx_pktnextp
;
121 int gx_rx_tail_idx
; /* receive ring tail index */
122 int gx_tx_tail_idx
; /* transmit ring tail index */
123 int gx_tx_head_idx
; /* transmit ring tail index */
125 int gx_txcontext
; /* current TX context */
126 struct gx_regs gx_reg
;
129 int gx_tx_intr_delay
;
130 int gx_rx_intr_delay
;
133 int gx_tx_interrupts
;
134 int gx_rx_interrupts
;
139 * flags to compensate for differing chip variants
141 #define GXF_FORCE_TBI 0x0001 /* force TBI mode on */
142 #define GXF_DMA 0x0002 /* has DMA control registers */
143 #define GXF_ENABLE_MWI 0x0004 /* supports MWI burst mode */
144 #define GXF_OLD_REGS 0x0008 /* use old register mapping */
145 #define GXF_CSUM 0x0010 /* hardware checksum offload */
148 * TX Context definitions.
150 #define GX_TXCONTEXT_NONE 0
151 #define GX_TXCONTEXT_TCPIP 1
152 #define GX_TXCONTEXT_UDPIP 2