sys/dev/netif/gx/if_gxreg.h

   1 /*-
   2  * Copyright (c) 1999,2000,2001 Jonathan Lemon
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the author nor the names of any co-contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $FreeBSD: src/sys/dev/gx/if_gxreg.h,v 1.1.2.1 2001/11/15 03:09:23 jlemon Exp $
  30  * $DragonFly: src/sys/dev/netif/gx/Attic/if_gxreg.h,v 1.4 2006/08/01 18:03:53 swildner Exp $
  31  */
  32
  33 /*
  34  * chip register offsets. These are memory mapped registers
  35  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
  36  * Each register must be accessed using 32 bit operations.
  37  */
  38
  39 #define GX_CTRL                 0x0000  /* control register */
  40 #define GX_STATUS               0x0008  /* status register */
  41 #define GX_EEPROM_CTRL          0x0010  /* EEPROM/Flash control/data */
  42 #define GX_CTRL_EXT             0x0018  /* extended device control */
  43 #define GX_MDIC                 0x0020  /* MDI control */
  44 #define GX_FLOW_CTRL_BASE       0x0028  /* flow control address low/high */
  45 #define GX_FLOW_CTRL_TYPE       0x0030  /* flow control type */
  46 #define GX_VET                  0x0038  /* VLAN ethertype */
  47 #define GX_RX_ADDR_BASE         0x0040  /* 16 pairs of receive address low/high */
  48
  49 #define GX_INT_READ             0x00C0  /* read interrupts */
  50 #define GX_INT_FORCE            0x00C8  /* force an interrupt */
  51 #define GX_INT_MASK_SET         0x00D0  /* interrupt mask set/read */
  52 #define GX_INT_MASK_CLR         0x00D8  /* interrupt mask clear */
  53
  54 #define GX_RX_CONTROL           0x0100  /* RX control */
  55
  56 /* 82542 and older 82543 chips */
  57 #define GX_RX_OLD_INTR_DELAY    0x0108  /* RX delay timer */
  58 #define GX_RX_OLD_RING_BASE     0x0110  /* RX descriptor base address */
  59 #define GX_RX_OLD_RING_LEN      0x0118  /* RX descriptor length */
  60 #define GX_RX_OLD_RING_HEAD     0x0120  /* RX descriptor head */
  61 #define GX_RX_OLD_RING_TAIL     0x0128  /* RX descriptor tail */
  62
  63 /* 82542 and older 82543 chips */
  64 #define GX_OLD_FCRTH            0x0160  /* flow control rcv threshhold high */
  65 #define GX_OLD_FCRTL            0x0168  /* flow control rcv threshhold low */
  66
  67 #define GX_FCTTV                0x0170  /* flow control xmit timer value */
  68 #define GX_TX_CONFIG            0x0178  /* xmit configuration (tbi mode) */
  69 #define GX_RX_CONFIG            0x0180  /* recv configuration word */
  70
  71 #define GX_MULTICAST_BASE       0x0200  /* multicast table array base */
  72
  73 #define GX_TX_CONTROL           0x0400  /* TX control */
  74 #define GX_TX_IPG               0x0410  /* TX interpacket gap */
  75
  76 /* 82542 and older 82543 chips */
  77 #define GX_TX_OLD_RING_BASE     0x0420  /* TX descriptor base address */
  78 #define GX_TX_OLD_RING_LEN      0x0428  /* TX descriptor length */
  79 #define GX_TX_OLD_RING_HEAD     0x0430  /* TX descriptor head */
  80 #define GX_TX_OLD_RING_TAIL     0x0438  /* TX descriptor tail */
  81 #define GX_TX_OLD_INTR_DELAY    0x0440  /* TX interrupt delay value */
  82
  83 #define GX_TBT                  0x0448  /* TX burst timer */
  84 #define GX_AIT                  0x0458  /* adaptive IFS throttle */
  85
  86 #define GX_VFTA_BASE            0x0600  /* VLAN filter table array base */
  87
  88 #define GX_PKT_BUFFER_ALLOC     0x1000  /* Packet buffer allocation */
  89 #define GX_ERT                  0x2000  /* Early receive threshold */
  90 #define GX_RX_OLD_DMA_CTRL      0x2028  /* RX descriptor control */
  91
  92 /* newer 82543 chips */
  93 #define GX_FCRTH                0x2160  /* flow control rcv threshhold high */
  94 #define GX_FCRTL                0x2168  /* flow control rcv threshhold low */
  95
  96 /* newer 82543 chips */
  97 #define GX_RX_RING_BASE         0x2800  /* RX descriptor base address */
  98 #define GX_RX_RING_LEN          0x2808  /* RX descriptor length */
  99 #define GX_RX_RING_HEAD         0x2810  /* RX descriptor head */
 100 #define GX_RX_RING_TAIL         0x2818  /* RX descriptor tail */
 101 #define GX_RX_INTR_DELAY        0x2820  /* RX delay timer */
 102 #define GX_RX_DMA_CTRL          0x2820  /* RX descriptor control */
 103
 104 #define GX_EARLY_TX_THRESH      0x3000  /* early transmit threshold */
 105 #define GX_TX_OLD_DMA_CTRL      0x3028  /* TX descriptor control */
 106
 107 /* newer 82543 chips */
 108 #define GX_TX_RING_BASE         0x3800  /* TX descriptor base address */
 109 #define GX_TX_RING_LEN          0x3808  /* TX descriptor length */
 110 #define GX_TX_RING_HEAD         0x3810  /* TX descriptor head */
 111 #define GX_TX_RING_TAIL         0x3818  /* TX descriptor tail */
 112 #define GX_TX_INTR_DELAY        0x3820  /* TX interrupt delay value */
 113 #define GX_TX_DMA_CTRL          0x3828  /* TX descriptor control */
 114
 115 #define GX_CRCERRS              0x4000  /* CRC error count */
 116 #define GX_ALGNERRC             0x4004  /* alignment error count */
 117 #define GX_SYMERRS              0x4008  /* symbol error count */
 118 #define GX_RXERRC               0x400C  /* RX error count */
 119 #define GX_MPC                  0x4010  /* missed packets count */
 120 #define GX_SCC                  0x4014  /* single collision count */
 121 #define GX_ECOL                 0x4018  /* excessive collision count */
 122 #define GX_MCC                  0x401C  /* multiple collision count */
 123 #define GX_LATECOL              0x4020  /* late collision count */
 124 #define GX_COLC                 0x4020  /* collision count */
 125 #define GX_TUC                  0x402C  /* transmit underrun count */
 126 #define GX_DC                   0x4030  /* defer count */
 127 #define GX_TNCRS                0x4034  /* transmit - no CRS */
 128 #define GX_SEC                  0x4038  /* sequence error count */
 129 #define GX_CEXTERR              0x403C  /* carrier extension error count */
 130 #define GX_RLEC                 0x4040  /* receive length error count */
 131 #define GX_RDMAUC               0x4044  /* receive DMA underrun count */
 132 #define GX_XONRXC               0x4048  /* XON received count */
 133 #define GX_XONTXC               0x404C  /* XON transmitted count */
 134 #define GX_XOFFRXC              0x4050  /* XOFF received count */
 135 #define GX_XOFFTXC              0x4054  /* XOFF transmitted count */
 136 #define GX_FCRUC                0x4058  /* FC received unsupported count */
 137 #define GX_PRC64                0x405C  /* packets rcvd (64 bytes) */
 138 #define GX_PRC127               0x4060  /* packets rcvd (65 - 127 bytes) */
 139 #define GX_PRC255               0x4064  /* packets rcvd (128 - 255 bytes) */
 140 #define GX_PRC511               0x4068  /* packets rcvd (256 - 511 bytes) */
 141 #define GX_PRC1023              0x406C  /* packets rcvd (512 - 1023 bytes) */
 142 #define GX_PRC1522              0x4070  /* packets rcvd (1023 - 1522 bytes) */
 143 #define GX_GPRC                 0x4074  /* good packets received */
 144 #define GX_BPRC                 0x4078  /* broadcast packets received */
 145 #define GX_MPRC                 0x407C  /* multicast packets received */
 146 #define GX_GPTC                 0x4080  /* good packets transmitted */
 147 #define GX_GORC                 0x4088  /* good octets received (low/high) */
 148 #define GX_GOTC                 0x4090  /* good octets transmitted (low/high) */
 149 #define GX_RNBC                 0x40A0  /* receive no buffers count */
 150 #define GX_RUC                  0x40A4  /* receive undersize count */
 151 #define GX_RFC                  0x40A8  /* receive fragment count */
 152 #define GX_ROC                  0x40AC  /* receive oversize count */
 153 #define GX_RJC                  0x40B0  /* receive jabber count */
 154 #define GX_TOR                  0x40C0  /* total octets received (low/high) */
 155 #define GX_TOT                  0x40C8  /* total octets transmitted (low/high) */
 156 #define GX_TPR                  0x40D0  /* total packets received */
 157 #define GX_TPT                  0x40D4  /* total packets transmitted */
 158 #define GX_PTC64                0x40D8  /* packets transmitted (64 B) */
 159 #define GX_PTC127               0x40DC  /* packets xmitted (65 - 127 B) */
 160 #define GX_PTC255               0x40E0  /* packets xmitted (128 - 255 B) */
 161 #define GX_PTC511               0x40E4  /* packets xmitted (256 - 511 B) */
 162 #define GX_PTC1023              0x40E8  /* packets xmitted (512 - 1023 B) */
 163 #define GX_PTC1522              0x40EC  /* packets xmitted (1023 - 1522 B) */
 164 #define GX_MPTC                 0x40F0  /* multicast packets transmitted */
 165 #define GX_BPTC                 0x40F4  /* broadcast packets transmitted */
 166 #define GX_TSCTC                0x40F8  /* TCP segmentation context xmitted */
 167 #define GX_TSCTFC               0x40FC  /* TCP segmentation context fail */
 168
 169 #define GX_RX_CSUM_CONTROL      0x5000  /* receive checksum control */
 170
 171 #define GX_RDFH                 0x8000  /* RX data fifo head */
 172 #define GX_RDFT                 0x8008  /* RX data fifo tail */
 173 #define GX_TDFH                 0x8010  /* TX data fifo head */
 174 #define GX_TDFT                 0x8018  /* TX data fifo tail */
 175
 176 #define GX_RBM_BASE             0x10000 /* packet buffer memory */
 177
 178 /* GX_RX_CSUM_CONTROL */
 179 #define GX_CSUM_START_MASK      0x000ff
 180 #define GX_CSUM_IP              0x00100
 181 #define GX_CSUM_TCP             0x00200
 182
 183 /* GX_CTRL register */
 184 #define GX_CTRL_DUPLEX          0x00000001      /* full duplex */
 185 #define GX_CTRL_BIGENDIAN       0x00000002      /* 1 == big endian */
 186 #define GX_CTRL_PCI_PRIORITY    0x00000004      /* 1 == fairness */
 187 #define GX_CTRL_LINK_RESET      0x00000008
 188 #define GX_CTRL_TEST_MODE       0x00000010
 189 #define GX_CTRL_AUTOSPEED       0x00000020
 190 #define GX_CTRL_SET_LINK_UP     0x00000040
 191 #define GX_CTRL_INVERT_LOS      0x00000080      /* invert loss of signal */
 192 #define GX_CTRL_SPEEDMASK       0x00000300      /* 2 bits */
 193 #define GX_CTRL_FORCESPEED      0x00000800
 194 #define GX_CTRL_FORCEDUPLEX     0x00001000
 195 #define GX_CTRL_GPIO_0          0x00040000      /* Software defined pin #0 */
 196 #define GX_CTRL_GPIO_1          0x00080000      /* Software defined pin #1 */
 197 #define GX_CTRL_GPIO_2          0x00100000      /* Software defined pin #2 */
 198 #define GX_CTRL_GPIO_3          0x00200000      /* Software defined pin #3 */
 199 #define GX_CTRL_GPIO_DIR_0      0x00400000      /* Pin is Input(0)/Output(1) */
 200 #define GX_CTRL_GPIO_DIR_1      0x00800000      /* Pin is Input(0)/Output(1) */
 201 #define GX_CTRL_GPIO_DIR_2      0x01000000      /* Pin is Input(0)/Output(1) */
 202 #define GX_CTRL_GPIO_DIR_3      0x02000000      /* Pin is Input(0)/Output(1) */
 203 #define GX_CTRL_DEVICE_RESET    0x04000000
 204 #define GX_CTRL_RX_FLOWCTRL     0x08000000      /* RX flowcontrol enable */
 205 #define GX_CTRL_TX_FLOWCTRL     0x10000000      /* TX flowcontrol enable */
 206 #define GX_CTRL_VLAN_ENABLE     0x40000000
 207
 208 /* GX_STATUS register */
 209 #define GX_STAT_DUPLEX          0x00000001
 210 #define GX_STAT_LINKUP          0x00000002
 211 #define GX_STAT_XMITCLK_OK      0x00000004
 212 #define GX_STAT_RECVCLK_OK      0x00000008
 213 #define GX_STAT_XMIT_OFF        0x00000010
 214 #define GX_STAT_TBIMODE         0x00000020
 215 #define GX_STAT_SPEED_MASK      0x000000C0      /* 2 bits, not valid w/TBI */
 216 #define GX_STAT_AUTOSPEED_MASK  0x00000300      /* 2 bits, not valid w/TBI */
 217 #define GX_STAT_MTXCLK_OK       0x00000400
 218 #define GX_STAT_PCI66           0x00000800
 219 #define GX_STAT_BUS64           0x00001000
 220
 221 #define GX_SPEED_10MB           0x00000000
 222 #define GX_SPEED_100MB          0x00000040
 223 #define GX_SPEED_1000MB         0x00000080
 224
 225 /* GX_EEPROM_CTRL register */
 226 #define GX_EE_CLOCK             0x0001          /* software clock */
 227 #define GX_EE_SELECT            0x0002          /* chip select */
 228 #define GX_EE_DATA_IN           0x0004
 229 #define GX_EE_DATA_OUT          0x0008
 230 #define GX_EE_FLASH_CTRL        0x0030          /* 0x02 == enable writes */
 231
 232 /* serial EEPROM opcodes */
 233 #define GX_EE_OPC_WRITE         0x5
 234 #define GX_EE_OPC_READ          0x6
 235 #define GX_EE_OPC_ERASE         0x7
 236
 237 #define GX_EE_OPC_SIZE          3               /* bits of opcode */
 238 #define GX_EE_ADDR_SIZE         6               /* bits of address */
 239
 240 /* EEPROM map offsets */
 241 #define GX_EEMAP_MAC            0x00            /* station address (6 bytes) */
 242 #define GX_EEMAP_INIT1          0x0A            /* init control (2 bytes) */
 243
 244 /* GX_CTRL_EXT register */
 245 #define GX_CTRLX_GPIO_4         0x00000010      /* Software defined pin #4 */
 246 #define GX_CTRLX_GPIO_5         0x00000020      /* Software defined pin #5 */
 247 #define GX_CTRLX_GPIO_6         0x00000040      /* Software defined pin #6 */
 248 #define GX_CTRLX_GPIO_7         0x00000080      /* Software defined pin #7 */
 249 #define GX_CTRLX_GPIO_DIR_4     0x00000100      /* Pin is Input(0)/Output(1) */
 250 #define GX_CTRLX_GPIO_DIR_5     0x00000200      /* Pin is Input(0)/Output(1) */
 251 #define GX_CTRLX_GPIO_DIR_6     0x00000400      /* Pin is Input(0)/Output(1) */
 252 #define GX_CTRLX_GPIO_DIR_7     0x00000800      /* Pin is Input(0)/Output(1) */
 253 #define GX_CTRLX_EEPROM_RESET   0x00002000      /* PCI_RST type EEPROM reset */
 254 #define GX_CTRLX_SPEED_BYPASS   0x00008000      /* use CTRL.SPEED setting */
 255
 256 /*
 257  * Defines for MII/GMII PHY.
 258  *
 259  * GPIO bits 0-3 are controlled by GX_CTRL, 4-7 by GX_CTRL_EXT.
 260  */
 261 #define GX_CTRL_GPIO_DIR        (GX_CTRL_GPIO_DIR_3)
 262 #define GX_CTRL_GPIO_DIR_MASK   (GX_CTRL_GPIO_DIR_0 | GX_CTRL_GPIO_DIR_1 | \
 263                                  GX_CTRL_GPIO_DIR_2 | GX_CTRL_GPIO_DIR_3)
 264 #define GX_CTRL_PHY_IO          GX_CTRL_GPIO_2
 265 #define GX_CTRL_PHY_IO_DIR      GX_CTRL_GPIO_DIR_2
 266 #define GX_CTRL_PHY_CLK         GX_CTRL_GPIO_3
 267
 268 #define GX_CTRLX_GPIO_DIR       (GX_CTRLX_GPIO_DIR_4)
 269 #define GX_CTRLX_GPIO_DIR_MASK  (GX_CTRLX_GPIO_DIR_4 | GX_CTRLX_GPIO_DIR_5 | \
 270                                  GX_CTRLX_GPIO_DIR_6 | GX_CTRLX_GPIO_DIR_7)
 271 #define GX_CTRLX_PHY_RESET      GX_CTRLX_GPIO_4
 272
 273 #define GX_PHY_PREAMBLE         0xffffffff
 274 #define GX_PHY_PREAMBLE_LEN     32
 275 #define GX_PHY_SOF              0x01
 276 #define GX_PHY_TURNAROUND       0x02
 277 #define GX_PHY_OP_WRITE 0x01
 278 #define GX_PHY_OP_READ          0x02
 279 #define GX_PHY_READ_LEN         14
 280 #define GX_PHY_WRITE_LEN        32
 281
 282 /* GX_RX_ADDR registers */
 283 #define GX_RA_VALID             0x80000000
 284
 285 /* GX_TX_CONFIG register */
 286 #define GX_TXCFG_AUTONEG        0x80000000
 287 #define GX_TXCFG_SWCONFIG       0x80000000
 288
 289 /* GX_RX_CONFIG register */
 290 #define GX_RXCFG_INVALID        0x08000000
 291
 292 /* GX_RX_CONTROL register */
 293 #define GX_RXC_RESET            0x00000001
 294 #define GX_RXC_ENABLE           0x00000002
 295 #define GX_RXC_STORE_BAD_PKT    0x00000004
 296 #define GX_RXC_UNI_PROMISC      0x00000008
 297 #define GX_RXC_MULTI_PROMISC    0x00000010
 298 #define GX_RXC_LONG_PKT_ENABLE  0x00000020
 299 #define GX_RXC_LOOPBACK         0x000000C0
 300 #define GX_RXC_RX_THOLD_MASK    0x00000300
 301 #define GX_RXC_MCAST_OFF_MASK   0x00003000
 302 #define GX_RXC_BCAST_ACCEPT     0x00008000
 303 #define GX_RXC_RX_BSIZE_MASK    0x00030000
 304 #define GX_RXC_VLAN_ENABLE      0x00040000
 305 #define GX_RXC_CFI_ENABLE       0x00080000      /* canonical form enable */
 306 #define GX_RXC_CFI              0x00100000
 307 #define GX_RXC_DISCARD_PAUSE    0x00400000
 308 #define GX_RXC_PASS_MAC         0x00800000
 309 #define GX_RXC_RX_BSIZE_SCALE   0x02000000      /* multiply BSIZE by 16 */
 310 #define GX_RXC_STRIP_ETHERCRC   0x04000000
 311
 312 /* bits for GX_RXC_RX_THOLD */
 313 #define GX_RXC_RX_THOLD_HALF    0x00000000
 314 #define GX_RXC_RX_THOLD_QUARTER 0x00000100
 315 #define GX_RXC_RX_THOLD_EIGHTH  0x00000200
 316
 317 /* bits for GX_RXC_RX_BSIZE_MASK */
 318 #define GX_RXC_RX_BSIZE_2K      0x00000000
 319 #define GX_RXC_RX_BSIZE_1K      0x00010000
 320 #define GX_RXC_RX_BSIZE_512     0x00020000
 321 #define GX_RXC_RX_BSIZE_256     0x00030000
 322
 323 /* GX_TX_CONTROL register */
 324 #define GX_TXC_RESET            0x00000001
 325 #define GX_TXC_ENABLE           0x00000002
 326 #define GX_TXC_PAD_SHORT_PKTS   0x00000008
 327 #define GX_TXC_COLL_RETRY_MASK  0x00000FF0
 328 #define GX_TXC_COLL_TIME_MASK   0x003FF000
 329 #define GX_TXC_XMIT_XOFF        0x00400000
 330 #define GX_TXC_PKT_BURST_ENABLE 0x00800000
 331 #define GX_TXC_REXMT_LATE_COLL  0x01000000
 332 #define GX_TXC_NO_REXMT_UNDERRN 0x02000000
 333
 334 /* bits for GX_TXC_COLL_RETRY_MASK */
 335 #define GX_TXC_COLL_RETRY_16    0x000000F0      /* 16 attempts at retransmit */
 336
 337 /* bits for GX_TXC_COLL_TIME_MASK */
 338 #define GX_TXC_COLL_TIME_HDX    0x00200000
 339 #define GX_TXC_COLL_TIME_FDX    0x00040000
 340
 341 /* GX_INT bits */
 342 #define GX_INT_XMIT_DONE        0x00000001
 343 #define GX_INT_XMIT_EMPTY       0x00000002
 344 #define GX_INT_LINK_CHANGE      0x00000004
 345 #define GX_INT_RCV_SEQ_ERR      0x00000008
 346 #define GX_INT_RCV_THOLD        0x00000010
 347 #define GX_INT_RCV_OVERRUN      0x00000040
 348 #define GX_INT_RCV_TIMER        0x00000080
 349 #define GX_INT_MDIO_DONE        0x00000200
 350 #define GX_INT_C_SETS           0x00000400
 351 #define GX_INT_GPI_MASK         0x00007800
 352
 353 #define GX_INT_ALL \
 354         (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY | GX_INT_LINK_CHANGE | \
 355         GX_INT_RCV_SEQ_ERR | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN | \
 356         GX_INT_RCV_TIMER | GX_INT_MDIO_DONE | GX_INT_C_SETS | GX_INT_GPI_MASK)
 357
 358 #if 0
 359 #define GX_INT_WANTED \
 360         (GX_INT_XMIT_DONE | /*GX_INT_XMIT_EMPTY |*/ GX_INT_LINK_CHANGE | \
 361         GX_INT_RCV_SEQ_ERR | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN | \
 362         GX_INT_RCV_TIMER | GX_INT_C_SETS)
 363 #else
 364 #define GX_INT_WANTED \
 365         (GX_INT_XMIT_DONE | GX_INT_RCV_THOLD | GX_INT_RCV_TIMER | \
 366         GX_INT_LINK_CHANGE)
 367 #endif
 368
 369 /* PCI space */
 370 #define GX_PCI_VENDOR_ID        0x0000
 371 #define GX_PCI_DEVICE_ID        0x0002
 372 #define GX_PCI_COMMAND          0x0004
 373 #define GX_PCI_STATUS           0x0006
 374 #define GX_PCI_REVID            0x0008
 375 #define GX_PCI_CLASSCODE        0x0009
 376 #define GX_PCI_CACHELEN         0x000C
 377 #define GX_PCI_LATENCY_TIMER    0x000D
 378 #define GX_PCI_HEADER_TYPE      0x000E
 379 #define GX_PCI_LOMEM            0x0010
 380 #define GX_PCI_SUBVEN_ID        0x002C
 381 #define GX_PCI_SYBSYS_ID        0x002E
 382 #define GX_PCI_BIOSROM          0x0030
 383 #define GX_PCI_CAPABILITY_PTR   0x0034
 384 #define GX_PCI_INTLINE          0x003C
 385 #define GX_PCI_INTPIN           0x003D
 386 #define GX_PCI_MINGNT           0x003E
 387 #define GX_PCI_MINLAT           0x003F
 388
 389 /* generic TX descriptor */
 390 struct gx_tx_desc {
 391         u_int64_t       :64;
 392         u_int16_t       :16;
 393         u_int8_t        :4,
 394                         tx_type:4,
 395         u_int8_t        :5,
 396                         tx_extended:1,
 397                         :2;
 398         u_int32_t       :32;
 399 };
 400
 401 /* legacy TX descriptor */
 402 struct gx_tx_desc_old {
 403         u_int64_t       tx_addr;
 404         u_int16_t       tx_len;
 405         u_int8_t        tx_csum_offset;
 406         u_int8_t        tx_command;
 407         u_int8_t        tx_status;
 408         u_int8_t        tx_csum_start;
 409         u_int16_t       tx_vlan;
 410 };
 411
 412 #define GX_TXOLD_END_OF_PKT     0x01    /* end of packet */
 413 #define GX_TXOLD_ETHER_CRC      0x02    /* insert ethernet CRC */
 414 #define GX_TXOLD_INSERT_CSUM    0x04    /* insert checksum */
 415 #define GX_TXOLD_REPORT_STATUS  0x08    /* report packet status */
 416 #define GX_TXOLD_REPORT_SENT    0x10    /* report packet sent */
 417 #define GX_TXOLD_EXTENSION      0x20    /* extended format */
 418 #define GX_TXOLD_VLAN_ENABLE    0x40    /* use vlan */
 419 #define GX_TXOLD_INT_DELAY      0x80    /* delay interrupt */
 420
 421 /* bits for tx_status */
 422 #define GX_TXSTAT_DONE          0x01    /* descriptor done */
 423 #define GX_TXSTAT_EXCESS_COLL   0x02    /* excess collisions */
 424 #define GX_TXSTAT_LATE_COLL     0x04    /* late collision */
 425 #define GX_TXSTAT_UNDERRUN      0x08    /* transmit underrun */
 426
 427 /* TX descriptor for checksum offloading context */
 428 struct gx_tx_desc_ctx {
 429         u_int8_t        tx_ip_csum_start;
 430         u_int8_t        tx_ip_csum_offset;
 431         u_int16_t       tx_ip_csum_end;
 432         u_int8_t        tx_tcp_csum_start;
 433         u_int8_t        tx_tcp_csum_offset;
 434         u_int16_t       tx_tcp_csum_end;
 435         u_int32_t       tx_len:20,
 436                         tx_type:4,
 437                         tx_command:8;
 438         u_int8_t        tx_status;
 439         u_int8_t        tx_hdrlen;
 440         u_int16_t       tx_mss;
 441 };
 442
 443 #define GX_TXCTX_TCP_PKT        0x01    /* its a TCP packet */
 444 #define GX_TXCTX_IP_PKT         0x02    /* its an IP packet */
 445 #define GX_TXCTX_TCP_SEG_EN     0x04    /* TCP segmentation enable */
 446 #define GX_TXCTX_REPORT_STATUS  0x08    /* report packet status */
 447 #define GX_TXCTX_EXTENSION      0x20    /* extended format */
 448 #define GX_TXCTX_INT_DELAY      0x80    /* delay interrupt */
 449
 450 /* TX descriptor for data */
 451 struct gx_tx_desc_data {
 452         u_int64_t       tx_addr;
 453         u_int32_t       tx_len:20,
 454                         tx_type:4,
 455                         tx_command:8;
 456         u_int8_t        tx_status;
 457         u_int8_t        tx_options;
 458         u_int16_t       tx_vlan;
 459 };
 460
 461 #define GX_TXTCP_END_OF_PKT     0x01    /* end of packet */
 462 #define GX_TXTCP_ETHER_CRC      0x02    /* insert ethernet CRC */
 463 #define GX_TXTCP_TCP_SEG_EN     0x04    /* TCP segmentation enable */
 464 #define GX_TXTCP_REPORT_STATUS  0x08    /* report packet status */
 465 #define GX_TXTCP_REPORT_SENT    0x10    /* report packet sent */
 466 #define GX_TXTCP_EXTENSION      0x20    /* extended format */
 467 #define GX_TXTCP_VLAN_ENABLE    0x40    /* use vlan */
 468 #define GX_TXTCP_INT_DELAY      0x80    /* delay interrupt */
 469
 470 /* bits for tx_options */
 471 #define GX_TXTCP_OPT_IP_CSUM    0x01    /* insert IP checksum */
 472 #define GX_TXTCP_OPT_TCP_CSUM   0x02    /* insert UDP/TCP checksum */
 473
 474 /* RX descriptor data structure */
 475 struct gx_rx_desc {
 476         u_int64_t       rx_addr;
 477         u_int16_t       rx_len;
 478         u_int16_t       rx_csum;
 479         u_int16_t       rx_staterr;     /* status + error fields */
 480         u_int16_t       rx_special;
 481 };
 482
 483 /* bits for rx_status portion of rx_staterr */
 484 #define GX_RXSTAT_COMPLETED     0x01    /* completed */
 485 #define GX_RXSTAT_END_OF_PACKET 0x02    /* end of this packet */
 486 #define GX_RXSTAT_IGNORE_CSUM   0x04    /* ignore computed checksum */
 487 #define GX_RXSTAT_VLAN_PKT      0x08    /* matched vlan */
 488 #define GX_RXSTAT_HAS_TCP_CSUM  0x20    /* TCP checksum calculated */
 489 #define GX_RXSTAT_HAS_IP_CSUM   0x40    /* IP checksum calculated */
 490 #define GX_RXSTAT_INEXACT_MATCH 0x80    /* must check address */
 491
 492 /* bits for rx_error portion of rx_staterr */
 493 #define GX_RXERR_CRC            0x0100  /* CRC or alignment error */
 494 #define GX_RXERR_SYMBOL         0x0200  /* symbol error */
 495 #define GX_RXERR_SEQUENCE       0x0400  /* sequence error */
 496 #define GX_RXERR_CARRIER        0x1000  /* carrier extension error */
 497 #define GX_RXERR_TCP_CSUM       0x2000  /* TCP/UDP checksum error */
 498 #define GX_RXERR_IP_CSUM        0x4000  /* IP checksum error */
 499 #define GX_RXERR_RX_DATA        0x8000  /* RX data error */
 500
 501 /* drop packet on these errors */
 502 #define GX_INPUT_ERROR \
 503         (GX_RXERR_CRC | GX_RXERR_SYMBOL | GX_RXERR_SEQUENCE | \
 504         GX_RXERR_CARRIER | GX_RXERR_RX_DATA)