sys/dev/netif/awi/awireg.h

   1 /* $NetBSD: awireg.h,v 1.3 2000/03/22 11:22:22 onoe Exp $ */
   2 /* $FreeBSD: src/sys/dev/awi/awireg.h,v 1.1.2.1 2000/12/07 04:09:39 imp Exp $ */
   3 /* $DragonFly: src/sys/dev/netif/awi/Attic/awireg.h,v 1.3 2004/07/27 14:25:56 joerg Exp $ */
   4
   5 /*-
   6  * Copyright (c) 1999 The NetBSD Foundation, Inc.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software contributed to The NetBSD Foundation
  10  * by Bill Sommerfeld
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *        This product includes software developed by the NetBSD
  23  *        Foundation, Inc. and its contributors.
  24  * 4. Neither the name of The NetBSD Foundation nor the names of its
  25  *    contributors may be used to endorse or promote products derived
  26  *    from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /*
  42  * The firmware typically loaded onto Am79C930-based 802.11 interfaces
  43  * uses a 32k or larger shared memory buffer to communicate with the
  44  * host.
  45  *
  46  * Depending on the exact configuration of the device, this buffer may
  47  * either be mapped into PCMCIA memory space, or accessible a byte at
  48  * a type through PCMCIA I/O space.
  49  *
  50  * This header defines offsets into this shared memory.
  51  */
  52
  53
  54 /*
  55  * LAST_TXD block.  5 32-bit words.
  56  *
  57  * There are five different output queues; this defines pointers to
  58  * the last completed descriptor for each one.
  59  */
  60 #define AWI_LAST_TXD            0x3ec   /* last completed Tx Descr */
  61
  62 #define AWI_LAST_BCAST_TXD              AWI_LAST_TXD+0
  63 #define AWI_LAST_MGT_TXD                AWI_LAST_TXD+4
  64 #define AWI_LAST_DATA_TXD               AWI_LAST_TXD+8
  65 #define AWI_LAST_PS_POLL_TXD            AWI_LAST_TXD+12
  66 #define AWI_LAST_CF_POLL_TXD            AWI_LAST_TXD+16
  67
  68 /*
  69  * Banner block; null-terminated string.
  70  *
  71  * The doc says it contains
  72  * "PCnetMobile:v2.00 mmddyy APIx.x\0"
  73  */
  74
  75 #define AWI_BANNER              0x480   /* Version string */
  76 #define AWI_BANNER_LEN                  0x20
  77
  78 /*
  79  * Command block protocol:
  80  * write command byte to a zero value.
  81  * write command status to a zero value.
  82  * write arguments to AWI_COMMAND_PARAMS
  83  * write command byte to a non-zero value.
  84  * wait for command status to be non-zero.
  85  * write command byte to a zero value.
  86  * write command status to a zero value.
  87  */
  88
  89 #define AWI_CMD                 0x4a0   /* Command opcode byte */
  90
  91 #define AWI_CMD_IDLE                    0x0
  92 #define AWI_CMD_NOP                     0x1
  93
  94 #define AWI_CMD_SET_MIB                 0x2
  95 #define AWI_CMD_GET_MIB                 0x9
  96
  97 #define AWI_CA_MIB_TYPE                 0x0
  98 #define AWI_CA_MIB_SIZE                 0x1
  99 #define AWI_CA_MIB_INDEX                0x2
 100 #define AWI_CA_MIB_DATA                 0x4
 101
 102 #define AWI_MIB_LOCAL                   0x0
 103 #define AWI_MIB_ADDR                    0x2
 104 #define AWI_MIB_MAC                     0x3
 105 #define AWI_MIB_STAT                    0x4
 106 #define AWI_MIB_MGT                     0x5
 107 #define AWI_MIB_DRVR                    0x6
 108 #define AWI_MIB_PHY                     0x7
 109
 110
 111 #define AWI_CMD_INIT_TX                 0x3
 112
 113 #define AWI_CA_TX_LEN                   0x14
 114 #define AWI_CA_TX_DATA                  0x0
 115 #define AWI_CA_TX_MGT                   0x4
 116 #define AWI_CA_TX_BCAST                 0x8
 117 #define AWI_CA_TX_PS                    0xc
 118 #define AWI_CA_TX_CF                    0x10
 119
 120 #define AWI_CMD_FLUSH_TX                0x4
 121
 122 #define AWI_CA_FTX_LEN                  0x5
 123 #define AWI_CA_FTX_DATA                 0x0
 124 #define AWI_CA_FTX_MGT                  0x1
 125 #define AWI_CA_FTX_BCAST                0x2
 126 #define AWI_CA_FTX_PS                   0x3
 127 #define AWI_CA_FTX_CF                   0x4
 128
 129 #define AWI_CMD_INIT_RX                 0x5
 130 #define AWI_CA_IRX_LEN                  0x8
 131 #define AWI_CA_IRX_DATA_DESC            0x0 /* return */
 132 #define AWI_CA_IRX_PS_DESC              0x4 /* return */
 133
 134 #define AWI_CMD_KILL_RX                 0x6
 135
 136 #define AWI_CMD_SLEEP                   0x7
 137 #define AWI_CA_SLEEP_LEN                0x8
 138 #define AWI_CA_WAKEUP                   0x0 /* uint64 */
 139
 140 #define AWI_CMD_WAKE                    0x8
 141
 142 #define AWI_CMD_SCAN                    0xa
 143 #define AWI_CA_SCAN_LEN                 0x6
 144 #define AWI_CA_SCAN_DURATION            0x0
 145 #define AWI_CA_SCAN_SET                 0x2
 146 #define AWI_CA_SCAN_PATTERN             0x3
 147 #define AWI_CA_SCAN_IDX                 0x4
 148 #define AWI_CA_SCAN_SUSP                0x5
 149
 150 #define AWI_CMD_SYNC                    0xb
 151 #define AWI_CA_SYNC_LEN                 0x14
 152 #define AWI_CA_SYNC_SET                 0x0
 153 #define AWI_CA_SYNC_PATTERN             0x1
 154 #define AWI_CA_SYNC_IDX                 0x2
 155 #define AWI_CA_SYNC_STARTBSS            0x3
 156 #define AWI_CA_SYNC_DWELL               0x4
 157 #define AWI_CA_SYNC_MBZ                 0x6
 158 #define AWI_CA_SYNC_TIMESTAMP           0x8
 159 #define AWI_CA_SYNC_REFTIME             0x10
 160
 161 #define AWI_CMD_RESUME                  0xc
 162
 163 #define AWI_CMD_STATUS                  0x4a1   /* Command status */
 164
 165 #define AWI_STAT_IDLE                   0x0
 166 #define AWI_STAT_OK                     0x1
 167 #define AWI_STAT_BADCMD                 0x2
 168 #define AWI_STAT_BADPARM                0x3
 169 #define AWI_STAT_NOTIMP                 0x4
 170 #define AWI_STAT_BADRES                 0x5
 171 #define AWI_STAT_BADMODE                0x6
 172
 173 #define AWI_ERROR_OFFSET        0x4a2   /* Offset to erroneous parameter */
 174 #define AWI_CMD_PARAMS          0x4a4   /* Command parameters */
 175
 176 #define AWI_CSB                 0x4f0   /* Control/Status block */
 177
 178 #define AWI_SELFTEST            0x4f0
 179
 180 #define AWI_SELFTEST_INIT               0x00 /* initial */
 181 #define AWI_SELFTEST_FIRMCKSUM          0x01 /* firmware cksum running */
 182 #define AWI_SELFTEST_HARDWARE           0x02 /* hardware tests running */
 183 #define AWI_SELFTEST_MIB                0x03 /* mib initializing */
 184
 185 #define AWI_SELFTEST_MIB_FAIL           0xfa
 186 #define AWI_SELFTEST_RADIO_FAIL         0xfb
 187 #define AWI_SELFTEST_MAC_FAIL           0xfc
 188 #define AWI_SELFTEST_FLASH_FAIL         0xfd
 189 #define AWI_SELFTEST_RAM_FAIL           0xfe
 190 #define AWI_SELFTEST_PASSED             0xff
 191
 192 #define AWI_STA_STATE           0x4f1
 193
 194 #define AWI_STA_AP                      0x20 /* acting as AP */
 195 #define AWI_STA_NOPSP                   0x10 /* Power Saving disabled */
 196 #define AWI_STA_DOZE                    0x08 /* about to go to sleep */
 197 #define AWI_STA_PSP                     0x04 /* enable PSP */
 198 #define AWI_STA_RXEN                    0x02 /* enable RX */
 199 #define AWI_STA_TXEN                    0x01 /* enable TX */
 200
 201 #define AWI_INTSTAT             0x4f3
 202 #define AWI_INTMASK             0x4f4
 203
 204 /* Bits in AWI_INTSTAT/AWI_INTMASK */
 205
 206 #define AWI_INT_GROGGY                  0x80 /* about to wake up */
 207 #define AWI_INT_CFP_ENDING              0x40 /* cont. free period ending */
 208 #define AWI_INT_DTIM                    0x20 /* beacon outgoing */
 209 #define AWI_INT_CFP_START               0x10 /* cont. free period starting */
 210 #define AWI_INT_SCAN_CMPLT              0x08 /* scan complete */
 211 #define AWI_INT_TX                      0x04 /* tx done */
 212 #define AWI_INT_RX                      0x02 /* rx done */
 213 #define AWI_INT_CMD                     0x01 /* cmd done */
 214
 215 /*
 216  * The following are used to implement a locking protocol between host
 217  * and MAC to protect the interrupt status and mask fields.
 218  *
 219  * driver: read lockout_host byte; if zero, set lockout_mac to non-zero,
 220  *      then reread lockout_host byte; if still zero, host has lock.
 221  *      if non-zero, clear lockout_mac, loop.
 222  */
 223
 224 #define AWI_LOCKOUT_MAC         0x4f5
 225 #define AWI_LOCKOUT_HOST        0x4f6
 226
 227
 228 #define AWI_INTSTAT2            0x4f7
 229 #define AWI_INTMASK2            0x4fd
 230
 231 /* Bits in AWI_INTSTAT2/INTMASK2 */
 232 #define AWI_INT2_RXMGT                  0x80            /* mgt/ps recieved */
 233 #define AWI_INT2_RXDATA                 0x40            /* data received */
 234 #define AWI_INT2_TXMGT                  0x10            /* mgt tx done */
 235 #define AWI_INT2_TXCF                   0x08            /* CF tx done */
 236 #define AWI_INT2_TXPS                   0x04            /* PS tx done */
 237 #define AWI_INT2_TXBCAST                0x02            /* Broadcast tx done */
 238 #define AWI_INT2_TXDATA                 0x01            /* data tx done */
 239
 240 #define AWI_DIS_PWRDN           0x4fc           /* disable powerdown if set */
 241
 242 #define AWI_DRIVERSTATE         0x4fe           /* driver state */
 243
 244 #define AWI_DRV_STATEMASK               0x0f
 245
 246 #define AWI_DRV_RESET                   0x0
 247 #define AWI_DRV_INFSY                   0x1 /* inf synced */
 248 #define AWI_DRV_ADHSC                   0x2 /* adhoc scan */
 249 #define AWI_DRV_ADHSY                   0x3 /* adhoc synced */
 250 #define AWI_DRV_INFSC                   0x4 /* inf scanning */
 251 #define AWI_DRV_INFAUTH                 0x5 /* inf authed */
 252 #define AWI_DRV_INFASSOC                0x6 /* inf associated */
 253 #define AWI_DRV_INFTOSS                 0x7 /* inf handoff */
 254 #define AWI_DRV_APNONE                  0x8 /* AP activity: no assoc */
 255 #define AWI_DRV_APQUIET                 0xc /* AP: >=one assoc, no traffic */
 256 #define AWI_DRV_APLO                    0xd /* AP: >=one assoc, light tfc */
 257 #define AWI_DRV_APMED                   0xe /* AP: >=one assoc, mod tfc */
 258 #define AWI_DRV_APHIGH                  0xf /* AP: >=one assoc, heavy tfc */
 259
 260 #define AWI_DRV_AUTORXLED               0x10
 261 #define AWI_DRV_AUTOTXLED               0x20
 262 #define AWI_DRV_RXLED                   0x40
 263 #define AWI_DRV_TXLED                   0x80
 264
 265 #define AWI_VBM                 0x500   /* Virtual Bit Map */
 266
 267 #define AWI_BUFFERS             0x600   /* Buffers */
 268 #define AWI_BUFFERS_END         0x6000
 269
 270 /*
 271  * Receive descriptors; there are a linked list of these chained
 272  * through the "NEXT" fields, starting from XXX
 273  */
 274
 275 #define AWI_RXD_SIZE                    0x18
 276
 277 #define AWI_RXD_NEXT                    0x4
 278 #define AWI_RXD_NEXT_LAST               0x80000000
 279
 280
 281 #define AWI_RXD_HOST_DESC_STATE         0x9
 282
 283 #define AWI_RXD_ST_OWN          0x80 /* host owns this */
 284 #define AWI_RXD_ST_CONSUMED     0x40 /* host is done */
 285 #define AWI_RXD_ST_LF           0x20 /* last frag */
 286 #define AWI_RXD_ST_CRC          0x08 /* CRC error */
 287 #define AWI_RXD_ST_OFLO         0x02 /* possible buffer overrun */
 288 #define AWI_RXD_ST_RXERROR      0x01 /* this frame is borked; discard me */
 289
 290 #define AWI_RXD_RSSI            0xa /* 1 byte: radio strength indicator */
 291 #define AWI_RXD_INDEX           0xb /* 1 byte: FH hop index or DS channel */
 292 #define AWI_RXD_LOCALTIME       0xc /* 4 bytes: local time of RX */
 293 #define AWI_RXD_START_FRAME     0x10 /* 4 bytes: ptr to first received byte */
 294 #define AWI_RXD_LEN             0x14 /* 2 bytes: rx len in bytes */
 295 #define AWI_RXD_RATE            0x16 /* 1 byte: rx rate in 1e5 bps */
 296
 297 /*
 298  * Transmit descriptors.
 299  */
 300
 301 #define AWI_TXD_SIZE            0x18
 302
 303 #define AWI_TXD_START           0x00 /* pointer to start of frame */
 304 #define AWI_TXD_NEXT            0x04 /* pointer to next TXD */
 305 #define AWI_TXD_LENGTH          0x08 /* length of frame */
 306 #define AWI_TXD_STATE           0x0a /* state */
 307
 308 #define AWI_TXD_ST_OWN          0x80 /* MAC owns this  */
 309 #define AWI_TXD_ST_DONE         0x40 /* MAC is done */
 310 #define AWI_TXD_ST_REJ          0x20 /* MAC doesn't like */
 311 #define AWI_TXD_ST_MSDU         0x10 /* MSDU timeout */
 312 #define AWI_TXD_ST_ABRT         0x08 /* TX aborted */
 313 #define AWI_TXD_ST_RETURNED     0x04 /* TX returned */
 314 #define AWI_TXD_ST_RETRY        0x02 /* TX retries exceeded */
 315 #define AWI_TXD_ST_ERROR        0x01 /* TX error */
 316
 317 #define AWI_TXD_RATE            0x0b /* rate */
 318
 319 #define AWI_RATE_1MBIT          10
 320 #define AWI_RATE_2MBIT          20
 321
 322 #define AWI_TXD_NDA             0x0c /* num DIFS attempts */
 323 #define AWI_TXD_NDF             0x0d /* num DIFS failures */
 324 #define AWI_TXD_NSA             0x0e /* num SIFS attempts */
 325 #define AWI_TXD_NSF             0x0f /* num SIFS failures */
 326
 327 #define AWI_TXD_NRA             0x14 /* num RTS attempts */
 328 #define AWI_TXD_NDTA            0x15 /* num data attempts */
 329 #define AWI_TXD_CTL             0x16 /* control */
 330
 331 #define AWI_TXD_CTL_PSN         0x80    /* preserve sequence in MAC frame */
 332 #define AWI_TXD_CTL_BURST       0x02    /* host is doing 802.11 fragmt. */
 333 #define AWI_TXD_CTL_FRAGS       0x01    /* override normal fragmentation */
 334
 335 /*
 336  * MIB structures.
 337  */
 338
 339 #define AWI_ESS_ID_SIZE                 (IEEE80211_NWID_LEN+2)
 340 struct awi_mib_local {
 341         u_int8_t        Fragmentation_Dis;
 342         u_int8_t        Add_PLCP_Dis;
 343         u_int8_t        MAC_Hdr_Prsv;
 344         u_int8_t        Rx_Mgmt_Que_En;
 345         u_int8_t        Re_Assembly_Dis;
 346         u_int8_t        Strip_PLCP_Dis;
 347         u_int8_t        Rx_Error_Dis;
 348         u_int8_t        Power_Saving_Mode_Dis;
 349         u_int8_t        Accept_All_Multicast_Dis;
 350         u_int8_t        Check_Seq_Cntl_Dis;
 351         u_int8_t        Flush_CFP_Queue_On_CF_End;
 352         u_int8_t        Network_Mode;
 353         u_int8_t        PWD_Lvl;
 354         u_int8_t        CFP_Mode;
 355         u_int8_t        Tx_Buffer_Offset[4];
 356         u_int8_t        Tx_Buffer_Size[4];
 357         u_int8_t        Rx_Buffer_Offset[4];
 358         u_int8_t        Rx_Buffer_Size[4];
 359         u_int8_t        Acting_as_AP;
 360         u_int8_t        Fill_CFP;
 361 };
 362
 363 struct awi_mib_mac {
 364         u_int8_t        _Reserved1[2];
 365         u_int8_t        _Reserved2[2];
 366         u_int8_t        aRTS_Threshold[2];
 367         u_int8_t        aCW_max[2];
 368         u_int8_t        aCW_min[2];
 369         u_int8_t        aPromiscuous_Enable;
 370         u_int8_t        _Reserved3;
 371         u_int8_t        _Reserved4[4];
 372         u_int8_t        aShort_Retry_Limit;
 373         u_int8_t        aLong_Retry_Limit;
 374         u_int8_t        aMax_Frame_Length[2];
 375         u_int8_t        aFragmentation_Threshold[2];
 376         u_int8_t        aProbe_Delay[2];
 377         u_int8_t        aMin_Probe_Response_Time[2];
 378         u_int8_t        aMax_Probe_Response_Time[2];
 379         u_int8_t        aMax_Transmit_MSDU_Lifetime[4];
 380         u_int8_t        aMax_Receive_MSDU_Lifetime[4];
 381         u_int8_t        aStation_Basic_Rate[2];
 382         u_int8_t        aDesired_ESS_ID[AWI_ESS_ID_SIZE];
 383 };
 384
 385 struct awi_mib_stat {
 386         u_int8_t        aTransmitted_MPDU_Count[4];
 387         u_int8_t        aTransmitted_MSDU_Count[4];
 388         u_int8_t        aOctets_Transmitted_Cnt[4];
 389         u_int8_t        aMulticast_Transmitted_Frame_Count[2];
 390         u_int8_t        aBroadcast_Transmitted_Frame_Count[2];
 391         u_int8_t        aFailed_Count[4];
 392         u_int8_t        aRetry_Count[4];
 393         u_int8_t        aMultiple_Retry_Count[4];
 394         u_int8_t        aFrame_Duplicate_Count[4];
 395         u_int8_t        aRTS_Success_Count[4];
 396         u_int8_t        aRTS_Failure_Count[4];
 397         u_int8_t        aACK_Failure_Count[4];
 398         u_int8_t        aReceived_Frame_Count [4];
 399         u_int8_t        aOctets_Received_Count[4];
 400         u_int8_t        aMulticast_Received_Count[2];
 401         u_int8_t        aBroadcast_Received_Count[2];
 402         u_int8_t        aFCS_Error_Count[4];
 403         u_int8_t        aError_Count[4];
 404         u_int8_t        aWEP_Undecryptable_Count[4];
 405 };
 406
 407 struct awi_mib_mgt {
 408         u_int8_t        aPower_Mgt_Mode;
 409         u_int8_t        aScan_Mode;
 410 #define AWI_SCAN_PASSIVE                0x00
 411 #define AWI_SCAN_ACTIVE                 0x01
 412 #define AWI_SCAN_BACKGROUND             0x02
 413         u_int8_t        aScan_State;
 414         u_int8_t        aDTIM_Period;
 415         u_int8_t        aATIM_Window[2];
 416         u_int8_t        Wep_Required;
 417         u_int8_t        _Reserved1;
 418         u_int8_t        aBeacon_Period[2];
 419         u_int8_t        aPassive_Scan_Duration[2];
 420         u_int8_t        aListen_Interval[2];
 421         u_int8_t        aMedium_Occupancy_Limit[2];
 422         u_int8_t        aMax_MPDU_Time[2];
 423         u_int8_t        aCFP_Max_Duration[2];
 424         u_int8_t        aCFP_Rate;
 425         u_int8_t        Do_Not_Receive_DTIMs;
 426         u_int8_t        aStation_ID[2];
 427         u_int8_t        aCurrent_BSS_ID[ETHER_ADDR_LEN];
 428         u_int8_t        aCurrent_ESS_ID[AWI_ESS_ID_SIZE];
 429 };
 430
 431 #define AWI_GROUP_ADDR_SIZE     4
 432 struct awi_mib_addr {
 433         u_int8_t        aMAC_Address[ETHER_ADDR_LEN];
 434         u_int8_t        aGroup_Addresses[AWI_GROUP_ADDR_SIZE][ETHER_ADDR_LEN];
 435         u_int8_t        aTransmit_Enable_Status;
 436         u_int8_t        _Reserved1;
 437 };
 438
 439 #define AWI_PWR_LEVEL_SIZE 4
 440 struct awi_mib_phy {
 441         u_int8_t        aSlot_Time[2];
 442         u_int8_t        aSIFS[2];
 443         u_int8_t        aMPDU_Maximum[2];
 444         u_int8_t        aHop_Time[2];
 445         u_int8_t        aSuprt_Data_Rates[4];
 446         u_int8_t        aCurrent_Reg_Domain;
 447 #define AWI_REG_DOMAIN_US       0x10
 448 #define AWI_REG_DOMAIN_CA       0x20
 449 #define AWI_REG_DOMAIN_EU       0x30
 450 #define AWI_REG_DOMAIN_ES       0x31
 451 #define AWI_REG_DOMAIN_FR       0x32
 452 #define AWI_REG_DOMAIN_JP       0x40
 453         u_int8_t        aPreamble_Lngth;
 454         u_int8_t        aPLCP_Hdr_Lngth;
 455         u_int8_t        Pwr_Up_Time[AWI_PWR_LEVEL_SIZE][2];
 456         u_int8_t        IEEE_PHY_Type;
 457 #define AWI_PHY_TYPE_FH         1
 458 #define AWI_PHY_TYPE_DS         2
 459 #define AWI_PHY_TYPE_IR         3
 460         u_int8_t        RCR_33A_Bits[8];
 461 };
 462
 463 /* the first member must be matched with struct ifreq */
 464 struct ieee80211_nwkey {
 465         char            i_name[IFNAMSIZ];       /* if_xname, e.g. "wi0" */
 466         int             i_wepon;                /* wep enabled flag */
 467         int             i_defkid;               /* default encrypt key id */
 468         struct {
 469                 int             i_keylen;
 470                 u_int8_t        *i_keydat;
 471         }               i_key[IEEE80211_WEP_NKID];
 472 };
 473
 474 #define SIOCS80211NWKEY          _IOW('i', 232, struct ieee80211_nwkey)
 475 #define SIOCG80211NWKEY         _IOWR('i', 233, struct ieee80211_nwkey)
 476
 477 #define SIOCS80211NWID          _IOWR('i', 230, struct ifreq)
 478 #define SIOCG80211NWID          _IOWR('i', 231, struct ifreq)
 479
 480 struct ieee80211_nwid {
 481         u_int8_t        i_len;
 482         u_int8_t        i_nwid[IEEE80211_NWID_LEN];
 483 };