2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
27 #include "intel_drv.h"
30 * DOC: csr support for dmc
32 * Display Context Save and Restore (CSR) firmware support added from gen9
33 * onwards to drive newly added DMC (Display microcontroller) in display
34 * engine to save and restore the state of display engine when it enter into
35 * low-power state and comes back to normal.
37 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
38 * FW_LOADED, FW_FAILED.
40 * Once the firmware is written into the registers status will be moved from
41 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
42 * be moved to FW_FAILED.
45 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
47 MODULE_FIRMWARE(I915_CSR_SKL
);
50 * SKL CSR registers for DC5 and DC6
52 #define CSR_PROGRAM_BASE 0x80000
53 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
54 #define CSR_HTP_ADDR_SKL 0x00500034
55 #define CSR_SSP_BASE 0x8F074
56 #define CSR_HTP_SKL 0x8F004
57 #define CSR_LAST_WRITE 0x8F034
58 #define CSR_LAST_WRITE_VALUE 0xc003b400
59 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
60 #define CSR_MAX_FW_SIZE 0x2FFF
61 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
62 #define CSR_MMIO_START_RANGE 0x80000
63 #define CSR_MMIO_END_RANGE 0x8FFFF
65 struct intel_css_header
{
69 /* Includes the DMC specific header in dwords */
72 /* always value would be 0x10000 */
79 uint32_t module_vendor
;
81 /* in YYYYMMDD format */
84 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
91 uint32_t modulus_size
;
94 uint32_t exponent_size
;
97 uint32_t reserved1
[12];
103 uint32_t reserved2
[8];
106 uint32_t kernel_header_info
;
109 struct intel_fw_info
{
112 /* Stepping (A, B, C, ..., *). * is a wildcard */
115 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
122 struct intel_package_header
{
123 /* DMC container header length in dwords */
124 unsigned char header_len
;
126 /* always value would be 0x01 */
127 unsigned char header_ver
;
129 unsigned char reserved
[10];
131 /* Number of valid entries in the FWInfo array below */
132 uint32_t num_entries
;
134 struct intel_fw_info fw_info
[20];
137 struct intel_dmc_header
{
138 /* always value would be 0x40403E3E */
141 /* DMC binary header length */
142 unsigned char header_len
;
145 unsigned char header_ver
;
153 /* Firmware program size (excluding header) in dwords */
156 /* Major Minor version */
159 /* Number of valid MMIO cycles present. */
163 uint32_t mmioaddr
[8];
166 uint32_t mmiodata
[8];
169 unsigned char dfile
[32];
171 uint32_t reserved1
[2];
174 struct stepping_info
{
179 static const struct stepping_info skl_stepping_info
[] = {
180 {'A', '0'}, {'B', '0'}, {'C', '0'},
181 {'D', '0'}, {'E', '0'}, {'F', '0'},
182 {'G', '0'}, {'H', '0'}, {'I', '0'}
186 static char intel_get_stepping(struct drm_device
*dev
)
188 if (IS_SKYLAKE(dev
) && (dev
->pdev
->revision
<
189 ARRAY_SIZE(skl_stepping_info
)))
190 return skl_stepping_info
[dev
->pdev
->revision
].stepping
;
195 static char intel_get_substepping(struct drm_device
*dev
)
197 if (IS_SKYLAKE(dev
) && (dev
->pdev
->revision
<
198 ARRAY_SIZE(skl_stepping_info
)))
199 return skl_stepping_info
[dev
->pdev
->revision
].substepping
;
206 * intel_csr_load_status_get() - to get firmware loading status.
207 * @dev_priv: i915 device.
209 * This function helps to get the firmware loading status.
211 * Return: Firmware loading status.
213 enum csr_state
intel_csr_load_status_get(struct drm_i915_private
*dev_priv
)
215 enum csr_state state
;
217 mutex_lock(&dev_priv
->csr_lock
);
218 state
= dev_priv
->csr
.state
;
219 mutex_unlock(&dev_priv
->csr_lock
);
225 * intel_csr_load_status_set() - help to set firmware loading status.
226 * @dev_priv: i915 device.
227 * @state: enumeration of firmware loading status.
229 * Set the firmware loading status.
231 void intel_csr_load_status_set(struct drm_i915_private
*dev_priv
,
232 enum csr_state state
)
234 mutex_lock(&dev_priv
->csr_lock
);
235 dev_priv
->csr
.state
= state
;
236 mutex_unlock(&dev_priv
->csr_lock
);
240 * intel_csr_load_program() - write the firmware from memory to register.
243 * CSR firmware is read from a .bin file and kept in internal memory one time.
244 * Everytime display comes back from low power state this function is called to
245 * copy the firmware from internal memory to registers.
247 void intel_csr_load_program(struct drm_device
*dev
)
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 u32
*payload
= dev_priv
->csr
.dmc_payload
;
254 DRM_ERROR("No CSR support available for this platform\n");
258 mutex_lock(&dev_priv
->csr_lock
);
259 fw_size
= dev_priv
->csr
.dmc_fw_size
;
260 for (i
= 0; i
< fw_size
; i
++)
261 I915_WRITE(CSR_PROGRAM_BASE
+ i
* 4,
264 for (i
= 0; i
< dev_priv
->csr
.mmio_count
; i
++) {
265 I915_WRITE(dev_priv
->csr
.mmioaddr
[i
],
266 dev_priv
->csr
.mmiodata
[i
]);
269 dev_priv
->csr
.state
= FW_LOADED
;
270 mutex_unlock(&dev_priv
->csr_lock
);
274 static void finish_csr_load(const struct firmware
*fw
, void *context
)
276 struct drm_i915_private
*dev_priv
= context
;
277 struct drm_device
*dev
= dev_priv
->dev
;
278 struct intel_css_header
*css_header
;
279 struct intel_package_header
*package_header
;
280 struct intel_dmc_header
*dmc_header
;
281 struct intel_csr
*csr
= &dev_priv
->csr
;
282 char stepping
= intel_get_stepping(dev
);
283 char substepping
= intel_get_substepping(dev
);
284 uint32_t dmc_offset
= CSR_DEFAULT_FW_OFFSET
, readcount
= 0, nbytes
;
286 uint32_t *dmc_payload
;
287 bool fw_loaded
= false;
290 i915_firmware_load_error_print(csr
->fw_path
, 0);
294 if ((stepping
== -ENODATA
) || (substepping
== -ENODATA
)) {
295 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
299 /* Extract CSS Header information*/
300 css_header
= (struct intel_css_header
*)fw
->data
;
301 if (sizeof(struct intel_css_header
) !=
302 (css_header
->header_len
* 4)) {
303 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
304 (css_header
->header_len
* 4));
307 readcount
+= sizeof(struct intel_css_header
);
309 /* Extract Package Header information*/
310 package_header
= (struct intel_package_header
*)
311 &fw
->data
[readcount
];
312 if (sizeof(struct intel_package_header
) !=
313 (package_header
->header_len
* 4)) {
314 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
315 (package_header
->header_len
* 4));
318 readcount
+= sizeof(struct intel_package_header
);
320 /* Search for dmc_offset to find firware binary. */
321 for (i
= 0; i
< package_header
->num_entries
; i
++) {
322 if (package_header
->fw_info
[i
].substepping
== '*' &&
323 stepping
== package_header
->fw_info
[i
].stepping
) {
324 dmc_offset
= package_header
->fw_info
[i
].offset
;
326 } else if (stepping
== package_header
->fw_info
[i
].stepping
&&
327 substepping
== package_header
->fw_info
[i
].substepping
) {
328 dmc_offset
= package_header
->fw_info
[i
].offset
;
330 } else if (package_header
->fw_info
[i
].stepping
== '*' &&
331 package_header
->fw_info
[i
].substepping
== '*')
332 dmc_offset
= package_header
->fw_info
[i
].offset
;
334 if (dmc_offset
== CSR_DEFAULT_FW_OFFSET
) {
335 DRM_ERROR("Firmware not supported for %c stepping\n", stepping
);
338 readcount
+= dmc_offset
;
340 /* Extract dmc_header information. */
341 dmc_header
= (struct intel_dmc_header
*)&fw
->data
[readcount
];
342 if (sizeof(struct intel_dmc_header
) != (dmc_header
->header_len
)) {
343 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
344 (dmc_header
->header_len
));
347 readcount
+= sizeof(struct intel_dmc_header
);
349 /* Cache the dmc header info. */
350 if (dmc_header
->mmio_count
> ARRAY_SIZE(csr
->mmioaddr
)) {
351 DRM_ERROR("Firmware has wrong mmio count %u\n",
352 dmc_header
->mmio_count
);
355 csr
->mmio_count
= dmc_header
->mmio_count
;
356 for (i
= 0; i
< dmc_header
->mmio_count
; i
++) {
357 if (dmc_header
->mmioaddr
[i
] < CSR_MMIO_START_RANGE
||
358 dmc_header
->mmioaddr
[i
] > CSR_MMIO_END_RANGE
) {
359 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
360 dmc_header
->mmioaddr
[i
]);
363 csr
->mmioaddr
[i
] = dmc_header
->mmioaddr
[i
];
364 csr
->mmiodata
[i
] = dmc_header
->mmiodata
[i
];
367 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
368 nbytes
= dmc_header
->fw_size
* 4;
369 if (nbytes
> CSR_MAX_FW_SIZE
) {
370 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes
);
373 csr
->dmc_fw_size
= dmc_header
->fw_size
;
375 csr
->dmc_payload
= kmalloc(nbytes
, M_DRM
, M_WAITOK
);
376 if (!csr
->dmc_payload
) {
377 DRM_ERROR("Memory allocation failed for dmc payload\n");
381 dmc_payload
= csr
->dmc_payload
;
382 memcpy(dmc_payload
, &fw
->data
[readcount
], nbytes
);
384 /* load csr program during system boot, as needed for DC states */
385 intel_csr_load_program(dev
);
388 DRM_DEBUG_KMS("Finished loading %s\n", dev_priv
->csr
.fw_path
);
391 intel_runtime_pm_put(dev_priv
);
393 intel_csr_load_status_set(dev_priv
, FW_FAILED
);
395 release_firmware(fw
);
400 * intel_csr_ucode_init() - initialize the firmware loading.
403 * This function is called at the time of loading the display driver to read
404 * firmware from a .bin file and copied into a internal memory.
406 void intel_csr_ucode_init(struct drm_device
*dev
)
409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
410 struct intel_csr
*csr
= &dev_priv
->csr
;
417 csr
->fw_path
= I915_CSR_SKL
;
419 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
420 intel_csr_load_status_set(dev_priv
, FW_FAILED
);
424 DRM_DEBUG_KMS("Loading %s\n", csr
->fw_path
);
427 * Obtain a runtime pm reference, until CSR is loaded,
428 * to avoid entering runtime-suspend.
430 intel_runtime_pm_get(dev_priv
);
432 /* CSR supported for platform, load firmware */
433 ret
= request_firmware_nowait(THIS_MODULE
, true, csr
->fw_path
,
434 &dev_priv
->dev
->pdev
->dev
,
435 GFP_KERNEL
, dev_priv
,
438 i915_firmware_load_error_print(csr
->fw_path
, ret
);
439 intel_csr_load_status_set(dev_priv
, FW_FAILED
);
445 * intel_csr_ucode_fini() - unload the CSR firmware.
448 * Firmmware unloading includes freeing the internal momory and reset the
449 * firmware loading status.
451 void intel_csr_ucode_fini(struct drm_device
*dev
)
454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
459 intel_csr_load_status_set(dev_priv
, FW_FAILED
);
460 kfree(dev_priv
->csr
.dmc_payload
);
464 void assert_csr_loaded(struct drm_i915_private
*dev_priv
)
466 WARN(intel_csr_load_status_get(dev_priv
) != FW_LOADED
,
467 "CSR is not loaded.\n");
468 WARN(!I915_READ(CSR_PROGRAM_BASE
),
469 "CSR program storage start is NULL\n");
470 WARN(!I915_READ(CSR_SSP_BASE
), "CSR SSP Base Not fine\n");
471 WARN(!I915_READ(CSR_HTP_SKL
), "CSR HTP Not fine\n");