sys/dev/powermng/memtemp/memtemp_core.c

   1 /*
   2  * Copyright (c) 2015 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/bitops.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/sensors.h>
  42
  43 #include <bus/pci/pcivar.h>
  44 #include <bus/pci/pcireg.h>
  45 #include <bus/pci/pci_cfgreg.h>
  46
  47 #include "coremctl_if.h"
  48 #include "pcib_if.h"
  49
  50 #include <dev/misc/coremctl/coremctl_reg.h>
  51 #include <dev/misc/dimm/dimm.h>
  52
  53 struct memtemp_core_softc;
  54
  55 struct memtemp_core_dimm {
  56         TAILQ_ENTRY(memtemp_core_dimm)  dimm_link;
  57         struct ksensor                  dimm_sensor;
  58         struct memtemp_core_softc       *dimm_parent;
  59         int                             dimm_reg;
  60         uint32_t                        dimm_mask;
  61
  62         struct dimm_softc               *dimm_softc;
  63 };
  64
  65 struct memtemp_core_type {
  66         uint16_t        did;
  67         const char      *desc;
  68 };
  69
  70 struct memtemp_core_softc {
  71         device_t                        temp_dev;
  72         device_t                        temp_parent;
  73         TAILQ_HEAD(, memtemp_core_dimm) temp_dimm;
  74 };
  75
  76 static int      memtemp_core_probe(device_t);
  77 static int      memtemp_core_attach(device_t);
  78 static int      memtemp_core_detach(device_t);
  79
  80 static void     memtemp_core_chan_attach(struct memtemp_core_softc *, int);
  81 static void     memtemp_core_dimm_attach(struct memtemp_core_softc *,
  82                     int, int, int);
  83 static void     memtemp_core_sensor_task(void *);
  84
  85 static const struct memtemp_core_type memtemp_core_types[] = {
  86         { PCI_E3V3_MEMCTL_DID,
  87           "Intel E3 v3 memory thermal sensor" },
  88
  89         { PCI_COREV3_MEMCTL_DID,
  90           "Intel i3/i5/i7 Haswell memory thermal sensor" },
  91
  92         { 0, NULL } /* required last entry */
  93 };
  94
  95 static device_method_t memtemp_core_methods[] = {
  96         /* Device interface */
  97         DEVMETHOD(device_probe,         memtemp_core_probe),
  98         DEVMETHOD(device_attach,        memtemp_core_attach),
  99         DEVMETHOD(device_detach,        memtemp_core_detach),
 100         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 101         DEVMETHOD(device_suspend,       bus_generic_suspend),
 102         DEVMETHOD(device_resume,        bus_generic_resume),
 103         DEVMETHOD_END
 104 };
 105
 106 static driver_t memtemp_core_driver = {
 107         "memtemp",
 108         memtemp_core_methods,
 109         sizeof(struct memtemp_core_softc)
 110 };
 111 static devclass_t memtemp_devclass;
 112 DRIVER_MODULE(memtemp_core, coremctl, memtemp_core_driver, memtemp_devclass,
 113     NULL, NULL);
 114 MODULE_DEPEND(memtemp_core, pci, 1, 1, 1);
 115 MODULE_DEPEND(memtemp_core, coremctl, 1, 1, 1);
 116 MODULE_DEPEND(memtemp_core, dimm, 1, 1, 1);
 117
 118 static __inline uint32_t
 119 CSR_READ_4(struct memtemp_core_softc *sc, int ofs)
 120 {
 121         uint32_t val;
 122         int error;
 123
 124         error = COREMCTL_MCH_READ(sc->temp_parent, ofs, &val);
 125         KASSERT(!error, ("mch read failed"));
 126
 127         return val;
 128 }
 129
 130 static __inline void
 131 CSR_WRITE_4(struct memtemp_core_softc *sc, int ofs, uint32_t val)
 132 {
 133         int error;
 134
 135         error = COREMCTL_MCH_WRITE(sc->temp_parent, ofs, val);
 136         KASSERT(!error, ("mch write failed"));
 137 }
 138
 139 static int
 140 memtemp_core_probe(device_t dev)
 141 {
 142         const struct memtemp_core_type *t;
 143         uint16_t did;
 144
 145         if (pci_get_vendor(dev) != PCI_CORE_MEMCTL_VID)
 146                 return ENXIO;
 147
 148         did = pci_get_device(dev);
 149         for (t = memtemp_core_types; t->desc != NULL; ++t) {
 150                 if (t->did == did) {
 151                         device_set_desc(dev, t->desc);
 152                         return 0;
 153                 }
 154         }
 155         return ENXIO;
 156 }
 157
 158 static int
 159 memtemp_core_attach(device_t dev)
 160 {
 161         struct memtemp_core_softc *sc = device_get_softc(dev);
 162         int i;
 163
 164         sc->temp_dev = dev;
 165         sc->temp_parent = device_get_parent(dev);
 166         TAILQ_INIT(&sc->temp_dimm);
 167
 168         for (i = 0; i < PCI_CORE_MEMCTL_CHN_MAX; ++i)
 169                 memtemp_core_chan_attach(sc, i);
 170
 171         return 0;
 172 }
 173
 174 static void
 175 memtemp_core_chan_attach(struct memtemp_core_softc *sc, int chan)
 176 {
 177         int dimm_ch_reg, dimm_chtemp_reg;
 178         int dimma_id, dimmb_id;
 179         int size_a, size_b;
 180         uint32_t dimm_ch;
 181
 182         if (chan == 0) {
 183                 dimm_ch_reg = MCH_CORE_DIMM_CH0;
 184                 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH0;
 185         } else {
 186                 KASSERT(chan == 1, ("unsupport channel%d", chan));
 187                 dimm_ch_reg = MCH_CORE_DIMM_CH1;
 188                 dimm_chtemp_reg = MCH_CORE_DIMM_TEMP_CH1;
 189         }
 190
 191         dimm_ch = CSR_READ_4(sc, dimm_ch_reg);
 192
 193         size_a = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_A_SIZE);
 194         size_b = __SHIFTOUT(dimm_ch, MCH_CORE_DIMM_B_SIZE);
 195         if (size_a == 0 && size_b == 0)
 196                 return;
 197
 198         dimma_id = 0;
 199         dimmb_id = 1;
 200         if (dimm_ch & MCH_CORE_DIMM_A_SELECT) {
 201                 dimma_id = 1;
 202                 dimmb_id = 0;
 203         }
 204
 205         if (size_a != 0)
 206                 memtemp_core_dimm_attach(sc, chan, dimma_id, dimm_chtemp_reg);
 207         if (size_b != 0)
 208                 memtemp_core_dimm_attach(sc, chan, dimmb_id, dimm_chtemp_reg);
 209 }
 210
 211 static void
 212 memtemp_core_dimm_attach(struct memtemp_core_softc *sc, int chan, int dimm_id,
 213     int dimm_reg)
 214 {
 215         struct memtemp_core_dimm *dimm_sc;
 216         struct ksensor *sens;
 217
 218         dimm_sc = kmalloc(sizeof(*dimm_sc), M_DEVBUF, M_WAITOK | M_ZERO);
 219         dimm_sc->dimm_parent = sc;
 220         dimm_sc->dimm_reg = dimm_reg;
 221         if (dimm_id == 0) {
 222                 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM0;
 223         } else {
 224                 KASSERT(dimm_id == 1, ("unsupported DIMM%d", dimm_id));
 225                 dimm_sc->dimm_mask = MCH_CORE_DIMM_TEMP_DIMM1;
 226         }
 227
 228         dimm_sc->dimm_softc = dimm_create(0, chan, dimm_id);
 229
 230         sens = &dimm_sc->dimm_sensor;
 231         ksnprintf(sens->desc, sizeof(sens->desc), "chan%d DIMM%d temp",
 232             chan, dimm_id);
 233         sens->type = SENSOR_TEMP;
 234         sensor_set_unknown(sens);
 235         dimm_sensor_attach(dimm_sc->dimm_softc, sens);
 236         sensor_task_register(dimm_sc, memtemp_core_sensor_task, 5);
 237
 238         TAILQ_INSERT_TAIL(&sc->temp_dimm, dimm_sc, dimm_link);
 239 }
 240
 241 static int
 242 memtemp_core_detach(device_t dev)
 243 {
 244         struct memtemp_core_softc *sc = device_get_softc(dev);
 245         struct memtemp_core_dimm *dimm_sc;
 246
 247         while ((dimm_sc = TAILQ_FIRST(&sc->temp_dimm)) != NULL) {
 248                 TAILQ_REMOVE(&sc->temp_dimm, dimm_sc, dimm_link);
 249
 250                 sensor_task_unregister(dimm_sc);
 251                 dimm_sensor_detach(dimm_sc->dimm_softc, &dimm_sc->dimm_sensor);
 252                 dimm_destroy(dimm_sc->dimm_softc);
 253
 254                 kfree(dimm_sc, M_DEVBUF);
 255         }
 256         return 0;
 257 }
 258
 259 static void
 260 memtemp_core_sensor_task(void *xdimm_sc)
 261 {
 262         struct memtemp_core_dimm *dimm_sc = xdimm_sc;
 263         uint32_t val;
 264         int temp;
 265
 266         val = CSR_READ_4(dimm_sc->dimm_parent, dimm_sc->dimm_reg);
 267         temp = __SHIFTOUT(val, dimm_sc->dimm_mask);
 268
 269         dimm_sensor_temp(dimm_sc->dimm_softc, &dimm_sc->dimm_sensor, temp);
 270 }