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kernel - Fix auto port assignment collision in network code
[dragonfly.git] / sys / dev / netif / fxp / if_fxp.c
blob6c2c7dc9b7dacc565253ac6d45292b11634a4bec
1 /*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 */
30
31 /*
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33 */
34
35 #include "opt_ifpoll.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/mbuf.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
45
46 #include <net/if.h>
47 #include <net/ifq_var.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50
51 #include <net/bpf.h>
52 #include <sys/sockio.h>
53 #include <sys/bus.h>
54 #include <sys/rman.h>
55
56 #include <net/ethernet.h>
57 #include <net/if_arp.h>
58 #include <net/if_poll.h>
59
60 #include <vm/vm.h> /* for vtophys */
61 #include <vm/pmap.h> /* for vtophys */
62
63 #include <net/if_types.h>
64 #include <net/vlan/if_vlan_var.h>
65
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
68
69 #include "../mii_layer/mii.h"
70 #include "../mii_layer/miivar.h"
71
72 #include "if_fxpreg.h"
73 #include "if_fxpvar.h"
74 #include "rcvbundl.h"
75
76 #include "miibus_if.h"
77
78 /*
79 * NOTE! On the Alpha, we have an alignment constraint. The
80 * card DMAs the packet immediately following the RFA. However,
81 * the first thing in the packet is a 14-byte Ethernet header.
82 * This means that the packet is misaligned. To compensate,
83 * we actually offset the RFA 2 bytes into the cluster. This
84 * alignes the packet after the Ethernet header at a 32-bit
85 * boundary. HOWEVER! This means that the RFA is misaligned!
86 */
87 #define RFA_ALIGNMENT_FUDGE 2
88
89 /*
90 * Set initial transmit threshold at 64 (512 bytes). This is
91 * increased by 64 (512 bytes) at a time, to maximum of 192
92 * (1536 bytes), if an underrun occurs.
93 */
94 static int tx_threshold = 64;
95
96 /*
97 * The configuration byte map has several undefined fields which
98 * must be one or must be zero. Set up a template for these bits
99 * only, (assuming a 82557 chip) leaving the actual configuration
100 * to fxp_init.
101 *
102 * See struct fxp_cb_config for the bit definitions.
103 */
104 static u_char fxp_cb_config_template[] = {
105 0x0, 0x0, /* cb_status */
106 0x0, 0x0, /* cb_command */
107 0x0, 0x0, 0x0, 0x0, /* link_addr */
108 0x0, /* 0 */
109 0x0, /* 1 */
110 0x0, /* 2 */
111 0x0, /* 3 */
112 0x0, /* 4 */
113 0x0, /* 5 */
114 0x32, /* 6 */
115 0x0, /* 7 */
116 0x0, /* 8 */
117 0x0, /* 9 */
118 0x6, /* 10 */
119 0x0, /* 11 */
120 0x0, /* 12 */
121 0x0, /* 13 */
122 0xf2, /* 14 */
123 0x48, /* 15 */
124 0x0, /* 16 */
125 0x40, /* 17 */
126 0xf0, /* 18 */
127 0x0, /* 19 */
128 0x3f, /* 20 */
129 0x5 /* 21 */
130 };
131
132 struct fxp_ident {
133 u_int16_t devid;
134 int16_t revid; /* -1 matches anything */
135 char *name;
136 };
137
138 /*
139 * Claim various Intel PCI device identifiers for this driver. The
140 * sub-vendor and sub-device field are extensively used to identify
141 * particular variants, but we don't currently differentiate between
142 * them.
143 */
144 static struct fxp_ident fxp_ident_table[] = {
145 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
146 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
147 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
148 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
149 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
150 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
151 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
152 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
153 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
154 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
156 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
157 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
158 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
159 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
160 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
161 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
162 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
163 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
164 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
165 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
166 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
167 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
168 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
169 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
170 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
171 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
172 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
173 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
174 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
175 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
177 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
178 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
179 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
180 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
182 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
183 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
184 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
186 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
187 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
188 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
189 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
190 { 0, -1, NULL },
191 };
192
193 static int fxp_probe(device_t dev);
194 static int fxp_attach(device_t dev);
195 static int fxp_detach(device_t dev);
196 static int fxp_shutdown(device_t dev);
197 static int fxp_suspend(device_t dev);
198 static int fxp_resume(device_t dev);
199
200 static void fxp_intr(void *xsc);
201 static void fxp_intr_body(struct fxp_softc *sc,
202 u_int8_t statack, int count);
203
204 static void fxp_init(void *xsc);
205 static void fxp_tick(void *xsc);
206 static void fxp_powerstate_d0(device_t dev);
207 static void fxp_start(struct ifnet *ifp, struct ifaltq_subque *);
208 static void fxp_stop(struct fxp_softc *sc);
209 static void fxp_release(device_t dev);
210 static int fxp_ioctl(struct ifnet *ifp, u_long command,
211 caddr_t data, struct ucred *);
212 static void fxp_watchdog(struct ifnet *ifp);
213 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
214 static int fxp_mc_addrs(struct fxp_softc *sc);
215 static void fxp_mc_setup(struct fxp_softc *sc);
216 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
217 int autosize);
218 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
219 u_int16_t data);
220 static void fxp_autosize_eeprom(struct fxp_softc *sc);
221 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
222 int offset, int words);
223 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
224 int offset, int words);
225 static int fxp_ifmedia_upd(struct ifnet *ifp);
226 static void fxp_ifmedia_sts(struct ifnet *ifp,
227 struct ifmediareq *ifmr);
228 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
229 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
230 struct ifmediareq *ifmr);
231 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
232 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
233 int value);
234 static void fxp_load_ucode(struct fxp_softc *sc);
235 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
236 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
237 #ifdef IFPOLL_ENABLE
238 static void fxp_npoll(struct ifnet *, struct ifpoll_info *);
239 static void fxp_npoll_compat(struct ifnet *, void *, int);
240 #endif
241
242 static void fxp_lwcopy(volatile u_int32_t *src,
243 volatile u_int32_t *dst);
244 static void fxp_scb_wait(struct fxp_softc *sc);
245 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
246 static void fxp_dma_wait(volatile u_int16_t *status,
247 struct fxp_softc *sc);
248
249 static device_method_t fxp_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, fxp_probe),
252 DEVMETHOD(device_attach, fxp_attach),
253 DEVMETHOD(device_detach, fxp_detach),
254 DEVMETHOD(device_shutdown, fxp_shutdown),
255 DEVMETHOD(device_suspend, fxp_suspend),
256 DEVMETHOD(device_resume, fxp_resume),
257
258 /* MII interface */
259 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
260 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
261
262 DEVMETHOD_END
263 };
264
265 static driver_t fxp_driver = {
266 "fxp",
267 fxp_methods,
268 sizeof(struct fxp_softc),
269 };
270
271 static devclass_t fxp_devclass;
272
273 DECLARE_DUMMY_MODULE(if_fxp);
274 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
275 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, NULL, NULL);
276 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, NULL, NULL);
277 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
278
279 static int fxp_rnr;
280 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
281
282 /*
283 * Copy a 16-bit aligned 32-bit quantity.
284 */
285 static void
286 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
287 {
288 volatile u_int16_t *a = (volatile u_int16_t *)src;
289 volatile u_int16_t *b = (volatile u_int16_t *)dst;
290
291 b[0] = a[0];
292 b[1] = a[1];
293 }
294
295 /*
296 * Wait for the previous command to be accepted (but not necessarily
297 * completed).
298 */
299 static void
300 fxp_scb_wait(struct fxp_softc *sc)
301 {
302 int i = 10000;
303
304 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
305 DELAY(2);
306 if (i == 0) {
307 if_printf(&sc->arpcom.ac_if,
308 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
309 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
310 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
311 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
312 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
313 }
314 }
315
316 static void
317 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
318 {
319
320 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
322 fxp_scb_wait(sc);
323 }
324 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
325 }
326
327 static void
328 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
329 {
330 int i = 10000;
331
332 while (!(*status & FXP_CB_STATUS_C) && --i)
333 DELAY(2);
334 if (i == 0)
335 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
336 }
337
338 /*
339 * Return identification string if this is device is ours.
340 */
341 static int
342 fxp_probe(device_t dev)
343 {
344 u_int16_t devid;
345 u_int8_t revid;
346 struct fxp_ident *ident;
347
348 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
349 devid = pci_get_device(dev);
350 revid = pci_get_revid(dev);
351 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
352 if (ident->devid == devid &&
353 (ident->revid == revid || ident->revid == -1)) {
354 device_set_desc(dev, ident->name);
355 return (0);
356 }
357 }
358 }
359 return (ENXIO);
360 }
361
362 static void
363 fxp_powerstate_d0(device_t dev)
364 {
365 u_int32_t iobase, membase, irq;
366
367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
368 /* Save important PCI config data. */
369 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
370 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
371 irq = pci_read_config(dev, PCIR_INTLINE, 4);
372
373 /* Reset the power state. */
374 device_printf(dev, "chip is in D%d power mode "
375 "-- setting to D0\n", pci_get_powerstate(dev));
376
377 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
378
379 /* Restore PCI config data. */
380 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
381 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
382 pci_write_config(dev, PCIR_INTLINE, irq, 4);
383 }
384 }
385
386 static int
387 fxp_attach(device_t dev)
388 {
389 int error = 0;
390 struct fxp_softc *sc = device_get_softc(dev);
391 struct ifnet *ifp;
392 struct sysctl_ctx_list *ctx;
393 struct sysctl_oid *tree;
394 u_int32_t val;
395 u_int16_t data;
396 int i, rid, m1, m2, prefer_iomap;
397
398 callout_init(&sc->fxp_stat_timer);
399
400 /*
401 * Enable bus mastering. Enable memory space too, in case
402 * BIOS/Prom forgot about it.
403 */
404 pci_enable_busmaster(dev);
405 pci_enable_io(dev, SYS_RES_MEMORY);
406 val = pci_read_config(dev, PCIR_COMMAND, 2);
407
408 fxp_powerstate_d0(dev);
409
410 /*
411 * Figure out which we should try first - memory mapping or i/o mapping?
412 * We default to memory mapping. Then we accept an override from the
413 * command line. Then we check to see which one is enabled.
414 */
415 m1 = PCIM_CMD_MEMEN;
416 m2 = PCIM_CMD_PORTEN;
417 prefer_iomap = 0;
418 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
419 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
420 m1 = PCIM_CMD_PORTEN;
421 m2 = PCIM_CMD_MEMEN;
422 }
423
424 if (val & m1) {
425 sc->rtp =
426 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
427 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
428 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
429 RF_ACTIVE);
430 }
431 if (sc->mem == NULL && (val & m2)) {
432 sc->rtp =
433 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
434 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
435 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
436 RF_ACTIVE);
437 }
438
439 if (!sc->mem) {
440 device_printf(dev, "could not map device registers\n");
441 error = ENXIO;
442 goto fail;
443 }
444 if (bootverbose) {
445 device_printf(dev, "using %s space register mapping\n",
446 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
447 }
448
449 sc->sc_st = rman_get_bustag(sc->mem);
450 sc->sc_sh = rman_get_bushandle(sc->mem);
451
452 /*
453 * Allocate our interrupt.
454 */
455 rid = 0;
456 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
457 RF_SHAREABLE | RF_ACTIVE);
458 if (sc->irq == NULL) {
459 device_printf(dev, "could not map interrupt\n");
460 error = ENXIO;
461 goto fail;
462 }
463
464 /*
465 * Reset to a stable state.
466 */
467 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
468 DELAY(10);
469
470 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
471 M_DEVBUF, M_WAITOK | M_ZERO);
472
473 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
474 M_WAITOK | M_ZERO);
475
476 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
477
478 /*
479 * Pre-allocate our receive buffers.
480 */
481 for (i = 0; i < FXP_NRFABUFS; i++) {
482 if (fxp_add_rfabuf(sc, NULL) != 0) {
483 goto failmem;
484 }
485 }
486
487 /*
488 * Find out how large of an SEEPROM we have.
489 */
490 fxp_autosize_eeprom(sc);
491
492 /*
493 * Determine whether we must use the 503 serial interface.
494 */
495 fxp_read_eeprom(sc, &data, 6, 1);
496 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
497 (data & FXP_PHY_SERIAL_ONLY))
498 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
499
500 /*
501 * Create the sysctl tree
502 */
503 ctx = device_get_sysctl_ctx(dev);
504 tree = device_get_sysctl_tree(dev);
505 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
506 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
507 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
508 "FXP driver receive interrupt microcode bundling delay");
509 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
510 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
511 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
512 "FXP driver receive interrupt microcode bundle size limit");
513
514 /*
515 * Pull in device tunables.
516 */
517 sc->tunable_int_delay = TUNABLE_INT_DELAY;
518 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
519 resource_int_value(device_get_name(dev), device_get_unit(dev),
520 "int_delay", &sc->tunable_int_delay);
521 resource_int_value(device_get_name(dev), device_get_unit(dev),
522 "bundle_max", &sc->tunable_bundle_max);
523
524 /*
525 * Find out the chip revision; lump all 82557 revs together.
526 */
527 fxp_read_eeprom(sc, &data, 5, 1);
528 if ((data >> 8) == 1)
529 sc->revision = FXP_REV_82557;
530 else
531 sc->revision = pci_get_revid(dev);
532
533 /*
534 * Enable workarounds for certain chip revision deficiencies.
535 *
536 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
537 * some systems based a normal 82559 design, have a defect where
538 * the chip can cause a PCI protocol violation if it receives
539 * a CU_RESUME command when it is entering the IDLE state. The
540 * workaround is to disable Dynamic Standby Mode, so the chip never
541 * deasserts CLKRUN#, and always remains in an active state.
542 *
543 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
544 */
545 i = pci_get_device(dev);
546 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
547 sc->revision >= FXP_REV_82559_A0) {
548 fxp_read_eeprom(sc, &data, 10, 1);
549 if (data & 0x02) { /* STB enable */
550 u_int16_t cksum;
551 int i;
552
553 device_printf(dev,
554 "Disabling dynamic standby mode in EEPROM\n");
555 data &= ~0x02;
556 fxp_write_eeprom(sc, &data, 10, 1);
557 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
558 cksum = 0;
559 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
560 fxp_read_eeprom(sc, &data, i, 1);
561 cksum += data;
562 }
563 i = (1 << sc->eeprom_size) - 1;
564 cksum = 0xBABA - cksum;
565 fxp_read_eeprom(sc, &data, i, 1);
566 fxp_write_eeprom(sc, &cksum, i, 1);
567 device_printf(dev,
568 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
569 i, data, cksum);
570 #if 1
571 /*
572 * If the user elects to continue, try the software
573 * workaround, as it is better than nothing.
574 */
575 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
576 #endif
577 }
578 }
579
580 /*
581 * If we are not a 82557 chip, we can enable extended features.
582 */
583 if (sc->revision != FXP_REV_82557) {
584 /*
585 * If MWI is enabled in the PCI configuration, and there
586 * is a valid cacheline size (8 or 16 dwords), then tell
587 * the board to turn on MWI.
588 */
589 if (val & PCIM_CMD_MWRICEN &&
590 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
591 sc->flags |= FXP_FLAG_MWI_ENABLE;
592
593 /* turn on the extended TxCB feature */
594 sc->flags |= FXP_FLAG_EXT_TXCB;
595
596 /* enable reception of long frames for VLAN */
597 sc->flags |= FXP_FLAG_LONG_PKT_EN;
598 }
599
600 /*
601 * Read MAC address.
602 */
603 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
604 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
605 device_printf(dev, "10Mbps\n");
606 if (bootverbose) {
607 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
608 pci_get_vendor(dev), pci_get_device(dev),
609 pci_get_subvendor(dev), pci_get_subdevice(dev),
610 pci_get_revid(dev));
611 fxp_read_eeprom(sc, &data, 10, 1);
612 device_printf(dev, "Dynamic Standby mode is %s\n",
613 data & 0x02 ? "enabled" : "disabled");
614 }
615
616 /*
617 * If this is only a 10Mbps device, then there is no MII, and
618 * the PHY will use a serial interface instead.
619 *
620 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
621 * doesn't have a programming interface of any sort. The
622 * media is sensed automatically based on how the link partner
623 * is configured. This is, in essence, manual configuration.
624 */
625 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
626 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
627 fxp_serial_ifmedia_sts);
628 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
629 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
630 } else {
631 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
632 fxp_ifmedia_sts)) {
633 device_printf(dev, "MII without any PHY!\n");
634 error = ENXIO;
635 goto fail;
636 }
637 }
638
639 ifp = &sc->arpcom.ac_if;
640 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
641 ifp->if_baudrate = 100000000;
642 ifp->if_init = fxp_init;
643 ifp->if_softc = sc;
644 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
645 ifp->if_ioctl = fxp_ioctl;
646 ifp->if_start = fxp_start;
647 #ifdef IFPOLL_ENABLE
648 ifp->if_npoll = fxp_npoll;
649 #endif
650 ifp->if_watchdog = fxp_watchdog;
651
652 /*
653 * Attach the interface.
654 */
655 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
656
657 #ifdef IFPOLL_ENABLE
658 ifpoll_compat_setup(&sc->fxp_npoll, ctx, (struct sysctl_oid *)tree,
659 device_get_unit(dev), ifp->if_serializer);
660 #endif
661
662 /*
663 * Tell the upper layer(s) we support long frames.
664 */
665 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
666
667 /*
668 * Let the system queue as many packets as we have available
669 * TX descriptors.
670 */
671 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
672 ifq_set_ready(&ifp->if_snd);
673
674 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
675
676 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
677 fxp_intr, sc, &sc->ih,
678 ifp->if_serializer);
679 if (error) {
680 ether_ifdetach(ifp);
681 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
682 ifmedia_removeall(&sc->sc_media);
683 device_printf(dev, "could not setup irq\n");
684 goto fail;
685 }
686
687 return (0);
688
689 failmem:
690 device_printf(dev, "Failed to malloc memory\n");
691 error = ENOMEM;
692 fail:
693 fxp_release(dev);
694 return (error);
695 }
696
697 /*
698 * release all resources
699 */
700 static void
701 fxp_release(device_t dev)
702 {
703 struct fxp_softc *sc = device_get_softc(dev);
704
705 if (sc->miibus)
706 device_delete_child(dev, sc->miibus);
707 bus_generic_detach(dev);
708
709 if (sc->cbl_base)
710 kfree(sc->cbl_base, M_DEVBUF);
711 if (sc->fxp_stats)
712 kfree(sc->fxp_stats, M_DEVBUF);
713 if (sc->mcsp)
714 kfree(sc->mcsp, M_DEVBUF);
715 if (sc->rfa_headm)
716 m_freem(sc->rfa_headm);
717
718 if (sc->irq)
719 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
720 if (sc->mem)
721 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
722 }
723
724 /*
725 * Detach interface.
726 */
727 static int
728 fxp_detach(device_t dev)
729 {
730 struct fxp_softc *sc = device_get_softc(dev);
731
732 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
733
734 /*
735 * Stop DMA and drop transmit queue.
736 */
737 fxp_stop(sc);
738
739 /*
740 * Disable interrupts.
741 *
742 * NOTE: This should be done after fxp_stop(), because software
743 * resetting in fxp_stop() may leave interrupts turned on.
744 */
745 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
746
747 /*
748 * Free all media structures.
749 */
750 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
751 ifmedia_removeall(&sc->sc_media);
752
753 if (sc->ih)
754 bus_teardown_intr(dev, sc->irq, sc->ih);
755
756 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
757
758 /*
759 * Close down routes etc.
760 */
761 ether_ifdetach(&sc->arpcom.ac_if);
762
763 /* Release our allocated resources. */
764 fxp_release(dev);
765
766 return (0);
767 }
768
769 /*
770 * Device shutdown routine. Called at system shutdown after sync. The
771 * main purpose of this routine is to shut off receiver DMA so that
772 * kernel memory doesn't get clobbered during warmboot.
773 */
774 static int
775 fxp_shutdown(device_t dev)
776 {
777 struct fxp_softc *sc = device_get_softc(dev);
778 struct ifnet *ifp = &sc->arpcom.ac_if;
779
780 lwkt_serialize_enter(ifp->if_serializer);
781 /*
782 * Make sure that DMA is disabled prior to reboot. Not doing
783 * do could allow DMA to corrupt kernel memory during the
784 * reboot before the driver initializes.
785 */
786 fxp_stop(sc);
787 lwkt_serialize_exit(ifp->if_serializer);
788 return (0);
789 }
790
791 /*
792 * Device suspend routine. Stop the interface and save some PCI
793 * settings in case the BIOS doesn't restore them properly on
794 * resume.
795 */
796 static int
797 fxp_suspend(device_t dev)
798 {
799 struct fxp_softc *sc = device_get_softc(dev);
800 int i;
801
802 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
803
804 fxp_stop(sc);
805
806 for (i = 0; i < 5; i++)
807 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
808 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
809 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
810 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
811 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
812
813 sc->suspended = 1;
814
815 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
816 return (0);
817 }
818
819 /*
820 * Device resume routine. Restore some PCI settings in case the BIOS
821 * doesn't, re-enable busmastering, and restart the interface if
822 * appropriate.
823 */
824 static int
825 fxp_resume(device_t dev)
826 {
827 struct fxp_softc *sc = device_get_softc(dev);
828 struct ifnet *ifp = &sc->arpcom.ac_if;
829 int i;
830
831 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
832
833 fxp_powerstate_d0(dev);
834
835 /* better way to do this? */
836 for (i = 0; i < 5; i++)
837 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
838 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
839 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
840 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
841 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
842
843 /* reenable busmastering and memory space */
844 pci_enable_busmaster(dev);
845 pci_enable_io(dev, SYS_RES_MEMORY);
846
847 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
848 DELAY(10);
849
850 /* reinitialize interface if necessary */
851 if (ifp->if_flags & IFF_UP)
852 fxp_init(sc);
853
854 sc->suspended = 0;
855
856 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
857 return (0);
858 }
859
860 static void
861 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
862 {
863 u_int16_t reg;
864 int x;
865
866 /*
867 * Shift in data.
868 */
869 for (x = 1 << (length - 1); x; x >>= 1) {
870 if (data & x)
871 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
872 else
873 reg = FXP_EEPROM_EECS;
874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
875 DELAY(1);
876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
877 DELAY(1);
878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
879 DELAY(1);
880 }
881 }
882
883 /*
884 * Read from the serial EEPROM. Basically, you manually shift in
885 * the read opcode (one bit at a time) and then shift in the address,
886 * and then you shift out the data (all of this one bit at a time).
887 * The word size is 16 bits, so you have to provide the address for
888 * every 16 bits of data.
889 */
890 static u_int16_t
891 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
892 {
893 u_int16_t reg, data;
894 int x;
895
896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
897 /*
898 * Shift in read opcode.
899 */
900 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
901 /*
902 * Shift in address.
903 */
904 data = 0;
905 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
906 if (offset & x)
907 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
908 else
909 reg = FXP_EEPROM_EECS;
910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
911 DELAY(1);
912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
913 DELAY(1);
914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
915 DELAY(1);
916 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
917 data++;
918 if (autosize && reg == 0) {
919 sc->eeprom_size = data;
920 break;
921 }
922 }
923 /*
924 * Shift out data.
925 */
926 data = 0;
927 reg = FXP_EEPROM_EECS;
928 for (x = 1 << 15; x; x >>= 1) {
929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
930 DELAY(1);
931 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
932 data |= x;
933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
934 DELAY(1);
935 }
936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
937 DELAY(1);
938
939 return (data);
940 }
941
942 static void
943 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
944 {
945 int i;
946
947 /*
948 * Erase/write enable.
949 */
950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
951 fxp_eeprom_shiftin(sc, 0x4, 3);
952 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
954 DELAY(1);
955 /*
956 * Shift in write opcode, address, data.
957 */
958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
959 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
960 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
961 fxp_eeprom_shiftin(sc, data, 16);
962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
963 DELAY(1);
964 /*
965 * Wait for EEPROM to finish up.
966 */
967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
968 DELAY(1);
969 for (i = 0; i < 1000; i++) {
970 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
971 break;
972 DELAY(50);
973 }
974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
975 DELAY(1);
976 /*
977 * Erase/write disable.
978 */
979 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
980 fxp_eeprom_shiftin(sc, 0x4, 3);
981 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
982 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
983 DELAY(1);
984 }
985
986 /*
987 * From NetBSD:
988 *
989 * Figure out EEPROM size.
990 *
991 * 559's can have either 64-word or 256-word EEPROMs, the 558
992 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
993 * talks about the existance of 16 to 256 word EEPROMs.
994 *
995 * The only known sizes are 64 and 256, where the 256 version is used
996 * by CardBus cards to store CIS information.
997 *
998 * The address is shifted in msb-to-lsb, and after the last
999 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1000 * after which follows the actual data. We try to detect this zero, by
1001 * probing the data-out bit in the EEPROM control register just after
1002 * having shifted in a bit. If the bit is zero, we assume we've
1003 * shifted enough address bits. The data-out should be tri-state,
1004 * before this, which should translate to a logical one.
1005 */
1006 static void
1007 fxp_autosize_eeprom(struct fxp_softc *sc)
1008 {
1009
1010 /* guess maximum size of 256 words */
1011 sc->eeprom_size = 8;
1012
1013 /* autosize */
1014 fxp_eeprom_getword(sc, 0, 1);
1015 }
1016
1017 static void
1018 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1019 {
1020 int i;
1021
1022 for (i = 0; i < words; i++)
1023 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1024 }
1025
1026 static void
1027 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1028 {
1029 int i;
1030
1031 for (i = 0; i < words; i++)
1032 fxp_eeprom_putword(sc, offset + i, data[i]);
1033 }
1034
1035 /*
1036 * Start packet transmission on the interface.
1037 */
1038 static void
1039 fxp_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1040 {
1041 struct fxp_softc *sc = ifp->if_softc;
1042 struct fxp_cb_tx *txp;
1043
1044 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1045 ASSERT_SERIALIZED(ifp->if_serializer);
1046
1047 /*
1048 * See if we need to suspend xmit until the multicast filter
1049 * has been reprogrammed (which can only be done at the head
1050 * of the command chain).
1051 */
1052 if (sc->need_mcsetup) {
1053 ifq_purge(&ifp->if_snd);
1054 return;
1055 }
1056
1057 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1058 return;
1059
1060 txp = NULL;
1061
1062 /*
1063 * We're finished if there is nothing more to add to the list or if
1064 * we're all filled up with buffers to transmit.
1065 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1066 * a NOP command when needed.
1067 */
1068 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1069 struct mbuf *m, *mb_head;
1070 int segment, ntries = 0;
1071
1072 /*
1073 * Grab a packet to transmit.
1074 */
1075 mb_head = ifq_dequeue(&ifp->if_snd);
1076 if (mb_head == NULL)
1077 break;
1078 tbdinit:
1079 /*
1080 * Make sure that the packet fits into one TX desc
1081 */
1082 segment = 0;
1083 for (m = mb_head; m != NULL; m = m->m_next) {
1084 if (m->m_len != 0) {
1085 ++segment;
1086 if (segment >= FXP_NTXSEG)
1087 break;
1088 }
1089 }
1090 if (segment >= FXP_NTXSEG) {
1091 struct mbuf *mn;
1092
1093 if (ntries) {
1094 /*
1095 * Packet is excessively fragmented,
1096 * and will never fit into one TX
1097 * desc. Give it up.
1098 */
1099 m_freem(mb_head);
1100 IFNET_STAT_INC(ifp, oerrors, 1);
1101 continue;
1102 }
1103
1104 mn = m_dup(mb_head, M_NOWAIT);
1105 if (mn == NULL) {
1106 m_freem(mb_head);
1107 IFNET_STAT_INC(ifp, oerrors, 1);
1108 continue;
1109 }
1110
1111 m_freem(mb_head);
1112 mb_head = mn;
1113 ntries = 1;
1114 goto tbdinit;
1115 }
1116
1117 /*
1118 * Get pointer to next available tx desc.
1119 */
1120 txp = sc->cbl_last->next;
1121
1122 /*
1123 * Go through each of the mbufs in the chain and initialize
1124 * the transmit buffer descriptors with the physical address
1125 * and size of the mbuf.
1126 */
1127 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1128 if (m->m_len != 0) {
1129 KKASSERT(segment < FXP_NTXSEG);
1130
1131 txp->tbd[segment].tb_addr =
1132 vtophys(mtod(m, vm_offset_t));
1133 txp->tbd[segment].tb_size = m->m_len;
1134 segment++;
1135 }
1136 }
1137 KKASSERT(m == NULL);
1138
1139 txp->tbd_number = segment;
1140 txp->mb_head = mb_head;
1141 txp->cb_status = 0;
1142 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1143 txp->cb_command =
1144 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1145 FXP_CB_COMMAND_S;
1146 } else {
1147 txp->cb_command =
1148 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1149 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1150 }
1151 txp->tx_threshold = tx_threshold;
1152
1153 /*
1154 * Advance the end of list forward.
1155 */
1156 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1157 sc->cbl_last = txp;
1158
1159 /*
1160 * Advance the beginning of the list forward if there are
1161 * no other packets queued (when nothing is queued, cbl_first
1162 * sits on the last TxCB that was sent out).
1163 */
1164 if (sc->tx_queued == 0)
1165 sc->cbl_first = txp;
1166
1167 sc->tx_queued++;
1168 /*
1169 * Set a 5 second timer just in case we don't hear
1170 * from the card again.
1171 */
1172 ifp->if_timer = 5;
1173
1174 BPF_MTAP(ifp, mb_head);
1175 }
1176
1177 if (sc->tx_queued >= FXP_USABLE_TXCB)
1178 ifq_set_oactive(&ifp->if_snd);
1179
1180 /*
1181 * We're finished. If we added to the list, issue a RESUME to get DMA
1182 * going again if suspended.
1183 */
1184 if (txp != NULL) {
1185 fxp_scb_wait(sc);
1186 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1187 }
1188 }
1189
1190 #ifdef IFPOLL_ENABLE
1191
1192 static void
1193 fxp_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1194 {
1195 struct fxp_softc *sc = ifp->if_softc;
1196 u_int8_t statack;
1197
1198 ASSERT_SERIALIZED(ifp->if_serializer);
1199
1200 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1201 FXP_SCB_STATACK_FR;
1202 if (sc->fxp_npoll.ifpc_stcount-- == 0) {
1203 u_int8_t tmp;
1204
1205 sc->fxp_npoll.ifpc_stcount = sc->fxp_npoll.ifpc_stfrac;
1206
1207 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1208 if (tmp == 0xff || tmp == 0)
1209 return; /* nothing to do */
1210 tmp &= ~statack;
1211 /* ack what we can */
1212 if (tmp != 0)
1213 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1214 statack |= tmp;
1215 }
1216 fxp_intr_body(sc, statack, count);
1217 }
1218
1219 static void
1220 fxp_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1221 {
1222 struct fxp_softc *sc = ifp->if_softc;
1223
1224 ASSERT_SERIALIZED(ifp->if_serializer);
1225
1226 if (info != NULL) {
1227 int cpuid = sc->fxp_npoll.ifpc_cpuid;
1228
1229 info->ifpi_rx[cpuid].poll_func = fxp_npoll_compat;
1230 info->ifpi_rx[cpuid].arg = NULL;
1231 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1232
1233 if (ifp->if_flags & IFF_RUNNING) {
1234 /* disable interrupts */
1235 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
1236 FXP_SCB_INTR_DISABLE);
1237 sc->fxp_npoll.ifpc_stcount = 0;
1238 }
1239 ifq_set_cpuid(&ifp->if_snd, cpuid);
1240 } else {
1241 if (ifp->if_flags & IFF_RUNNING) {
1242 /* enable interrupts */
1243 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1244 }
1245 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
1246 }
1247 }
1248
1249 #endif /* IFPOLL_ENABLE */
1250
1251 /*
1252 * Process interface interrupts.
1253 */
1254 static void
1255 fxp_intr(void *xsc)
1256 {
1257 struct fxp_softc *sc = xsc;
1258 u_int8_t statack;
1259
1260 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1261
1262 if (sc->suspended) {
1263 return;
1264 }
1265
1266 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1267 /*
1268 * It should not be possible to have all bits set; the
1269 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1270 * all bits are set, this may indicate that the card has
1271 * been physically ejected, so ignore it.
1272 */
1273 if (statack == 0xff)
1274 return;
1275
1276 /*
1277 * First ACK all the interrupts in this pass.
1278 */
1279 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1280 fxp_intr_body(sc, statack, -1);
1281 }
1282 }
1283
1284 static void
1285 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1286 {
1287 struct ifnet *ifp = &sc->arpcom.ac_if;
1288 struct mbuf *m;
1289 struct fxp_rfa *rfa;
1290 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1291
1292 if (rnr)
1293 fxp_rnr++;
1294 #ifdef IFPOLL_ENABLE
1295 /* Pick up a deferred RNR condition if `count' ran out last time. */
1296 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1297 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1298 rnr = 1;
1299 }
1300 #endif
1301
1302 /*
1303 * Free any finished transmit mbuf chains.
1304 *
1305 * Handle the CNA event likt a CXTNO event. It used to
1306 * be that this event (control unit not ready) was not
1307 * encountered, but it is now with the SMPng modifications.
1308 * The exact sequence of events that occur when the interface
1309 * is brought up are different now, and if this event
1310 * goes unhandled, the configuration/rxfilter setup sequence
1311 * can stall for several seconds. The result is that no
1312 * packets go out onto the wire for about 5 to 10 seconds
1313 * after the interface is ifconfig'ed for the first time.
1314 */
1315 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1316 struct fxp_cb_tx *txp;
1317
1318 for (txp = sc->cbl_first; sc->tx_queued &&
1319 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1320 txp = txp->next) {
1321 if ((m = txp->mb_head) != NULL) {
1322 txp->mb_head = NULL;
1323 sc->tx_queued--;
1324 m_freem(m);
1325 } else {
1326 sc->tx_queued--;
1327 }
1328 }
1329 sc->cbl_first = txp;
1330
1331 if (sc->tx_queued < FXP_USABLE_TXCB)
1332 ifq_clr_oactive(&ifp->if_snd);
1333
1334 if (sc->tx_queued == 0) {
1335 ifp->if_timer = 0;
1336 if (sc->need_mcsetup)
1337 fxp_mc_setup(sc);
1338 }
1339
1340 /*
1341 * Try to start more packets transmitting.
1342 */
1343 if (!ifq_is_empty(&ifp->if_snd))
1344 if_devstart(ifp);
1345 }
1346
1347 /*
1348 * Just return if nothing happened on the receive side.
1349 */
1350 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1351 return;
1352
1353 /*
1354 * Process receiver interrupts. If a no-resource (RNR)
1355 * condition exists, get whatever packets we can and
1356 * re-start the receiver.
1357 *
1358 * When using polling, we do not process the list to completion,
1359 * so when we get an RNR interrupt we must defer the restart
1360 * until we hit the last buffer with the C bit set.
1361 * If we run out of cycles and rfa_headm has the C bit set,
1362 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1363 * that the info will be used in the subsequent polling cycle.
1364 */
1365 for (;;) {
1366 m = sc->rfa_headm;
1367 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1368 RFA_ALIGNMENT_FUDGE);
1369
1370 #ifdef IFPOLL_ENABLE /* loop at most count times if count >=0 */
1371 if (count >= 0 && count-- == 0) {
1372 if (rnr) {
1373 /* Defer RNR processing until the next time. */
1374 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1375 rnr = 0;
1376 }
1377 break;
1378 }
1379 #endif /* IFPOLL_ENABLE */
1380
1381 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1382 break;
1383
1384 /*
1385 * Remove first packet from the chain.
1386 */
1387 sc->rfa_headm = m->m_next;
1388 if (sc->rfa_headm == NULL)
1389 sc->rfa_tailm = NULL;
1390 m->m_next = NULL;
1391
1392 /*
1393 * Add a new buffer to the receive chain.
1394 * If this fails, the old buffer is recycled
1395 * instead.
1396 */
1397 if (fxp_add_rfabuf(sc, m) == 0) {
1398 int total_len;
1399
1400 /*
1401 * Fetch packet length (the top 2 bits of
1402 * actual_size are flags set by the controller
1403 * upon completion), and drop the packet in case
1404 * of bogus length or CRC errors.
1405 */
1406 total_len = rfa->actual_size & 0x3fff;
1407 if (total_len < sizeof(struct ether_header) ||
1408 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1409 sizeof(struct fxp_rfa) ||
1410 (rfa->rfa_status & FXP_RFA_STATUS_CRC)) {
1411 m_freem(m);
1412 continue;
1413 }
1414 m->m_pkthdr.len = m->m_len = total_len;
1415 ifp->if_input(ifp, m, NULL, -1);
1416 }
1417 }
1418
1419 if (rnr) {
1420 fxp_scb_wait(sc);
1421 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1422 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1423 RFA_ALIGNMENT_FUDGE);
1424 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1425 }
1426 }
1427
1428 /*
1429 * Update packet in/out/collision statistics. The i82557 doesn't
1430 * allow you to access these counters without doing a fairly
1431 * expensive DMA to get _all_ of the statistics it maintains, so
1432 * we do this operation here only once per second. The statistics
1433 * counters in the kernel are updated from the previous dump-stats
1434 * DMA and then a new dump-stats DMA is started. The on-chip
1435 * counters are zeroed when the DMA completes. If we can't start
1436 * the DMA immediately, we don't wait - we just prepare to read
1437 * them again next time.
1438 */
1439 static void
1440 fxp_tick(void *xsc)
1441 {
1442 struct fxp_softc *sc = xsc;
1443 struct ifnet *ifp = &sc->arpcom.ac_if;
1444 struct fxp_stats *sp = sc->fxp_stats;
1445 struct fxp_cb_tx *txp;
1446 struct mbuf *m;
1447
1448 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1449
1450 IFNET_STAT_INC(ifp, opackets, sp->tx_good);
1451 IFNET_STAT_INC(ifp, collisions, sp->tx_total_collisions);
1452 if (sp->rx_good) {
1453 IFNET_STAT_INC(ifp, ipackets, sp->rx_good);
1454 sc->rx_idle_secs = 0;
1455 } else {
1456 /*
1457 * Receiver's been idle for another second.
1458 */
1459 sc->rx_idle_secs++;
1460 }
1461 IFNET_STAT_INC(ifp, ierrors,
1462 sp->rx_crc_errors +
1463 sp->rx_alignment_errors +
1464 sp->rx_rnr_errors +
1465 sp->rx_overrun_errors);
1466 /*
1467 * If any transmit underruns occured, bump up the transmit
1468 * threshold by another 512 bytes (64 * 8).
1469 */
1470 if (sp->tx_underruns) {
1471 IFNET_STAT_INC(ifp, oerrors, sp->tx_underruns);
1472 if (tx_threshold < 192)
1473 tx_threshold += 64;
1474 }
1475
1476 /*
1477 * Release any xmit buffers that have completed DMA. This isn't
1478 * strictly necessary to do here, but it's advantagous for mbufs
1479 * with external storage to be released in a timely manner rather
1480 * than being defered for a potentially long time. This limits
1481 * the delay to a maximum of one second.
1482 */
1483 for (txp = sc->cbl_first; sc->tx_queued &&
1484 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1485 txp = txp->next) {
1486 if ((m = txp->mb_head) != NULL) {
1487 txp->mb_head = NULL;
1488 sc->tx_queued--;
1489 m_freem(m);
1490 } else {
1491 sc->tx_queued--;
1492 }
1493 }
1494 sc->cbl_first = txp;
1495
1496 if (sc->tx_queued < FXP_USABLE_TXCB)
1497 ifq_clr_oactive(&ifp->if_snd);
1498 if (sc->tx_queued == 0)
1499 ifp->if_timer = 0;
1500
1501 /*
1502 * Try to start more packets transmitting.
1503 */
1504 if (!ifq_is_empty(&ifp->if_snd))
1505 if_devstart(ifp);
1506
1507 /*
1508 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1509 * then assume the receiver has locked up and attempt to clear
1510 * the condition by reprogramming the multicast filter. This is
1511 * a work-around for a bug in the 82557 where the receiver locks
1512 * up if it gets certain types of garbage in the syncronization
1513 * bits prior to the packet header. This bug is supposed to only
1514 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1515 * mode as well (perhaps due to a 10/100 speed transition).
1516 */
1517 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1518 sc->rx_idle_secs = 0;
1519 fxp_mc_setup(sc);
1520 }
1521 /*
1522 * If there is no pending command, start another stats
1523 * dump. Otherwise punt for now.
1524 */
1525 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1526 /*
1527 * Start another stats dump.
1528 */
1529 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1530 } else {
1531 /*
1532 * A previous command is still waiting to be accepted.
1533 * Just zero our copy of the stats and wait for the
1534 * next timer event to update them.
1535 */
1536 sp->tx_good = 0;
1537 sp->tx_underruns = 0;
1538 sp->tx_total_collisions = 0;
1539
1540 sp->rx_good = 0;
1541 sp->rx_crc_errors = 0;
1542 sp->rx_alignment_errors = 0;
1543 sp->rx_rnr_errors = 0;
1544 sp->rx_overrun_errors = 0;
1545 }
1546 if (sc->miibus != NULL)
1547 mii_tick(device_get_softc(sc->miibus));
1548 /*
1549 * Schedule another timeout one second from now.
1550 */
1551 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1552
1553 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1554 }
1555
1556 /*
1557 * Stop the interface. Cancels the statistics updater and resets
1558 * the interface.
1559 */
1560 static void
1561 fxp_stop(struct fxp_softc *sc)
1562 {
1563 struct ifnet *ifp = &sc->arpcom.ac_if;
1564 struct fxp_cb_tx *txp;
1565 int i;
1566
1567 ASSERT_SERIALIZED(ifp->if_serializer);
1568
1569 ifp->if_flags &= ~IFF_RUNNING;
1570 ifq_clr_oactive(&ifp->if_snd);
1571 ifp->if_timer = 0;
1572
1573 /*
1574 * Cancel stats updater.
1575 */
1576 callout_stop(&sc->fxp_stat_timer);
1577
1578 /*
1579 * Issue software reset, which also unloads the microcode.
1580 */
1581 sc->flags &= ~FXP_FLAG_UCODE;
1582 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1583 DELAY(50);
1584
1585 /*
1586 * Release any xmit buffers.
1587 */
1588 txp = sc->cbl_base;
1589 if (txp != NULL) {
1590 for (i = 0; i < FXP_NTXCB; i++) {
1591 if (txp[i].mb_head != NULL) {
1592 m_freem(txp[i].mb_head);
1593 txp[i].mb_head = NULL;
1594 }
1595 }
1596 }
1597 sc->tx_queued = 0;
1598
1599 /*
1600 * Free all the receive buffers then reallocate/reinitialize
1601 */
1602 if (sc->rfa_headm != NULL)
1603 m_freem(sc->rfa_headm);
1604 sc->rfa_headm = NULL;
1605 sc->rfa_tailm = NULL;
1606 for (i = 0; i < FXP_NRFABUFS; i++) {
1607 if (fxp_add_rfabuf(sc, NULL) != 0) {
1608 /*
1609 * This "can't happen" - we're at splimp()
1610 * and we just freed all the buffers we need
1611 * above.
1612 */
1613 panic("fxp_stop: no buffers!");
1614 }
1615 }
1616 }
1617
1618 /*
1619 * Watchdog/transmission transmit timeout handler. Called when a
1620 * transmission is started on the interface, but no interrupt is
1621 * received before the timeout. This usually indicates that the
1622 * card has wedged for some reason.
1623 */
1624 static void
1625 fxp_watchdog(struct ifnet *ifp)
1626 {
1627 ASSERT_SERIALIZED(ifp->if_serializer);
1628
1629 if_printf(ifp, "device timeout\n");
1630 IFNET_STAT_INC(ifp, oerrors, 1);
1631 fxp_init(ifp->if_softc);
1632 }
1633
1634 static void
1635 fxp_init(void *xsc)
1636 {
1637 struct fxp_softc *sc = xsc;
1638 struct ifnet *ifp = &sc->arpcom.ac_if;
1639 struct fxp_cb_config *cbp;
1640 struct fxp_cb_ias *cb_ias;
1641 struct fxp_cb_tx *txp;
1642 struct fxp_cb_mcs *mcsp;
1643 int i, prm;
1644
1645 ASSERT_SERIALIZED(ifp->if_serializer);
1646
1647 /*
1648 * Cancel any pending I/O
1649 */
1650 fxp_stop(sc);
1651
1652 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1653
1654 /*
1655 * Initialize base of CBL and RFA memory. Loading with zero
1656 * sets it up for regular linear addressing.
1657 */
1658 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1659 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1660
1661 fxp_scb_wait(sc);
1662 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1663
1664 /*
1665 * Initialize base of dump-stats buffer.
1666 */
1667 fxp_scb_wait(sc);
1668 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1669 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1670
1671 /*
1672 * Attempt to load microcode if requested.
1673 */
1674 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1675 fxp_load_ucode(sc);
1676
1677 /*
1678 * Initialize the multicast address list.
1679 */
1680 if (fxp_mc_addrs(sc)) {
1681 mcsp = sc->mcsp;
1682 mcsp->cb_status = 0;
1683 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1684 mcsp->link_addr = -1;
1685 /*
1686 * Start the multicast setup command.
1687 */
1688 fxp_scb_wait(sc);
1689 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1690 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1691 /* ...and wait for it to complete. */
1692 fxp_dma_wait(&mcsp->cb_status, sc);
1693 }
1694
1695 /*
1696 * We temporarily use memory that contains the TxCB list to
1697 * construct the config CB. The TxCB list memory is rebuilt
1698 * later.
1699 */
1700 cbp = (struct fxp_cb_config *) sc->cbl_base;
1701
1702 /*
1703 * This bcopy is kind of disgusting, but there are a bunch of must be
1704 * zero and must be one bits in this structure and this is the easiest
1705 * way to initialize them all to proper values.
1706 */
1707 bcopy(fxp_cb_config_template,
1708 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1709 sizeof(fxp_cb_config_template));
1710
1711 cbp->cb_status = 0;
1712 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1713 cbp->link_addr = -1; /* (no) next command */
1714 cbp->byte_count = 22; /* (22) bytes to config */
1715 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1716 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1717 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1718 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1719 cbp->type_enable = 0; /* actually reserved */
1720 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1721 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1722 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1723 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1724 cbp->dma_mbce = 0; /* (disable) dma max counters */
1725 cbp->late_scb = 0; /* (don't) defer SCB update */
1726 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1727 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1728 cbp->ci_int = 1; /* interrupt on CU idle */
1729 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1730 cbp->ext_stats_dis = 1; /* disable extended counters */
1731 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1732 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1733 cbp->disc_short_rx = !prm; /* discard short packets */
1734 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1735 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1736 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1737 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1738 cbp->csma_dis = 0; /* (don't) disable link */
1739 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1740 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1741 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1742 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1743 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1744 cbp->nsai = 1; /* (don't) disable source addr insert */
1745 cbp->preamble_length = 2; /* (7 byte) preamble */
1746 cbp->loopback = 0; /* (don't) loopback */
1747 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1748 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1749 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1750 cbp->promiscuous = prm; /* promiscuous mode */
1751 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1752 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1753 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1754 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1755 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1756
1757 cbp->stripping = !prm; /* truncate rx packet to byte count */
1758 cbp->padding = 1; /* (do) pad short tx packets */
1759 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1760 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1761 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1762 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1763 /* must set wake_en in PMCSR also */
1764 cbp->force_fdx = 0; /* (don't) force full duplex */
1765 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1766 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1767 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1768
1769 if (sc->revision == FXP_REV_82557) {
1770 /*
1771 * The 82557 has no hardware flow control, the values
1772 * below are the defaults for the chip.
1773 */
1774 cbp->fc_delay_lsb = 0;
1775 cbp->fc_delay_msb = 0x40;
1776 cbp->pri_fc_thresh = 3;
1777 cbp->tx_fc_dis = 0;
1778 cbp->rx_fc_restop = 0;
1779 cbp->rx_fc_restart = 0;
1780 cbp->fc_filter = 0;
1781 cbp->pri_fc_loc = 1;
1782 } else {
1783 cbp->fc_delay_lsb = 0x1f;
1784 cbp->fc_delay_msb = 0x01;
1785 cbp->pri_fc_thresh = 3;
1786 cbp->tx_fc_dis = 0; /* enable transmit FC */
1787 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1788 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1789 cbp->fc_filter = !prm; /* drop FC frames to host */
1790 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1791 }
1792
1793 /*
1794 * Start the config command/DMA.
1795 */
1796 fxp_scb_wait(sc);
1797 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1798 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1799 /* ...and wait for it to complete. */
1800 fxp_dma_wait(&cbp->cb_status, sc);
1801
1802 /*
1803 * Now initialize the station address. Temporarily use the TxCB
1804 * memory area like we did above for the config CB.
1805 */
1806 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1807 cb_ias->cb_status = 0;
1808 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1809 cb_ias->link_addr = -1;
1810 bcopy(sc->arpcom.ac_enaddr,
1811 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1812 sizeof(sc->arpcom.ac_enaddr));
1813
1814 /*
1815 * Start the IAS (Individual Address Setup) command/DMA.
1816 */
1817 fxp_scb_wait(sc);
1818 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1819 /* ...and wait for it to complete. */
1820 fxp_dma_wait(&cb_ias->cb_status, sc);
1821
1822 /*
1823 * Initialize transmit control block (TxCB) list.
1824 */
1825
1826 txp = sc->cbl_base;
1827 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1828 for (i = 0; i < FXP_NTXCB; i++) {
1829 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1830 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1831 txp[i].link_addr =
1832 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1833 if (sc->flags & FXP_FLAG_EXT_TXCB)
1834 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1835 else
1836 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1837 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1838 }
1839 /*
1840 * Set the suspend flag on the first TxCB and start the control
1841 * unit. It will execute the NOP and then suspend.
1842 */
1843 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1844 sc->cbl_first = sc->cbl_last = txp;
1845 sc->tx_queued = 1;
1846
1847 fxp_scb_wait(sc);
1848 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1849
1850 /*
1851 * Initialize receiver buffer area - RFA.
1852 */
1853 fxp_scb_wait(sc);
1854 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1855 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1856 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1857
1858 /*
1859 * Set current media.
1860 */
1861 if (sc->miibus != NULL)
1862 mii_mediachg(device_get_softc(sc->miibus));
1863
1864 ifp->if_flags |= IFF_RUNNING;
1865 ifq_clr_oactive(&ifp->if_snd);
1866
1867 /*
1868 * Enable interrupts.
1869 */
1870 #ifdef IFPOLL_ENABLE
1871 /*
1872 * ... but only do that if we are not polling. And because (presumably)
1873 * the default is interrupts on, we need to disable them explicitly!
1874 */
1875 if (ifp->if_flags & IFF_NPOLLING) {
1876 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1877 sc->fxp_npoll.ifpc_stcount = 0;
1878 } else
1879 #endif /* IFPOLL_ENABLE */
1880 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1881
1882 /*
1883 * Start stats updater.
1884 */
1885 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1886 }
1887
1888 static int
1889 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1890 {
1891 ASSERT_SERIALIZED(ifp->if_serializer);
1892 return (0);
1893 }
1894
1895 static void
1896 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1897 {
1898 ASSERT_SERIALIZED(ifp->if_serializer);
1899 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1900 }
1901
1902 /*
1903 * Change media according to request.
1904 */
1905 static int
1906 fxp_ifmedia_upd(struct ifnet *ifp)
1907 {
1908 struct fxp_softc *sc = ifp->if_softc;
1909 struct mii_data *mii;
1910
1911 ASSERT_SERIALIZED(ifp->if_serializer);
1912
1913 mii = device_get_softc(sc->miibus);
1914 mii_mediachg(mii);
1915 return (0);
1916 }
1917
1918 /*
1919 * Notify the world which media we're using.
1920 */
1921 static void
1922 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1923 {
1924 struct fxp_softc *sc = ifp->if_softc;
1925 struct mii_data *mii;
1926
1927 ASSERT_SERIALIZED(ifp->if_serializer);
1928
1929 mii = device_get_softc(sc->miibus);
1930 mii_pollstat(mii);
1931 ifmr->ifm_active = mii->mii_media_active;
1932 ifmr->ifm_status = mii->mii_media_status;
1933
1934 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1935 sc->cu_resume_bug = 1;
1936 else
1937 sc->cu_resume_bug = 0;
1938 }
1939
1940 /*
1941 * Add a buffer to the end of the RFA buffer list.
1942 * Return 0 if successful, 1 for failure. A failure results in
1943 * adding the 'oldm' (if non-NULL) on to the end of the list -
1944 * tossing out its old contents and recycling it.
1945 * The RFA struct is stuck at the beginning of mbuf cluster and the
1946 * data pointer is fixed up to point just past it.
1947 */
1948 static int
1949 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1950 {
1951 u_int32_t v;
1952 struct mbuf *m;
1953 struct fxp_rfa *rfa, *p_rfa;
1954
1955 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1956 if (m == NULL) { /* try to recycle the old mbuf instead */
1957 if (oldm == NULL)
1958 return 1;
1959 m = oldm;
1960 m->m_data = m->m_ext.ext_buf;
1961 }
1962
1963 /*
1964 * Move the data pointer up so that the incoming data packet
1965 * will be 32-bit aligned.
1966 */
1967 m->m_data += RFA_ALIGNMENT_FUDGE;
1968
1969 /*
1970 * Get a pointer to the base of the mbuf cluster and move
1971 * data start past it.
1972 */
1973 rfa = mtod(m, struct fxp_rfa *);
1974 m->m_data += sizeof(struct fxp_rfa);
1975 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) -
1976 RFA_ALIGNMENT_FUDGE);
1977
1978 /*
1979 * Initialize the rest of the RFA. Note that since the RFA
1980 * is misaligned, we cannot store values directly. Instead,
1981 * we use an optimized, inline copy.
1982 */
1983
1984 rfa->rfa_status = 0;
1985 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1986 rfa->actual_size = 0;
1987
1988 v = -1;
1989 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1990 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1991
1992 /*
1993 * If there are other buffers already on the list, attach this
1994 * one to the end by fixing up the tail to point to this one.
1995 */
1996 if (sc->rfa_headm != NULL) {
1997 p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf +
1998 RFA_ALIGNMENT_FUDGE);
1999 sc->rfa_tailm->m_next = m;
2000 v = vtophys(rfa);
2001 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
2002 p_rfa->rfa_control = 0;
2003 } else {
2004 sc->rfa_headm = m;
2005 }
2006 sc->rfa_tailm = m;
2007
2008 return (m == oldm);
2009 }
2010
2011 static int
2012 fxp_miibus_readreg(device_t dev, int phy, int reg)
2013 {
2014 struct fxp_softc *sc = device_get_softc(dev);
2015 int count = 10000;
2016 int value;
2017
2018 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2019 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2020
2021 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2022 && count--)
2023 DELAY(10);
2024
2025 if (count <= 0)
2026 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2027
2028 return (value & 0xffff);
2029 }
2030
2031 static void
2032 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2033 {
2034 struct fxp_softc *sc = device_get_softc(dev);
2035 int count = 10000;
2036
2037 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2038 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2039 (value & 0xffff));
2040
2041 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2042 count--)
2043 DELAY(10);
2044
2045 if (count <= 0)
2046 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2047 }
2048
2049 static int
2050 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2051 {
2052 struct fxp_softc *sc = ifp->if_softc;
2053 struct ifreq *ifr = (struct ifreq *)data;
2054 struct mii_data *mii;
2055 int error = 0;
2056
2057 ASSERT_SERIALIZED(ifp->if_serializer);
2058
2059 switch (command) {
2060
2061 case SIOCSIFFLAGS:
2062 if (ifp->if_flags & IFF_ALLMULTI)
2063 sc->flags |= FXP_FLAG_ALL_MCAST;
2064 else
2065 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2066
2067 /*
2068 * If interface is marked up and not running, then start it.
2069 * If it is marked down and running, stop it.
2070 * XXX If it's up then re-initialize it. This is so flags
2071 * such as IFF_PROMISC are handled.
2072 */
2073 if (ifp->if_flags & IFF_UP) {
2074 fxp_init(sc);
2075 } else {
2076 if (ifp->if_flags & IFF_RUNNING)
2077 fxp_stop(sc);
2078 }
2079 break;
2080
2081 case SIOCADDMULTI:
2082 case SIOCDELMULTI:
2083 if (ifp->if_flags & IFF_ALLMULTI)
2084 sc->flags |= FXP_FLAG_ALL_MCAST;
2085 else
2086 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2087 /*
2088 * Multicast list has changed; set the hardware filter
2089 * accordingly.
2090 */
2091 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2092 fxp_mc_setup(sc);
2093 /*
2094 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2095 * again rather than else {}.
2096 */
2097 if (sc->flags & FXP_FLAG_ALL_MCAST)
2098 fxp_init(sc);
2099 error = 0;
2100 break;
2101
2102 case SIOCSIFMEDIA:
2103 case SIOCGIFMEDIA:
2104 if (sc->miibus != NULL) {
2105 mii = device_get_softc(sc->miibus);
2106 error = ifmedia_ioctl(ifp, ifr,
2107 &mii->mii_media, command);
2108 } else {
2109 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2110 }
2111 break;
2112
2113 default:
2114 error = ether_ioctl(ifp, command, data);
2115 break;
2116 }
2117 return (error);
2118 }
2119
2120 /*
2121 * Fill in the multicast address list and return number of entries.
2122 */
2123 static int
2124 fxp_mc_addrs(struct fxp_softc *sc)
2125 {
2126 struct fxp_cb_mcs *mcsp = sc->mcsp;
2127 struct ifnet *ifp = &sc->arpcom.ac_if;
2128 struct ifmultiaddr *ifma;
2129 int nmcasts;
2130
2131 nmcasts = 0;
2132 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2133 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2134 if (ifma->ifma_addr->sa_family != AF_LINK)
2135 continue;
2136 if (nmcasts >= MAXMCADDR) {
2137 sc->flags |= FXP_FLAG_ALL_MCAST;
2138 nmcasts = 0;
2139 break;
2140 }
2141 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2142 (void *)(uintptr_t)(volatile void *)
2143 &sc->mcsp->mc_addr[nmcasts][0], 6);
2144 nmcasts++;
2145 }
2146 }
2147 mcsp->mc_cnt = nmcasts * 6;
2148 return (nmcasts);
2149 }
2150
2151 /*
2152 * Program the multicast filter.
2153 *
2154 * We have an artificial restriction that the multicast setup command
2155 * must be the first command in the chain, so we take steps to ensure
2156 * this. By requiring this, it allows us to keep up the performance of
2157 * the pre-initialized command ring (esp. link pointers) by not actually
2158 * inserting the mcsetup command in the ring - i.e. its link pointer
2159 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2160 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2161 * lead into the regular TxCB ring when it completes.
2162 *
2163 * This function must be called at splimp.
2164 */
2165 static void
2166 fxp_mc_setup(struct fxp_softc *sc)
2167 {
2168 struct fxp_cb_mcs *mcsp = sc->mcsp;
2169 struct ifnet *ifp = &sc->arpcom.ac_if;
2170 int count;
2171
2172 /*
2173 * If there are queued commands, we must wait until they are all
2174 * completed. If we are already waiting, then add a NOP command
2175 * with interrupt option so that we're notified when all commands
2176 * have been completed - fxp_start() ensures that no additional
2177 * TX commands will be added when need_mcsetup is true.
2178 */
2179 if (sc->tx_queued) {
2180 struct fxp_cb_tx *txp;
2181
2182 /*
2183 * need_mcsetup will be true if we are already waiting for the
2184 * NOP command to be completed (see below). In this case, bail.
2185 */
2186 if (sc->need_mcsetup)
2187 return;
2188 sc->need_mcsetup = 1;
2189
2190 /*
2191 * Add a NOP command with interrupt so that we are notified
2192 * when all TX commands have been processed.
2193 */
2194 txp = sc->cbl_last->next;
2195 txp->mb_head = NULL;
2196 txp->cb_status = 0;
2197 txp->cb_command = FXP_CB_COMMAND_NOP |
2198 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2199 /*
2200 * Advance the end of list forward.
2201 */
2202 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2203 sc->cbl_last = txp;
2204 sc->tx_queued++;
2205 /*
2206 * Issue a resume in case the CU has just suspended.
2207 */
2208 fxp_scb_wait(sc);
2209 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2210 /*
2211 * Set a 5 second timer just in case we don't hear from the
2212 * card again.
2213 */
2214 ifp->if_timer = 5;
2215
2216 return;
2217 }
2218 sc->need_mcsetup = 0;
2219
2220 /*
2221 * Initialize multicast setup descriptor.
2222 */
2223 mcsp->next = sc->cbl_base;
2224 mcsp->mb_head = NULL;
2225 mcsp->cb_status = 0;
2226 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2227 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2228 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2229 fxp_mc_addrs(sc);
2230 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2231 sc->tx_queued = 1;
2232
2233 /*
2234 * Wait until command unit is not active. This should never
2235 * be the case when nothing is queued, but make sure anyway.
2236 */
2237 count = 100;
2238 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2239 FXP_SCB_CUS_ACTIVE && --count)
2240 DELAY(10);
2241 if (count == 0) {
2242 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2243 return;
2244 }
2245
2246 /*
2247 * Start the multicast setup command.
2248 */
2249 fxp_scb_wait(sc);
2250 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2251 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2252
2253 ifp->if_timer = 2;
2254 return;
2255 }
2256
2257 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2258 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2259 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2260 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2261 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2262 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2263
2264 #define UCODE(x) x, sizeof(x)
2265
2266 struct ucode {
2267 u_int32_t revision;
2268 u_int32_t *ucode;
2269 int length;
2270 u_short int_delay_offset;
2271 u_short bundle_max_offset;
2272 } ucode_table[] = {
2273 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2274 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2275 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2276 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2277 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2278 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2279 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2280 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2281 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2282 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2283 { 0, NULL, 0, 0, 0 }
2284 };
2285
2286 static void
2287 fxp_load_ucode(struct fxp_softc *sc)
2288 {
2289 struct ucode *uc;
2290 struct fxp_cb_ucode *cbp;
2291
2292 for (uc = ucode_table; uc->ucode != NULL; uc++)
2293 if (sc->revision == uc->revision)
2294 break;
2295 if (uc->ucode == NULL)
2296 return;
2297 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2298 cbp->cb_status = 0;
2299 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2300 cbp->link_addr = -1; /* (no) next command */
2301 memcpy(cbp->ucode, uc->ucode, uc->length);
2302 if (uc->int_delay_offset)
2303 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2304 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2305 if (uc->bundle_max_offset)
2306 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2307 sc->tunable_bundle_max;
2308 /*
2309 * Download the ucode to the chip.
2310 */
2311 fxp_scb_wait(sc);
2312 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2314 /* ...and wait for it to complete. */
2315 fxp_dma_wait(&cbp->cb_status, sc);
2316 if_printf(&sc->arpcom.ac_if,
2317 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2318 sc->tunable_int_delay,
2319 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2320 sc->flags |= FXP_FLAG_UCODE;
2321 }
2322
2323 /*
2324 * Interrupt delay is expressed in microseconds, a multiplier is used
2325 * to convert this to the appropriate clock ticks before using.
2326 */
2327 static int
2328 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2329 {
2330 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2331 }
2332
2333 static int
2334 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2335 {
2336 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2337 }
DragonFly BSD