2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/module.h>
28 #include "radeon_asic.h"
29 #include "radeon_audio.h"
30 #include <drm/radeon_drm.h>
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
39 * Indirect registers accessor
41 u32
tn_smc_rreg(struct radeon_device
*rdev
, u32 reg
)
45 lockmgr(&rdev
->smc_idx_lock
, LK_EXCLUSIVE
);
46 WREG32(TN_SMC_IND_INDEX_0
, (reg
));
47 r
= RREG32(TN_SMC_IND_DATA_0
);
48 lockmgr(&rdev
->smc_idx_lock
, LK_RELEASE
);
52 void tn_smc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
54 lockmgr(&rdev
->smc_idx_lock
, LK_EXCLUSIVE
);
55 WREG32(TN_SMC_IND_INDEX_0
, (reg
));
56 WREG32(TN_SMC_IND_DATA_0
, (v
));
57 lockmgr(&rdev
->smc_idx_lock
, LK_RELEASE
);
60 static const u32 tn_rlc_save_restore_register_list
[] =
187 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
188 MODULE_FIRMWARE("radeon/BARTS_me.bin");
189 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
190 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
191 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
192 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
193 MODULE_FIRMWARE("radeon/TURKS_me.bin");
194 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
195 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
196 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
197 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
198 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
199 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
200 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
201 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
202 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
203 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
204 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
205 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
206 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
207 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
210 static const u32 cayman_golden_registers2
[] =
212 0x3e5c, 0xffffffff, 0x00000000,
213 0x3e48, 0xffffffff, 0x00000000,
214 0x3e4c, 0xffffffff, 0x00000000,
215 0x3e64, 0xffffffff, 0x00000000,
216 0x3e50, 0xffffffff, 0x00000000,
217 0x3e60, 0xffffffff, 0x00000000
220 static const u32 cayman_golden_registers
[] =
222 0x5eb4, 0xffffffff, 0x00000002,
223 0x5e78, 0x8f311ff1, 0x001000f0,
224 0x3f90, 0xffff0000, 0xff000000,
225 0x9148, 0xffff0000, 0xff000000,
226 0x3f94, 0xffff0000, 0xff000000,
227 0x914c, 0xffff0000, 0xff000000,
228 0xc78, 0x00000080, 0x00000080,
229 0xbd4, 0x70073777, 0x00011003,
230 0xd02c, 0xbfffff1f, 0x08421000,
231 0xd0b8, 0x73773777, 0x02011003,
232 0x5bc0, 0x00200000, 0x50100000,
233 0x98f8, 0x33773777, 0x02011003,
234 0x98fc, 0xffffffff, 0x76541032,
235 0x7030, 0x31000311, 0x00000011,
236 0x2f48, 0x33773777, 0x42010001,
237 0x6b28, 0x00000010, 0x00000012,
238 0x7728, 0x00000010, 0x00000012,
239 0x10328, 0x00000010, 0x00000012,
240 0x10f28, 0x00000010, 0x00000012,
241 0x11b28, 0x00000010, 0x00000012,
242 0x12728, 0x00000010, 0x00000012,
243 0x240c, 0x000007ff, 0x00000000,
244 0x8a14, 0xf000001f, 0x00000007,
245 0x8b24, 0x3fff3fff, 0x00ff0fff,
246 0x8b10, 0x0000ff0f, 0x00000000,
247 0x28a4c, 0x07ffffff, 0x06000000,
248 0x10c, 0x00000001, 0x00010003,
249 0xa02c, 0xffffffff, 0x0000009b,
250 0x913c, 0x0000010f, 0x01000100,
251 0x8c04, 0xf8ff00ff, 0x40600060,
252 0x28350, 0x00000f01, 0x00000000,
253 0x9508, 0x3700001f, 0x00000002,
254 0x960c, 0xffffffff, 0x54763210,
255 0x88c4, 0x001f3ae3, 0x00000082,
256 0x88d0, 0xffffffff, 0x0f40df40,
257 0x88d4, 0x0000001f, 0x00000010,
258 0x8974, 0xffffffff, 0x00000000
261 static const u32 dvst_golden_registers2
[] =
263 0x8f8, 0xffffffff, 0,
264 0x8fc, 0x00380000, 0,
265 0x8f8, 0xffffffff, 1,
269 static const u32 dvst_golden_registers
[] =
271 0x690, 0x3fff3fff, 0x20c00033,
272 0x918c, 0x0fff0fff, 0x00010006,
273 0x91a8, 0x0fff0fff, 0x00010006,
274 0x9150, 0xffffdfff, 0x6e944040,
275 0x917c, 0x0fff0fff, 0x00030002,
276 0x9198, 0x0fff0fff, 0x00030002,
277 0x915c, 0x0fff0fff, 0x00010000,
278 0x3f90, 0xffff0001, 0xff000000,
279 0x9178, 0x0fff0fff, 0x00070000,
280 0x9194, 0x0fff0fff, 0x00070000,
281 0x9148, 0xffff0001, 0xff000000,
282 0x9190, 0x0fff0fff, 0x00090008,
283 0x91ac, 0x0fff0fff, 0x00090008,
284 0x3f94, 0xffff0000, 0xff000000,
285 0x914c, 0xffff0000, 0xff000000,
286 0x929c, 0x00000fff, 0x00000001,
287 0x55e4, 0xff607fff, 0xfc000100,
288 0x8a18, 0xff000fff, 0x00000100,
289 0x8b28, 0xff000fff, 0x00000100,
290 0x9144, 0xfffc0fff, 0x00000100,
291 0x6ed8, 0x00010101, 0x00010000,
292 0x9830, 0xffffffff, 0x00000000,
293 0x9834, 0xf00fffff, 0x00000400,
294 0x9838, 0xfffffffe, 0x00000000,
295 0xd0c0, 0xff000fff, 0x00000100,
296 0xd02c, 0xbfffff1f, 0x08421000,
297 0xd0b8, 0x73773777, 0x12010001,
298 0x5bb0, 0x000000f0, 0x00000070,
299 0x98f8, 0x73773777, 0x12010001,
300 0x98fc, 0xffffffff, 0x00000010,
301 0x9b7c, 0x00ff0000, 0x00fc0000,
302 0x8030, 0x00001f0f, 0x0000100a,
303 0x2f48, 0x73773777, 0x12010001,
304 0x2408, 0x00030000, 0x000c007f,
305 0x8a14, 0xf000003f, 0x00000007,
306 0x8b24, 0x3fff3fff, 0x00ff0fff,
307 0x8b10, 0x0000ff0f, 0x00000000,
308 0x28a4c, 0x07ffffff, 0x06000000,
309 0x4d8, 0x00000fff, 0x00000100,
310 0xa008, 0xffffffff, 0x00010000,
311 0x913c, 0xffff03ff, 0x01000100,
312 0x8c00, 0x000000ff, 0x00000003,
313 0x8c04, 0xf8ff00ff, 0x40600060,
314 0x8cf0, 0x1fff1fff, 0x08e00410,
315 0x28350, 0x00000f01, 0x00000000,
316 0x9508, 0xf700071f, 0x00000002,
317 0x960c, 0xffffffff, 0x54763210,
318 0x20ef8, 0x01ff01ff, 0x00000002,
319 0x20e98, 0xfffffbff, 0x00200000,
320 0x2015c, 0xffffffff, 0x00000f40,
321 0x88c4, 0x001f3ae3, 0x00000082,
322 0x8978, 0x3fffffff, 0x04050140,
323 0x88d4, 0x0000001f, 0x00000010,
324 0x8974, 0xffffffff, 0x00000000
327 static const u32 scrapper_golden_registers
[] =
329 0x690, 0x3fff3fff, 0x20c00033,
330 0x918c, 0x0fff0fff, 0x00010006,
331 0x918c, 0x0fff0fff, 0x00010006,
332 0x91a8, 0x0fff0fff, 0x00010006,
333 0x91a8, 0x0fff0fff, 0x00010006,
334 0x9150, 0xffffdfff, 0x6e944040,
335 0x9150, 0xffffdfff, 0x6e944040,
336 0x917c, 0x0fff0fff, 0x00030002,
337 0x917c, 0x0fff0fff, 0x00030002,
338 0x9198, 0x0fff0fff, 0x00030002,
339 0x9198, 0x0fff0fff, 0x00030002,
340 0x915c, 0x0fff0fff, 0x00010000,
341 0x915c, 0x0fff0fff, 0x00010000,
342 0x3f90, 0xffff0001, 0xff000000,
343 0x3f90, 0xffff0001, 0xff000000,
344 0x9178, 0x0fff0fff, 0x00070000,
345 0x9178, 0x0fff0fff, 0x00070000,
346 0x9194, 0x0fff0fff, 0x00070000,
347 0x9194, 0x0fff0fff, 0x00070000,
348 0x9148, 0xffff0001, 0xff000000,
349 0x9148, 0xffff0001, 0xff000000,
350 0x9190, 0x0fff0fff, 0x00090008,
351 0x9190, 0x0fff0fff, 0x00090008,
352 0x91ac, 0x0fff0fff, 0x00090008,
353 0x91ac, 0x0fff0fff, 0x00090008,
354 0x3f94, 0xffff0000, 0xff000000,
355 0x3f94, 0xffff0000, 0xff000000,
356 0x914c, 0xffff0000, 0xff000000,
357 0x914c, 0xffff0000, 0xff000000,
358 0x929c, 0x00000fff, 0x00000001,
359 0x929c, 0x00000fff, 0x00000001,
360 0x55e4, 0xff607fff, 0xfc000100,
361 0x8a18, 0xff000fff, 0x00000100,
362 0x8a18, 0xff000fff, 0x00000100,
363 0x8b28, 0xff000fff, 0x00000100,
364 0x8b28, 0xff000fff, 0x00000100,
365 0x9144, 0xfffc0fff, 0x00000100,
366 0x9144, 0xfffc0fff, 0x00000100,
367 0x6ed8, 0x00010101, 0x00010000,
368 0x9830, 0xffffffff, 0x00000000,
369 0x9830, 0xffffffff, 0x00000000,
370 0x9834, 0xf00fffff, 0x00000400,
371 0x9834, 0xf00fffff, 0x00000400,
372 0x9838, 0xfffffffe, 0x00000000,
373 0x9838, 0xfffffffe, 0x00000000,
374 0xd0c0, 0xff000fff, 0x00000100,
375 0xd02c, 0xbfffff1f, 0x08421000,
376 0xd02c, 0xbfffff1f, 0x08421000,
377 0xd0b8, 0x73773777, 0x12010001,
378 0xd0b8, 0x73773777, 0x12010001,
379 0x5bb0, 0x000000f0, 0x00000070,
380 0x98f8, 0x73773777, 0x12010001,
381 0x98f8, 0x73773777, 0x12010001,
382 0x98fc, 0xffffffff, 0x00000010,
383 0x98fc, 0xffffffff, 0x00000010,
384 0x9b7c, 0x00ff0000, 0x00fc0000,
385 0x9b7c, 0x00ff0000, 0x00fc0000,
386 0x8030, 0x00001f0f, 0x0000100a,
387 0x8030, 0x00001f0f, 0x0000100a,
388 0x2f48, 0x73773777, 0x12010001,
389 0x2f48, 0x73773777, 0x12010001,
390 0x2408, 0x00030000, 0x000c007f,
391 0x8a14, 0xf000003f, 0x00000007,
392 0x8a14, 0xf000003f, 0x00000007,
393 0x8b24, 0x3fff3fff, 0x00ff0fff,
394 0x8b24, 0x3fff3fff, 0x00ff0fff,
395 0x8b10, 0x0000ff0f, 0x00000000,
396 0x8b10, 0x0000ff0f, 0x00000000,
397 0x28a4c, 0x07ffffff, 0x06000000,
398 0x28a4c, 0x07ffffff, 0x06000000,
399 0x4d8, 0x00000fff, 0x00000100,
400 0x4d8, 0x00000fff, 0x00000100,
401 0xa008, 0xffffffff, 0x00010000,
402 0xa008, 0xffffffff, 0x00010000,
403 0x913c, 0xffff03ff, 0x01000100,
404 0x913c, 0xffff03ff, 0x01000100,
405 0x90e8, 0x001fffff, 0x010400c0,
406 0x8c00, 0x000000ff, 0x00000003,
407 0x8c00, 0x000000ff, 0x00000003,
408 0x8c04, 0xf8ff00ff, 0x40600060,
409 0x8c04, 0xf8ff00ff, 0x40600060,
410 0x8c30, 0x0000000f, 0x00040005,
411 0x8cf0, 0x1fff1fff, 0x08e00410,
412 0x8cf0, 0x1fff1fff, 0x08e00410,
413 0x900c, 0x00ffffff, 0x0017071f,
414 0x28350, 0x00000f01, 0x00000000,
415 0x28350, 0x00000f01, 0x00000000,
416 0x9508, 0xf700071f, 0x00000002,
417 0x9508, 0xf700071f, 0x00000002,
418 0x9688, 0x00300000, 0x0017000f,
419 0x960c, 0xffffffff, 0x54763210,
420 0x960c, 0xffffffff, 0x54763210,
421 0x20ef8, 0x01ff01ff, 0x00000002,
422 0x20e98, 0xfffffbff, 0x00200000,
423 0x2015c, 0xffffffff, 0x00000f40,
424 0x88c4, 0x001f3ae3, 0x00000082,
425 0x88c4, 0x001f3ae3, 0x00000082,
426 0x8978, 0x3fffffff, 0x04050140,
427 0x8978, 0x3fffffff, 0x04050140,
428 0x88d4, 0x0000001f, 0x00000010,
429 0x88d4, 0x0000001f, 0x00000010,
430 0x8974, 0xffffffff, 0x00000000,
431 0x8974, 0xffffffff, 0x00000000
434 static void ni_init_golden_registers(struct radeon_device
*rdev
)
436 switch (rdev
->family
) {
438 radeon_program_register_sequence(rdev
,
439 cayman_golden_registers
,
440 (const u32
)ARRAY_SIZE(cayman_golden_registers
));
441 radeon_program_register_sequence(rdev
,
442 cayman_golden_registers2
,
443 (const u32
)ARRAY_SIZE(cayman_golden_registers2
));
446 if ((rdev
->pdev
->device
== 0x9900) ||
447 (rdev
->pdev
->device
== 0x9901) ||
448 (rdev
->pdev
->device
== 0x9903) ||
449 (rdev
->pdev
->device
== 0x9904) ||
450 (rdev
->pdev
->device
== 0x9905) ||
451 (rdev
->pdev
->device
== 0x9906) ||
452 (rdev
->pdev
->device
== 0x9907) ||
453 (rdev
->pdev
->device
== 0x9908) ||
454 (rdev
->pdev
->device
== 0x9909) ||
455 (rdev
->pdev
->device
== 0x990A) ||
456 (rdev
->pdev
->device
== 0x990B) ||
457 (rdev
->pdev
->device
== 0x990C) ||
458 (rdev
->pdev
->device
== 0x990D) ||
459 (rdev
->pdev
->device
== 0x990E) ||
460 (rdev
->pdev
->device
== 0x990F) ||
461 (rdev
->pdev
->device
== 0x9910) ||
462 (rdev
->pdev
->device
== 0x9913) ||
463 (rdev
->pdev
->device
== 0x9917) ||
464 (rdev
->pdev
->device
== 0x9918)) {
465 radeon_program_register_sequence(rdev
,
466 dvst_golden_registers
,
467 (const u32
)ARRAY_SIZE(dvst_golden_registers
));
468 radeon_program_register_sequence(rdev
,
469 dvst_golden_registers2
,
470 (const u32
)ARRAY_SIZE(dvst_golden_registers2
));
472 radeon_program_register_sequence(rdev
,
473 scrapper_golden_registers
,
474 (const u32
)ARRAY_SIZE(scrapper_golden_registers
));
475 radeon_program_register_sequence(rdev
,
476 dvst_golden_registers2
,
477 (const u32
)ARRAY_SIZE(dvst_golden_registers2
));
485 #define BTC_IO_MC_REGS_SIZE 29
487 static const u32 barts_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
488 {0x00000077, 0xff010100},
489 {0x00000078, 0x00000000},
490 {0x00000079, 0x00001434},
491 {0x0000007a, 0xcc08ec08},
492 {0x0000007b, 0x00040000},
493 {0x0000007c, 0x000080c0},
494 {0x0000007d, 0x09000000},
495 {0x0000007e, 0x00210404},
496 {0x00000081, 0x08a8e800},
497 {0x00000082, 0x00030444},
498 {0x00000083, 0x00000000},
499 {0x00000085, 0x00000001},
500 {0x00000086, 0x00000002},
501 {0x00000087, 0x48490000},
502 {0x00000088, 0x20244647},
503 {0x00000089, 0x00000005},
504 {0x0000008b, 0x66030000},
505 {0x0000008c, 0x00006603},
506 {0x0000008d, 0x00000100},
507 {0x0000008f, 0x00001c0a},
508 {0x00000090, 0xff000001},
509 {0x00000094, 0x00101101},
510 {0x00000095, 0x00000fff},
511 {0x00000096, 0x00116fff},
512 {0x00000097, 0x60010000},
513 {0x00000098, 0x10010000},
514 {0x00000099, 0x00006000},
515 {0x0000009a, 0x00001000},
516 {0x0000009f, 0x00946a00}
519 static const u32 turks_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
520 {0x00000077, 0xff010100},
521 {0x00000078, 0x00000000},
522 {0x00000079, 0x00001434},
523 {0x0000007a, 0xcc08ec08},
524 {0x0000007b, 0x00040000},
525 {0x0000007c, 0x000080c0},
526 {0x0000007d, 0x09000000},
527 {0x0000007e, 0x00210404},
528 {0x00000081, 0x08a8e800},
529 {0x00000082, 0x00030444},
530 {0x00000083, 0x00000000},
531 {0x00000085, 0x00000001},
532 {0x00000086, 0x00000002},
533 {0x00000087, 0x48490000},
534 {0x00000088, 0x20244647},
535 {0x00000089, 0x00000005},
536 {0x0000008b, 0x66030000},
537 {0x0000008c, 0x00006603},
538 {0x0000008d, 0x00000100},
539 {0x0000008f, 0x00001c0a},
540 {0x00000090, 0xff000001},
541 {0x00000094, 0x00101101},
542 {0x00000095, 0x00000fff},
543 {0x00000096, 0x00116fff},
544 {0x00000097, 0x60010000},
545 {0x00000098, 0x10010000},
546 {0x00000099, 0x00006000},
547 {0x0000009a, 0x00001000},
548 {0x0000009f, 0x00936a00}
551 static const u32 caicos_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
552 {0x00000077, 0xff010100},
553 {0x00000078, 0x00000000},
554 {0x00000079, 0x00001434},
555 {0x0000007a, 0xcc08ec08},
556 {0x0000007b, 0x00040000},
557 {0x0000007c, 0x000080c0},
558 {0x0000007d, 0x09000000},
559 {0x0000007e, 0x00210404},
560 {0x00000081, 0x08a8e800},
561 {0x00000082, 0x00030444},
562 {0x00000083, 0x00000000},
563 {0x00000085, 0x00000001},
564 {0x00000086, 0x00000002},
565 {0x00000087, 0x48490000},
566 {0x00000088, 0x20244647},
567 {0x00000089, 0x00000005},
568 {0x0000008b, 0x66030000},
569 {0x0000008c, 0x00006603},
570 {0x0000008d, 0x00000100},
571 {0x0000008f, 0x00001c0a},
572 {0x00000090, 0xff000001},
573 {0x00000094, 0x00101101},
574 {0x00000095, 0x00000fff},
575 {0x00000096, 0x00116fff},
576 {0x00000097, 0x60010000},
577 {0x00000098, 0x10010000},
578 {0x00000099, 0x00006000},
579 {0x0000009a, 0x00001000},
580 {0x0000009f, 0x00916a00}
583 static const u32 cayman_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
584 {0x00000077, 0xff010100},
585 {0x00000078, 0x00000000},
586 {0x00000079, 0x00001434},
587 {0x0000007a, 0xcc08ec08},
588 {0x0000007b, 0x00040000},
589 {0x0000007c, 0x000080c0},
590 {0x0000007d, 0x09000000},
591 {0x0000007e, 0x00210404},
592 {0x00000081, 0x08a8e800},
593 {0x00000082, 0x00030444},
594 {0x00000083, 0x00000000},
595 {0x00000085, 0x00000001},
596 {0x00000086, 0x00000002},
597 {0x00000087, 0x48490000},
598 {0x00000088, 0x20244647},
599 {0x00000089, 0x00000005},
600 {0x0000008b, 0x66030000},
601 {0x0000008c, 0x00006603},
602 {0x0000008d, 0x00000100},
603 {0x0000008f, 0x00001c0a},
604 {0x00000090, 0xff000001},
605 {0x00000094, 0x00101101},
606 {0x00000095, 0x00000fff},
607 {0x00000096, 0x00116fff},
608 {0x00000097, 0x60010000},
609 {0x00000098, 0x10010000},
610 {0x00000099, 0x00006000},
611 {0x0000009a, 0x00001000},
612 {0x0000009f, 0x00976b00}
615 int ni_mc_load_microcode(struct radeon_device
*rdev
)
617 const __be32
*fw_data
;
618 u32 mem_type
, running
, blackout
= 0;
620 int i
, ucode_size
, regs_size
;
625 switch (rdev
->family
) {
627 io_mc_regs
= (u32
*)&barts_io_mc_regs
;
628 ucode_size
= BTC_MC_UCODE_SIZE
;
629 regs_size
= BTC_IO_MC_REGS_SIZE
;
632 io_mc_regs
= (u32
*)&turks_io_mc_regs
;
633 ucode_size
= BTC_MC_UCODE_SIZE
;
634 regs_size
= BTC_IO_MC_REGS_SIZE
;
638 io_mc_regs
= (u32
*)&caicos_io_mc_regs
;
639 ucode_size
= BTC_MC_UCODE_SIZE
;
640 regs_size
= BTC_IO_MC_REGS_SIZE
;
643 io_mc_regs
= (u32
*)&cayman_io_mc_regs
;
644 ucode_size
= CAYMAN_MC_UCODE_SIZE
;
645 regs_size
= BTC_IO_MC_REGS_SIZE
;
649 mem_type
= (RREG32(MC_SEQ_MISC0
) & MC_SEQ_MISC0_GDDR5_MASK
) >> MC_SEQ_MISC0_GDDR5_SHIFT
;
650 running
= RREG32(MC_SEQ_SUP_CNTL
) & RUN_MASK
;
652 if ((mem_type
== MC_SEQ_MISC0_GDDR5_VALUE
) && (running
== 0)) {
654 blackout
= RREG32(MC_SHARED_BLACKOUT_CNTL
);
655 WREG32(MC_SHARED_BLACKOUT_CNTL
, 1);
658 /* reset the engine and set to writable */
659 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
660 WREG32(MC_SEQ_SUP_CNTL
, 0x00000010);
662 /* load mc io regs */
663 for (i
= 0; i
< regs_size
; i
++) {
664 WREG32(MC_SEQ_IO_DEBUG_INDEX
, io_mc_regs
[(i
<< 1)]);
665 WREG32(MC_SEQ_IO_DEBUG_DATA
, io_mc_regs
[(i
<< 1) + 1]);
667 /* load the MC ucode */
668 fw_data
= (const __be32
*)rdev
->mc_fw
->data
;
669 for (i
= 0; i
< ucode_size
; i
++)
670 WREG32(MC_SEQ_SUP_PGM
, be32_to_cpup(fw_data
++));
672 /* put the engine back into the active state */
673 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
674 WREG32(MC_SEQ_SUP_CNTL
, 0x00000004);
675 WREG32(MC_SEQ_SUP_CNTL
, 0x00000001);
677 /* wait for training to complete */
678 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
679 if (RREG32(MC_IO_PAD_CNTL_D0
) & MEM_FALL_OUT_CMD
)
685 WREG32(MC_SHARED_BLACKOUT_CNTL
, blackout
);
691 int ni_init_microcode(struct radeon_device
*rdev
)
693 const char *chip_name
;
694 const char *rlc_chip_name
;
695 size_t pfp_req_size
, me_req_size
, rlc_req_size
, mc_req_size
;
696 size_t smc_req_size
= 0;
702 switch (rdev
->family
) {
705 rlc_chip_name
= "BTC";
706 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
707 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
708 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
709 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
710 smc_req_size
= ALIGN(BARTS_SMC_UCODE_SIZE
, 4);
714 rlc_chip_name
= "BTC";
715 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
716 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
717 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
718 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
719 smc_req_size
= ALIGN(TURKS_SMC_UCODE_SIZE
, 4);
722 chip_name
= "CAICOS";
723 rlc_chip_name
= "BTC";
724 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
725 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
726 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
727 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
728 smc_req_size
= ALIGN(CAICOS_SMC_UCODE_SIZE
, 4);
731 chip_name
= "CAYMAN";
732 rlc_chip_name
= "CAYMAN";
733 pfp_req_size
= CAYMAN_PFP_UCODE_SIZE
* 4;
734 me_req_size
= CAYMAN_PM4_UCODE_SIZE
* 4;
735 rlc_req_size
= CAYMAN_RLC_UCODE_SIZE
* 4;
736 mc_req_size
= CAYMAN_MC_UCODE_SIZE
* 4;
737 smc_req_size
= ALIGN(CAYMAN_SMC_UCODE_SIZE
, 4);
741 rlc_chip_name
= "ARUBA";
742 /* pfp/me same size as CAYMAN */
743 pfp_req_size
= CAYMAN_PFP_UCODE_SIZE
* 4;
744 me_req_size
= CAYMAN_PM4_UCODE_SIZE
* 4;
745 rlc_req_size
= ARUBA_RLC_UCODE_SIZE
* 4;
751 DRM_INFO("Loading %s Microcode\n", chip_name
);
753 ksnprintf(fw_name
, sizeof(fw_name
), "radeonkmsfw_%s_pfp", chip_name
);
754 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, rdev
->dev
);
757 if (rdev
->pfp_fw
->datasize
!= pfp_req_size
) {
759 "ni_pfp: Bogus length %zu in firmware \"%s\"\n",
760 rdev
->pfp_fw
->datasize
, fw_name
);
765 ksnprintf(fw_name
, sizeof(fw_name
), "radeonkmsfw_%s_me", chip_name
);
766 err
= request_firmware(&rdev
->me_fw
, fw_name
, rdev
->dev
);
769 if (rdev
->me_fw
->datasize
!= me_req_size
) {
771 "ni_me: Bogus length %zu in firmware \"%s\"\n",
772 rdev
->me_fw
->datasize
, fw_name
);
776 ksnprintf(fw_name
, sizeof(fw_name
), "radeonkmsfw_%s_rlc",
778 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, rdev
->dev
);
781 if (rdev
->rlc_fw
->datasize
!= rlc_req_size
) {
783 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
784 rdev
->rlc_fw
->datasize
, fw_name
);
788 /* no MC ucode on TN */
789 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
790 ksnprintf(fw_name
, sizeof(fw_name
), "radeonkmsfw_%s_mc", chip_name
);
791 err
= request_firmware(&rdev
->mc_fw
, fw_name
, rdev
->dev
);
794 if (rdev
->mc_fw
->datasize
!= mc_req_size
) {
796 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
797 rdev
->mc_fw
->datasize
, fw_name
);
802 if ((rdev
->family
>= CHIP_BARTS
) && (rdev
->family
<= CHIP_CAYMAN
)) {
803 ksnprintf(fw_name
, sizeof(fw_name
), "radeonkmsfw_%s_smc", chip_name
);
804 err
= request_firmware(&rdev
->smc_fw
, fw_name
, rdev
->dev
);
807 "smc: error loading firmware \"%s\"\n",
809 release_firmware(rdev
->smc_fw
);
812 } else if (rdev
->smc_fw
->datasize
!= smc_req_size
) {
814 "ni_smc: Bogus length %zu in firmware \"%s\"\n",
815 rdev
->smc_fw
->datasize
, fw_name
);
823 pr_err("ni_cp: Failed to load firmware \"%s\"\n",
825 release_firmware(rdev
->pfp_fw
);
827 release_firmware(rdev
->me_fw
);
829 release_firmware(rdev
->rlc_fw
);
831 release_firmware(rdev
->mc_fw
);
833 release_firmware(rdev
->smc_fw
);
840 * ni_fini_microcode - drop the firmwares image references
842 * @rdev: radeon_device pointer
844 * Drop the pfp, me, mc and rlc firmwares image references.
845 * Called at driver shutdown.
847 void ni_fini_microcode(struct radeon_device
*rdev
)
849 release_firmware(rdev
->pfp_fw
);
851 release_firmware(rdev
->me_fw
);
853 release_firmware(rdev
->rlc_fw
);
855 release_firmware(rdev
->mc_fw
);
857 release_firmware(rdev
->smc_fw
);
862 * cayman_get_allowed_info_register - fetch the register for the info ioctl
864 * @rdev: radeon_device pointer
865 * @reg: register offset in bytes
866 * @val: register value
868 * Returns 0 for success or -EINVAL for an invalid register
871 int cayman_get_allowed_info_register(struct radeon_device
*rdev
,
876 case GRBM_STATUS_SE0
:
877 case GRBM_STATUS_SE1
:
880 case (DMA_STATUS_REG
+ DMA0_REGISTER_OFFSET
):
881 case (DMA_STATUS_REG
+ DMA1_REGISTER_OFFSET
):
890 int tn_get_temp(struct radeon_device
*rdev
)
892 u32 temp
= RREG32_SMC(TN_CURRENT_GNB_TEMP
) & 0x7ff;
893 int actual_temp
= (temp
/ 8) - 49;
895 return actual_temp
* 1000;
901 static void cayman_gpu_init(struct radeon_device
*rdev
)
903 u32 gb_addr_config
= 0;
904 u32 mc_shared_chmap
, mc_arb_ramcfg
;
905 u32 cgts_tcc_disable
;
908 u32 cgts_sm_ctrl_reg
;
909 u32 hdp_host_path_cntl
;
911 u32 disabled_rb_mask
;
914 switch (rdev
->family
) {
916 rdev
->config
.cayman
.max_shader_engines
= 2;
917 rdev
->config
.cayman
.max_pipes_per_simd
= 4;
918 rdev
->config
.cayman
.max_tile_pipes
= 8;
919 rdev
->config
.cayman
.max_simds_per_se
= 12;
920 rdev
->config
.cayman
.max_backends_per_se
= 4;
921 rdev
->config
.cayman
.max_texture_channel_caches
= 8;
922 rdev
->config
.cayman
.max_gprs
= 256;
923 rdev
->config
.cayman
.max_threads
= 256;
924 rdev
->config
.cayman
.max_gs_threads
= 32;
925 rdev
->config
.cayman
.max_stack_entries
= 512;
926 rdev
->config
.cayman
.sx_num_of_sets
= 8;
927 rdev
->config
.cayman
.sx_max_export_size
= 256;
928 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
929 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
930 rdev
->config
.cayman
.max_hw_contexts
= 8;
931 rdev
->config
.cayman
.sq_num_cf_insts
= 2;
933 rdev
->config
.cayman
.sc_prim_fifo_size
= 0x100;
934 rdev
->config
.cayman
.sc_hiz_tile_fifo_size
= 0x30;
935 rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
= 0x130;
936 gb_addr_config
= CAYMAN_GB_ADDR_CONFIG_GOLDEN
;
940 rdev
->config
.cayman
.max_shader_engines
= 1;
941 rdev
->config
.cayman
.max_pipes_per_simd
= 4;
942 rdev
->config
.cayman
.max_tile_pipes
= 2;
943 if ((rdev
->pdev
->device
== 0x9900) ||
944 (rdev
->pdev
->device
== 0x9901) ||
945 (rdev
->pdev
->device
== 0x9905) ||
946 (rdev
->pdev
->device
== 0x9906) ||
947 (rdev
->pdev
->device
== 0x9907) ||
948 (rdev
->pdev
->device
== 0x9908) ||
949 (rdev
->pdev
->device
== 0x9909) ||
950 (rdev
->pdev
->device
== 0x990B) ||
951 (rdev
->pdev
->device
== 0x990C) ||
952 (rdev
->pdev
->device
== 0x990F) ||
953 (rdev
->pdev
->device
== 0x9910) ||
954 (rdev
->pdev
->device
== 0x9917) ||
955 (rdev
->pdev
->device
== 0x9999) ||
956 (rdev
->pdev
->device
== 0x999C)) {
957 rdev
->config
.cayman
.max_simds_per_se
= 6;
958 rdev
->config
.cayman
.max_backends_per_se
= 2;
959 rdev
->config
.cayman
.max_hw_contexts
= 8;
960 rdev
->config
.cayman
.sx_max_export_size
= 256;
961 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
962 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
963 } else if ((rdev
->pdev
->device
== 0x9903) ||
964 (rdev
->pdev
->device
== 0x9904) ||
965 (rdev
->pdev
->device
== 0x990A) ||
966 (rdev
->pdev
->device
== 0x990D) ||
967 (rdev
->pdev
->device
== 0x990E) ||
968 (rdev
->pdev
->device
== 0x9913) ||
969 (rdev
->pdev
->device
== 0x9918) ||
970 (rdev
->pdev
->device
== 0x999D)) {
971 rdev
->config
.cayman
.max_simds_per_se
= 4;
972 rdev
->config
.cayman
.max_backends_per_se
= 2;
973 rdev
->config
.cayman
.max_hw_contexts
= 8;
974 rdev
->config
.cayman
.sx_max_export_size
= 256;
975 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
976 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
977 } else if ((rdev
->pdev
->device
== 0x9919) ||
978 (rdev
->pdev
->device
== 0x9990) ||
979 (rdev
->pdev
->device
== 0x9991) ||
980 (rdev
->pdev
->device
== 0x9994) ||
981 (rdev
->pdev
->device
== 0x9995) ||
982 (rdev
->pdev
->device
== 0x9996) ||
983 (rdev
->pdev
->device
== 0x999A) ||
984 (rdev
->pdev
->device
== 0x99A0)) {
985 rdev
->config
.cayman
.max_simds_per_se
= 3;
986 rdev
->config
.cayman
.max_backends_per_se
= 1;
987 rdev
->config
.cayman
.max_hw_contexts
= 4;
988 rdev
->config
.cayman
.sx_max_export_size
= 128;
989 rdev
->config
.cayman
.sx_max_export_pos_size
= 32;
990 rdev
->config
.cayman
.sx_max_export_smx_size
= 96;
992 rdev
->config
.cayman
.max_simds_per_se
= 2;
993 rdev
->config
.cayman
.max_backends_per_se
= 1;
994 rdev
->config
.cayman
.max_hw_contexts
= 4;
995 rdev
->config
.cayman
.sx_max_export_size
= 128;
996 rdev
->config
.cayman
.sx_max_export_pos_size
= 32;
997 rdev
->config
.cayman
.sx_max_export_smx_size
= 96;
999 rdev
->config
.cayman
.max_texture_channel_caches
= 2;
1000 rdev
->config
.cayman
.max_gprs
= 256;
1001 rdev
->config
.cayman
.max_threads
= 256;
1002 rdev
->config
.cayman
.max_gs_threads
= 32;
1003 rdev
->config
.cayman
.max_stack_entries
= 512;
1004 rdev
->config
.cayman
.sx_num_of_sets
= 8;
1005 rdev
->config
.cayman
.sq_num_cf_insts
= 2;
1007 rdev
->config
.cayman
.sc_prim_fifo_size
= 0x40;
1008 rdev
->config
.cayman
.sc_hiz_tile_fifo_size
= 0x30;
1009 rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
= 0x130;
1010 gb_addr_config
= ARUBA_GB_ADDR_CONFIG_GOLDEN
;
1014 /* Initialize HDP */
1015 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1016 WREG32((0x2c14 + j
), 0x00000000);
1017 WREG32((0x2c18 + j
), 0x00000000);
1018 WREG32((0x2c1c + j
), 0x00000000);
1019 WREG32((0x2c20 + j
), 0x00000000);
1020 WREG32((0x2c24 + j
), 0x00000000);
1023 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1024 WREG32(SRBM_INT_CNTL
, 0x1);
1025 WREG32(SRBM_INT_ACK
, 0x1);
1027 evergreen_fix_pci_max_read_req_size(rdev
);
1029 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1030 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1032 tmp
= (mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
;
1033 rdev
->config
.cayman
.mem_row_size_in_kb
= (4 * (1 << (8 + tmp
))) / 1024;
1034 if (rdev
->config
.cayman
.mem_row_size_in_kb
> 4)
1035 rdev
->config
.cayman
.mem_row_size_in_kb
= 4;
1036 /* XXX use MC settings? */
1037 rdev
->config
.cayman
.shader_engine_tile_size
= 32;
1038 rdev
->config
.cayman
.num_gpus
= 1;
1039 rdev
->config
.cayman
.multi_gpu_tile_size
= 64;
1041 tmp
= (gb_addr_config
& NUM_PIPES_MASK
) >> NUM_PIPES_SHIFT
;
1042 rdev
->config
.cayman
.num_tile_pipes
= (1 << tmp
);
1043 tmp
= (gb_addr_config
& PIPE_INTERLEAVE_SIZE_MASK
) >> PIPE_INTERLEAVE_SIZE_SHIFT
;
1044 rdev
->config
.cayman
.mem_max_burst_length_bytes
= (tmp
+ 1) * 256;
1045 tmp
= (gb_addr_config
& NUM_SHADER_ENGINES_MASK
) >> NUM_SHADER_ENGINES_SHIFT
;
1046 rdev
->config
.cayman
.num_shader_engines
= tmp
+ 1;
1047 tmp
= (gb_addr_config
& NUM_GPUS_MASK
) >> NUM_GPUS_SHIFT
;
1048 rdev
->config
.cayman
.num_gpus
= tmp
+ 1;
1049 tmp
= (gb_addr_config
& MULTI_GPU_TILE_SIZE_MASK
) >> MULTI_GPU_TILE_SIZE_SHIFT
;
1050 rdev
->config
.cayman
.multi_gpu_tile_size
= 1 << tmp
;
1051 tmp
= (gb_addr_config
& ROW_SIZE_MASK
) >> ROW_SIZE_SHIFT
;
1052 rdev
->config
.cayman
.mem_row_size_in_kb
= 1 << tmp
;
1055 /* setup tiling info dword. gb_addr_config is not adequate since it does
1056 * not have bank info, so create a custom tiling dword.
1057 * bits 3:0 num_pipes
1058 * bits 7:4 num_banks
1059 * bits 11:8 group_size
1060 * bits 15:12 row_size
1062 rdev
->config
.cayman
.tile_config
= 0;
1063 switch (rdev
->config
.cayman
.num_tile_pipes
) {
1066 rdev
->config
.cayman
.tile_config
|= (0 << 0);
1069 rdev
->config
.cayman
.tile_config
|= (1 << 0);
1072 rdev
->config
.cayman
.tile_config
|= (2 << 0);
1075 rdev
->config
.cayman
.tile_config
|= (3 << 0);
1079 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1080 if (rdev
->flags
& RADEON_IS_IGP
)
1081 rdev
->config
.cayman
.tile_config
|= 1 << 4;
1083 switch ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) {
1084 case 0: /* four banks */
1085 rdev
->config
.cayman
.tile_config
|= 0 << 4;
1087 case 1: /* eight banks */
1088 rdev
->config
.cayman
.tile_config
|= 1 << 4;
1090 case 2: /* sixteen banks */
1092 rdev
->config
.cayman
.tile_config
|= 2 << 4;
1096 rdev
->config
.cayman
.tile_config
|=
1097 ((gb_addr_config
& PIPE_INTERLEAVE_SIZE_MASK
) >> PIPE_INTERLEAVE_SIZE_SHIFT
) << 8;
1098 rdev
->config
.cayman
.tile_config
|=
1099 ((gb_addr_config
& ROW_SIZE_MASK
) >> ROW_SIZE_SHIFT
) << 12;
1102 for (i
= (rdev
->config
.cayman
.max_shader_engines
- 1); i
>= 0; i
--) {
1103 u32 rb_disable_bitmap
;
1105 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1106 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1107 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
1109 tmp
|= rb_disable_bitmap
;
1111 /* enabled rb are just the one not disabled :) */
1112 disabled_rb_mask
= tmp
;
1114 for (i
= 0; i
< (rdev
->config
.cayman
.max_backends_per_se
* rdev
->config
.cayman
.max_shader_engines
); i
++)
1116 /* if all the backends are disabled, fix it up here */
1117 if ((disabled_rb_mask
& tmp
) == tmp
) {
1118 for (i
= 0; i
< (rdev
->config
.cayman
.max_backends_per_se
* rdev
->config
.cayman
.max_shader_engines
); i
++)
1119 disabled_rb_mask
&= ~(1 << i
);
1122 for (i
= 0; i
< rdev
->config
.cayman
.max_shader_engines
; i
++) {
1123 u32 simd_disable_bitmap
;
1125 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1126 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1127 simd_disable_bitmap
= (RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffff0000) >> 16;
1128 simd_disable_bitmap
|= 0xffffffff << rdev
->config
.cayman
.max_simds_per_se
;
1130 tmp
|= simd_disable_bitmap
;
1132 rdev
->config
.cayman
.active_simds
= hweight32(~tmp
);
1134 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1135 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1137 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1138 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1139 if (ASIC_IS_DCE6(rdev
))
1140 WREG32(DMIF_ADDR_CALC
, gb_addr_config
);
1141 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1142 WREG32(DMA_TILING_CONFIG
+ DMA0_REGISTER_OFFSET
, gb_addr_config
);
1143 WREG32(DMA_TILING_CONFIG
+ DMA1_REGISTER_OFFSET
, gb_addr_config
);
1144 WREG32(UVD_UDEC_ADDR_CONFIG
, gb_addr_config
);
1145 WREG32(UVD_UDEC_DB_ADDR_CONFIG
, gb_addr_config
);
1146 WREG32(UVD_UDEC_DBW_ADDR_CONFIG
, gb_addr_config
);
1148 if ((rdev
->config
.cayman
.max_backends_per_se
== 1) &&
1149 (rdev
->flags
& RADEON_IS_IGP
)) {
1150 if ((disabled_rb_mask
& 3) == 2) {
1151 /* RB1 disabled, RB0 enabled */
1154 /* RB0 disabled, RB1 enabled */
1158 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
1159 tmp
= r6xx_remap_render_backend(rdev
, tmp
,
1160 rdev
->config
.cayman
.max_backends_per_se
*
1161 rdev
->config
.cayman
.max_shader_engines
,
1162 CAYMAN_MAX_BACKENDS
, disabled_rb_mask
);
1164 WREG32(GB_BACKEND_MAP
, tmp
);
1166 cgts_tcc_disable
= 0xffff0000;
1167 for (i
= 0; i
< rdev
->config
.cayman
.max_texture_channel_caches
; i
++)
1168 cgts_tcc_disable
&= ~(1 << (16 + i
));
1169 WREG32(CGTS_TCC_DISABLE
, cgts_tcc_disable
);
1170 WREG32(CGTS_SYS_TCC_DISABLE
, cgts_tcc_disable
);
1171 WREG32(CGTS_USER_SYS_TCC_DISABLE
, cgts_tcc_disable
);
1172 WREG32(CGTS_USER_TCC_DISABLE
, cgts_tcc_disable
);
1174 /* reprogram the shader complex */
1175 cgts_sm_ctrl_reg
= RREG32(CGTS_SM_CTRL_REG
);
1176 for (i
= 0; i
< 16; i
++)
1177 WREG32(CGTS_SM_CTRL_REG
, OVERRIDE
);
1178 WREG32(CGTS_SM_CTRL_REG
, cgts_sm_ctrl_reg
);
1180 /* set HW defaults for 3D engine */
1181 WREG32(CP_MEQ_THRESHOLDS
, MEQ1_START(0x30) | MEQ2_START(0x60));
1183 sx_debug_1
= RREG32(SX_DEBUG_1
);
1184 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1185 WREG32(SX_DEBUG_1
, sx_debug_1
);
1187 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1188 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1189 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.cayman
.sx_num_of_sets
);
1190 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1192 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE
);
1194 /* need to be explicitly zero-ed */
1195 WREG32(VGT_OFFCHIP_LDS_BASE
, 0);
1196 WREG32(SQ_LSTMP_RING_BASE
, 0);
1197 WREG32(SQ_HSTMP_RING_BASE
, 0);
1198 WREG32(SQ_ESTMP_RING_BASE
, 0);
1199 WREG32(SQ_GSTMP_RING_BASE
, 0);
1200 WREG32(SQ_VSTMP_RING_BASE
, 0);
1201 WREG32(SQ_PSTMP_RING_BASE
, 0);
1203 WREG32(TA_CNTL_AUX
, DISABLE_CUBE_ANISO
);
1205 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_size
/ 4) - 1) |
1206 POSITION_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_pos_size
/ 4) - 1) |
1207 SMX_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_smx_size
/ 4) - 1)));
1209 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.cayman
.sc_prim_fifo_size
) |
1210 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.cayman
.sc_hiz_tile_fifo_size
) |
1211 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
)));
1214 WREG32(VGT_NUM_INSTANCES
, 1);
1216 WREG32(CP_PERFMON_CNTL
, 0);
1218 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.cayman
.sq_num_cf_insts
) |
1219 FETCH_FIFO_HIWATER(0x4) |
1220 DONE_FIFO_HIWATER(0xe0) |
1221 ALU_UPDATE_FIFO_HIWATER(0x8)));
1223 WREG32(SQ_GPR_RESOURCE_MGMT_1
, NUM_CLAUSE_TEMP_GPRS(4));
1224 WREG32(SQ_CONFIG
, (VC_ENABLE
|
1229 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, DYN_GPR_ENABLE
);
1231 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
1232 FORCE_EOV_MAX_REZ_CNT(255)));
1234 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
) |
1235 AUTO_INVLD_EN(ES_AND_GS_AUTO
));
1237 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1238 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1240 WREG32(CB_PERF_CTR0_SEL_0
, 0);
1241 WREG32(CB_PERF_CTR0_SEL_1
, 0);
1242 WREG32(CB_PERF_CTR1_SEL_0
, 0);
1243 WREG32(CB_PERF_CTR1_SEL_1
, 0);
1244 WREG32(CB_PERF_CTR2_SEL_0
, 0);
1245 WREG32(CB_PERF_CTR2_SEL_1
, 0);
1246 WREG32(CB_PERF_CTR3_SEL_0
, 0);
1247 WREG32(CB_PERF_CTR3_SEL_1
, 0);
1249 tmp
= RREG32(HDP_MISC_CNTL
);
1250 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
1251 WREG32(HDP_MISC_CNTL
, tmp
);
1253 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
1254 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1256 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
1260 /* set clockgating golden values on TN */
1261 if (rdev
->family
== CHIP_ARUBA
) {
1262 tmp
= RREG32_CG(CG_CGTT_LOCAL_0
);
1264 WREG32_CG(CG_CGTT_LOCAL_0
, tmp
);
1265 tmp
= RREG32_CG(CG_CGTT_LOCAL_1
);
1267 WREG32_CG(CG_CGTT_LOCAL_1
, tmp
);
1274 void cayman_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
1276 /* flush hdp cache */
1277 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
1279 /* bits 0-7 are the VM contexts0-7 */
1280 WREG32(VM_INVALIDATE_REQUEST
, 1);
1283 static int cayman_pcie_gart_enable(struct radeon_device
*rdev
)
1287 if (rdev
->gart
.robj
== NULL
) {
1288 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1291 r
= radeon_gart_table_vram_pin(rdev
);
1294 /* Setup TLB control */
1295 WREG32(MC_VM_MX_L1_TLB_CNTL
,
1298 ENABLE_L1_FRAGMENT_PROCESSING
|
1299 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1300 ENABLE_ADVANCED_DRIVER_MODEL
|
1301 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
1302 /* Setup L2 cache */
1303 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
|
1304 ENABLE_L2_FRAGMENT_PROCESSING
|
1305 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1306 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
1307 EFFECTIVE_L2_QUEUE_SIZE(7) |
1308 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1309 WREG32(VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
| INVALIDATE_L2_CACHE
);
1310 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
1312 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1313 /* setup context0 */
1314 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1315 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1316 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1317 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1318 (u32
)(rdev
->dummy_page
.addr
>> 12));
1319 WREG32(VM_CONTEXT0_CNTL2
, 0);
1320 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1321 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1327 /* empty context1-7 */
1328 /* Assign the pt base to something valid for now; the pts used for
1329 * the VMs are determined by the application and setup and assigned
1330 * on the fly in the vm part of radeon_gart.c
1332 for (i
= 1; i
< 8; i
++) {
1333 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
+ (i
<< 2), 0);
1334 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
+ (i
<< 2),
1335 rdev
->vm_manager
.max_pfn
- 1);
1336 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (i
<< 2),
1337 rdev
->vm_manager
.saved_table_addr
[i
]);
1340 /* enable context1-7 */
1341 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
1342 (u32
)(rdev
->dummy_page
.addr
>> 12));
1343 WREG32(VM_CONTEXT1_CNTL2
, 4);
1344 WREG32(VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(1) |
1345 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size
- 9) |
1346 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1347 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
1348 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1349 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
1350 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1351 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
|
1352 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1353 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
|
1354 READ_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1355 READ_PROTECTION_FAULT_ENABLE_DEFAULT
|
1356 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1357 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1359 cayman_pcie_gart_tlb_flush(rdev
);
1360 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1361 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1362 (unsigned long long)rdev
->gart
.table_addr
);
1363 rdev
->gart
.ready
= true;
1367 static void cayman_pcie_gart_disable(struct radeon_device
*rdev
)
1371 for (i
= 1; i
< 8; ++i
) {
1372 rdev
->vm_manager
.saved_table_addr
[i
] = RREG32(
1373 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (i
<< 2));
1376 /* Disable all tables */
1377 WREG32(VM_CONTEXT0_CNTL
, 0);
1378 WREG32(VM_CONTEXT1_CNTL
, 0);
1379 /* Setup TLB control */
1380 WREG32(MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
|
1381 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1382 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
1383 /* Setup L2 cache */
1384 WREG32(VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1385 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
1386 EFFECTIVE_L2_QUEUE_SIZE(7) |
1387 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1388 WREG32(VM_L2_CNTL2
, 0);
1389 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
1390 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1391 radeon_gart_table_vram_unpin(rdev
);
1394 static void cayman_pcie_gart_fini(struct radeon_device
*rdev
)
1396 cayman_pcie_gart_disable(rdev
);
1397 radeon_gart_table_vram_free(rdev
);
1398 radeon_gart_fini(rdev
);
1401 void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
1402 int ring
, u32 cp_int_cntl
)
1404 WREG32(SRBM_GFX_CNTL
, RINGID(ring
));
1405 WREG32(CP_INT_CNTL
, cp_int_cntl
);
1411 void cayman_fence_ring_emit(struct radeon_device
*rdev
,
1412 struct radeon_fence
*fence
)
1414 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
1415 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
1416 u32 cp_coher_cntl
= PACKET3_FULL_CACHE_ENA
| PACKET3_TC_ACTION_ENA
|
1417 PACKET3_SH_ACTION_ENA
;
1419 /* flush read cache over gart for this vmid */
1420 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1421 radeon_ring_write(ring
, PACKET3_ENGINE_ME
| cp_coher_cntl
);
1422 radeon_ring_write(ring
, 0xFFFFFFFF);
1423 radeon_ring_write(ring
, 0);
1424 radeon_ring_write(ring
, 10); /* poll interval */
1425 /* EVENT_WRITE_EOP - flush caches, send int */
1426 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
1427 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
1428 radeon_ring_write(ring
, lower_32_bits(addr
));
1429 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1430 radeon_ring_write(ring
, fence
->seq
);
1431 radeon_ring_write(ring
, 0);
1434 void cayman_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1436 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1437 unsigned vm_id
= ib
->vm
? ib
->vm
->ids
[ib
->ring
].id
: 0;
1438 u32 cp_coher_cntl
= PACKET3_FULL_CACHE_ENA
| PACKET3_TC_ACTION_ENA
|
1439 PACKET3_SH_ACTION_ENA
;
1441 /* set to DX10/11 mode */
1442 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1443 radeon_ring_write(ring
, 1);
1445 if (ring
->rptr_save_reg
) {
1446 uint32_t next_rptr
= ring
->wptr
+ 3 + 4 + 8;
1447 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1448 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
1449 PACKET3_SET_CONFIG_REG_START
) >> 2));
1450 radeon_ring_write(ring
, next_rptr
);
1453 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1454 radeon_ring_write(ring
,
1458 (ib
->gpu_addr
& 0xFFFFFFFC));
1459 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1460 radeon_ring_write(ring
, ib
->length_dw
| (vm_id
<< 24));
1462 /* flush read cache over gart for this vmid */
1463 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1464 radeon_ring_write(ring
, PACKET3_ENGINE_ME
| cp_coher_cntl
);
1465 radeon_ring_write(ring
, 0xFFFFFFFF);
1466 radeon_ring_write(ring
, 0);
1467 radeon_ring_write(ring
, (vm_id
<< 24) | 10); /* poll interval */
1470 static void cayman_cp_enable(struct radeon_device
*rdev
, bool enable
)
1473 WREG32(CP_ME_CNTL
, 0);
1475 if (rdev
->asic
->copy
.copy_ring_index
== RADEON_RING_TYPE_GFX_INDEX
)
1476 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
1477 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
1478 WREG32(SCRATCH_UMSK
, 0);
1479 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
1483 u32
cayman_gfx_get_rptr(struct radeon_device
*rdev
,
1484 struct radeon_ring
*ring
)
1488 if (rdev
->wb
.enabled
)
1489 rptr
= rdev
->wb
.wb
[ring
->rptr_offs
/4];
1491 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
)
1492 rptr
= RREG32(CP_RB0_RPTR
);
1493 else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
)
1494 rptr
= RREG32(CP_RB1_RPTR
);
1496 rptr
= RREG32(CP_RB2_RPTR
);
1502 u32
cayman_gfx_get_wptr(struct radeon_device
*rdev
,
1503 struct radeon_ring
*ring
)
1507 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
)
1508 wptr
= RREG32(CP_RB0_WPTR
);
1509 else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
)
1510 wptr
= RREG32(CP_RB1_WPTR
);
1512 wptr
= RREG32(CP_RB2_WPTR
);
1517 void cayman_gfx_set_wptr(struct radeon_device
*rdev
,
1518 struct radeon_ring
*ring
)
1520 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
) {
1521 WREG32(CP_RB0_WPTR
, ring
->wptr
);
1522 (void)RREG32(CP_RB0_WPTR
);
1523 } else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
) {
1524 WREG32(CP_RB1_WPTR
, ring
->wptr
);
1525 (void)RREG32(CP_RB1_WPTR
);
1527 WREG32(CP_RB2_WPTR
, ring
->wptr
);
1528 (void)RREG32(CP_RB2_WPTR
);
1532 static int cayman_cp_load_microcode(struct radeon_device
*rdev
)
1534 const __be32
*fw_data
;
1537 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1540 cayman_cp_enable(rdev
, false);
1542 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1543 WREG32(CP_PFP_UCODE_ADDR
, 0);
1544 for (i
= 0; i
< CAYMAN_PFP_UCODE_SIZE
; i
++)
1545 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1546 WREG32(CP_PFP_UCODE_ADDR
, 0);
1548 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1549 WREG32(CP_ME_RAM_WADDR
, 0);
1550 for (i
= 0; i
< CAYMAN_PM4_UCODE_SIZE
; i
++)
1551 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1553 WREG32(CP_PFP_UCODE_ADDR
, 0);
1554 WREG32(CP_ME_RAM_WADDR
, 0);
1555 WREG32(CP_ME_RAM_RADDR
, 0);
1559 static int cayman_cp_start(struct radeon_device
*rdev
)
1561 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1564 r
= radeon_ring_lock(rdev
, ring
, 7);
1566 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1569 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1570 radeon_ring_write(ring
, 0x1);
1571 radeon_ring_write(ring
, 0x0);
1572 radeon_ring_write(ring
, rdev
->config
.cayman
.max_hw_contexts
- 1);
1573 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1574 radeon_ring_write(ring
, 0);
1575 radeon_ring_write(ring
, 0);
1576 radeon_ring_unlock_commit(rdev
, ring
, false);
1578 cayman_cp_enable(rdev
, true);
1580 r
= radeon_ring_lock(rdev
, ring
, cayman_default_size
+ 19);
1582 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1586 /* setup clear context state */
1587 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1588 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1590 for (i
= 0; i
< cayman_default_size
; i
++)
1591 radeon_ring_write(ring
, cayman_default_state
[i
]);
1593 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1594 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1596 /* set clear context state */
1597 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1598 radeon_ring_write(ring
, 0);
1600 /* SQ_VTX_BASE_VTX_LOC */
1601 radeon_ring_write(ring
, 0xc0026f00);
1602 radeon_ring_write(ring
, 0x00000000);
1603 radeon_ring_write(ring
, 0x00000000);
1604 radeon_ring_write(ring
, 0x00000000);
1607 radeon_ring_write(ring
, 0xc0036f00);
1608 radeon_ring_write(ring
, 0x00000bc4);
1609 radeon_ring_write(ring
, 0xffffffff);
1610 radeon_ring_write(ring
, 0xffffffff);
1611 radeon_ring_write(ring
, 0xffffffff);
1613 radeon_ring_write(ring
, 0xc0026900);
1614 radeon_ring_write(ring
, 0x00000316);
1615 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1616 radeon_ring_write(ring
, 0x00000010); /* */
1618 radeon_ring_unlock_commit(rdev
, ring
, false);
1620 /* XXX init other rings */
1625 static void cayman_cp_fini(struct radeon_device
*rdev
)
1627 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1628 cayman_cp_enable(rdev
, false);
1629 radeon_ring_fini(rdev
, ring
);
1630 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
1633 static int cayman_cp_resume(struct radeon_device
*rdev
)
1635 static const int ridx
[] = {
1636 RADEON_RING_TYPE_GFX_INDEX
,
1637 CAYMAN_RING_TYPE_CP1_INDEX
,
1638 CAYMAN_RING_TYPE_CP2_INDEX
1640 static const unsigned cp_rb_cntl
[] = {
1645 static const unsigned cp_rb_rptr_addr
[] = {
1650 static const unsigned cp_rb_rptr_addr_hi
[] = {
1651 CP_RB0_RPTR_ADDR_HI
,
1652 CP_RB1_RPTR_ADDR_HI
,
1655 static const unsigned cp_rb_base
[] = {
1660 static const unsigned cp_rb_rptr
[] = {
1665 static const unsigned cp_rb_wptr
[] = {
1670 struct radeon_ring
*ring
;
1673 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1674 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1680 RREG32(GRBM_SOFT_RESET
);
1682 WREG32(GRBM_SOFT_RESET
, 0);
1683 RREG32(GRBM_SOFT_RESET
);
1685 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1686 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1688 /* Set the write pointer delay */
1689 WREG32(CP_RB_WPTR_DELAY
, 0);
1691 WREG32(CP_DEBUG
, (1 << 27));
1693 /* set the wb address whether it's enabled or not */
1694 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1695 WREG32(SCRATCH_UMSK
, 0xff);
1697 for (i
= 0; i
< 3; ++i
) {
1701 /* Set ring buffer size */
1702 ring
= &rdev
->ring
[ridx
[i
]];
1703 rb_cntl
= order_base_2(ring
->ring_size
/ 8);
1704 rb_cntl
|= order_base_2(RADEON_GPU_PAGE_SIZE
/8) << 8;
1706 rb_cntl
|= BUF_SWAP_32BIT
;
1708 WREG32(cp_rb_cntl
[i
], rb_cntl
);
1710 /* set the wb address whether it's enabled or not */
1711 addr
= rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
;
1712 WREG32(cp_rb_rptr_addr
[i
], addr
& 0xFFFFFFFC);
1713 WREG32(cp_rb_rptr_addr_hi
[i
], upper_32_bits(addr
) & 0xFF);
1716 /* set the rb base addr, this causes an internal reset of ALL rings */
1717 for (i
= 0; i
< 3; ++i
) {
1718 ring
= &rdev
->ring
[ridx
[i
]];
1719 WREG32(cp_rb_base
[i
], ring
->gpu_addr
>> 8);
1722 for (i
= 0; i
< 3; ++i
) {
1723 /* Initialize the ring buffer's read and write pointers */
1724 ring
= &rdev
->ring
[ridx
[i
]];
1725 WREG32_P(cp_rb_cntl
[i
], RB_RPTR_WR_ENA
, ~RB_RPTR_WR_ENA
);
1728 WREG32(cp_rb_rptr
[i
], 0);
1729 WREG32(cp_rb_wptr
[i
], ring
->wptr
);
1732 WREG32_P(cp_rb_cntl
[i
], 0, ~RB_RPTR_WR_ENA
);
1735 /* start the rings */
1736 cayman_cp_start(rdev
);
1737 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= true;
1738 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
1739 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
1740 /* this only test cp0 */
1741 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
]);
1743 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
1744 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
1745 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
1749 if (rdev
->asic
->copy
.copy_ring_index
== RADEON_RING_TYPE_GFX_INDEX
)
1750 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);
1755 u32
cayman_gpu_check_soft_reset(struct radeon_device
*rdev
)
1761 tmp
= RREG32(GRBM_STATUS
);
1762 if (tmp
& (PA_BUSY
| SC_BUSY
|
1764 TA_BUSY
| VGT_BUSY
|
1766 GDS_BUSY
| SPI_BUSY
|
1767 IA_BUSY
| IA_BUSY_NO_DMA
))
1768 reset_mask
|= RADEON_RESET_GFX
;
1770 if (tmp
& (CF_RQ_PENDING
| PF_RQ_PENDING
|
1771 CP_BUSY
| CP_COHERENCY_BUSY
))
1772 reset_mask
|= RADEON_RESET_CP
;
1774 if (tmp
& GRBM_EE_BUSY
)
1775 reset_mask
|= RADEON_RESET_GRBM
| RADEON_RESET_GFX
| RADEON_RESET_CP
;
1777 /* DMA_STATUS_REG 0 */
1778 tmp
= RREG32(DMA_STATUS_REG
+ DMA0_REGISTER_OFFSET
);
1779 if (!(tmp
& DMA_IDLE
))
1780 reset_mask
|= RADEON_RESET_DMA
;
1782 /* DMA_STATUS_REG 1 */
1783 tmp
= RREG32(DMA_STATUS_REG
+ DMA1_REGISTER_OFFSET
);
1784 if (!(tmp
& DMA_IDLE
))
1785 reset_mask
|= RADEON_RESET_DMA1
;
1788 tmp
= RREG32(SRBM_STATUS2
);
1790 reset_mask
|= RADEON_RESET_DMA
;
1792 if (tmp
& DMA1_BUSY
)
1793 reset_mask
|= RADEON_RESET_DMA1
;
1796 tmp
= RREG32(SRBM_STATUS
);
1797 if (tmp
& (RLC_RQ_PENDING
| RLC_BUSY
))
1798 reset_mask
|= RADEON_RESET_RLC
;
1801 reset_mask
|= RADEON_RESET_IH
;
1804 reset_mask
|= RADEON_RESET_SEM
;
1806 if (tmp
& GRBM_RQ_PENDING
)
1807 reset_mask
|= RADEON_RESET_GRBM
;
1810 reset_mask
|= RADEON_RESET_VMC
;
1812 if (tmp
& (MCB_BUSY
| MCB_NON_DISPLAY_BUSY
|
1813 MCC_BUSY
| MCD_BUSY
))
1814 reset_mask
|= RADEON_RESET_MC
;
1816 if (evergreen_is_display_hung(rdev
))
1817 reset_mask
|= RADEON_RESET_DISPLAY
;
1820 tmp
= RREG32(VM_L2_STATUS
);
1822 reset_mask
|= RADEON_RESET_VMC
;
1824 /* Skip MC reset as it's mostly likely not hung, just busy */
1825 if (reset_mask
& RADEON_RESET_MC
) {
1826 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
1827 reset_mask
&= ~RADEON_RESET_MC
;
1833 static void cayman_gpu_soft_reset(struct radeon_device
*rdev
, u32 reset_mask
)
1835 struct evergreen_mc_save save
;
1836 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
1839 if (reset_mask
== 0)
1842 dev_info(rdev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
1844 evergreen_print_gpu_status_regs(rdev
);
1845 dev_info(rdev
->dev
, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1847 dev_info(rdev
->dev
, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1849 dev_info(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1851 dev_info(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1854 /* Disable CP parsing/prefetching */
1855 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
1857 if (reset_mask
& RADEON_RESET_DMA
) {
1859 tmp
= RREG32(DMA_RB_CNTL
+ DMA0_REGISTER_OFFSET
);
1860 tmp
&= ~DMA_RB_ENABLE
;
1861 WREG32(DMA_RB_CNTL
+ DMA0_REGISTER_OFFSET
, tmp
);
1864 if (reset_mask
& RADEON_RESET_DMA1
) {
1866 tmp
= RREG32(DMA_RB_CNTL
+ DMA1_REGISTER_OFFSET
);
1867 tmp
&= ~DMA_RB_ENABLE
;
1868 WREG32(DMA_RB_CNTL
+ DMA1_REGISTER_OFFSET
, tmp
);
1873 evergreen_mc_stop(rdev
, &save
);
1874 if (evergreen_mc_wait_for_idle(rdev
)) {
1875 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1878 if (reset_mask
& (RADEON_RESET_GFX
| RADEON_RESET_COMPUTE
)) {
1879 grbm_soft_reset
= SOFT_RESET_CB
|
1893 if (reset_mask
& RADEON_RESET_CP
) {
1894 grbm_soft_reset
|= SOFT_RESET_CP
| SOFT_RESET_VGT
;
1896 srbm_soft_reset
|= SOFT_RESET_GRBM
;
1899 if (reset_mask
& RADEON_RESET_DMA
)
1900 srbm_soft_reset
|= SOFT_RESET_DMA
;
1902 if (reset_mask
& RADEON_RESET_DMA1
)
1903 srbm_soft_reset
|= SOFT_RESET_DMA1
;
1905 if (reset_mask
& RADEON_RESET_DISPLAY
)
1906 srbm_soft_reset
|= SOFT_RESET_DC
;
1908 if (reset_mask
& RADEON_RESET_RLC
)
1909 srbm_soft_reset
|= SOFT_RESET_RLC
;
1911 if (reset_mask
& RADEON_RESET_SEM
)
1912 srbm_soft_reset
|= SOFT_RESET_SEM
;
1914 if (reset_mask
& RADEON_RESET_IH
)
1915 srbm_soft_reset
|= SOFT_RESET_IH
;
1917 if (reset_mask
& RADEON_RESET_GRBM
)
1918 srbm_soft_reset
|= SOFT_RESET_GRBM
;
1920 if (reset_mask
& RADEON_RESET_VMC
)
1921 srbm_soft_reset
|= SOFT_RESET_VMC
;
1923 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
1924 if (reset_mask
& RADEON_RESET_MC
)
1925 srbm_soft_reset
|= SOFT_RESET_MC
;
1928 if (grbm_soft_reset
) {
1929 tmp
= RREG32(GRBM_SOFT_RESET
);
1930 tmp
|= grbm_soft_reset
;
1931 dev_info(rdev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
1932 WREG32(GRBM_SOFT_RESET
, tmp
);
1933 tmp
= RREG32(GRBM_SOFT_RESET
);
1937 tmp
&= ~grbm_soft_reset
;
1938 WREG32(GRBM_SOFT_RESET
, tmp
);
1939 tmp
= RREG32(GRBM_SOFT_RESET
);
1942 if (srbm_soft_reset
) {
1943 tmp
= RREG32(SRBM_SOFT_RESET
);
1944 tmp
|= srbm_soft_reset
;
1945 dev_info(rdev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1946 WREG32(SRBM_SOFT_RESET
, tmp
);
1947 tmp
= RREG32(SRBM_SOFT_RESET
);
1951 tmp
&= ~srbm_soft_reset
;
1952 WREG32(SRBM_SOFT_RESET
, tmp
);
1953 tmp
= RREG32(SRBM_SOFT_RESET
);
1956 /* Wait a little for things to settle down */
1959 evergreen_mc_resume(rdev
, &save
);
1962 evergreen_print_gpu_status_regs(rdev
);
1965 int cayman_asic_reset(struct radeon_device
*rdev
, bool hard
)
1970 evergreen_gpu_pci_config_reset(rdev
);
1974 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
1977 r600_set_bios_scratch_engine_hung(rdev
, true);
1979 cayman_gpu_soft_reset(rdev
, reset_mask
);
1981 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
1984 evergreen_gpu_pci_config_reset(rdev
);
1986 r600_set_bios_scratch_engine_hung(rdev
, false);
1992 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1994 * @rdev: radeon_device pointer
1995 * @ring: radeon_ring structure holding ring information
1997 * Check if the GFX engine is locked up.
1998 * Returns true if the engine appears to be locked up, false if not.
2000 bool cayman_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2002 u32 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
2004 if (!(reset_mask
& (RADEON_RESET_GFX
|
2005 RADEON_RESET_COMPUTE
|
2006 RADEON_RESET_CP
))) {
2007 radeon_ring_lockup_update(rdev
, ring
);
2010 return radeon_ring_test_lockup(rdev
, ring
);
2013 static void cayman_uvd_init(struct radeon_device
*rdev
)
2020 r
= radeon_uvd_init(rdev
);
2022 dev_err(rdev
->dev
, "failed UVD (%d) init.\n", r
);
2024 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
2025 * to early fails uvd_v2_2_resume() and thus nothing happens
2026 * there. So it is pointless to try to go through that code
2027 * hence why we disable uvd here.
2032 rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_obj
= NULL
;
2033 r600_ring_init(rdev
, &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
], 4096);
2036 static void cayman_uvd_start(struct radeon_device
*rdev
)
2043 r
= uvd_v2_2_resume(rdev
);
2045 dev_err(rdev
->dev
, "failed UVD resume (%d).\n", r
);
2048 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_UVD_INDEX
);
2050 dev_err(rdev
->dev
, "failed initializing UVD fences (%d).\n", r
);
2056 rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_size
= 0;
2059 static void cayman_uvd_resume(struct radeon_device
*rdev
)
2061 struct radeon_ring
*ring
;
2064 if (!rdev
->has_uvd
|| !rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_size
)
2067 ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2068 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, 0, PACKET0(UVD_NO_OP
, 0));
2070 dev_err(rdev
->dev
, "failed initializing UVD ring (%d).\n", r
);
2073 r
= uvd_v1_0_init(rdev
);
2075 dev_err(rdev
->dev
, "failed initializing UVD (%d).\n", r
);
2080 static void cayman_vce_init(struct radeon_device
*rdev
)
2084 /* Only set for CHIP_ARUBA */
2088 r
= radeon_vce_init(rdev
);
2090 dev_err(rdev
->dev
, "failed VCE (%d) init.\n", r
);
2092 * At this point rdev->vce.vcpu_bo is NULL which trickles down
2093 * to early fails cayman_vce_start() and thus nothing happens
2094 * there. So it is pointless to try to go through that code
2095 * hence why we disable vce here.
2100 rdev
->ring
[TN_RING_TYPE_VCE1_INDEX
].ring_obj
= NULL
;
2101 r600_ring_init(rdev
, &rdev
->ring
[TN_RING_TYPE_VCE1_INDEX
], 4096);
2102 rdev
->ring
[TN_RING_TYPE_VCE2_INDEX
].ring_obj
= NULL
;
2103 r600_ring_init(rdev
, &rdev
->ring
[TN_RING_TYPE_VCE2_INDEX
], 4096);
2106 static void cayman_vce_start(struct radeon_device
*rdev
)
2113 r
= radeon_vce_resume(rdev
);
2115 dev_err(rdev
->dev
, "failed VCE resume (%d).\n", r
);
2118 r
= vce_v1_0_resume(rdev
);
2120 dev_err(rdev
->dev
, "failed VCE resume (%d).\n", r
);
2123 r
= radeon_fence_driver_start_ring(rdev
, TN_RING_TYPE_VCE1_INDEX
);
2125 dev_err(rdev
->dev
, "failed initializing VCE1 fences (%d).\n", r
);
2128 r
= radeon_fence_driver_start_ring(rdev
, TN_RING_TYPE_VCE2_INDEX
);
2130 dev_err(rdev
->dev
, "failed initializing VCE2 fences (%d).\n", r
);
2136 rdev
->ring
[TN_RING_TYPE_VCE1_INDEX
].ring_size
= 0;
2137 rdev
->ring
[TN_RING_TYPE_VCE2_INDEX
].ring_size
= 0;
2140 static void cayman_vce_resume(struct radeon_device
*rdev
)
2142 struct radeon_ring
*ring
;
2145 if (!rdev
->has_vce
|| !rdev
->ring
[TN_RING_TYPE_VCE1_INDEX
].ring_size
)
2148 ring
= &rdev
->ring
[TN_RING_TYPE_VCE1_INDEX
];
2149 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, 0, 0x0);
2151 dev_err(rdev
->dev
, "failed initializing VCE1 ring (%d).\n", r
);
2154 ring
= &rdev
->ring
[TN_RING_TYPE_VCE2_INDEX
];
2155 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, 0, 0x0);
2157 dev_err(rdev
->dev
, "failed initializing VCE1 ring (%d).\n", r
);
2160 r
= vce_v1_0_init(rdev
);
2162 dev_err(rdev
->dev
, "failed initializing VCE (%d).\n", r
);
2167 static int cayman_startup(struct radeon_device
*rdev
)
2169 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2172 /* enable pcie gen2 link */
2173 evergreen_pcie_gen2_enable(rdev
);
2175 evergreen_program_aspm(rdev
);
2177 /* scratch needs to be initialized before MC */
2178 r
= r600_vram_scratch_init(rdev
);
2182 evergreen_mc_program(rdev
);
2184 if (!(rdev
->flags
& RADEON_IS_IGP
) && !rdev
->pm
.dpm_enabled
) {
2185 r
= ni_mc_load_microcode(rdev
);
2187 DRM_ERROR("Failed to load MC firmware!\n");
2192 r
= cayman_pcie_gart_enable(rdev
);
2195 cayman_gpu_init(rdev
);
2197 /* allocate rlc buffers */
2198 if (rdev
->flags
& RADEON_IS_IGP
) {
2199 rdev
->rlc
.reg_list
= tn_rlc_save_restore_register_list
;
2200 rdev
->rlc
.reg_list_size
=
2201 (u32
)ARRAY_SIZE(tn_rlc_save_restore_register_list
);
2202 rdev
->rlc
.cs_data
= cayman_cs_data
;
2203 r
= sumo_rlc_init(rdev
);
2205 DRM_ERROR("Failed to init rlc BOs!\n");
2210 /* allocate wb buffer */
2211 r
= radeon_wb_init(rdev
);
2215 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2217 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2221 cayman_uvd_start(rdev
);
2222 cayman_vce_start(rdev
);
2224 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
2226 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2230 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
2232 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2236 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
2238 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
2242 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_DMA1_INDEX
);
2244 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
2249 if (!rdev
->irq
.installed
) {
2250 r
= radeon_irq_kms_init(rdev
);
2255 r
= r600_irq_init(rdev
);
2257 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2258 radeon_irq_kms_fini(rdev
);
2261 evergreen_irq_set(rdev
);
2263 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
2268 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2269 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
2270 DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
2274 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
2275 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, CAYMAN_WB_DMA1_RPTR_OFFSET
,
2276 DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
2280 r
= cayman_cp_load_microcode(rdev
);
2283 r
= cayman_cp_resume(rdev
);
2287 r
= cayman_dma_resume(rdev
);
2291 cayman_uvd_resume(rdev
);
2292 cayman_vce_resume(rdev
);
2294 r
= radeon_ib_pool_init(rdev
);
2296 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
2300 r
= radeon_vm_manager_init(rdev
);
2302 dev_err(rdev
->dev
, "vm manager initialization failed (%d).\n", r
);
2306 r
= radeon_audio_init(rdev
);
2313 int cayman_resume(struct radeon_device
*rdev
)
2317 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2318 * posting will perform necessary task to bring back GPU into good
2322 atom_asic_init(rdev
->mode_info
.atom_context
);
2324 /* init golden registers */
2325 ni_init_golden_registers(rdev
);
2327 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
2328 radeon_pm_resume(rdev
);
2330 rdev
->accel_working
= true;
2331 r
= cayman_startup(rdev
);
2333 DRM_ERROR("cayman startup failed on resume\n");
2334 rdev
->accel_working
= false;
2340 int cayman_suspend(struct radeon_device
*rdev
)
2342 radeon_pm_suspend(rdev
);
2343 radeon_audio_fini(rdev
);
2344 radeon_vm_manager_fini(rdev
);
2345 cayman_cp_enable(rdev
, false);
2346 cayman_dma_stop(rdev
);
2347 if (rdev
->has_uvd
) {
2348 uvd_v1_0_fini(rdev
);
2349 radeon_uvd_suspend(rdev
);
2351 evergreen_irq_suspend(rdev
);
2352 radeon_wb_disable(rdev
);
2353 cayman_pcie_gart_disable(rdev
);
2357 /* Plan is to move initialization in that function and use
2358 * helper function so that radeon_device_init pretty much
2359 * do nothing more than calling asic specific function. This
2360 * should also allow to remove a bunch of callback function
2363 int cayman_init(struct radeon_device
*rdev
)
2365 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2369 if (!radeon_get_bios(rdev
)) {
2370 if (ASIC_IS_AVIVO(rdev
))
2373 /* Must be an ATOMBIOS */
2374 if (!rdev
->is_atom_bios
) {
2375 dev_err(rdev
->dev
, "Expecting atombios for cayman GPU\n");
2378 r
= radeon_atombios_init(rdev
);
2382 /* Post card if necessary */
2383 if (!radeon_card_posted(rdev
)) {
2385 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2388 DRM_INFO("GPU not posted. posting now...\n");
2389 atom_asic_init(rdev
->mode_info
.atom_context
);
2391 /* init golden registers */
2392 ni_init_golden_registers(rdev
);
2393 /* Initialize scratch registers */
2394 r600_scratch_init(rdev
);
2395 /* Initialize surface registers */
2396 radeon_surface_init(rdev
);
2397 /* Initialize clocks */
2398 radeon_get_clock_info(rdev
->ddev
);
2400 r
= radeon_fence_driver_init(rdev
);
2403 /* initialize memory controller */
2404 r
= evergreen_mc_init(rdev
);
2407 /* Memory manager */
2408 r
= radeon_bo_init(rdev
);
2412 if (rdev
->flags
& RADEON_IS_IGP
) {
2413 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2414 r
= ni_init_microcode(rdev
);
2416 DRM_ERROR("Failed to load firmware!\n");
2421 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
2422 r
= ni_init_microcode(rdev
);
2424 DRM_ERROR("Failed to load firmware!\n");
2430 /* Initialize power management */
2431 radeon_pm_init(rdev
);
2433 ring
->ring_obj
= NULL
;
2434 r600_ring_init(rdev
, ring
, 1024 * 1024);
2436 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2437 ring
->ring_obj
= NULL
;
2438 r600_ring_init(rdev
, ring
, 64 * 1024);
2440 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
2441 ring
->ring_obj
= NULL
;
2442 r600_ring_init(rdev
, ring
, 64 * 1024);
2444 cayman_uvd_init(rdev
);
2445 cayman_vce_init(rdev
);
2447 rdev
->ih
.ring_obj
= NULL
;
2448 r600_ih_ring_init(rdev
, 64 * 1024);
2450 r
= r600_pcie_gart_init(rdev
);
2454 rdev
->accel_working
= true;
2455 r
= cayman_startup(rdev
);
2457 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2458 cayman_cp_fini(rdev
);
2459 cayman_dma_fini(rdev
);
2460 r600_irq_fini(rdev
);
2461 if (rdev
->flags
& RADEON_IS_IGP
)
2462 sumo_rlc_fini(rdev
);
2463 radeon_wb_fini(rdev
);
2464 radeon_ib_pool_fini(rdev
);
2465 radeon_vm_manager_fini(rdev
);
2466 radeon_irq_kms_fini(rdev
);
2467 cayman_pcie_gart_fini(rdev
);
2468 rdev
->accel_working
= false;
2471 /* Don't start up if the MC ucode is missing.
2472 * The default clocks and voltages before the MC ucode
2473 * is loaded are not suffient for advanced operations.
2475 * We can skip this check for TN, because there is no MC
2478 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
2479 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2486 void cayman_fini(struct radeon_device
*rdev
)
2488 radeon_pm_fini(rdev
);
2489 cayman_cp_fini(rdev
);
2490 cayman_dma_fini(rdev
);
2491 r600_irq_fini(rdev
);
2492 if (rdev
->flags
& RADEON_IS_IGP
)
2493 sumo_rlc_fini(rdev
);
2494 radeon_wb_fini(rdev
);
2495 radeon_vm_manager_fini(rdev
);
2496 radeon_ib_pool_fini(rdev
);
2497 radeon_irq_kms_fini(rdev
);
2498 uvd_v1_0_fini(rdev
);
2499 radeon_uvd_fini(rdev
);
2501 radeon_vce_fini(rdev
);
2502 cayman_pcie_gart_fini(rdev
);
2503 r600_vram_scratch_fini(rdev
);
2504 radeon_gem_fini(rdev
);
2505 radeon_fence_driver_fini(rdev
);
2506 radeon_bo_fini(rdev
);
2507 radeon_atombios_fini(rdev
);
2508 ni_fini_microcode(rdev
);
2516 int cayman_vm_init(struct radeon_device
*rdev
)
2519 rdev
->vm_manager
.nvm
= 8;
2520 /* base offset of vram pages */
2521 if (rdev
->flags
& RADEON_IS_IGP
) {
2522 u64 tmp
= RREG32(FUS_MC_VM_FB_OFFSET
);
2524 rdev
->vm_manager
.vram_base_offset
= tmp
;
2526 rdev
->vm_manager
.vram_base_offset
= 0;
2530 void cayman_vm_fini(struct radeon_device
*rdev
)
2535 * cayman_vm_decode_fault - print human readable fault info
2537 * @rdev: radeon_device pointer
2538 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2539 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2541 * Print human readable fault information (cayman/TN).
2543 void cayman_vm_decode_fault(struct radeon_device
*rdev
,
2544 u32 status
, u32 addr
)
2546 u32 mc_id
= (status
& MEMORY_CLIENT_ID_MASK
) >> MEMORY_CLIENT_ID_SHIFT
;
2547 u32 vmid
= (status
& FAULT_VMID_MASK
) >> FAULT_VMID_SHIFT
;
2548 u32 protections
= (status
& PROTECTIONS_MASK
) >> PROTECTIONS_SHIFT
;
2640 block
= "TC_TFETCH";
2650 block
= "TC_VFETCH";
2689 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2690 protections
, vmid
, addr
,
2691 (status
& MEMORY_CLIENT_RW_MASK
) ? "write" : "read",
2696 * cayman_vm_flush - vm flush using the CP
2698 * @rdev: radeon_device pointer
2700 * Update the page table base and flush the VM TLB
2701 * using the CP (cayman-si).
2703 void cayman_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
2704 unsigned vm_id
, uint64_t pd_addr
)
2706 radeon_ring_write(ring
, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (vm_id
<< 2), 0));
2707 radeon_ring_write(ring
, pd_addr
>> 12);
2709 /* flush hdp cache */
2710 radeon_ring_write(ring
, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0));
2711 radeon_ring_write(ring
, 0x1);
2713 /* bits 0-7 are the VM contexts0-7 */
2714 radeon_ring_write(ring
, PACKET0(VM_INVALIDATE_REQUEST
, 0));
2715 radeon_ring_write(ring
, 1 << vm_id
);
2717 /* wait for the invalidate to complete */
2718 radeon_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
2719 radeon_ring_write(ring
, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2720 WAIT_REG_MEM_ENGINE(0))); /* me */
2721 radeon_ring_write(ring
, VM_INVALIDATE_REQUEST
>> 2);
2722 radeon_ring_write(ring
, 0);
2723 radeon_ring_write(ring
, 0); /* ref */
2724 radeon_ring_write(ring
, 0); /* mask */
2725 radeon_ring_write(ring
, 0x20); /* poll interval */
2727 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2728 radeon_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
2729 radeon_ring_write(ring
, 0x0);
2732 int tn_set_vce_clocks(struct radeon_device
*rdev
, u32 evclk
, u32 ecclk
)
2734 struct atom_clock_dividers dividers
;
2737 r
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
2738 ecclk
, false, ÷rs
);
2742 for (i
= 0; i
< 100; i
++) {
2743 if (RREG32(CG_ECLK_STATUS
) & ECLK_STATUS
)
2750 WREG32_P(CG_ECLK_CNTL
, dividers
.post_div
, ~(ECLK_DIR_CNTL_EN
|ECLK_DIVIDER_MASK
));
2752 for (i
= 0; i
< 100; i
++) {
2753 if (RREG32(CG_ECLK_STATUS
) & ECLK_STATUS
)