2 * Copyright © 2016-2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/types.h>
27 #include "intel_huc.h"
34 * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
35 * Efficiency Video Coding) operations. Userspace can use the firmware
36 * capabilities by adding HuC specific commands to batch buffers.
39 * The same firmware loader is used as the GuC. However, the actual
40 * loading to HW is deferred until GEM initialization is done.
42 * Note that HuC firmware loading must be done before GuC loading.
45 #define BXT_HUC_FW_MAJOR 01
46 #define BXT_HUC_FW_MINOR 07
47 #define BXT_BLD_NUM 1398
49 #define SKL_HUC_FW_MAJOR 01
50 #define SKL_HUC_FW_MINOR 07
51 #define SKL_BLD_NUM 1398
53 #define KBL_HUC_FW_MAJOR 02
54 #define KBL_HUC_FW_MINOR 00
55 #define KBL_BLD_NUM 1810
57 #define HUC_FW_PATH(platform, major, minor, bld_num) \
58 "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
59 __stringify(minor) "_" __stringify(bld_num) ".bin"
61 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
62 SKL_HUC_FW_MINOR, SKL_BLD_NUM)
63 MODULE_FIRMWARE(I915_SKL_HUC_UCODE
);
65 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
66 BXT_HUC_FW_MINOR, BXT_BLD_NUM)
67 MODULE_FIRMWARE(I915_BXT_HUC_UCODE
);
69 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
70 KBL_HUC_FW_MINOR, KBL_BLD_NUM)
71 MODULE_FIRMWARE(I915_KBL_HUC_UCODE
);
74 * intel_huc_select_fw() - selects HuC firmware for loading
75 * @huc: intel_huc struct
77 void intel_huc_select_fw(struct intel_huc
*huc
)
79 struct drm_i915_private
*dev_priv
= huc_to_i915(huc
);
81 intel_uc_fw_init(&huc
->fw
, INTEL_UC_FW_TYPE_HUC
);
83 if (i915_modparams
.huc_firmware_path
) {
84 huc
->fw
.path
= i915_modparams
.huc_firmware_path
;
85 huc
->fw
.major_ver_wanted
= 0;
86 huc
->fw
.minor_ver_wanted
= 0;
87 } else if (IS_SKYLAKE(dev_priv
)) {
88 huc
->fw
.path
= I915_SKL_HUC_UCODE
;
89 huc
->fw
.major_ver_wanted
= SKL_HUC_FW_MAJOR
;
90 huc
->fw
.minor_ver_wanted
= SKL_HUC_FW_MINOR
;
91 } else if (IS_BROXTON(dev_priv
)) {
92 huc
->fw
.path
= I915_BXT_HUC_UCODE
;
93 huc
->fw
.major_ver_wanted
= BXT_HUC_FW_MAJOR
;
94 huc
->fw
.minor_ver_wanted
= BXT_HUC_FW_MINOR
;
95 } else if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) {
96 huc
->fw
.path
= I915_KBL_HUC_UCODE
;
97 huc
->fw
.major_ver_wanted
= KBL_HUC_FW_MAJOR
;
98 huc
->fw
.minor_ver_wanted
= KBL_HUC_FW_MINOR
;
100 DRM_ERROR("No HuC firmware known for platform with HuC!\n");
106 * huc_ucode_xfer() - DMA's the firmware
107 * @dev_priv: the drm_i915_private device
109 * Transfer the firmware image to RAM for execution by the microcontroller.
111 * Return: 0 on success, non-zero on failure
113 static int huc_ucode_xfer(struct intel_uc_fw
*huc_fw
, struct i915_vma
*vma
)
115 struct intel_huc
*huc
= container_of(huc_fw
, struct intel_huc
, fw
);
116 struct drm_i915_private
*dev_priv
= huc_to_i915(huc
);
117 unsigned long offset
= 0;
121 GEM_BUG_ON(huc_fw
->type
!= INTEL_UC_FW_TYPE_HUC
);
123 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
125 /* Set the source address for the uCode */
126 offset
= guc_ggtt_offset(vma
) + huc_fw
->header_offset
;
127 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
128 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
130 /* Hardware doesn't look at destination address for HuC. Set it to 0,
131 * but still program the correct address space.
133 I915_WRITE(DMA_ADDR_1_LOW
, 0);
134 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
136 size
= huc_fw
->header_size
+ huc_fw
->ucode_size
;
137 I915_WRITE(DMA_COPY_SIZE
, size
);
140 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(HUC_UKERNEL
| START_DMA
));
142 /* Wait for DMA to finish */
143 ret
= wait_for((I915_READ(DMA_CTRL
) & START_DMA
) == 0, 100);
145 DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret
);
147 /* Disable the bits once DMA is over */
148 I915_WRITE(DMA_CTRL
, _MASKED_BIT_DISABLE(HUC_UKERNEL
));
150 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
156 * intel_huc_init_hw() - load HuC uCode to device
157 * @huc: intel_huc structure
159 * Called from guc_setup() during driver loading and also after a GPU reset.
160 * Be note that HuC loading must be done before GuC loading.
162 * The firmware image should have already been fetched into memory by the
163 * earlier call to intel_huc_init(), so here we need only check that
164 * is succeeded, and then transfer the image to the h/w.
167 void intel_huc_init_hw(struct intel_huc
*huc
)
169 intel_uc_fw_upload(&huc
->fw
, huc_ucode_xfer
);
173 * intel_huc_auth() - Authenticate HuC uCode
174 * @huc: intel_huc structure
176 * Called after HuC and GuC firmware loading during intel_uc_init_hw().
178 * This function pins HuC firmware image object into GGTT.
179 * Then it invokes GuC action to authenticate passing the offset to RSA
180 * signature through intel_guc_auth_huc(). It then waits for 50ms for
181 * firmware verification ACK and unpins the object.
183 void intel_huc_auth(struct intel_huc
*huc
)
185 struct drm_i915_private
*i915
= huc_to_i915(huc
);
186 struct intel_guc
*guc
= &i915
->guc
;
187 struct i915_vma
*vma
;
190 if (huc
->fw
.load_status
!= INTEL_UC_FIRMWARE_SUCCESS
)
193 vma
= i915_gem_object_ggtt_pin(huc
->fw
.obj
, NULL
, 0, 0,
194 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
196 DRM_ERROR("failed to pin huc fw object %d\n",
201 ret
= intel_guc_auth_huc(guc
,
202 guc_ggtt_offset(vma
) + huc
->fw
.rsa_offset
);
204 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret
);
208 /* Check authentication status, it should be done by now */
209 ret
= intel_wait_for_register(i915
,
215 DRM_ERROR("HuC: Authentication failed %d\n", ret
);