2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
30 #include "intel_guc_fw.h"
33 #define SKL_FW_MAJOR 6
34 #define SKL_FW_MINOR 1
36 #define BXT_FW_MAJOR 8
37 #define BXT_FW_MINOR 7
39 #define KBL_FW_MAJOR 9
40 #define KBL_FW_MINOR 14
42 #define GUC_FW_PATH(platform, major, minor) \
43 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
45 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
46 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
48 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
49 MODULE_FIRMWARE(I915_BXT_GUC_UCODE
);
51 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
52 MODULE_FIRMWARE(I915_KBL_GUC_UCODE
);
55 * intel_guc_fw_select() - selects GuC firmware for uploading
57 * @guc: intel_guc struct
59 * Return: zero when we know firmware, non-zero in other case
61 int intel_guc_fw_select(struct intel_guc
*guc
)
63 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
65 intel_uc_fw_init(&guc
->fw
, INTEL_UC_FW_TYPE_GUC
);
67 if (i915_modparams
.guc_firmware_path
) {
68 guc
->fw
.path
= i915_modparams
.guc_firmware_path
;
69 guc
->fw
.major_ver_wanted
= 0;
70 guc
->fw
.minor_ver_wanted
= 0;
71 } else if (IS_SKYLAKE(dev_priv
)) {
72 guc
->fw
.path
= I915_SKL_GUC_UCODE
;
73 guc
->fw
.major_ver_wanted
= SKL_FW_MAJOR
;
74 guc
->fw
.minor_ver_wanted
= SKL_FW_MINOR
;
75 } else if (IS_BROXTON(dev_priv
)) {
76 guc
->fw
.path
= I915_BXT_GUC_UCODE
;
77 guc
->fw
.major_ver_wanted
= BXT_FW_MAJOR
;
78 guc
->fw
.minor_ver_wanted
= BXT_FW_MINOR
;
79 } else if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) {
80 guc
->fw
.path
= I915_KBL_GUC_UCODE
;
81 guc
->fw
.major_ver_wanted
= KBL_FW_MAJOR
;
82 guc
->fw
.minor_ver_wanted
= KBL_FW_MINOR
;
84 DRM_ERROR("No GuC firmware known for platform with GuC!\n");
92 * Read the GuC status register (GUC_STATUS) and store it in the
93 * specified location; then return a boolean indicating whether
94 * the value matches either of two values representing completion
95 * of the GuC boot process.
97 * This is used for polling the GuC status in a wait_for()
100 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
103 u32 val
= I915_READ(GUC_STATUS
);
104 u32 uk_val
= val
& GS_UKERNEL_MASK
;
106 return (uk_val
== GS_UKERNEL_READY
||
107 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
111 * Transfer the firmware image to RAM for execution by the microcontroller.
113 * Architecturally, the DMA engine is bidirectional, and can potentially even
114 * transfer between GTT locations. This functionality is left out of the API
115 * for now as there is no need for it.
117 * Note that GuC needs the CSS header plus uKernel code to be copied by the
118 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
120 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
,
121 struct i915_vma
*vma
)
123 struct intel_uc_fw
*guc_fw
= &dev_priv
->guc
.fw
;
124 unsigned long offset
;
125 struct sg_table
*sg
= vma
->pages
;
126 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
129 /* where RSA signature starts */
130 offset
= guc_fw
->rsa_offset
;
132 /* Copy RSA signature from the fw image to HW for verification */
133 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
134 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
135 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
137 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
138 * other components */
139 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
141 /* Set the source address for the new blob */
142 offset
= guc_ggtt_offset(vma
) + guc_fw
->header_offset
;
143 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
144 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
147 * Set the DMA destination. Current uCode expects the code to be
148 * loaded at 8k; locations below this are used for the stack.
150 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
151 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
153 /* Finally start the DMA */
154 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
157 * Wait for the DMA to complete & the GuC to start up.
158 * NB: Docs recommend not using the interrupt for completion.
159 * Measurements indicate this should take no more than 20ms, so a
160 * timeout here indicates that the GuC has failed and is unusable.
161 * (Higher levels of the driver will attempt to fall back to
162 * execlist mode if this happens.)
164 ret
= wait_for(guc_ucode_response(dev_priv
, &status
), 100);
166 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
167 I915_READ(DMA_CTRL
), status
);
169 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
170 DRM_ERROR("GuC firmware signature verification failed\n");
174 DRM_DEBUG_DRIVER("returning %d\n", ret
);
180 * Load the GuC firmware blob into the MinuteIA.
182 static int guc_ucode_xfer(struct intel_uc_fw
*guc_fw
, struct i915_vma
*vma
)
184 struct intel_guc
*guc
= container_of(guc_fw
, struct intel_guc
, fw
);
185 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
188 GEM_BUG_ON(guc_fw
->type
!= INTEL_UC_FW_TYPE_GUC
);
190 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
192 /* Enable MIA caching. GuC clock gating is disabled. */
193 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
195 /* WaDisableMinuteIaClockGating:bxt */
196 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
197 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
198 ~GUC_ENABLE_MIA_CLOCK_GATING
));
201 /* WaC6DisallowByGfxPause:bxt */
202 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
203 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
205 if (IS_GEN9_LP(dev_priv
))
206 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
208 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
210 if (IS_GEN9(dev_priv
)) {
211 /* DOP Clock Gating Enable for GuC clocks */
212 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
213 I915_READ(GEN7_MISCCPCTL
)));
215 /* allows for 5us (in 10ns units) before GT can go to RC6 */
216 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
219 ret
= guc_ucode_xfer_dma(dev_priv
, vma
);
221 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
227 * intel_guc_fw_upload() - finish preparing the GuC for activity
228 * @guc: intel_guc structure
230 * Called during driver loading and also after a GPU reset.
232 * The main action required here it to load the GuC uCode into the device.
233 * The firmware image should have already been fetched into memory by the
234 * earlier call to intel_guc_init(), so here we need only check that
235 * worked, and then transfer the image to the h/w.
237 * Return: non-zero code on error
239 int intel_guc_fw_upload(struct intel_guc
*guc
)
241 return intel_uc_fw_upload(&guc
->fw
, guc_ucode_xfer
);