2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
30 #include "i915_selftest.h"
32 #define GEN_DEFAULT_PIPEOFFSETS \
33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
39 #define GEN_CHV_PIPEOFFSETS \
40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
41 CHV_PIPE_C_OFFSET }, \
42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
43 CHV_TRANSCODER_C_OFFSET, }, \
44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
45 CHV_PALETTE_C_OFFSET }
47 #define CURSOR_OFFSETS \
48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
50 #define IVB_CURSOR_OFFSETS \
51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
58 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
60 /* Keep in gen based order, and chronological order within a gen */
62 #define GEN_DEFAULT_PAGE_SIZES \
63 .page_sizes = I915_GTT_PAGE_SIZE_4K
65 #define GEN2_FEATURES \
66 .gen = 2, .num_pipes = 1, \
67 .has_overlay = 1, .overlay_needs_physical = 1, \
68 .has_gmch_display = 1, \
69 .hws_needs_physical = 1, \
70 .unfenced_needs_alignment = 1, \
71 .ring_mask = RENDER_RING, \
73 GEN_DEFAULT_PIPEOFFSETS, \
74 GEN_DEFAULT_PAGE_SIZES, \
77 static const struct intel_device_info intel_i830_info
= {
79 .platform
= INTEL_I830
,
80 .is_mobile
= 1, .cursor_needs_physical
= 1,
81 .num_pipes
= 2, /* legal, last one wins */
84 static const struct intel_device_info intel_i845g_info
= {
86 .platform
= INTEL_I845G
,
89 static const struct intel_device_info intel_i85x_info
= {
91 .platform
= INTEL_I85X
, .is_mobile
= 1,
92 .num_pipes
= 2, /* legal, last one wins */
93 .cursor_needs_physical
= 1,
97 static const struct intel_device_info intel_i865g_info
= {
99 .platform
= INTEL_I865G
,
102 #define GEN3_FEATURES \
103 .gen = 3, .num_pipes = 2, \
104 .has_gmch_display = 1, \
105 .ring_mask = RENDER_RING, \
107 GEN_DEFAULT_PIPEOFFSETS, \
108 GEN_DEFAULT_PAGE_SIZES, \
111 static const struct intel_device_info intel_i915g_info
= {
113 .platform
= INTEL_I915G
, .cursor_needs_physical
= 1,
114 .has_overlay
= 1, .overlay_needs_physical
= 1,
115 .hws_needs_physical
= 1,
116 .unfenced_needs_alignment
= 1,
119 static const struct intel_device_info intel_i915gm_info
= {
121 .platform
= INTEL_I915GM
,
123 .cursor_needs_physical
= 1,
124 .has_overlay
= 1, .overlay_needs_physical
= 1,
127 .hws_needs_physical
= 1,
128 .unfenced_needs_alignment
= 1,
131 static const struct intel_device_info intel_i945g_info
= {
133 .platform
= INTEL_I945G
,
134 .has_hotplug
= 1, .cursor_needs_physical
= 1,
135 .has_overlay
= 1, .overlay_needs_physical
= 1,
136 .hws_needs_physical
= 1,
137 .unfenced_needs_alignment
= 1,
140 static const struct intel_device_info intel_i945gm_info
= {
142 .platform
= INTEL_I945GM
, .is_mobile
= 1,
143 .has_hotplug
= 1, .cursor_needs_physical
= 1,
144 .has_overlay
= 1, .overlay_needs_physical
= 1,
147 .hws_needs_physical
= 1,
148 .unfenced_needs_alignment
= 1,
151 static const struct intel_device_info intel_g33_info
= {
153 .platform
= INTEL_G33
,
158 static const struct intel_device_info intel_pineview_info
= {
160 .platform
= INTEL_PINEVIEW
, .is_mobile
= 1,
165 #define GEN4_FEATURES \
166 .gen = 4, .num_pipes = 2, \
168 .has_gmch_display = 1, \
169 .ring_mask = RENDER_RING, \
171 GEN_DEFAULT_PIPEOFFSETS, \
172 GEN_DEFAULT_PAGE_SIZES, \
175 static const struct intel_device_info intel_i965g_info
= {
177 .platform
= INTEL_I965G
,
179 .hws_needs_physical
= 1,
183 static const struct intel_device_info intel_i965gm_info
= {
185 .platform
= INTEL_I965GM
,
186 .is_mobile
= 1, .has_fbc
= 1,
189 .hws_needs_physical
= 1,
193 static const struct intel_device_info intel_g45_info
= {
195 .platform
= INTEL_G45
,
196 .ring_mask
= RENDER_RING
| BSD_RING
,
199 static const struct intel_device_info intel_gm45_info
= {
201 .platform
= INTEL_GM45
,
202 .is_mobile
= 1, .has_fbc
= 1,
204 .ring_mask
= RENDER_RING
| BSD_RING
,
207 #define GEN5_FEATURES \
208 .gen = 5, .num_pipes = 2, \
210 .ring_mask = RENDER_RING | BSD_RING, \
212 GEN_DEFAULT_PIPEOFFSETS, \
213 GEN_DEFAULT_PAGE_SIZES, \
216 static const struct intel_device_info intel_ironlake_d_info
= {
218 .platform
= INTEL_IRONLAKE
,
221 static const struct intel_device_info intel_ironlake_m_info
= {
223 .platform
= INTEL_IRONLAKE
,
224 .is_mobile
= 1, .has_fbc
= 1,
227 #define GEN6_FEATURES \
228 .gen = 6, .num_pipes = 2, \
231 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
235 .has_aliasing_ppgtt = 1, \
236 GEN_DEFAULT_PIPEOFFSETS, \
237 GEN_DEFAULT_PAGE_SIZES, \
240 #define SNB_D_PLATFORM \
242 .platform = INTEL_SANDYBRIDGE
244 static const struct intel_device_info intel_sandybridge_d_gt1_info
= {
249 static const struct intel_device_info intel_sandybridge_d_gt2_info
= {
254 #define SNB_M_PLATFORM \
256 .platform = INTEL_SANDYBRIDGE, \
260 static const struct intel_device_info intel_sandybridge_m_gt1_info
= {
265 static const struct intel_device_info intel_sandybridge_m_gt2_info
= {
270 #define GEN7_FEATURES \
271 .gen = 7, .num_pipes = 3, \
274 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
278 .has_aliasing_ppgtt = 1, \
279 .has_full_ppgtt = 1, \
280 GEN_DEFAULT_PIPEOFFSETS, \
281 GEN_DEFAULT_PAGE_SIZES, \
284 #define IVB_D_PLATFORM \
286 .platform = INTEL_IVYBRIDGE, \
289 static const struct intel_device_info intel_ivybridge_d_gt1_info
= {
294 static const struct intel_device_info intel_ivybridge_d_gt2_info
= {
299 #define IVB_M_PLATFORM \
301 .platform = INTEL_IVYBRIDGE, \
305 static const struct intel_device_info intel_ivybridge_m_gt1_info
= {
310 static const struct intel_device_info intel_ivybridge_m_gt2_info
= {
315 static const struct intel_device_info intel_ivybridge_q_info
= {
317 .platform
= INTEL_IVYBRIDGE
,
319 .num_pipes
= 0, /* legal, last one wins */
323 static const struct intel_device_info intel_valleyview_info
= {
324 .platform
= INTEL_VALLEYVIEW
,
331 .has_gmch_display
= 1,
333 .has_aliasing_ppgtt
= 1,
336 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
337 .display_mmio_offset
= VLV_DISPLAY_BASE
,
338 GEN_DEFAULT_PAGE_SIZES
,
339 GEN_DEFAULT_PIPEOFFSETS
,
343 #define G75_FEATURES \
345 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
349 .has_resource_streamer = 1, \
351 .has_rc6p = 0 /* RC6p removed-by HSW */, \
354 #define HSW_PLATFORM \
356 .platform = INTEL_HASWELL, \
359 static const struct intel_device_info intel_haswell_gt1_info
= {
364 static const struct intel_device_info intel_haswell_gt2_info
= {
369 static const struct intel_device_info intel_haswell_gt3_info
= {
374 #define GEN8_FEATURES \
377 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
378 I915_GTT_PAGE_SIZE_2M, \
379 .has_logical_ring_contexts = 1, \
380 .has_full_48bit_ppgtt = 1, \
381 .has_64bit_reloc = 1, \
382 .has_reset_engine = 1
384 #define BDW_PLATFORM \
387 .platform = INTEL_BROADWELL
389 static const struct intel_device_info intel_broadwell_gt1_info
= {
394 static const struct intel_device_info intel_broadwell_gt2_info
= {
399 static const struct intel_device_info intel_broadwell_rsvd_info
= {
402 /* According to the device ID those devices are GT3, they were
403 * previously treated as not GT3, keep it like that.
407 static const struct intel_device_info intel_broadwell_gt3_info
= {
410 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
413 static const struct intel_device_info intel_cherryview_info
= {
414 .gen
= 8, .num_pipes
= 3,
417 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
418 .platform
= INTEL_CHERRYVIEW
,
419 .has_64bit_reloc
= 1,
422 .has_resource_streamer
= 1,
424 .has_logical_ring_contexts
= 1,
425 .has_gmch_display
= 1,
426 .has_aliasing_ppgtt
= 1,
428 .has_reset_engine
= 1,
430 .display_mmio_offset
= VLV_DISPLAY_BASE
,
431 GEN_DEFAULT_PAGE_SIZES
,
437 #define GEN9_DEFAULT_PAGE_SIZES \
438 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
439 I915_GTT_PAGE_SIZE_64K | \
440 I915_GTT_PAGE_SIZE_2M
442 #define GEN9_FEATURES \
444 GEN9_DEFAULT_PAGE_SIZES, \
445 .has_logical_ring_preemption = 1, \
451 #define SKL_PLATFORM \
454 .platform = INTEL_SKYLAKE
456 static const struct intel_device_info intel_skylake_gt1_info
= {
461 static const struct intel_device_info intel_skylake_gt2_info
= {
466 #define SKL_GT3_PLUS_PLATFORM \
468 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
471 static const struct intel_device_info intel_skylake_gt3_info
= {
472 SKL_GT3_PLUS_PLATFORM
,
476 static const struct intel_device_info intel_skylake_gt4_info
= {
477 SKL_GT3_PLUS_PLATFORM
,
481 #define GEN9_LP_FEATURES \
485 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
487 .has_64bit_reloc = 1, \
492 .has_runtime_pm = 1, \
493 .has_pooled_eu = 0, \
495 .has_resource_streamer = 1, \
498 .has_logical_ring_contexts = 1, \
499 .has_logical_ring_preemption = 1, \
501 .has_aliasing_ppgtt = 1, \
502 .has_full_ppgtt = 1, \
503 .has_full_48bit_ppgtt = 1, \
504 .has_reset_engine = 1, \
507 GEN9_DEFAULT_PAGE_SIZES, \
508 GEN_DEFAULT_PIPEOFFSETS, \
509 IVB_CURSOR_OFFSETS, \
512 static const struct intel_device_info intel_broxton_info
= {
514 .platform
= INTEL_BROXTON
,
518 static const struct intel_device_info intel_geminilake_info
= {
520 .platform
= INTEL_GEMINILAKE
,
525 #define KBL_PLATFORM \
528 .platform = INTEL_KABYLAKE
530 static const struct intel_device_info intel_kabylake_gt1_info
= {
535 static const struct intel_device_info intel_kabylake_gt2_info
= {
540 static const struct intel_device_info intel_kabylake_gt3_info
= {
543 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
546 #define CFL_PLATFORM \
549 .platform = INTEL_COFFEELAKE
551 static const struct intel_device_info intel_coffeelake_gt1_info
= {
556 static const struct intel_device_info intel_coffeelake_gt2_info
= {
561 static const struct intel_device_info intel_coffeelake_gt3_info
= {
564 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
567 #define GEN10_FEATURES \
572 static const struct intel_device_info intel_cannonlake_gt2_info
= {
574 .is_alpha_support
= 1,
575 .platform
= INTEL_CANNONLAKE
,
581 * Make sure any device matches here are from most specific to most
582 * general. For example, since the Quanta match is based on the subsystem
583 * and subvendor IDs, we need it to come before the more general IVB
584 * PCI ID matches, otherwise we'll use the wrong info struct above.
586 static const struct pci_device_id pciidlist
[] = {
587 INTEL_I830_IDS(&intel_i830_info
),
588 INTEL_I845G_IDS(&intel_i845g_info
),
589 INTEL_I85X_IDS(&intel_i85x_info
),
590 INTEL_I865G_IDS(&intel_i865g_info
),
591 INTEL_I915G_IDS(&intel_i915g_info
),
592 INTEL_I915GM_IDS(&intel_i915gm_info
),
593 INTEL_I945G_IDS(&intel_i945g_info
),
594 INTEL_I945GM_IDS(&intel_i945gm_info
),
595 INTEL_I965G_IDS(&intel_i965g_info
),
596 INTEL_G33_IDS(&intel_g33_info
),
597 INTEL_I965GM_IDS(&intel_i965gm_info
),
598 INTEL_GM45_IDS(&intel_gm45_info
),
599 INTEL_G45_IDS(&intel_g45_info
),
600 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
601 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
602 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
603 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info
),
604 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info
),
605 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info
),
606 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info
),
607 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
608 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info
),
609 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info
),
610 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info
),
611 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info
),
612 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info
),
613 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info
),
614 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info
),
615 INTEL_VLV_IDS(&intel_valleyview_info
),
616 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info
),
617 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info
),
618 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info
),
619 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info
),
620 INTEL_CHV_IDS(&intel_cherryview_info
),
621 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info
),
622 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info
),
623 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
624 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info
),
625 INTEL_BXT_IDS(&intel_broxton_info
),
626 INTEL_GLK_IDS(&intel_geminilake_info
),
627 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info
),
628 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info
),
629 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
630 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
631 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info
),
632 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info
),
633 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info
),
634 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info
),
635 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info
),
636 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info
),
637 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info
),
638 INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info
),
639 INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info
),
642 MODULE_DEVICE_TABLE(pci
, pciidlist
);
644 static void i915_pci_remove(struct pci_dev
*pdev
)
646 struct drm_device
*dev
= pci_get_drvdata(pdev
);
648 i915_driver_unload(dev
);
652 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
654 struct intel_device_info
*intel_info
=
655 (struct intel_device_info
*) ent
->driver_data
;
658 if (IS_ALPHA_SUPPORT(intel_info
) && !i915_modparams
.alpha_support
) {
659 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
660 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
661 "to enable support in this kernel version, or check for kernel updates.\n");
665 /* Only bind to function 0 of the device. Early generations
666 * used function 1 as a placeholder for multi-head. This causes
667 * us confusion instead, especially on the systems where both
668 * functions have the same PCI-ID!
670 if (PCI_FUNC(pdev
->devfn
))
674 * apple-gmux is needed on dual GPU MacBook Pro
675 * to probe the panel if we're the inactive GPU.
677 if (vga_switcheroo_client_probe_defer(pdev
))
678 return -EPROBE_DEFER
;
680 err
= i915_driver_load(pdev
, ent
);
684 err
= i915_live_selftests(pdev
);
686 i915_pci_remove(pdev
);
687 return err
> 0 ? -ENOTTY
: err
;
693 static struct pci_driver i915_pci_driver
= {
695 .id_table
= pciidlist
,
696 .probe
= i915_pci_probe
,
697 .remove
= i915_pci_remove
,
699 .driver
.pm
= &i915_pm_ops
,
703 static int __init
i915_init(void)
708 err
= i915_mock_selftests();
710 return err
> 0 ? 0 : err
;
713 * Enable KMS by default, unless explicitly overriden by
714 * either the i915.modeset prarameter or by the
715 * vga_text_mode_force boot option.
718 if (i915_modparams
.modeset
== 0)
721 if (vgacon_text_force() && i915_modparams
.modeset
== -1)
725 /* Silently fail loading to not upset userspace. */
726 DRM_DEBUG_DRIVER("KMS disabled.\n");
730 return pci_register_driver(&i915_pci_driver
);
733 static void __exit
i915_exit(void)
736 if (!i915_pci_driver
.driver
.owner
)
740 pci_unregister_driver(&i915_pci_driver
);
743 module_init(i915_init
);
744 module_exit(i915_exit
);
746 MODULE_AUTHOR("Tungsten Graphics, Inc.");
747 MODULE_AUTHOR("Intel Corporation");
750 i915_pci_probe_dfly(device_t kdev
)
753 const struct pci_device_id
*ent
;
754 static struct pci_dev
*pdev
= NULL
;
755 static device_t bsddev
;
757 if (pci_get_class(kdev
) != PCIC_DISPLAY
)
760 if (pci_get_vendor(kdev
) != PCI_VENDOR_ID_INTEL
)
763 device
= pci_get_device(kdev
);
765 for (i
= 0; pciidlist
[i
].device
!= 0; i
++) {
766 if (pciidlist
[i
].device
== device
) {
774 if (!strcmp(device_get_name(kdev
), "drmsub"))
775 bsddev
= device_get_parent(kdev
);
779 drm_init_pdev(bsddev
, &pdev
);
781 /* Print the contents of pdev struct. */
782 drm_print_pdev(pdev
);
784 return i915_pci_probe(pdev
, ent
);
787 static int i915_driver_attach(device_t kdev
)
792 static device_method_t i915_methods
[] = {
793 /* Device interface */
794 DEVMETHOD(device_probe
, i915_pci_probe_dfly
),
795 DEVMETHOD(device_attach
, i915_driver_attach
),
797 DEVMETHOD(device_suspend
, i915_suspend_switcheroo
),
798 DEVMETHOD(device_resume
, i915_resume_switcheroo
),
800 DEVMETHOD(device_detach
, drm_release
),
804 static driver_t i915_driver
= {
807 sizeof(struct drm_softc
)
810 extern devclass_t drm_devclass
;
812 DRIVER_MODULE_ORDERED(i915
, vgapci
, i915_driver
, &drm_devclass
, NULL
, NULL
, SI_ORDER_ANY
);
813 MODULE_DEPEND(i915
, drm
, 1, 1, 1);
815 MODULE_DEPEND(i915
, acpi
, 1, 1, 1);