sys/dev/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define GEN_DEFAULT_PIPEOFFSETS \
  33         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  34                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  35         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  36                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  37         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  38
  39 #define GEN_CHV_PIPEOFFSETS \
  40         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  41                           CHV_PIPE_C_OFFSET }, \
  42         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  43                            CHV_TRANSCODER_C_OFFSET, }, \
  44         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  45                              CHV_PALETTE_C_OFFSET }
  46
  47 #define CURSOR_OFFSETS \
  48         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  49
  50 #define IVB_CURSOR_OFFSETS \
  51         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  52
  53 #define BDW_COLORS \
  54         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  55 #define CHV_COLORS \
  56         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  57 #define GLK_COLORS \
  58         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  59
  60 /* Keep in gen based order, and chronological order within a gen */
  61
  62 #define GEN_DEFAULT_PAGE_SIZES \
  63         .page_sizes = I915_GTT_PAGE_SIZE_4K
  64
  65 #define GEN2_FEATURES \
  66         .gen = 2, .num_pipes = 1, \
  67         .has_overlay = 1, .overlay_needs_physical = 1, \
  68         .has_gmch_display = 1, \
  69         .hws_needs_physical = 1, \
  70         .unfenced_needs_alignment = 1, \
  71         .ring_mask = RENDER_RING, \
  72         .has_snoop = true, \
  73         GEN_DEFAULT_PIPEOFFSETS, \
  74         GEN_DEFAULT_PAGE_SIZES, \
  75         CURSOR_OFFSETS
  76
  77 static const struct intel_device_info intel_i830_info = {
  78         GEN2_FEATURES,
  79         .platform = INTEL_I830,
  80         .is_mobile = 1, .cursor_needs_physical = 1,
  81         .num_pipes = 2, /* legal, last one wins */
  82 };
  83
  84 static const struct intel_device_info intel_i845g_info = {
  85         GEN2_FEATURES,
  86         .platform = INTEL_I845G,
  87 };
  88
  89 static const struct intel_device_info intel_i85x_info = {
  90         GEN2_FEATURES,
  91         .platform = INTEL_I85X, .is_mobile = 1,
  92         .num_pipes = 2, /* legal, last one wins */
  93         .cursor_needs_physical = 1,
  94         .has_fbc = 1,
  95 };
  96
  97 static const struct intel_device_info intel_i865g_info = {
  98         GEN2_FEATURES,
  99         .platform = INTEL_I865G,
 100 };
 101
 102 #define GEN3_FEATURES \
 103         .gen = 3, .num_pipes = 2, \
 104         .has_gmch_display = 1, \
 105         .ring_mask = RENDER_RING, \
 106         .has_snoop = true, \
 107         GEN_DEFAULT_PIPEOFFSETS, \
 108         GEN_DEFAULT_PAGE_SIZES, \
 109         CURSOR_OFFSETS
 110
 111 static const struct intel_device_info intel_i915g_info = {
 112         GEN3_FEATURES,
 113         .platform = INTEL_I915G, .cursor_needs_physical = 1,
 114         .has_overlay = 1, .overlay_needs_physical = 1,
 115         .hws_needs_physical = 1,
 116         .unfenced_needs_alignment = 1,
 117 };
 118
 119 static const struct intel_device_info intel_i915gm_info = {
 120         GEN3_FEATURES,
 121         .platform = INTEL_I915GM,
 122         .is_mobile = 1,
 123         .cursor_needs_physical = 1,
 124         .has_overlay = 1, .overlay_needs_physical = 1,
 125         .supports_tv = 1,
 126         .has_fbc = 1,
 127         .hws_needs_physical = 1,
 128         .unfenced_needs_alignment = 1,
 129 };
 130
 131 static const struct intel_device_info intel_i945g_info = {
 132         GEN3_FEATURES,
 133         .platform = INTEL_I945G,
 134         .has_hotplug = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136         .hws_needs_physical = 1,
 137         .unfenced_needs_alignment = 1,
 138 };
 139
 140 static const struct intel_device_info intel_i945gm_info = {
 141         GEN3_FEATURES,
 142         .platform = INTEL_I945GM, .is_mobile = 1,
 143         .has_hotplug = 1, .cursor_needs_physical = 1,
 144         .has_overlay = 1, .overlay_needs_physical = 1,
 145         .supports_tv = 1,
 146         .has_fbc = 1,
 147         .hws_needs_physical = 1,
 148         .unfenced_needs_alignment = 1,
 149 };
 150
 151 static const struct intel_device_info intel_g33_info = {
 152         GEN3_FEATURES,
 153         .platform = INTEL_G33,
 154         .has_hotplug = 1,
 155         .has_overlay = 1,
 156 };
 157
 158 static const struct intel_device_info intel_pineview_info = {
 159         GEN3_FEATURES,
 160         .platform = INTEL_PINEVIEW, .is_mobile = 1,
 161         .has_hotplug = 1,
 162         .has_overlay = 1,
 163 };
 164
 165 #define GEN4_FEATURES \
 166         .gen = 4, .num_pipes = 2, \
 167         .has_hotplug = 1, \
 168         .has_gmch_display = 1, \
 169         .ring_mask = RENDER_RING, \
 170         .has_snoop = true, \
 171         GEN_DEFAULT_PIPEOFFSETS, \
 172         GEN_DEFAULT_PAGE_SIZES, \
 173         CURSOR_OFFSETS
 174
 175 static const struct intel_device_info intel_i965g_info = {
 176         GEN4_FEATURES,
 177         .platform = INTEL_I965G,
 178         .has_overlay = 1,
 179         .hws_needs_physical = 1,
 180         .has_snoop = false,
 181 };
 182
 183 static const struct intel_device_info intel_i965gm_info = {
 184         GEN4_FEATURES,
 185         .platform = INTEL_I965GM,
 186         .is_mobile = 1, .has_fbc = 1,
 187         .has_overlay = 1,
 188         .supports_tv = 1,
 189         .hws_needs_physical = 1,
 190         .has_snoop = false,
 191 };
 192
 193 static const struct intel_device_info intel_g45_info = {
 194         GEN4_FEATURES,
 195         .platform = INTEL_G45,
 196         .ring_mask = RENDER_RING | BSD_RING,
 197 };
 198
 199 static const struct intel_device_info intel_gm45_info = {
 200         GEN4_FEATURES,
 201         .platform = INTEL_GM45,
 202         .is_mobile = 1, .has_fbc = 1,
 203         .supports_tv = 1,
 204         .ring_mask = RENDER_RING | BSD_RING,
 205 };
 206
 207 #define GEN5_FEATURES \
 208         .gen = 5, .num_pipes = 2, \
 209         .has_hotplug = 1, \
 210         .ring_mask = RENDER_RING | BSD_RING, \
 211         .has_snoop = true, \
 212         GEN_DEFAULT_PIPEOFFSETS, \
 213         GEN_DEFAULT_PAGE_SIZES, \
 214         CURSOR_OFFSETS
 215
 216 static const struct intel_device_info intel_ironlake_d_info = {
 217         GEN5_FEATURES,
 218         .platform = INTEL_IRONLAKE,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_m_info = {
 222         GEN5_FEATURES,
 223         .platform = INTEL_IRONLAKE,
 224         .is_mobile = 1, .has_fbc = 1,
 225 };
 226
 227 #define GEN6_FEATURES \
 228         .gen = 6, .num_pipes = 2, \
 229         .has_hotplug = 1, \
 230         .has_fbc = 1, \
 231         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 232         .has_llc = 1, \
 233         .has_rc6 = 1, \
 234         .has_rc6p = 1, \
 235         .has_aliasing_ppgtt = 1, \
 236         GEN_DEFAULT_PIPEOFFSETS, \
 237         GEN_DEFAULT_PAGE_SIZES, \
 238         CURSOR_OFFSETS
 239
 240 #define SNB_D_PLATFORM \
 241         GEN6_FEATURES, \
 242         .platform = INTEL_SANDYBRIDGE
 243
 244 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 245         SNB_D_PLATFORM,
 246         .gt = 1,
 247 };
 248
 249 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 250         SNB_D_PLATFORM,
 251         .gt = 2,
 252 };
 253
 254 #define SNB_M_PLATFORM \
 255         GEN6_FEATURES, \
 256         .platform = INTEL_SANDYBRIDGE, \
 257         .is_mobile = 1
 258
 259
 260 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 261         SNB_M_PLATFORM,
 262         .gt = 1,
 263 };
 264
 265 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 266         SNB_M_PLATFORM,
 267         .gt = 2,
 268 };
 269
 270 #define GEN7_FEATURES  \
 271         .gen = 7, .num_pipes = 3, \
 272         .has_hotplug = 1, \
 273         .has_fbc = 1, \
 274         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 275         .has_llc = 1, \
 276         .has_rc6 = 1, \
 277         .has_rc6p = 1, \
 278         .has_aliasing_ppgtt = 1, \
 279         .has_full_ppgtt = 1, \
 280         GEN_DEFAULT_PIPEOFFSETS, \
 281         GEN_DEFAULT_PAGE_SIZES, \
 282         IVB_CURSOR_OFFSETS
 283
 284 #define IVB_D_PLATFORM \
 285         GEN7_FEATURES, \
 286         .platform = INTEL_IVYBRIDGE, \
 287         .has_l3_dpf = 1
 288
 289 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 290         IVB_D_PLATFORM,
 291         .gt = 1,
 292 };
 293
 294 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 295         IVB_D_PLATFORM,
 296         .gt = 2,
 297 };
 298
 299 #define IVB_M_PLATFORM \
 300         GEN7_FEATURES, \
 301         .platform = INTEL_IVYBRIDGE, \
 302         .is_mobile = 1, \
 303         .has_l3_dpf = 1
 304
 305 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 306         IVB_M_PLATFORM,
 307         .gt = 1,
 308 };
 309
 310 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 311         IVB_M_PLATFORM,
 312         .gt = 2,
 313 };
 314
 315 static const struct intel_device_info intel_ivybridge_q_info = {
 316         GEN7_FEATURES,
 317         .platform = INTEL_IVYBRIDGE,
 318         .gt = 2,
 319         .num_pipes = 0, /* legal, last one wins */
 320         .has_l3_dpf = 1,
 321 };
 322
 323 static const struct intel_device_info intel_valleyview_info = {
 324         .platform = INTEL_VALLEYVIEW,
 325         .gen = 7,
 326         .is_lp = 1,
 327         .num_pipes = 2,
 328         .has_psr = 1,
 329         .has_runtime_pm = 1,
 330         .has_rc6 = 1,
 331         .has_gmch_display = 1,
 332         .has_hotplug = 1,
 333         .has_aliasing_ppgtt = 1,
 334         .has_full_ppgtt = 1,
 335         .has_snoop = true,
 336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 337         .display_mmio_offset = VLV_DISPLAY_BASE,
 338         GEN_DEFAULT_PAGE_SIZES,
 339         GEN_DEFAULT_PIPEOFFSETS,
 340         CURSOR_OFFSETS
 341 };
 342
 343 #define G75_FEATURES  \
 344         GEN7_FEATURES, \
 345         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 346         .has_ddi = 1, \
 347         .has_fpga_dbg = 1, \
 348         .has_psr = 1, \
 349         .has_resource_streamer = 1, \
 350         .has_dp_mst = 1, \
 351         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 352         .has_runtime_pm = 1
 353
 354 #define HSW_PLATFORM \
 355         G75_FEATURES, \
 356         .platform = INTEL_HASWELL, \
 357         .has_l3_dpf = 1
 358
 359 static const struct intel_device_info intel_haswell_gt1_info = {
 360         HSW_PLATFORM,
 361         .gt = 1,
 362 };
 363
 364 static const struct intel_device_info intel_haswell_gt2_info = {
 365         HSW_PLATFORM,
 366         .gt = 2,
 367 };
 368
 369 static const struct intel_device_info intel_haswell_gt3_info = {
 370         HSW_PLATFORM,
 371         .gt = 3,
 372 };
 373
 374 #define GEN8_FEATURES \
 375         G75_FEATURES, \
 376         BDW_COLORS, \
 377         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 378                       I915_GTT_PAGE_SIZE_2M, \
 379         .has_logical_ring_contexts = 1, \
 380         .has_full_48bit_ppgtt = 1, \
 381         .has_64bit_reloc = 1, \
 382         .has_reset_engine = 1
 383
 384 #define BDW_PLATFORM \
 385         GEN8_FEATURES, \
 386         .gen = 8, \
 387         .platform = INTEL_BROADWELL
 388
 389 static const struct intel_device_info intel_broadwell_gt1_info = {
 390         BDW_PLATFORM,
 391         .gt = 1,
 392 };
 393
 394 static const struct intel_device_info intel_broadwell_gt2_info = {
 395         BDW_PLATFORM,
 396         .gt = 2,
 397 };
 398
 399 static const struct intel_device_info intel_broadwell_rsvd_info = {
 400         BDW_PLATFORM,
 401         .gt = 3,
 402         /* According to the device ID those devices are GT3, they were
 403          * previously treated as not GT3, keep it like that.
 404          */
 405 };
 406
 407 static const struct intel_device_info intel_broadwell_gt3_info = {
 408         BDW_PLATFORM,
 409         .gt = 3,
 410         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 411 };
 412
 413 static const struct intel_device_info intel_cherryview_info = {
 414         .gen = 8, .num_pipes = 3,
 415         .has_hotplug = 1,
 416         .is_lp = 1,
 417         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 418         .platform = INTEL_CHERRYVIEW,
 419         .has_64bit_reloc = 1,
 420         .has_psr = 1,
 421         .has_runtime_pm = 1,
 422         .has_resource_streamer = 1,
 423         .has_rc6 = 1,
 424         .has_logical_ring_contexts = 1,
 425         .has_gmch_display = 1,
 426         .has_aliasing_ppgtt = 1,
 427         .has_full_ppgtt = 1,
 428         .has_reset_engine = 1,
 429         .has_snoop = true,
 430         .display_mmio_offset = VLV_DISPLAY_BASE,
 431         GEN_DEFAULT_PAGE_SIZES,
 432         GEN_CHV_PIPEOFFSETS,
 433         CURSOR_OFFSETS,
 434         CHV_COLORS,
 435 };
 436
 437 #define GEN9_DEFAULT_PAGE_SIZES \
 438         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 439                       I915_GTT_PAGE_SIZE_64K | \
 440                       I915_GTT_PAGE_SIZE_2M
 441
 442 #define GEN9_FEATURES \
 443         GEN8_FEATURES, \
 444         GEN9_DEFAULT_PAGE_SIZES, \
 445         .has_logical_ring_preemption = 1, \
 446         .has_csr = 1, \
 447         .has_guc = 1, \
 448         .has_ipc = 1, \
 449         .ddb_size = 896
 450
 451 #define SKL_PLATFORM \
 452         GEN9_FEATURES, \
 453         .gen = 9, \
 454         .platform = INTEL_SKYLAKE
 455
 456 static const struct intel_device_info intel_skylake_gt1_info = {
 457         SKL_PLATFORM,
 458         .gt = 1,
 459 };
 460
 461 static const struct intel_device_info intel_skylake_gt2_info = {
 462         SKL_PLATFORM,
 463         .gt = 2,
 464 };
 465
 466 #define SKL_GT3_PLUS_PLATFORM \
 467         SKL_PLATFORM, \
 468         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 469
 470
 471 static const struct intel_device_info intel_skylake_gt3_info = {
 472         SKL_GT3_PLUS_PLATFORM,
 473         .gt = 3,
 474 };
 475
 476 static const struct intel_device_info intel_skylake_gt4_info = {
 477         SKL_GT3_PLUS_PLATFORM,
 478         .gt = 4,
 479 };
 480
 481 #define GEN9_LP_FEATURES \
 482         .gen = 9, \
 483         .is_lp = 1, \
 484         .has_hotplug = 1, \
 485         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 486         .num_pipes = 3, \
 487         .has_64bit_reloc = 1, \
 488         .has_ddi = 1, \
 489         .has_fpga_dbg = 1, \
 490         .has_fbc = 1, \
 491         .has_psr = 1, \
 492         .has_runtime_pm = 1, \
 493         .has_pooled_eu = 0, \
 494         .has_csr = 1, \
 495         .has_resource_streamer = 1, \
 496         .has_rc6 = 1, \
 497         .has_dp_mst = 1, \
 498         .has_logical_ring_contexts = 1, \
 499         .has_logical_ring_preemption = 1, \
 500         .has_guc = 1, \
 501         .has_aliasing_ppgtt = 1, \
 502         .has_full_ppgtt = 1, \
 503         .has_full_48bit_ppgtt = 1, \
 504         .has_reset_engine = 1, \
 505         .has_snoop = true, \
 506         .has_ipc = 1, \
 507         GEN9_DEFAULT_PAGE_SIZES, \
 508         GEN_DEFAULT_PIPEOFFSETS, \
 509         IVB_CURSOR_OFFSETS, \
 510         BDW_COLORS
 511
 512 static const struct intel_device_info intel_broxton_info = {
 513         GEN9_LP_FEATURES,
 514         .platform = INTEL_BROXTON,
 515         .ddb_size = 512,
 516 };
 517
 518 static const struct intel_device_info intel_geminilake_info = {
 519         GEN9_LP_FEATURES,
 520         .platform = INTEL_GEMINILAKE,
 521         .ddb_size = 1024,
 522         GLK_COLORS,
 523 };
 524
 525 #define KBL_PLATFORM \
 526         GEN9_FEATURES, \
 527         .gen = 9, \
 528         .platform = INTEL_KABYLAKE
 529
 530 static const struct intel_device_info intel_kabylake_gt1_info = {
 531         KBL_PLATFORM,
 532         .gt = 1,
 533 };
 534
 535 static const struct intel_device_info intel_kabylake_gt2_info = {
 536         KBL_PLATFORM,
 537         .gt = 2,
 538 };
 539
 540 static const struct intel_device_info intel_kabylake_gt3_info = {
 541         KBL_PLATFORM,
 542         .gt = 3,
 543         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 544 };
 545
 546 #define CFL_PLATFORM \
 547         GEN9_FEATURES, \
 548         .gen = 9, \
 549         .platform = INTEL_COFFEELAKE
 550
 551 static const struct intel_device_info intel_coffeelake_gt1_info = {
 552         CFL_PLATFORM,
 553         .gt = 1,
 554 };
 555
 556 static const struct intel_device_info intel_coffeelake_gt2_info = {
 557         CFL_PLATFORM,
 558         .gt = 2,
 559 };
 560
 561 static const struct intel_device_info intel_coffeelake_gt3_info = {
 562         CFL_PLATFORM,
 563         .gt = 3,
 564         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 565 };
 566
 567 #define GEN10_FEATURES \
 568         GEN9_FEATURES, \
 569         .ddb_size = 1024, \
 570         GLK_COLORS
 571
 572 static const struct intel_device_info intel_cannonlake_gt2_info = {
 573         GEN10_FEATURES,
 574         .is_alpha_support = 1,
 575         .platform = INTEL_CANNONLAKE,
 576         .gen = 10,
 577         .gt = 2,
 578 };
 579
 580 /*
 581  * Make sure any device matches here are from most specific to most
 582  * general.  For example, since the Quanta match is based on the subsystem
 583  * and subvendor IDs, we need it to come before the more general IVB
 584  * PCI ID matches, otherwise we'll use the wrong info struct above.
 585  */
 586 static const struct pci_device_id pciidlist[] = {
 587         INTEL_I830_IDS(&intel_i830_info),
 588         INTEL_I845G_IDS(&intel_i845g_info),
 589         INTEL_I85X_IDS(&intel_i85x_info),
 590         INTEL_I865G_IDS(&intel_i865g_info),
 591         INTEL_I915G_IDS(&intel_i915g_info),
 592         INTEL_I915GM_IDS(&intel_i915gm_info),
 593         INTEL_I945G_IDS(&intel_i945g_info),
 594         INTEL_I945GM_IDS(&intel_i945gm_info),
 595         INTEL_I965G_IDS(&intel_i965g_info),
 596         INTEL_G33_IDS(&intel_g33_info),
 597         INTEL_I965GM_IDS(&intel_i965gm_info),
 598         INTEL_GM45_IDS(&intel_gm45_info),
 599         INTEL_G45_IDS(&intel_g45_info),
 600         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 601         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 602         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 603         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 604         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 605         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 606         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 607         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 608         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 609         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 610         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 611         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 612         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 613         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 614         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 615         INTEL_VLV_IDS(&intel_valleyview_info),
 616         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 617         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 618         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 619         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 620         INTEL_CHV_IDS(&intel_cherryview_info),
 621         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 622         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 623         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 624         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 625         INTEL_BXT_IDS(&intel_broxton_info),
 626         INTEL_GLK_IDS(&intel_geminilake_info),
 627         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 628         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 629         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 630         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 631         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 632         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 633         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 634         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 635         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 636         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 637         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 638         INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
 639         INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
 640         {0, 0, 0}
 641 };
 642 MODULE_DEVICE_TABLE(pci, pciidlist);
 643
 644 static void i915_pci_remove(struct pci_dev *pdev)
 645 {
 646         struct drm_device *dev = pci_get_drvdata(pdev);
 647
 648         i915_driver_unload(dev);
 649         drm_dev_put(dev);
 650 }
 651
 652 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 653 {
 654         struct intel_device_info *intel_info =
 655                 (struct intel_device_info *) ent->driver_data;
 656         int err;
 657
 658         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 659                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 660                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 661                          "to enable support in this kernel version, or check for kernel updates.\n");
 662                 return -ENODEV;
 663         }
 664
 665         /* Only bind to function 0 of the device. Early generations
 666          * used function 1 as a placeholder for multi-head. This causes
 667          * us confusion instead, especially on the systems where both
 668          * functions have the same PCI-ID!
 669          */
 670         if (PCI_FUNC(pdev->devfn))
 671                 return -ENODEV;
 672
 673         /*
 674          * apple-gmux is needed on dual GPU MacBook Pro
 675          * to probe the panel if we're the inactive GPU.
 676          */
 677         if (vga_switcheroo_client_probe_defer(pdev))
 678                 return -EPROBE_DEFER;
 679
 680         err = i915_driver_load(pdev, ent);
 681         if (err)
 682                 return err;
 683
 684         err = i915_live_selftests(pdev);
 685         if (err) {
 686                 i915_pci_remove(pdev);
 687                 return err > 0 ? -ENOTTY : err;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static struct pci_driver i915_pci_driver = {
 694         .name = DRIVER_NAME,
 695         .id_table = pciidlist,
 696         .probe = i915_pci_probe,
 697         .remove = i915_pci_remove,
 698 #if 0
 699         .driver.pm = &i915_pm_ops,
 700 #endif
 701 };
 702
 703 static int __init i915_init(void)
 704 {
 705         bool use_kms = true;
 706         int err;
 707
 708         err = i915_mock_selftests();
 709         if (err)
 710                 return err > 0 ? 0 : err;
 711
 712         /*
 713          * Enable KMS by default, unless explicitly overriden by
 714          * either the i915.modeset prarameter or by the
 715          * vga_text_mode_force boot option.
 716          */
 717
 718         if (i915_modparams.modeset == 0)
 719                 use_kms = false;
 720
 721         if (vgacon_text_force() && i915_modparams.modeset == -1)
 722                 use_kms = false;
 723
 724         if (!use_kms) {
 725                 /* Silently fail loading to not upset userspace. */
 726                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 727                 return 0;
 728         }
 729
 730         return pci_register_driver(&i915_pci_driver);
 731 }
 732
 733 static void __exit i915_exit(void)
 734 {
 735 #if 0
 736         if (!i915_pci_driver.driver.owner)
 737                 return;
 738 #endif
 739
 740         pci_unregister_driver(&i915_pci_driver);
 741 }
 742
 743 module_init(i915_init);
 744 module_exit(i915_exit);
 745
 746 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 747 MODULE_AUTHOR("Intel Corporation");
 748
 749 static int
 750 i915_pci_probe_dfly(device_t kdev)
 751 {
 752         int device, i = 0;
 753         const struct pci_device_id *ent;
 754         static struct pci_dev *pdev = NULL;
 755         static device_t bsddev;
 756
 757         if (pci_get_class(kdev) != PCIC_DISPLAY)
 758                 return ENXIO;
 759
 760         if (pci_get_vendor(kdev) != PCI_VENDOR_ID_INTEL)
 761                 return ENXIO;
 762
 763         device = pci_get_device(kdev);
 764
 765         for (i = 0; pciidlist[i].device != 0; i++) {
 766                 if (pciidlist[i].device == device) {
 767                         ent = &pciidlist[i];
 768                         goto found;
 769                 }
 770         }
 771
 772         return ENXIO;
 773 found:
 774         if (!strcmp(device_get_name(kdev), "drmsub"))
 775                 bsddev = device_get_parent(kdev);
 776         else
 777                 bsddev = kdev;
 778
 779         drm_init_pdev(bsddev, &pdev);
 780
 781         /* Print the contents of pdev struct. */
 782         drm_print_pdev(pdev);
 783
 784         return i915_pci_probe(pdev, ent);
 785 }
 786
 787 static int i915_driver_attach(device_t kdev)
 788 {
 789         return 0;
 790 }
 791
 792 static device_method_t i915_methods[] = {
 793         /* Device interface */
 794         DEVMETHOD(device_probe,         i915_pci_probe_dfly),
 795         DEVMETHOD(device_attach,        i915_driver_attach),
 796 #if 0
 797         DEVMETHOD(device_suspend,       i915_suspend_switcheroo),
 798         DEVMETHOD(device_resume,        i915_resume_switcheroo),
 799 #endif
 800         DEVMETHOD(device_detach,        drm_release),
 801         DEVMETHOD_END
 802 };
 803
 804 static driver_t i915_driver = {
 805         "drm",
 806         i915_methods,
 807         sizeof(struct drm_softc)
 808 };
 809
 810 extern devclass_t drm_devclass;
 811
 812 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, &drm_devclass, NULL, NULL, SI_ORDER_ANY);
 813 MODULE_DEPEND(i915, drm, 1, 1, 1);
 814 #ifdef CONFIG_ACPI
 815 MODULE_DEPEND(i915, acpi, 1, 1, 1);
 816 #endif