sys/dev/disk/sdhci/sdhci.h

   1 /*-
   2  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * $FreeBSD: src/sys/dev/sdhci/sdhci.h,v 1.1 2008/10/21 20:33:40 mav Exp $
  26  */
  27
  28 #ifndef __SDHCI_H__
  29 #define __SDHCI_H__
  30
  31 #define DMA_BLOCK_SIZE  4096
  32 #define DMA_BOUNDARY    0       /* DMA reload every 4K */
  33
  34 /* Controller doesn't honor resets unless we touch the clock register */
  35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  36 /* Controller really supports SDMA */
  37 #define SDHCI_QUIRK_FORCE_SDMA                          (1<<1)
  38 /* Controller has unusable DMA engine */
  39 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<2)
  40 /* Controller doesn't like to be reset when there is no card inserted. */
  41 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<3)
  42 /* Controller has flaky internal state so reset it on each ios change */
  43 #define SDHCI_QUIRK_RESET_ON_IOS                        (1<<4)
  44 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
  45 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<5)
  46 /* Controller needs to be reset after each request to stay stable */
  47 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<6)
  48 /* Controller has an off-by-one issue with timeout value */
  49 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL                (1<<7)
  50 /* Controller has broken read timings */
  51 #define SDHCI_QUIRK_BROKEN_TIMINGS                      (1<<8)
  52 /* Controller needs lowered frequency */
  53 #define SDHCI_QUIRK_LOWER_FREQUENCY                     (1<<9)
  54 /* Data timeout is invalid, should use SD clock */
  55 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<10)
  56 /* Timeout value is invalid, should be overridden */
  57 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<11)
  58 /* SDHCI_CAPABILITIES is invalid */
  59 #define SDHCI_QUIRK_MISSING_CAPS                        (1<<12)
  60 /* Hardware shifts the 136-bit response, don't do it in software. */
  61 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE                 (1<<13)
  62 /* Wait to see reset bit asserted before waiting for de-asserted  */
  63 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED              (1<<14)
  64 /* Leave controller in standard mode when putting card in HS mode. */
  65 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT                  (1<<15)
  66 /* Alternate clock source is required when supplying a 400 KHz clock. */
  67 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC              (1<<16)
  68 /* Allow ADMA2 to be used. */
  69 #define SDHCI_QUIRK_WHITELIST_ADMA2                     (1<<17)
  70 /* Controller waits for busy responses. */
  71 #define SDHCI_QUIRK_WAIT_WHILE_BUSY                     (1<<22)
  72 /* Controller supports eMMC DDR52 mode. */
  73 #define SDHCI_QUIRK_MMC_DDR52                           (1 << 23)
  74 /* Controller support for UHS DDR50 mode is broken. */
  75 #define SDHCI_QUIRK_BROKEN_UHS_DDR50                    (1 << 24)
  76 /* Controller support for eMMC HS200 mode is broken. */
  77 #define SDHCI_QUIRK_BROKEN_MMC_HS200                    (1 << 25)
  78 /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */
  79 #define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400            (1 << 26)
  80 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
  81 #define SDHCI_QUIRK_PRESET_VALUE_BROKEN                 (1 << 27)
  82
  83 /*
  84  * Controller registers
  85  */
  86 #define SDHCI_SDMA_ADDRESS      0x00
  87
  88 #define SDHCI_BLOCK_SIZE        0x04
  89 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  90
  91 #define SDHCI_BLOCK_COUNT       0x06
  92
  93 #define SDHCI_ARGUMENT          0x08
  94
  95 #define SDHCI_TRANSFER_MODE     0x0C
  96 #define  SDHCI_TRNS_DMA         0x01
  97 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  98 #define  SDHCI_TRNS_ACMD12      0x04
  99 #define  SDHCI_TRNS_READ        0x10
 100 #define  SDHCI_TRNS_MULTI       0x20
 101
 102 #define SDHCI_COMMAND_FLAGS     0x0E
 103 #define  SDHCI_CMD_RESP_NONE    0x00
 104 #define  SDHCI_CMD_RESP_LONG    0x01
 105 #define  SDHCI_CMD_RESP_SHORT   0x02
 106 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
 107 #define  SDHCI_CMD_RESP_MASK    0x03
 108 #define  SDHCI_CMD_CRC          0x08
 109 #define  SDHCI_CMD_INDEX        0x10
 110 #define  SDHCI_CMD_DATA         0x20
 111 #define  SDHCI_CMD_TYPE_NORMAL  0x00
 112 #define  SDHCI_CMD_TYPE_SUSPEND 0x40
 113 #define  SDHCI_CMD_TYPE_RESUME  0x80
 114 #define  SDHCI_CMD_TYPE_ABORT   0xc0
 115 #define  SDHCI_CMD_TYPE_MASK    0xc0
 116
 117 #define SDHCI_COMMAND           0x0F
 118
 119 #define SDHCI_RESPONSE          0x10
 120
 121 #define SDHCI_BUFFER            0x20
 122
 123 #define SDHCI_PRESENT_STATE     0x24
 124 #define  SDHCI_CMD_INHIBIT      0x00000001
 125 #define  SDHCI_DAT_INHIBIT      0x00000002
 126 #define  SDHCI_DAT_ACTIVE       0x00000004
 127 #define  SDHCI_RETUNE_REQUEST   0x00000008
 128 #define  SDHCI_DOING_WRITE      0x00000100
 129 #define  SDHCI_DOING_READ       0x00000200
 130 #define  SDHCI_SPACE_AVAILABLE  0x00000400
 131 #define  SDHCI_DATA_AVAILABLE   0x00000800
 132 #define  SDHCI_CARD_PRESENT     0x00010000
 133 #define  SDHCI_CARD_STABLE      0x00020000
 134 #define  SDHCI_CARD_PIN         0x00040000
 135 #define  SDHCI_WRITE_PROTECT    0x00080000
 136 #define  SDHCI_STATE_DAT_MASK   0x00f00000
 137 #define  SDHCI_STATE_CMD        0x01000000
 138
 139 #define SDHCI_HOST_CONTROL      0x28
 140 #define  SDHCI_CTRL_LED         0x01
 141 #define  SDHCI_CTRL_4BITBUS     0x02
 142 #define  SDHCI_CTRL_HISPD       0x04
 143 #define  SDHCI_CTRL_SDMA        0x00
 144 #define  SDHCI_CTRL_ADMA2       0x10
 145 #define  SDHCI_CTRL_ADMA264     0x18
 146 #define  SDHCI_CTRL_DMA_MASK    0x18
 147 #define  SDHCI_CTRL_8BITBUS     0x20
 148 #define  SDHCI_CTRL_CARD_DET    0x40
 149 #define  SDHCI_CTRL_FORCE_CARD  0x80
 150
 151 #define SDHCI_POWER_CONTROL     0x29
 152 #define  SDHCI_POWER_ON         0x01
 153 #define  SDHCI_POWER_180        0x0A
 154 #define  SDHCI_POWER_300        0x0C
 155 #define  SDHCI_POWER_330        0x0E
 156
 157 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
 158
 159 #define SDHCI_WAKE_UP_CONTROL   0x2B
 160
 161 #define SDHCI_CLOCK_CONTROL     0x2C
 162 #define  SDHCI_DIVIDER_MASK     0xff
 163 #define  SDHCI_DIVIDER_MASK_LEN 8
 164 #define  SDHCI_DIVIDER_SHIFT    8
 165 #define  SDHCI_DIVIDER_HI_MASK  3
 166 #define  SDHCI_DIVIDER_HI_SHIFT 6
 167 #define  SDHCI_CLOCK_CARD_EN    0x0004
 168 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 169 #define  SDHCI_CLOCK_INT_EN     0x0001
 170
 171 #define SDHCI_TIMEOUT_CONTROL   0x2E
 172
 173 #define SDHCI_SOFTWARE_RESET    0x2F
 174 #define  SDHCI_RESET_ALL        0x01
 175 #define  SDHCI_RESET_CMD        0x02
 176 #define  SDHCI_RESET_DATA       0x04
 177
 178 #define SDHCI_INT_STATUS        0x30
 179 #define SDHCI_INT_ENABLE        0x34
 180 #define SDHCI_SIGNAL_ENABLE     0x38
 181 #define  SDHCI_INT_RESPONSE     0x00000001
 182 #define  SDHCI_INT_DATA_END     0x00000002
 183 #define  SDHCI_INT_BLOCK_GAP    0x00000004
 184 #define  SDHCI_INT_DMA_END      0x00000008
 185 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 186 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 187 #define  SDHCI_INT_CARD_INSERT  0x00000040
 188 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 189 #define  SDHCI_INT_CARD_INT     0x00000100
 190 #define  SDHCI_INT_INT_A        0x00000200
 191 #define  SDHCI_INT_INT_B        0x00000400
 192 #define  SDHCI_INT_INT_C        0x00000800
 193 #define  SDHCI_INT_RETUNE       0x00001000
 194 #define  SDHCI_INT_ERROR        0x00008000
 195 #define  SDHCI_INT_TIMEOUT      0x00010000
 196 #define  SDHCI_INT_CRC          0x00020000
 197 #define  SDHCI_INT_END_BIT      0x00040000
 198 #define  SDHCI_INT_INDEX        0x00080000
 199 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 200 #define  SDHCI_INT_DATA_CRC     0x00200000
 201 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 202 #define  SDHCI_INT_BUS_POWER    0x00800000
 203 #define  SDHCI_INT_ACMD12ERR    0x01000000
 204 #define  SDHCI_INT_ADMAERR      0x02000000
 205 #define  SDHCI_INT_TUNEERR      0x04000000
 206
 207 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 208 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 209
 210 #define  SDHCI_INT_CMD_ERROR_MASK       (SDHCI_INT_TIMEOUT | \
 211                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 212
 213 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
 214
 215 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 216                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 217                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 218                 SDHCI_INT_DATA_END_BIT)
 219
 220 #define SDHCI_ACMD12_ERR        0x3C
 221
 222 #define SDHCI_HOST_CONTROL2     0x3E
 223 #define  SDHCI_CTRL2_PRESET_VALUE       0x8000
 224 #define  SDHCI_CTRL2_ASYNC_INTR 0x4000
 225 #define  SDHCI_CTRL2_64BIT_ENABLE       0x2000
 226 #define  SDHCI_CTRL2_HOST_V4_ENABLE     0x1000
 227 #define  SDHCI_CTRL2_CMD23_ENABLE       0x0800
 228 #define  SDHCI_CTRL2_ADMA2_LENGTH_MODE  0x0400
 229 #define  SDHCI_CTRL2_UHS2_IFACE_ENABLE  0x0100
 230 #define  SDHCI_CTRL2_SAMPLING_CLOCK     0x0080
 231 #define  SDHCI_CTRL2_EXEC_TUNING        0x0040
 232 #define  SDHCI_CTRL2_DRIVER_TYPE_MASK   0x0030
 233 #define  SDHCI_CTRL2_DRIVER_TYPE_B      0x0000
 234 #define  SDHCI_CTRL2_DRIVER_TYPE_A      0x0010
 235 #define  SDHCI_CTRL2_DRIVER_TYPE_C      0x0020
 236 #define  SDHCI_CTRL2_DRIVER_TYPE_D      0x0030
 237 #define  SDHCI_CTRL2_S18_ENABLE 0x0008
 238 #define  SDHCI_CTRL2_UHS_MASK   0x0007
 239 #define  SDHCI_CTRL2_UHS_SDR12  0x0000
 240 #define  SDHCI_CTRL2_UHS_SDR25  0x0001
 241 #define  SDHCI_CTRL2_UHS_SDR50  0x0002
 242 #define  SDHCI_CTRL2_UHS_SDR104 0x0003
 243 #define  SDHCI_CTRL2_UHS_DDR50  0x0004
 244 #define SDHCI_CTRL2_MMC_HS400   0x0005  /* non-standard */
 245
 246 #define SDHCI_CAPABILITIES      0x40
 247 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 248 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 249 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 250 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 251 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 252 #define  SDHCI_CLOCK_BASE_SHIFT 8
 253 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 254 #define  SDHCI_MAX_BLOCK_SHIFT  16
 255 #define  SDHCI_CAN_DO_8BITBUS   0x00040000
 256 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 257 #define  SDHCI_CAN_DO_HISPD     0x00200000
 258 #define  SDHCI_CAN_DO_DMA       0x00400000
 259 #define  SDHCI_CAN_DO_SUSPEND   0x00800000
 260 #define  SDHCI_CAN_VDD_330      0x01000000
 261 #define  SDHCI_CAN_VDD_300      0x02000000
 262 #define  SDHCI_CAN_VDD_180      0x04000000
 263 #define  SDHCI_CAN_DO_64BIT     0x10000000
 264 #define  SDHCI_CAN_ASYNC_INTR   0x20000000
 265 #define  SDHCI_SLOTTYPE_MASK    0xC0000000
 266 #define  SDHCI_SLOTTYPE_REMOVABLE       0x00000000
 267 #define  SDHCI_SLOTTYPE_EMBEDDED        0x40000000
 268 #define  SDHCI_SLOTTYPE_SHARED  0x80000000
 269
 270 #define SDHCI_CAPABILITIES2     0x44
 271 #define  SDHCI_CAN_SDR50        0x00000001
 272 #define  SDHCI_CAN_SDR104       0x00000002
 273 #define  SDHCI_CAN_DDR50        0x00000004
 274 #define  SDHCI_CAN_DRIVE_TYPE_A 0x00000010
 275 #define  SDHCI_CAN_DRIVE_TYPE_C 0x00000020
 276 #define  SDHCI_CAN_DRIVE_TYPE_D 0x00000040
 277 #define  SDHCI_RETUNE_CNT_MASK  0x00000F00
 278 #define  SDHCI_RETUNE_CNT_SHIFT 8
 279 #define  SDHCI_TUNE_SDR50       0x00002000
 280 #define  SDHCI_RETUNE_MODES_MASK  0x0000C000
 281 #define  SDHCI_RETUNE_MODES_SHIFT 14
 282 #define  SDHCI_CLOCK_MULT_MASK  0x00FF0000
 283 #define  SDHCI_CLOCK_MULT_SHIFT 16
 284 #define SDHCI_CAN_MMC_HS400     0x80000000      /* non-standard */
 285
 286 #define SDHCI_MAX_CURRENT       0x48
 287 #define SDHCI_FORCE_AUTO_EVENT  0x50
 288 #define SDHCI_FORCE_INTR_EVENT  0x52
 289
 290 #define SDHCI_ADMA_ERR          0x54
 291 #define  SDHCI_ADMA_ERR_LENGTH  0x04
 292 #define  SDHCI_ADMA_ERR_STATE_MASK      0x03
 293 #define  SDHCI_ADMA_ERR_STATE_STOP      0x00
 294 #define  SDHCI_ADMA_ERR_STATE_FDS       0x01
 295 #define  SDHCI_ADMA_ERR_STATE_TFR       0x03
 296
 297 #define SDHCI_ADMA_ADDRESS_LOW  0x58
 298 #define SDHCI_ADMA_ADDRESS_HI   0x5C
 299
 300 #define SDHCI_PRESET_VALUE      0x60
 301 #define SDHCI_SHARED_BUS_CTRL   0xE0
 302
 303 #define SDHCI_SLOT_INT_STATUS   0xFC
 304
 305 #define SDHCI_HOST_VERSION      0xFE
 306 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 307 #define  SDHCI_VENDOR_VER_SHIFT 8
 308 #define  SDHCI_SPEC_VER_MASK    0x00FF
 309 #define  SDHCI_SPEC_VER_SHIFT   0
 310 #define SDHCI_SPEC_100          0
 311 #define SDHCI_SPEC_200          1
 312 #define SDHCI_SPEC_300          2
 313 #define SDHCI_SPEC_400          3
 314 #define SDHCI_SPEC_410          4
 315 #define SDHCI_SPEC_420          5
 316
 317
 318 /*
 319  * ADMA2 descriptors
 320  */
 321 #define SDHCI_ADMA2_ATTR_VALID  0x0001
 322 #define SDHCI_ADMA2_ATTR_END    0x0002
 323 #define SDHCI_ADMA2_ATTR_INT    0x0004
 324 #define SDHCI_ADMA2_ATTR_OP_MASK 0x0030
 325 #define SDHCI_ADMA2_ATTR_OP_NOP 0x0000
 326 #define SDHCI_ADMA2_ATTR_OP_TRAN 0x0020
 327 #define SDHCI_ADMA2_ATTR_OP_LINK 0x0030
 328
 329 /* DMA buffer constants for our ADMA2 descriptor table */
 330 #define SDHCI_ADMA2_DESCBUF_SIZE        PAGE_SIZE
 331 #define SDHCI_ADMA2_DESC_COUNT  \
 332         (SDHCI_ADMA2_DESCBUF_SIZE / sizeof(struct sdhci_adma2_desc32))
 333
 334 /* The maximum data length for one descriptor entry */
 335 #define SDHCI_ADMA2_MAX_SEGSIZE 32768   /* 65536 is broken on some chipsets */
 336
 337 struct sdhci_adma2_desc32 {
 338         uint16_t attribute;
 339         uint16_t length;
 340         uint32_t address;
 341 } __packed;
 342
 343 struct sdhci_adma2_desc64 {
 344         uint16_t attribute;
 345         uint16_t length;
 346         uint64_t address;
 347 } __packed;
 348
 349 _Static_assert(SDHCI_ADMA2_DESC_COUNT >= MAXPHYS / PAGE_SIZE + 1,
 350     "SDHCI_ADMA2_DESC_COUNT is not big enough");
 351
 352 extern u_int sdhci_quirk_clear;
 353 extern u_int sdhci_quirk_set;
 354
 355 struct sdhci_slot {
 356         u_int           quirks;         /* Chip specific quirks */
 357         u_int           caps;           /* Override SDHCI_CAPABILITIES */
 358         u_int           caps2;          /* Override SDHCI_CAPABILITIES2 */
 359         device_t        bus;            /* Bus device */
 360         device_t        dev;            /* Slot device */
 361         u_char          num;            /* Slot number */
 362         u_char          opt;            /* Slot options */
 363 #define SDHCI_HAVE_SDMA                 1
 364 #define SDHCI_PLATFORM_TRANSFER         2
 365 #define SDHCI_HAVE_ADMA2                4
 366 #define SDHCI_SLOT_EMBEDDED             8
 367         u_char          version;
 368         int             timeout;        /* Transfer timeout */
 369         int             failures;       /* N Failures in a row */
 370         uint32_t        max_clk;        /* Max possible freq */
 371         uint32_t        timeout_clk;    /* Timeout freq */
 372         bus_dmamem_t    sdma_mem;       /* DMA block for SDMA */
 373         bus_dmamem_t    adma2_descs;    /* DMA block for ADMA2 descriptors */
 374         bus_dma_tag_t   adma2_tag;      /* DMA tag for ADMA2 data buffer */
 375         bus_dmamap_t    adma2_map;      /* DMA map for ADMA2 data buffer */
 376         struct task     card_task;      /* Card presence check task */
 377         struct callout  card_callout;   /* Card insert delay callout */
 378         struct callout  timeout_callout;/* Card command/data response timeout */
 379         struct mmc_host host;           /* Host parameters */
 380         struct mmc_request *req;        /* Current request */
 381         struct mmc_command *curcmd;     /* Current command of current request */
 382
 383         uint32_t        intmask;        /* Current interrupt mask */
 384         uint32_t        clock;          /* Current clock freq. */
 385         size_t          offset;         /* Data buffer offset */
 386         uint8_t         hostctrl;       /* Current host control register */
 387         u_char          power;          /* Current power */
 388         u_char          bus_busy;       /* Bus busy status */
 389         u_char          cmd_done;       /* CMD command part done flag */
 390         u_char          data_done;      /* DAT command part done flag */
 391         u_char          flags;          /* Request execution flags */
 392 #define CMD_STARTED             1
 393 #define STOP_STARTED            2
 394 #define SDHCI_USE_SDMA          4       /* Use SDMA for this req. */
 395 #define PLATFORM_DATA_STARTED   8       /* Data transfer is handled by platform */
 396 #define SDHCI_USE_ADMA2         16      /* Use ADMA2 for this req. */
 397         struct lock     lock;           /* Slot mutex */
 398 };
 399
 400 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result);
 401 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value);
 402 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
 403 void sdhci_start_slot(struct sdhci_slot *slot);
 404 /* performs generic clean-up for platform transfers */
 405 void sdhci_finish_data(struct sdhci_slot *slot);
 406 int sdhci_cleanup_slot(struct sdhci_slot *slot);
 407 int sdhci_generic_suspend(struct sdhci_slot *slot);
 408 int sdhci_generic_resume(struct sdhci_slot *slot);
 409 int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
 410 int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev);
 411 int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req);
 412 int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
 413 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
 414 int sdhci_generic_release_host(device_t brdev, device_t reqdev);
 415 void sdhci_generic_intr(struct sdhci_slot *slot);
 416 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot);
 417 boolean_t sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot);
 418 void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot);
 419
 420 #endif  /* __SDHCI_H__ */