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rc.conf: Add and document the missing root_rw_mount=YES
[dragonfly.git] / sys / dev / disk / isp / isp_pci.c
blob560f35ce8f0f473c7cb7f13728a3097ac80e5772
1 /*-
2 * Copyright (c) 1997-2008 by Matthew Jacob
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice immediately at the beginning of the file, without modification,
10 * this list of conditions, and the following disclaimer.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/isp/isp_pci.c,v 1.159 2011/11/16 02:52:24 mjacob Exp $
27 */
28 /*
29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
30 * FreeBSD Version.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
39 #include <sys/bus.h>
40 #include <sys/stdint.h>
41 #include <bus/pci/pcireg.h>
42 #include <bus/pci/pcivar.h>
43 #include <sys/rman.h>
44 #include <sys/malloc.h>
45 #include <sys/uio.h>
46
47 #include <dev/disk/isp/isp_freebsd.h>
48
49 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
50 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
51 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
52 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
53 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
54 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
55 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
56 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
57 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
58 static int isp_pci_mbxdma(ispsoftc_t *);
59 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *);
60
61
62 static void isp_pci_reset0(ispsoftc_t *);
63 static void isp_pci_reset1(ispsoftc_t *);
64 static void isp_pci_dumpregs(ispsoftc_t *, const char *);
65
66 static struct ispmdvec mdvec = {
67 isp_pci_rd_isr,
68 isp_pci_rd_reg,
69 isp_pci_wr_reg,
70 isp_pci_mbxdma,
71 isp_pci_dmasetup,
72 isp_common_dmateardown,
73 isp_pci_reset0,
74 isp_pci_reset1,
75 isp_pci_dumpregs,
76 NULL,
77 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
78 };
79
80 static struct ispmdvec mdvec_1080 = {
81 isp_pci_rd_isr,
82 isp_pci_rd_reg_1080,
83 isp_pci_wr_reg_1080,
84 isp_pci_mbxdma,
85 isp_pci_dmasetup,
86 isp_common_dmateardown,
87 isp_pci_reset0,
88 isp_pci_reset1,
89 isp_pci_dumpregs,
90 NULL,
91 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
92 };
93
94 static struct ispmdvec mdvec_12160 = {
95 isp_pci_rd_isr,
96 isp_pci_rd_reg_1080,
97 isp_pci_wr_reg_1080,
98 isp_pci_mbxdma,
99 isp_pci_dmasetup,
100 isp_common_dmateardown,
101 isp_pci_reset0,
102 isp_pci_reset1,
103 isp_pci_dumpregs,
104 NULL,
105 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
106 };
107
108 static struct ispmdvec mdvec_2100 = {
109 isp_pci_rd_isr,
110 isp_pci_rd_reg,
111 isp_pci_wr_reg,
112 isp_pci_mbxdma,
113 isp_pci_dmasetup,
114 isp_common_dmateardown,
115 isp_pci_reset0,
116 isp_pci_reset1,
117 isp_pci_dumpregs
118 };
119
120 static struct ispmdvec mdvec_2200 = {
121 isp_pci_rd_isr,
122 isp_pci_rd_reg,
123 isp_pci_wr_reg,
124 isp_pci_mbxdma,
125 isp_pci_dmasetup,
126 isp_common_dmateardown,
127 isp_pci_reset0,
128 isp_pci_reset1,
129 isp_pci_dumpregs
130 };
131
132 static struct ispmdvec mdvec_2300 = {
133 isp_pci_rd_isr_2300,
134 isp_pci_rd_reg,
135 isp_pci_wr_reg,
136 isp_pci_mbxdma,
137 isp_pci_dmasetup,
138 isp_common_dmateardown,
139 isp_pci_reset0,
140 isp_pci_reset1,
141 isp_pci_dumpregs
142 };
143
144 static struct ispmdvec mdvec_2400 = {
145 isp_pci_rd_isr_2400,
146 isp_pci_rd_reg_2400,
147 isp_pci_wr_reg_2400,
148 isp_pci_mbxdma,
149 isp_pci_dmasetup,
150 isp_common_dmateardown,
151 isp_pci_reset0,
152 isp_pci_reset1,
153 NULL
154 };
155
156 static struct ispmdvec mdvec_2500 = {
157 isp_pci_rd_isr_2400,
158 isp_pci_rd_reg_2400,
159 isp_pci_wr_reg_2400,
160 isp_pci_mbxdma,
161 isp_pci_dmasetup,
162 isp_common_dmateardown,
163 isp_pci_reset0,
164 isp_pci_reset1,
165 NULL
166 };
167
168 #ifndef PCIM_CMD_INVEN
169 #define PCIM_CMD_INVEN 0x10
170 #endif
171 #ifndef PCIM_CMD_BUSMASTEREN
172 #define PCIM_CMD_BUSMASTEREN 0x0004
173 #endif
174 #ifndef PCIM_CMD_PERRESPEN
175 #define PCIM_CMD_PERRESPEN 0x0040
176 #endif
177 #ifndef PCIM_CMD_SEREN
178 #define PCIM_CMD_SEREN 0x0100
179 #endif
180 #ifndef PCIM_CMD_INTX_DISABLE
181 #define PCIM_CMD_INTX_DISABLE 0x0400
182 #endif
183
184 #ifndef PCIR_COMMAND
185 #define PCIR_COMMAND 0x04
186 #endif
187
188 #ifndef PCIR_CACHELNSZ
189 #define PCIR_CACHELNSZ 0x0c
190 #endif
191
192 #ifndef PCIR_LATTIMER
193 #define PCIR_LATTIMER 0x0d
194 #endif
195
196 #ifndef PCIR_ROMADDR
197 #define PCIR_ROMADDR 0x30
198 #endif
199
200 #ifndef PCI_VENDOR_QLOGIC
201 #define PCI_VENDOR_QLOGIC 0x1077
202 #endif
203
204 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
205 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
206 #endif
207
208 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
209 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
210 #endif
211
212 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
213 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
214 #endif
215
216 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
217 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
218 #endif
219
220 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
221 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
222 #endif
223
224 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
225 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
226 #endif
227
228 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
229 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
230 #endif
231
232 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
233 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
234 #endif
235
236 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
237 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
238 #endif
239
240 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
241 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
242 #endif
243
244 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
245 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
246 #endif
247
248 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
249 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
250 #endif
251
252 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
253 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
254 #endif
255
256 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
257 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
258 #endif
259
260 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
261 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
262 #endif
263
264 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
265 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
266 #endif
267
268 #ifndef PCI_PRODUCT_QLOGIC_ISP5432
269 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432
270 #endif
271
272 #define PCI_QLOGIC_ISP5432 \
273 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC)
274
275 #define PCI_QLOGIC_ISP1020 \
276 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
277
278 #define PCI_QLOGIC_ISP1080 \
279 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
280
281 #define PCI_QLOGIC_ISP10160 \
282 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
283
284 #define PCI_QLOGIC_ISP12160 \
285 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
286
287 #define PCI_QLOGIC_ISP1240 \
288 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
289
290 #define PCI_QLOGIC_ISP1280 \
291 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
292
293 #define PCI_QLOGIC_ISP2100 \
294 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
295
296 #define PCI_QLOGIC_ISP2200 \
297 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
298
299 #define PCI_QLOGIC_ISP2300 \
300 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
301
302 #define PCI_QLOGIC_ISP2312 \
303 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
304
305 #define PCI_QLOGIC_ISP2322 \
306 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
307
308 #define PCI_QLOGIC_ISP2422 \
309 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
310
311 #define PCI_QLOGIC_ISP2432 \
312 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
313
314 #define PCI_QLOGIC_ISP2532 \
315 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
316
317 #define PCI_QLOGIC_ISP6312 \
318 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
319
320 #define PCI_QLOGIC_ISP6322 \
321 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
322
323 /*
324 * Odd case for some AMI raid cards... We need to *not* attach to this.
325 */
326 #define AMI_RAID_SUBVENDOR_ID 0x101e
327
328 #define IO_MAP_REG 0x10
329 #define MEM_MAP_REG 0x14
330
331 #define PCI_DFLT_LTNCY 0x40
332 #define PCI_DFLT_LNSZ 0x10
333
334 static int isp_pci_probe (device_t);
335 static int isp_pci_attach (device_t);
336 static int isp_pci_detach (device_t);
337
338
339 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev
340 struct isp_pcisoftc {
341 ispsoftc_t pci_isp;
342 device_t pci_dev;
343 struct resource * regs;
344 void * irq;
345 int irq_type;
346 int iqd;
347 int rtp;
348 int rgd;
349 void * ih;
350 int16_t pci_poff[_NREG_BLKS];
351 bus_dma_tag_t dmat;
352 };
353
354 static int isp_msi_enable = 1;
355 TUNABLE_INT("hw.isp.msi.enable", &isp_msi_enable);
356
357 static device_method_t isp_pci_methods[] = {
358 /* Device interface */
359 DEVMETHOD(device_probe, isp_pci_probe),
360 DEVMETHOD(device_attach, isp_pci_attach),
361 DEVMETHOD(device_detach, isp_pci_detach),
362 DEVMETHOD_END
363 };
364
365 static driver_t isp_pci_driver = {
366 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
367 };
368 static devclass_t isp_devclass;
369 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, NULL, NULL);
370
371 static int
372 isp_pci_probe(device_t dev)
373 {
374 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) {
375 case PCI_QLOGIC_ISP1020:
376 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter");
377 break;
378 case PCI_QLOGIC_ISP1080:
379 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter");
380 break;
381 case PCI_QLOGIC_ISP1240:
382 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter");
383 break;
384 case PCI_QLOGIC_ISP1280:
385 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter");
386 break;
387 case PCI_QLOGIC_ISP10160:
388 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter");
389 break;
390 case PCI_QLOGIC_ISP12160:
391 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) {
392 return (ENXIO);
393 }
394 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter");
395 break;
396 case PCI_QLOGIC_ISP2100:
397 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter");
398 break;
399 case PCI_QLOGIC_ISP2200:
400 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter");
401 break;
402 case PCI_QLOGIC_ISP2300:
403 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
404 break;
405 case PCI_QLOGIC_ISP2312:
406 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
407 break;
408 case PCI_QLOGIC_ISP2322:
409 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
410 break;
411 case PCI_QLOGIC_ISP2422:
412 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
413 break;
414 case PCI_QLOGIC_ISP2432:
415 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter");
416 break;
417 case PCI_QLOGIC_ISP2532:
418 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter");
419 break;
420 case PCI_QLOGIC_ISP5432:
421 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter");
422 break;
423 case PCI_QLOGIC_ISP6312:
424 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
425 break;
426 case PCI_QLOGIC_ISP6322:
427 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
428 break;
429 default:
430 return (ENXIO);
431 }
432 if (isp_announced == 0 && bootverbose) {
433 kprintf("Qlogic ISP Driver, FreeBSD Version %d.%d, "
434 "Core Version %d.%d\n",
435 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
436 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
437 isp_announced++;
438 }
439 /*
440 * XXXX: Here is where we might load the f/w module
441 * XXXX: (or increase a reference count to it).
442 */
443 return (BUS_PROBE_DEFAULT);
444 }
445
446 static void
447 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp)
448 {
449 int tval;
450
451 /*
452 * Figure out if we're supposed to skip this one.
453 */
454 tval = 0;
455 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) {
456 device_printf(dev, "disabled at user request\n");
457 isp->isp_osinfo.disabled = 1;
458 return;
459 }
460
461 tval = 0;
462 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) {
463 isp->isp_confopts |= ISP_CFG_NORELOAD;
464 }
465 tval = 0;
466 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) {
467 isp->isp_confopts |= ISP_CFG_NONVRAM;
468 }
469 tval = 0;
470 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval);
471 if (tval) {
472 isp->isp_dblev = tval;
473 } else {
474 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
475 }
476 if (bootverbose) {
477 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
478 }
479 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval);
480 if (tval > 0 && tval < 127) {
481 *nvp = tval;
482 } else {
483 *nvp = 0;
484 }
485 tval = 1;
486 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval);
487 isp_autoconfig = tval;
488 tval = 7;
489 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval);
490 isp_quickboot_time = tval;
491
492 tval = 0;
493 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) {
494 isp->isp_osinfo.forcemulti = 1;
495 }
496 }
497
498 static void
499 isp_get_pci_options(device_t dev, int *m1, int *m2)
500 {
501 int tval;
502 /*
503 * Which we should try first - memory mapping or i/o mapping?
504 *
505 * We used to try memory first followed by i/o on alpha, otherwise
506 * the reverse, but we should just try memory first all the time now.
507 */
508 *m1 = PCIM_CMD_MEMEN;
509 *m2 = PCIM_CMD_PORTEN;
510
511 tval = 0;
512 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) {
513 *m1 = PCIM_CMD_PORTEN;
514 *m2 = PCIM_CMD_MEMEN;
515 }
516 tval = 0;
517 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) {
518 *m1 = PCIM_CMD_MEMEN;
519 *m2 = PCIM_CMD_PORTEN;
520 }
521 }
522
523 static void
524 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp)
525 {
526 const char *sptr;
527 int tval;
528
529 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) {
530 if (IS_FC(isp)) {
531 ISP_FC_PC(isp, chan)->default_id = 109 - chan;
532 } else {
533 ISP_SPI_PC(isp, chan)->iid = 7;
534 }
535 } else {
536 if (IS_FC(isp)) {
537 ISP_FC_PC(isp, chan)->default_id = tval - chan;
538 } else {
539 ISP_SPI_PC(isp, chan)->iid = tval;
540 }
541 isp->isp_confopts |= ISP_CFG_OWNLOOPID;
542 }
543
544 tval = -1;
545 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) {
546 switch (tval) {
547 case ISP_ROLE_NONE:
548 case ISP_ROLE_INITIATOR:
549 case ISP_ROLE_TARGET:
550 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET:
551 device_printf(dev, "setting role to 0x%x\n", tval);
552 break;
553 default:
554 tval = -1;
555 break;
556 }
557 }
558 if (tval == -1) {
559 tval = ISP_DEFAULT_ROLES;
560 }
561
562 if (IS_SCSI(isp)) {
563 ISP_SPI_PC(isp, chan)->def_role = tval;
564 return;
565 }
566 ISP_FC_PC(isp, chan)->def_role = tval;
567
568 tval = 0;
569 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) {
570 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX;
571 }
572 sptr = NULL;
573 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", &sptr) == 0 && sptr != NULL) {
574 if (strcmp(sptr, "lport") == 0) {
575 isp->isp_confopts |= ISP_CFG_LPORT;
576 } else if (strcmp(sptr, "nport") == 0) {
577 isp->isp_confopts |= ISP_CFG_NPORT;
578 } else if (strcmp(sptr, "lport-only") == 0) {
579 isp->isp_confopts |= ISP_CFG_LPORT_ONLY;
580 } else if (strcmp(sptr, "nport-only") == 0) {
581 isp->isp_confopts |= ISP_CFG_NPORT_ONLY;
582 }
583 }
584
585 /*
586 * Because the resource_*_value functions can neither return
587 * 64 bit integer values, nor can they be directly coerced
588 * to interpret the right hand side of the assignment as
589 * you want them to interpret it, we have to force WWN
590 * hint replacement to specify WWN strings with a leading
591 * 'w' (e..g w50000000aaaa0001). Sigh.
592 */
593 sptr = NULL;
594 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", &sptr);
595 if (tval == 0 && sptr != NULL && *sptr++ == 'w') {
596 char *eptr = NULL;
597 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16);
598 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) {
599 device_printf(dev, "mangled portwwn hint '%s'\n", sptr);
600 ISP_FC_PC(isp, chan)->def_wwpn = 0;
601 }
602 }
603
604 sptr = NULL;
605 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", &sptr);
606 if (tval == 0 && sptr != NULL && *sptr++ == 'w') {
607 char *eptr = NULL;
608 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16);
609 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) {
610 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr);
611 ISP_FC_PC(isp, chan)->def_wwnn = 0;
612 }
613 }
614
615 tval = 0;
616 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval);
617 if (tval >= 0 && tval < 256) {
618 ISP_FC_PC(isp, chan)->hysteresis = tval;
619 } else {
620 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis;
621 }
622
623 tval = -1;
624 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval);
625 if (tval >= 0 && tval < 0xffff) {
626 ISP_FC_PC(isp, chan)->loop_down_limit = tval;
627 } else {
628 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit;
629 }
630
631 tval = -1;
632 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval);
633 if (tval >= 0 && tval < 0xffff) {
634 ISP_FC_PC(isp, chan)->gone_device_time = tval;
635 } else {
636 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time;
637 }
638 }
639
640 static int
641 isp_pci_attach(device_t dev)
642 {
643 int i, m1, m2, locksetup = 0;
644 int isp_nvports = 0;
645 uint32_t data, cmd, linesz, did;
646 struct isp_pcisoftc *pcs;
647 ispsoftc_t *isp;
648 size_t psize, xsize;
649 char fwname[32];
650 u_int irq_flags;
651
652 pcs = device_get_softc(dev);
653 if (pcs == NULL) {
654 device_printf(dev, "cannot get softc\n");
655 return (ENOMEM);
656 }
657 memset(pcs, 0, sizeof (*pcs));
658
659 pcs->pci_dev = dev;
660 isp = &pcs->pci_isp;
661 isp->isp_dev = dev;
662 isp->isp_nchan = 1;
663
664 /*
665 * Get Generic Options
666 */
667 isp_get_generic_options(dev, isp, &isp_nvports);
668
669 /*
670 * Check to see if options have us disabled
671 */
672 if (isp->isp_osinfo.disabled) {
673 /*
674 * But return zero to preserve unit numbering
675 */
676 return (0);
677 }
678
679 /*
680 * Get PCI options- which in this case are just mapping preferences.
681 */
682 isp_get_pci_options(dev, &m1, &m2);
683
684 linesz = PCI_DFLT_LNSZ;
685 pcs->irq = pcs->regs = NULL;
686 pcs->rgd = pcs->rtp = pcs->iqd = 0;
687
688 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
689 if (cmd & m1) {
690 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
691 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
692 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
693 }
694 if (pcs->regs == NULL && (cmd & m2)) {
695 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
696 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
697 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
698 }
699 if (pcs->regs == NULL) {
700 device_printf(dev, "unable to map any ports\n");
701 goto bad;
702 }
703 if (bootverbose) {
704 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory");
705 }
706 isp->isp_bus_tag = rman_get_bustag(pcs->regs);
707 isp->isp_bus_handle = rman_get_bushandle(pcs->regs);
708
709 pcs->pci_dev = dev;
710 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
711 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
712 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
713 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
714 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
715
716 switch (pci_get_devid(dev)) {
717 case PCI_QLOGIC_ISP1020:
718 did = 0x1040;
719 isp->isp_mdvec = &mdvec;
720 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
721 break;
722 case PCI_QLOGIC_ISP1080:
723 did = 0x1080;
724 isp->isp_mdvec = &mdvec_1080;
725 isp->isp_type = ISP_HA_SCSI_1080;
726 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
727 break;
728 case PCI_QLOGIC_ISP1240:
729 did = 0x1080;
730 isp->isp_mdvec = &mdvec_1080;
731 isp->isp_type = ISP_HA_SCSI_1240;
732 isp->isp_nchan = 2;
733 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
734 break;
735 case PCI_QLOGIC_ISP1280:
736 did = 0x1080;
737 isp->isp_mdvec = &mdvec_1080;
738 isp->isp_type = ISP_HA_SCSI_1280;
739 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
740 break;
741 case PCI_QLOGIC_ISP10160:
742 did = 0x12160;
743 isp->isp_mdvec = &mdvec_12160;
744 isp->isp_type = ISP_HA_SCSI_10160;
745 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
746 break;
747 case PCI_QLOGIC_ISP12160:
748 did = 0x12160;
749 isp->isp_nchan = 2;
750 isp->isp_mdvec = &mdvec_12160;
751 isp->isp_type = ISP_HA_SCSI_12160;
752 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
753 break;
754 case PCI_QLOGIC_ISP2100:
755 did = 0x2100;
756 isp->isp_mdvec = &mdvec_2100;
757 isp->isp_type = ISP_HA_FC_2100;
758 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
759 if (pci_get_revid(dev) < 3) {
760 /*
761 * XXX: Need to get the actual revision
762 * XXX: number of the 2100 FB. At any rate,
763 * XXX: lower cache line size for early revision
764 * XXX; boards.
765 */
766 linesz = 1;
767 }
768 break;
769 case PCI_QLOGIC_ISP2200:
770 did = 0x2200;
771 isp->isp_mdvec = &mdvec_2200;
772 isp->isp_type = ISP_HA_FC_2200;
773 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
774 break;
775 case PCI_QLOGIC_ISP2300:
776 did = 0x2300;
777 isp->isp_mdvec = &mdvec_2300;
778 isp->isp_type = ISP_HA_FC_2300;
779 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
780 break;
781 case PCI_QLOGIC_ISP2312:
782 case PCI_QLOGIC_ISP6312:
783 did = 0x2300;
784 isp->isp_mdvec = &mdvec_2300;
785 isp->isp_type = ISP_HA_FC_2312;
786 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
787 break;
788 case PCI_QLOGIC_ISP2322:
789 case PCI_QLOGIC_ISP6322:
790 did = 0x2322;
791 isp->isp_mdvec = &mdvec_2300;
792 isp->isp_type = ISP_HA_FC_2322;
793 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
794 break;
795 case PCI_QLOGIC_ISP2422:
796 case PCI_QLOGIC_ISP2432:
797 did = 0x2400;
798 isp->isp_nchan += isp_nvports;
799 isp->isp_mdvec = &mdvec_2400;
800 isp->isp_type = ISP_HA_FC_2400;
801 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
802 break;
803 case PCI_QLOGIC_ISP2532:
804 did = 0x2500;
805 isp->isp_nchan += isp_nvports;
806 isp->isp_mdvec = &mdvec_2500;
807 isp->isp_type = ISP_HA_FC_2500;
808 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
809 break;
810 case PCI_QLOGIC_ISP5432:
811 did = 0x2500;
812 isp->isp_mdvec = &mdvec_2500;
813 isp->isp_type = ISP_HA_FC_2500;
814 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
815 break;
816 default:
817 device_printf(dev, "unknown device type\n");
818 goto bad;
819 break;
820 }
821 isp->isp_revision = pci_get_revid(dev);
822
823 if (IS_FC(isp)) {
824 psize = sizeof (fcparam);
825 xsize = sizeof (struct isp_fc);
826 } else {
827 psize = sizeof (sdparam);
828 xsize = sizeof (struct isp_spi);
829 }
830 psize *= isp->isp_nchan;
831 xsize *= isp->isp_nchan;
832 isp->isp_param = kmalloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
833 if (isp->isp_param == NULL) {
834 device_printf(dev, "cannot allocate parameter data\n");
835 goto bad;
836 }
837 isp->isp_osinfo.pc.ptr = kmalloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO);
838 if (isp->isp_osinfo.pc.ptr == NULL) {
839 device_printf(dev, "cannot allocate parameter data\n");
840 goto bad;
841 }
842
843 /*
844 * Now that we know who we are (roughly) get/set specific options
845 */
846 for (i = 0; i < isp->isp_nchan; i++) {
847 isp_get_specific_options(dev, i, isp);
848 }
849
850 /*
851 * The 'it' suffix really only matters for SCSI cards in target mode.
852 */
853 isp->isp_osinfo.fw = NULL;
854 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) {
855 ksnprintf(fwname, sizeof (fwname), "isp_%04x_it", did);
856 isp->isp_osinfo.fw = firmware_get(fwname);
857 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) {
858 ksnprintf(fwname, sizeof (fwname), "isp_%04x_multi", did);
859 isp->isp_osinfo.fw = firmware_get(fwname);
860 }
861 if (isp->isp_osinfo.fw == NULL) {
862 ksnprintf(fwname, sizeof (fwname), "isp_%04x", did);
863 #ifdef USE_SMALLER_2100_FIRMWARE
864 if (IS_21XX(isp)) {
865 ksnprintf(fwname, sizeof (fwname), "%s_variant_1", fwname);
866 }
867 #endif
868 isp->isp_osinfo.fw = firmware_get(fwname);
869 }
870 if (isp->isp_osinfo.fw != NULL) {
871 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data;
872 }
873
874 /*
875 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER
876 * are set.
877 */
878 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN |
879 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
880
881 if (IS_2300(isp)) { /* per QLogic errata */
882 cmd &= ~PCIM_CMD_INVEN;
883 }
884
885 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
886 cmd &= ~PCIM_CMD_INTX_DISABLE;
887 }
888
889 if (IS_24XX(isp)) {
890 cmd &= ~PCIM_CMD_INTX_DISABLE;
891 }
892
893 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
894
895 /*
896 * Make sure the Cache Line Size register is set sensibly.
897 */
898 data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
899 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) {
900 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data);
901 data = linesz;
902 pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
903 }
904
905 /*
906 * Make sure the Latency Timer is sane.
907 */
908 data = pci_read_config(dev, PCIR_LATTIMER, 1);
909 if (data < PCI_DFLT_LTNCY) {
910 data = PCI_DFLT_LTNCY;
911 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data);
912 pci_write_config(dev, PCIR_LATTIMER, data, 1);
913 }
914
915 /*
916 * Make sure we've disabled the ROM.
917 */
918 data = pci_read_config(dev, PCIR_ROMADDR, 4);
919 data &= ~1;
920 pci_write_config(dev, PCIR_ROMADDR, data, 4);
921
922 pcs->irq_type = pci_alloc_1intr(dev, isp_msi_enable, &pcs->iqd,
923 &irq_flags);
924 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd,
925 irq_flags);
926 if (pcs->irq == NULL) {
927 device_printf(dev, "could not allocate interrupt\n");
928 goto bad;
929 }
930
931 /* Make sure the lock is set up. */
932 lockinit(&isp->isp_osinfo.lock, "isp", 0, LK_CANRECURSE);
933 locksetup++;
934
935 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, isp_platform_intr, isp, &pcs->ih, NULL)) {
936 device_printf(dev, "could not setup interrupt\n");
937 goto bad;
938 }
939
940 /*
941 * Last minute checks...
942 */
943 if (IS_23XX(isp) || IS_24XX(isp)) {
944 isp->isp_port = pci_get_function(dev);
945 }
946
947 /*
948 * Make sure we're in reset state.
949 */
950 ISP_LOCK(isp);
951 isp_reset(isp, 1);
952 if (isp->isp_state != ISP_RESETSTATE) {
953 ISP_UNLOCK(isp);
954 goto bad;
955 }
956 isp_init(isp);
957 if (isp->isp_state == ISP_INITSTATE) {
958 isp->isp_state = ISP_RUNSTATE;
959 }
960 ISP_UNLOCK(isp);
961 if (isp_attach(isp)) {
962 ISP_LOCK(isp);
963 isp_uninit(isp);
964 ISP_UNLOCK(isp);
965 goto bad;
966 }
967 return (0);
968
969 bad:
970 if (pcs->ih) {
971 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
972 }
973 if (locksetup) {
974 lockuninit(&isp->isp_osinfo.lock);
975 }
976 if (pcs->irq) {
977 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
978 }
979 if (pcs->irq_type == PCI_INTR_TYPE_MSI) {
980 pci_release_msi(dev);
981 }
982 if (pcs->regs) {
983 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
984 }
985 if (pcs->pci_isp.isp_param) {
986 kfree(pcs->pci_isp.isp_param, M_DEVBUF);
987 pcs->pci_isp.isp_param = NULL;
988 }
989 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
990 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
991 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
992 }
993 return (ENXIO);
994 }
995
996 static int
997 isp_pci_detach(device_t dev)
998 {
999 struct isp_pcisoftc *pcs;
1000 ispsoftc_t *isp;
1001 int status;
1002
1003 pcs = device_get_softc(dev);
1004 if (pcs == NULL) {
1005 return (ENXIO);
1006 }
1007 isp = (ispsoftc_t *) pcs;
1008 status = isp_detach(isp);
1009 if (status)
1010 return (status);
1011 ISP_LOCK(isp);
1012 isp_uninit(isp);
1013 if (pcs->ih) {
1014 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1015 }
1016 ISP_UNLOCK(isp);
1017 lockuninit(&isp->isp_osinfo.lock);
1018 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1019 if (pcs->irq_type == PCI_INTR_TYPE_MSI) {
1020 pci_release_msi(dev);
1021 }
1022 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1023 if (pcs->pci_isp.isp_param) {
1024 kfree(pcs->pci_isp.isp_param, M_DEVBUF);
1025 pcs->pci_isp.isp_param = NULL;
1026 }
1027 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1028 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1029 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1030 }
1031 return (0);
1032 }
1033
1034 #define IspVirt2Off(a, x) \
1035 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1036 _BLK_REG_SHFT] + ((x) & 0xfff))
1037
1038 #define BXR2(isp, off) \
1039 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off)
1040 #define BXW2(isp, off, v) \
1041 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
1042 #define BXR4(isp, off) \
1043 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off)
1044 #define BXW4(isp, off, v) \
1045 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
1046
1047
1048 static ISP_INLINE int
1049 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1050 {
1051 uint32_t val0, val1;
1052 int i = 0;
1053
1054 do {
1055 val0 = BXR2(isp, IspVirt2Off(isp, off));
1056 val1 = BXR2(isp, IspVirt2Off(isp, off));
1057 } while (val0 != val1 && ++i < 1000);
1058 if (val0 != val1) {
1059 return (1);
1060 }
1061 *rp = val0;
1062 return (0);
1063 }
1064
1065 static int
1066 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp)
1067 {
1068 uint16_t isr, sema;
1069
1070 if (IS_2100(isp)) {
1071 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1072 return (0);
1073 }
1074 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
1075 return (0);
1076 }
1077 } else {
1078 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR));
1079 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA));
1080 }
1081 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
1082 isr &= INT_PENDING_MASK(isp);
1083 sema &= BIU_SEMA_LOCK;
1084 if (isr == 0 && sema == 0) {
1085 return (0);
1086 }
1087 *isrp = isr;
1088 if ((*semap = sema) != 0) {
1089 if (IS_2100(isp)) {
1090 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
1091 return (0);
1092 }
1093 } else {
1094 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0));
1095 }
1096 }
1097 return (1);
1098 }
1099
1100 static int
1101 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p)
1102 {
1103 uint32_t hccr;
1104 uint32_t r2hisr;
1105
1106 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1107 *isrp = 0;
1108 return (0);
1109 }
1110 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO));
1111 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1112 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1113 *isrp = 0;
1114 return (0);
1115 }
1116 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
1117 case ISPR2HST_ROM_MBX_OK:
1118 case ISPR2HST_ROM_MBX_FAIL:
1119 case ISPR2HST_MBX_OK:
1120 case ISPR2HST_MBX_FAIL:
1121 case ISPR2HST_ASYNC_EVENT:
1122 *isrp = r2hisr & 0xffff;
1123 *mbox0p = (r2hisr >> 16);
1124 *semap = 1;
1125 return (1);
1126 case ISPR2HST_RIO_16:
1127 *isrp = r2hisr & 0xffff;
1128 *mbox0p = ASYNC_RIO16_1;
1129 *semap = 1;
1130 return (1);
1131 case ISPR2HST_FPOST:
1132 *isrp = r2hisr & 0xffff;
1133 *mbox0p = ASYNC_CMD_CMPLT;
1134 *semap = 1;
1135 return (1);
1136 case ISPR2HST_FPOST_CTIO:
1137 *isrp = r2hisr & 0xffff;
1138 *mbox0p = ASYNC_CTIO_DONE;
1139 *semap = 1;
1140 return (1);
1141 case ISPR2HST_RSPQ_UPDATE:
1142 *isrp = r2hisr & 0xffff;
1143 *mbox0p = 0;
1144 *semap = 0;
1145 return (1);
1146 default:
1147 hccr = ISP_READ(isp, HCCR);
1148 if (hccr & HCCR_PAUSE) {
1149 ISP_WRITE(isp, HCCR, HCCR_RESET);
1150 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR));
1151 ISP_WRITE(isp, BIU_ICR, 0);
1152 } else {
1153 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1154 }
1155 return (0);
1156 }
1157 }
1158
1159 static int
1160 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p)
1161 {
1162 uint32_t r2hisr;
1163
1164 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO));
1165 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1166 if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
1167 *isrp = 0;
1168 return (0);
1169 }
1170 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
1171 case ISP2400R2HST_ROM_MBX_OK:
1172 case ISP2400R2HST_ROM_MBX_FAIL:
1173 case ISP2400R2HST_MBX_OK:
1174 case ISP2400R2HST_MBX_FAIL:
1175 case ISP2400R2HST_ASYNC_EVENT:
1176 *isrp = r2hisr & 0xffff;
1177 *mbox0p = (r2hisr >> 16);
1178 *semap = 1;
1179 return (1);
1180 case ISP2400R2HST_RSPQ_UPDATE:
1181 case ISP2400R2HST_ATIO_RSPQ_UPDATE:
1182 case ISP2400R2HST_ATIO_RQST_UPDATE:
1183 *isrp = r2hisr & 0xffff;
1184 *mbox0p = 0;
1185 *semap = 0;
1186 return (1);
1187 default:
1188 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1189 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1190 return (0);
1191 }
1192 }
1193
1194 static uint32_t
1195 isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1196 {
1197 uint16_t rv;
1198 int oldconf = 0;
1199
1200 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1201 /*
1202 * We will assume that someone has paused the RISC processor.
1203 */
1204 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1205 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP);
1206 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1207 }
1208 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1209 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1210 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1211 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1212 }
1213 return (rv);
1214 }
1215
1216 static void
1217 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1218 {
1219 int oldconf = 0;
1220
1221 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1222 /*
1223 * We will assume that someone has paused the RISC processor.
1224 */
1225 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1226 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1227 oldconf | BIU_PCI_CONF1_SXP);
1228 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1229 }
1230 BXW2(isp, IspVirt2Off(isp, regoff), val);
1231 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1232 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1233 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1234 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1235 }
1236
1237 }
1238
1239 static uint32_t
1240 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1241 {
1242 uint32_t rv, oc = 0;
1243
1244 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1245 uint32_t tc;
1246 /*
1247 * We will assume that someone has paused the RISC processor.
1248 */
1249 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1250 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1251 if (regoff & SXP_BANK1_SELECT)
1252 tc |= BIU_PCI1080_CONF1_SXP1;
1253 else
1254 tc |= BIU_PCI1080_CONF1_SXP0;
1255 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1256 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1257 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1258 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1259 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1260 oc | BIU_PCI1080_CONF1_DMA);
1261 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1262 }
1263 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1264 if (oc) {
1265 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1266 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1267 }
1268 return (rv);
1269 }
1270
1271 static void
1272 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1273 {
1274 int oc = 0;
1275
1276 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1277 uint32_t tc;
1278 /*
1279 * We will assume that someone has paused the RISC processor.
1280 */
1281 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1282 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1283 if (regoff & SXP_BANK1_SELECT)
1284 tc |= BIU_PCI1080_CONF1_SXP1;
1285 else
1286 tc |= BIU_PCI1080_CONF1_SXP0;
1287 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1288 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1289 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1290 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1291 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1292 oc | BIU_PCI1080_CONF1_DMA);
1293 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1294 }
1295 BXW2(isp, IspVirt2Off(isp, regoff), val);
1296 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1297 if (oc) {
1298 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1299 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1300 }
1301 }
1302
1303 static uint32_t
1304 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1305 {
1306 uint32_t rv;
1307 int block = regoff & _BLK_REG_MASK;
1308
1309 switch (block) {
1310 case BIU_BLOCK:
1311 break;
1312 case MBOX_BLOCK:
1313 return (BXR2(isp, IspVirt2Off(isp, regoff)));
1314 case SXP_BLOCK:
1315 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
1316 return (0xffffffff);
1317 case RISC_BLOCK:
1318 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
1319 return (0xffffffff);
1320 case DMA_BLOCK:
1321 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
1322 return (0xffffffff);
1323 default:
1324 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
1325 return (0xffffffff);
1326 }
1327
1328
1329 switch (regoff) {
1330 case BIU2400_FLASH_ADDR:
1331 case BIU2400_FLASH_DATA:
1332 case BIU2400_ICR:
1333 case BIU2400_ISR:
1334 case BIU2400_CSR:
1335 case BIU2400_REQINP:
1336 case BIU2400_REQOUTP:
1337 case BIU2400_RSPINP:
1338 case BIU2400_RSPOUTP:
1339 case BIU2400_PRI_REQINP:
1340 case BIU2400_PRI_REQOUTP:
1341 case BIU2400_ATIO_RSPINP:
1342 case BIU2400_ATIO_RSPOUTP:
1343 case BIU2400_HCCR:
1344 case BIU2400_GPIOD:
1345 case BIU2400_GPIOE:
1346 case BIU2400_HSEMA:
1347 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1348 break;
1349 case BIU2400_R2HSTSLO:
1350 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1351 break;
1352 case BIU2400_R2HSTSHI:
1353 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
1354 break;
1355 default:
1356 isp_prt(isp, ISP_LOGERR,
1357 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1358 rv = 0xffffffff;
1359 break;
1360 }
1361 return (rv);
1362 }
1363
1364 static void
1365 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1366 {
1367 int block = regoff & _BLK_REG_MASK;
1368
1369 switch (block) {
1370 case BIU_BLOCK:
1371 break;
1372 case MBOX_BLOCK:
1373 BXW2(isp, IspVirt2Off(isp, regoff), val);
1374 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1375 return;
1376 case SXP_BLOCK:
1377 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1378 return;
1379 case RISC_BLOCK:
1380 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1381 return;
1382 case DMA_BLOCK:
1383 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1384 return;
1385 default:
1386 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1387 regoff);
1388 break;
1389 }
1390
1391 switch (regoff) {
1392 case BIU2400_FLASH_ADDR:
1393 case BIU2400_FLASH_DATA:
1394 case BIU2400_ICR:
1395 case BIU2400_ISR:
1396 case BIU2400_CSR:
1397 case BIU2400_REQINP:
1398 case BIU2400_REQOUTP:
1399 case BIU2400_RSPINP:
1400 case BIU2400_RSPOUTP:
1401 case BIU2400_PRI_REQINP:
1402 case BIU2400_PRI_REQOUTP:
1403 case BIU2400_ATIO_RSPINP:
1404 case BIU2400_ATIO_RSPOUTP:
1405 case BIU2400_HCCR:
1406 case BIU2400_GPIOD:
1407 case BIU2400_GPIOE:
1408 case BIU2400_HSEMA:
1409 BXW4(isp, IspVirt2Off(isp, regoff), val);
1410 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
1411 break;
1412 default:
1413 isp_prt(isp, ISP_LOGERR,
1414 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1415 break;
1416 }
1417 }
1418
1419
1420 struct imush {
1421 ispsoftc_t *isp;
1422 caddr_t vbase;
1423 int chan;
1424 int error;
1425 };
1426
1427 static void imc(void *, bus_dma_segment_t *, int, int);
1428 static void imc1(void *, bus_dma_segment_t *, int, int);
1429
1430 static void
1431 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1432 {
1433 struct imush *imushp = (struct imush *) arg;
1434
1435 if (error) {
1436 imushp->error = error;
1437 return;
1438 }
1439 if (nseg != 1) {
1440 imushp->error = EINVAL;
1441 return;
1442 }
1443 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1444 imushp->isp->isp_rquest = imushp->vbase;
1445 imushp->isp->isp_rquest_dma = segs->ds_addr;
1446 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1447 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1448 imushp->isp->isp_result_dma = segs->ds_addr;
1449 imushp->isp->isp_result = imushp->vbase;
1450
1451 #ifdef ISP_TARGET_MODE
1452 if (IS_24XX(imushp->isp)) {
1453 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1454 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1455 imushp->isp->isp_atioq_dma = segs->ds_addr;
1456 imushp->isp->isp_atioq = imushp->vbase;
1457 }
1458 #endif
1459 }
1460
1461 static void
1462 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1463 {
1464 struct imush *imushp = (struct imush *) arg;
1465 if (error) {
1466 imushp->error = error;
1467 return;
1468 }
1469 if (nseg != 1) {
1470 imushp->error = EINVAL;
1471 return;
1472 }
1473 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1474 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr;
1475 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase;
1476 }
1477
1478 static int
1479 isp_pci_mbxdma(ispsoftc_t *isp)
1480 {
1481 caddr_t base;
1482 uint32_t len;
1483 int i, error, ns, cmap = 0;
1484 bus_size_t slim; /* segment size */
1485 bus_addr_t llim; /* low limit of unavailable dma */
1486 bus_addr_t hlim; /* high limit of unavailable dma */
1487 struct imush im;
1488
1489 /*
1490 * Already been here? If so, leave...
1491 */
1492 if (isp->isp_rquest) {
1493 return (0);
1494 }
1495 ISP_UNLOCK(isp);
1496
1497 if (isp->isp_maxcmds == 0) {
1498 isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1499 ISP_LOCK(isp);
1500 return (1);
1501 }
1502
1503 hlim = BUS_SPACE_MAXADDR;
1504 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1505 if (sizeof (bus_size_t) > 4) {
1506 slim = (bus_size_t) (1ULL << 32);
1507 } else {
1508 slim = (bus_size_t) (1UL << 31);
1509 }
1510 llim = BUS_SPACE_MAXADDR;
1511 } else {
1512 llim = BUS_SPACE_MAXADDR_32BIT;
1513 slim = (1UL << 24);
1514 }
1515
1516 len = isp->isp_maxcmds * sizeof (struct isp_pcmd);
1517 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1518 if (isp->isp_osinfo.pcmd_pool == NULL) {
1519 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds");
1520 ISP_LOCK(isp);
1521 return (1);
1522 }
1523
1524 /*
1525 * XXX: We don't really support 64 bit target mode for parallel scsi yet
1526 */
1527 #ifdef ISP_TARGET_MODE
1528 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) {
1529 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1530 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet");
1531 ISP_LOCK(isp);
1532 return (1);
1533 }
1534 #endif
1535
1536 if (isp_dma_tag_create(NULL, 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) {
1537 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1538 ISP_LOCK(isp);
1539 isp_prt(isp, ISP_LOGERR, "could not create master dma tag");
1540 return (1);
1541 }
1542
1543 len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1544 isp->isp_xflist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1545 if (isp->isp_xflist == NULL) {
1546 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1547 ISP_LOCK(isp);
1548 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array");
1549 return (1);
1550 }
1551 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1552 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1553 }
1554 isp->isp_xffree = isp->isp_xflist;
1555 #ifdef ISP_TARGET_MODE
1556 len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1557 isp->isp_tgtlist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1558 if (isp->isp_tgtlist == NULL) {
1559 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1560 kfree(isp->isp_xflist, M_DEVBUF);
1561 ISP_LOCK(isp);
1562 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array");
1563 return (1);
1564 }
1565 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1566 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1];
1567 }
1568 isp->isp_tgtfree = isp->isp_tgtlist;
1569 #endif
1570
1571 /*
1572 * Allocate and map the request and result queues (and ATIO queue
1573 * if we're a 2400 supporting target mode).
1574 */
1575 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1576 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1577 #ifdef ISP_TARGET_MODE
1578 if (IS_24XX(isp)) {
1579 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1580 }
1581 #endif
1582
1583 ns = (len / PAGE_SIZE) + 1;
1584
1585 /*
1586 * Create a tag for the control spaces. We don't always need this
1587 * to be 32 bits, but we do this for simplicity and speed's sake.
1588 */
1589 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) {
1590 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces");
1591 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1592 kfree(isp->isp_xflist, M_DEVBUF);
1593 #ifdef ISP_TARGET_MODE
1594 kfree(isp->isp_tgtlist, M_DEVBUF);
1595 #endif
1596 ISP_LOCK(isp);
1597 return (1);
1598 }
1599
1600 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) {
1601 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len);
1602 bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1603 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1604 kfree(isp->isp_xflist, M_DEVBUF);
1605 #ifdef ISP_TARGET_MODE
1606 kfree(isp->isp_tgtlist, M_DEVBUF);
1607 #endif
1608 ISP_LOCK(isp);
1609 return (1);
1610 }
1611
1612 im.isp = isp;
1613 im.chan = 0;
1614 im.vbase = base;
1615 im.error = 0;
1616
1617 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0);
1618 if (im.error) {
1619 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error);
1620 goto bad;
1621 }
1622
1623 if (IS_FC(isp)) {
1624 for (cmap = 0; cmap < isp->isp_nchan; cmap++) {
1625 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1626 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) {
1627 goto bad;
1628 }
1629 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) {
1630 bus_dma_tag_destroy(fc->tdmat);
1631 goto bad;
1632 }
1633 im.isp = isp;
1634 im.chan = cmap;
1635 im.vbase = base;
1636 im.error = 0;
1637 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0);
1638 if (im.error) {
1639 bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1640 bus_dma_tag_destroy(fc->tdmat);
1641 goto bad;
1642 }
1643 }
1644 }
1645
1646 for (i = 0; i < isp->isp_maxcmds; i++) {
1647 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i];
1648 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap);
1649 if (error) {
1650 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error);
1651 while (--i >= 0) {
1652 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap);
1653 }
1654 goto bad;
1655 }
1656 callout_init(&pcmd->wdog);
1657 if (i == isp->isp_maxcmds-1) {
1658 pcmd->next = NULL;
1659 } else {
1660 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1];
1661 }
1662 }
1663 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0];
1664 ISP_LOCK(isp);
1665 return (0);
1666
1667 bad:
1668 while (--cmap >= 0) {
1669 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1670 bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1671 bus_dma_tag_destroy(fc->tdmat);
1672 }
1673 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap);
1674 bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1675 kfree(isp->isp_xflist, M_DEVBUF);
1676 #ifdef ISP_TARGET_MODE
1677 kfree(isp->isp_tgtlist, M_DEVBUF);
1678 #endif
1679 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1680 isp->isp_rquest = NULL;
1681 ISP_LOCK(isp);
1682 return (1);
1683 }
1684
1685 typedef struct {
1686 ispsoftc_t *isp;
1687 void *cmd_token;
1688 void *rq; /* original request */
1689 int error;
1690 bus_size_t mapsize;
1691 } mush_t;
1692
1693 #define MUSHERR_NOQENTRIES -2
1694
1695 #ifdef ISP_TARGET_MODE
1696 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1697 static void tdma2(void *, bus_dma_segment_t *, int, int);
1698
1699 static void
1700 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1701 {
1702 mush_t *mp;
1703 mp = (mush_t *)arg;
1704 mp->mapsize = mapsize;
1705 tdma2(arg, dm_segs, nseg, error);
1706 }
1707
1708 static void
1709 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1710 {
1711 mush_t *mp;
1712 ispsoftc_t *isp;
1713 struct ccb_scsiio *csio;
1714 isp_ddir_t ddir;
1715 ispreq_t *rq;
1716
1717 mp = (mush_t *) arg;
1718 if (error) {
1719 mp->error = error;
1720 return;
1721 }
1722 csio = mp->cmd_token;
1723 isp = mp->isp;
1724 rq = mp->rq;
1725 if (nseg) {
1726 if (sizeof (bus_addr_t) > 4) {
1727 if (nseg >= ISP_NSEG64_MAX) {
1728 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1729 mp->error = EFAULT;
1730 return;
1731 }
1732 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) {
1733 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3;
1734 }
1735 } else {
1736 if (nseg >= ISP_NSEG_MAX) {
1737 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1738 mp->error = EFAULT;
1739 return;
1740 }
1741 }
1742 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1743 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1744 ddir = ISP_TO_DEVICE;
1745 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1746 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1747 ddir = ISP_FROM_DEVICE;
1748 } else {
1749 dm_segs = NULL;
1750 nseg = 0;
1751 ddir = ISP_NOXFR;
1752 }
1753 } else {
1754 dm_segs = NULL;
1755 nseg = 0;
1756 ddir = ISP_NOXFR;
1757 }
1758
1759 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) {
1760 mp->error = MUSHERR_NOQENTRIES;
1761 }
1762 }
1763 #endif
1764
1765 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1766 static void dma2(void *, bus_dma_segment_t *, int, int);
1767
1768 static void
1769 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1770 {
1771 mush_t *mp;
1772 mp = (mush_t *)arg;
1773 mp->mapsize = mapsize;
1774 dma2(arg, dm_segs, nseg, error);
1775 }
1776
1777 static void
1778 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1779 {
1780 mush_t *mp;
1781 ispsoftc_t *isp;
1782 struct ccb_scsiio *csio;
1783 isp_ddir_t ddir;
1784 ispreq_t *rq;
1785
1786 mp = (mush_t *) arg;
1787 if (error) {
1788 mp->error = error;
1789 return;
1790 }
1791 csio = mp->cmd_token;
1792 isp = mp->isp;
1793 rq = mp->rq;
1794 if (nseg) {
1795 if (sizeof (bus_addr_t) > 4) {
1796 if (nseg >= ISP_NSEG64_MAX) {
1797 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1798 mp->error = EFAULT;
1799 return;
1800 }
1801 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1802 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1803 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1804 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1805 }
1806 } else {
1807 if (nseg >= ISP_NSEG_MAX) {
1808 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1809 mp->error = EFAULT;
1810 return;
1811 }
1812 }
1813 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1814 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1815 ddir = ISP_FROM_DEVICE;
1816 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1817 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1818 ddir = ISP_TO_DEVICE;
1819 } else {
1820 ddir = ISP_NOXFR;
1821 }
1822 } else {
1823 dm_segs = NULL;
1824 nseg = 0;
1825 ddir = ISP_NOXFR;
1826 }
1827
1828 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) {
1829 mp->error = MUSHERR_NOQENTRIES;
1830 }
1831 }
1832
1833 static int
1834 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff)
1835 {
1836 mush_t mush, *mp;
1837 void (*eptr)(void *, bus_dma_segment_t *, int, int);
1838 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int);
1839
1840 mp = &mush;
1841 mp->isp = isp;
1842 mp->cmd_token = csio;
1843 mp->rq = ff;
1844 mp->error = 0;
1845 mp->mapsize = 0;
1846
1847 #ifdef ISP_TARGET_MODE
1848 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) {
1849 eptr = tdma2;
1850 eptr2 = tdma2_2;
1851 } else
1852 #endif
1853 {
1854 eptr = dma2;
1855 eptr2 = dma2_2;
1856 }
1857
1858
1859 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) {
1860 (*eptr)(mp, NULL, 0, 0);
1861 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
1862 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) {
1863 int error;
1864 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0);
1865 #if 0
1866 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error);
1867 #endif
1868
1869 if (error == EINPROGRESS) {
1870 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap);
1871 mp->error = EINVAL;
1872 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported");
1873 } else if (error && mp->error == 0) {
1874 #ifdef DIAGNOSTIC
1875 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
1876 #endif
1877 mp->error = error;
1878 }
1879 } else {
1880 /* Pointer to physical buffer */
1881 struct bus_dma_segment seg;
1882 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr;
1883 seg.ds_len = csio->dxfer_len;
1884 (*eptr)(mp, &seg, 1, 0);
1885 }
1886 } else {
1887 struct bus_dma_segment *segs;
1888
1889 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) {
1890 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported");
1891 mp->error = EINVAL;
1892 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) {
1893 struct uio sguio;
1894 int error;
1895
1896 /*
1897 * We're taking advantage of the fact that
1898 * the pointer/length sizes and layout of the iovec
1899 * structure are the same as the bus_dma_segment
1900 * structure. This might be a little dangerous,
1901 * but only if they change the structures, which
1902 * seems unlikely.
1903 */
1904 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) &&
1905 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) &&
1906 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed"));
1907 sguio.uio_iov = (struct iovec *)csio->data_ptr;
1908 sguio.uio_iovcnt = csio->sglist_cnt;
1909 sguio.uio_resid = csio->dxfer_len;
1910 sguio.uio_segflg = UIO_SYSSPACE;
1911
1912 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0);
1913
1914 if (error != 0 && mp->error == 0) {
1915 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
1916 mp->error = error;
1917 }
1918 } else {
1919 /* Just use the segments provided */
1920 segs = (struct bus_dma_segment *) csio->data_ptr;
1921 (*eptr)(mp, segs, csio->sglist_cnt, 0);
1922 }
1923 }
1924 if (mp->error) {
1925 int retval = CMD_COMPLETE;
1926 if (mp->error == MUSHERR_NOQENTRIES) {
1927 retval = CMD_EAGAIN;
1928 } else if (mp->error == EFBIG) {
1929 XS_SETERR(csio, CAM_REQ_TOO_BIG);
1930 } else if (mp->error == EINVAL) {
1931 XS_SETERR(csio, CAM_REQ_INVALID);
1932 } else {
1933 XS_SETERR(csio, CAM_UNREC_HBA_ERROR);
1934 }
1935 return (retval);
1936 }
1937 return (CMD_QUEUED);
1938 }
1939
1940 static void
1941 isp_pci_reset0(ispsoftc_t *isp)
1942 {
1943 ISP_DISABLE_INTS(isp);
1944 }
1945
1946 static void
1947 isp_pci_reset1(ispsoftc_t *isp)
1948 {
1949 if (!IS_24XX(isp)) {
1950 /* Make sure the BIOS is disabled */
1951 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1952 }
1953 /* and enable interrupts */
1954 ISP_ENABLE_INTS(isp);
1955 }
1956
1957 static void
1958 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
1959 {
1960 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1961 if (msg)
1962 kprintf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);
1963 else
1964 kprintf("%s:\n", device_get_nameunit(isp->isp_dev));
1965 if (IS_SCSI(isp))
1966 kprintf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1967 else
1968 kprintf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
1969 kprintf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
1970 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
1971 kprintf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
1972
1973
1974 if (IS_SCSI(isp)) {
1975 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1976 kprintf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
1977 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
1978 ISP_READ(isp, CDMA_FIFO_STS));
1979 kprintf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
1980 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
1981 ISP_READ(isp, DDMA_FIFO_STS));
1982 kprintf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1983 ISP_READ(isp, SXP_INTERRUPT),
1984 ISP_READ(isp, SXP_GROSS_ERR),
1985 ISP_READ(isp, SXP_PINS_CTRL));
1986 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1987 }
1988 kprintf(" mbox regs: %x %x %x %x %x\n",
1989 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1990 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1991 ISP_READ(isp, OUTMAILBOX4));
1992 kprintf(" PCI Status Command/Status=%x\n",
1993 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));
1994 }
DragonFly BSD