bridge(4): document net.link.bridge.pfil_onlyip
[dragonfly.git] / sys / bus / gpio / gpio_intel / gpio_intel_var.h
blobbb2d56ac87e2abbc09a52867b2b30e1b44edeae4
1 #ifndef _GPIO_INTEL_VAR_H
2 #define _GPIO_INTEL_VAR_H
4 struct pinrange {
5 int start;
6 int end;
7 };
9 struct pin_intr_map {
10 int pin;
11 int intidx;
12 void *arg;
13 driver_intr_t *handler;
14 int is_level;
15 uint32_t orig_intcfg;
16 uint32_t orig_gpiocfg;
19 struct pin_io_map {
20 int pin;
21 int flags;
24 struct gpio_intel_softc {
25 device_t dev;
26 struct resource *mem_res;
27 struct resource *irq_res;
28 void *intrhand;
29 struct lock lk;
30 struct pinrange *ranges;
31 struct pin_intr_map intrmaps[16];
32 struct pin_io_map iomaps[128];
33 struct gpio_intel_fns *fns;
36 typedef void(*gpio_intel_init_fn)(struct gpio_intel_softc *sc);
37 typedef int(*gpio_intel_map_intr_fn)(struct gpio_intel_softc *sc,
38 uint16_t pin, int trigger, int polarity, int termination);
39 typedef void(*gpio_intel_unmap_intr_fn)(struct gpio_intel_softc *sc,
40 struct pin_intr_map *map);
41 typedef void(*gpio_intel_enable_intr_fn)(struct gpio_intel_softc *sc,
42 struct pin_intr_map *map);
43 typedef void(*gpio_intel_disable_intr_fn)(struct gpio_intel_softc *sc,
44 struct pin_intr_map *map);
45 typedef int(*gpio_intel_check_io_pin_fn)(struct gpio_intel_softc *sc,
46 uint16_t pin, int flags);
47 typedef void(*gpio_intel_write_pin_fn)(struct gpio_intel_softc *sc,
48 uint16_t pin, int value);
49 typedef int(*gpio_intel_read_pin_fn)(struct gpio_intel_softc *sc,
50 uint16_t pin);
52 struct gpio_intel_fns {
53 gpio_intel_init_fn init;
54 driver_intr_t *intr;
55 gpio_intel_map_intr_fn map_intr;
56 gpio_intel_unmap_intr_fn unmap_intr;
57 gpio_intel_enable_intr_fn enable_intr;
58 gpio_intel_disable_intr_fn disable_intr;
59 gpio_intel_check_io_pin_fn check_io_pin;
60 gpio_intel_write_pin_fn write_pin;
61 gpio_intel_read_pin_fn read_pin;
64 int gpio_cherryview_matchuid(struct gpio_intel_softc *sc);
66 #endif