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Eliminate some dead initialization.
[dragonfly.git] / sys / dev / drm / r128_state.c
bloba8bbf8845af0b5ee3da047ac1ceb25694a6c1e10
1 /* r128_state.c -- State support for r128 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
3 */
4 /*
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $DragonFly: src/sys/dev/drm/r128_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "r128_drm.h"
36 #include "r128_drv.h"
37
38 /* ================================================================
39 * CCE hardware state programming functions
40 */
41
42 static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
43 struct drm_clip_rect * boxes, int count)
44 {
45 u32 aux_sc_cntl = 0x00000000;
46 RING_LOCALS;
47 DRM_DEBUG("\n");
48
49 BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
50
51 if (count >= 1) {
52 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
53 OUT_RING(boxes[0].x1);
54 OUT_RING(boxes[0].x2 - 1);
55 OUT_RING(boxes[0].y1);
56 OUT_RING(boxes[0].y2 - 1);
57
58 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
59 }
60 if (count >= 2) {
61 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
62 OUT_RING(boxes[1].x1);
63 OUT_RING(boxes[1].x2 - 1);
64 OUT_RING(boxes[1].y1);
65 OUT_RING(boxes[1].y2 - 1);
66
67 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
68 }
69 if (count >= 3) {
70 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
71 OUT_RING(boxes[2].x1);
72 OUT_RING(boxes[2].x2 - 1);
73 OUT_RING(boxes[2].y1);
74 OUT_RING(boxes[2].y2 - 1);
75
76 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
77 }
78
79 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
80 OUT_RING(aux_sc_cntl);
81
82 ADVANCE_RING();
83 }
84
85 static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
86 {
87 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
88 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
89 RING_LOCALS;
90 DRM_DEBUG("\n");
91
92 BEGIN_RING(2);
93
94 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
95 OUT_RING(ctx->scale_3d_cntl);
96
97 ADVANCE_RING();
98 }
99
100 static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
101 {
102 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
103 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
104 RING_LOCALS;
105 DRM_DEBUG("\n");
106
107 BEGIN_RING(13);
108
109 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
110 OUT_RING(ctx->dst_pitch_offset_c);
111 OUT_RING(ctx->dp_gui_master_cntl_c);
112 OUT_RING(ctx->sc_top_left_c);
113 OUT_RING(ctx->sc_bottom_right_c);
114 OUT_RING(ctx->z_offset_c);
115 OUT_RING(ctx->z_pitch_c);
116 OUT_RING(ctx->z_sten_cntl_c);
117 OUT_RING(ctx->tex_cntl_c);
118 OUT_RING(ctx->misc_3d_state_cntl_reg);
119 OUT_RING(ctx->texture_clr_cmp_clr_c);
120 OUT_RING(ctx->texture_clr_cmp_msk_c);
121 OUT_RING(ctx->fog_color_c);
122
123 ADVANCE_RING();
124 }
125
126 static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
127 {
128 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
129 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
130 RING_LOCALS;
131 DRM_DEBUG("\n");
132
133 BEGIN_RING(3);
134
135 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
136 OUT_RING(ctx->setup_cntl);
137 OUT_RING(ctx->pm4_vc_fpu_setup);
138
139 ADVANCE_RING();
140 }
141
142 static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
143 {
144 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
145 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
146 RING_LOCALS;
147 DRM_DEBUG("\n");
148
149 BEGIN_RING(5);
150
151 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
152 OUT_RING(ctx->dp_write_mask);
153
154 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
155 OUT_RING(ctx->sten_ref_mask_c);
156 OUT_RING(ctx->plane_3d_mask_c);
157
158 ADVANCE_RING();
159 }
160
161 static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
162 {
163 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
164 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
165 RING_LOCALS;
166 DRM_DEBUG("\n");
167
168 BEGIN_RING(2);
169
170 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
171 OUT_RING(ctx->window_xy_offset);
172
173 ADVANCE_RING();
174 }
175
176 static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
177 {
178 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
179 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
180 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
181 int i;
182 RING_LOCALS;
183 DRM_DEBUG("\n");
184
185 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
186
187 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
188 2 + R128_MAX_TEXTURE_LEVELS));
189 OUT_RING(tex->tex_cntl);
190 OUT_RING(tex->tex_combine_cntl);
191 OUT_RING(ctx->tex_size_pitch_c);
192 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
193 OUT_RING(tex->tex_offset[i]);
194 }
195
196 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
197 OUT_RING(ctx->constant_color_c);
198 OUT_RING(tex->tex_border_color);
199
200 ADVANCE_RING();
201 }
202
203 static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
204 {
205 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
207 int i;
208 RING_LOCALS;
209 DRM_DEBUG("\n");
210
211 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
212
213 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
214 OUT_RING(tex->tex_cntl);
215 OUT_RING(tex->tex_combine_cntl);
216 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
217 OUT_RING(tex->tex_offset[i]);
218 }
219
220 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
221 OUT_RING(tex->tex_border_color);
222
223 ADVANCE_RING();
224 }
225
226 static void r128_emit_state(drm_r128_private_t * dev_priv)
227 {
228 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
229 unsigned int dirty = sarea_priv->dirty;
230
231 DRM_DEBUG("dirty=0x%08x\n", dirty);
232
233 if (dirty & R128_UPLOAD_CORE) {
234 r128_emit_core(dev_priv);
235 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
236 }
237
238 if (dirty & R128_UPLOAD_CONTEXT) {
239 r128_emit_context(dev_priv);
240 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
241 }
242
243 if (dirty & R128_UPLOAD_SETUP) {
244 r128_emit_setup(dev_priv);
245 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
246 }
247
248 if (dirty & R128_UPLOAD_MASKS) {
249 r128_emit_masks(dev_priv);
250 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
251 }
252
253 if (dirty & R128_UPLOAD_WINDOW) {
254 r128_emit_window(dev_priv);
255 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
256 }
257
258 if (dirty & R128_UPLOAD_TEX0) {
259 r128_emit_tex0(dev_priv);
260 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
261 }
262
263 if (dirty & R128_UPLOAD_TEX1) {
264 r128_emit_tex1(dev_priv);
265 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
266 }
267
268 /* Turn off the texture cache flushing */
269 sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
270
271 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
272 }
273
274 #if R128_PERFORMANCE_BOXES
275 /* ================================================================
276 * Performance monitoring functions
277 */
278
279 static void r128_clear_box(drm_r128_private_t * dev_priv,
280 int x, int y, int w, int h, int r, int g, int b)
281 {
282 u32 pitch, offset;
283 u32 fb_bpp, color;
284 RING_LOCALS;
285
286 switch (dev_priv->fb_bpp) {
287 case 16:
288 fb_bpp = R128_GMC_DST_16BPP;
289 color = (((r & 0xf8) << 8) |
290 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
291 break;
292 case 24:
293 fb_bpp = R128_GMC_DST_24BPP;
294 color = ((r << 16) | (g << 8) | b);
295 break;
296 case 32:
297 fb_bpp = R128_GMC_DST_32BPP;
298 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
299 break;
300 default:
301 return;
302 }
303
304 offset = dev_priv->back_offset;
305 pitch = dev_priv->back_pitch >> 3;
306
307 BEGIN_RING(6);
308
309 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
310 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
311 R128_GMC_BRUSH_SOLID_COLOR |
312 fb_bpp |
313 R128_GMC_SRC_DATATYPE_COLOR |
314 R128_ROP3_P |
315 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
316
317 OUT_RING((pitch << 21) | (offset >> 5));
318 OUT_RING(color);
319
320 OUT_RING((x << 16) | y);
321 OUT_RING((w << 16) | h);
322
323 ADVANCE_RING();
324 }
325
326 static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
327 {
328 if (atomic_read(&dev_priv->idle_count) == 0) {
329 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
330 } else {
331 atomic_set(&dev_priv->idle_count, 0);
332 }
333 }
334
335 #endif
336
337 /* ================================================================
338 * CCE command dispatch functions
339 */
340
341 static void r128_print_dirty(const char *msg, unsigned int flags)
342 {
343 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
344 msg,
345 flags,
346 (flags & R128_UPLOAD_CORE) ? "core, " : "",
347 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
348 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
349 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
350 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
351 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
352 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
353 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
354 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
355 }
356
357 static void r128_cce_dispatch_clear(struct drm_device * dev,
358 drm_r128_clear_t * clear)
359 {
360 drm_r128_private_t *dev_priv = dev->dev_private;
361 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
362 int nbox = sarea_priv->nbox;
363 struct drm_clip_rect *pbox = sarea_priv->boxes;
364 unsigned int flags = clear->flags;
365 int i;
366 RING_LOCALS;
367 DRM_DEBUG("\n");
368
369 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
370 unsigned int tmp = flags;
371
372 flags &= ~(R128_FRONT | R128_BACK);
373 if (tmp & R128_FRONT)
374 flags |= R128_BACK;
375 if (tmp & R128_BACK)
376 flags |= R128_FRONT;
377 }
378
379 for (i = 0; i < nbox; i++) {
380 int x = pbox[i].x1;
381 int y = pbox[i].y1;
382 int w = pbox[i].x2 - x;
383 int h = pbox[i].y2 - y;
384
385 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
386 pbox[i].x1, pbox[i].y1, pbox[i].x2,
387 pbox[i].y2, flags);
388
389 if (flags & (R128_FRONT | R128_BACK)) {
390 BEGIN_RING(2);
391
392 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
393 OUT_RING(clear->color_mask);
394
395 ADVANCE_RING();
396 }
397
398 if (flags & R128_FRONT) {
399 BEGIN_RING(6);
400
401 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
402 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
403 R128_GMC_BRUSH_SOLID_COLOR |
404 (dev_priv->color_fmt << 8) |
405 R128_GMC_SRC_DATATYPE_COLOR |
406 R128_ROP3_P |
407 R128_GMC_CLR_CMP_CNTL_DIS |
408 R128_GMC_AUX_CLIP_DIS);
409
410 OUT_RING(dev_priv->front_pitch_offset_c);
411 OUT_RING(clear->clear_color);
412
413 OUT_RING((x << 16) | y);
414 OUT_RING((w << 16) | h);
415
416 ADVANCE_RING();
417 }
418
419 if (flags & R128_BACK) {
420 BEGIN_RING(6);
421
422 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
423 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
424 R128_GMC_BRUSH_SOLID_COLOR |
425 (dev_priv->color_fmt << 8) |
426 R128_GMC_SRC_DATATYPE_COLOR |
427 R128_ROP3_P |
428 R128_GMC_CLR_CMP_CNTL_DIS |
429 R128_GMC_AUX_CLIP_DIS);
430
431 OUT_RING(dev_priv->back_pitch_offset_c);
432 OUT_RING(clear->clear_color);
433
434 OUT_RING((x << 16) | y);
435 OUT_RING((w << 16) | h);
436
437 ADVANCE_RING();
438 }
439
440 if (flags & R128_DEPTH) {
441 BEGIN_RING(6);
442
443 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
444 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
445 R128_GMC_BRUSH_SOLID_COLOR |
446 (dev_priv->depth_fmt << 8) |
447 R128_GMC_SRC_DATATYPE_COLOR |
448 R128_ROP3_P |
449 R128_GMC_CLR_CMP_CNTL_DIS |
450 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
451
452 OUT_RING(dev_priv->depth_pitch_offset_c);
453 OUT_RING(clear->clear_depth);
454
455 OUT_RING((x << 16) | y);
456 OUT_RING((w << 16) | h);
457
458 ADVANCE_RING();
459 }
460 }
461 }
462
463 static void r128_cce_dispatch_swap(struct drm_device * dev)
464 {
465 drm_r128_private_t *dev_priv = dev->dev_private;
466 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
467 int nbox = sarea_priv->nbox;
468 struct drm_clip_rect *pbox = sarea_priv->boxes;
469 int i;
470 RING_LOCALS;
471 DRM_DEBUG("\n");
472
473 #if R128_PERFORMANCE_BOXES
474 /* Do some trivial performance monitoring...
475 */
476 r128_cce_performance_boxes(dev_priv);
477 #endif
478
479 for (i = 0; i < nbox; i++) {
480 int x = pbox[i].x1;
481 int y = pbox[i].y1;
482 int w = pbox[i].x2 - x;
483 int h = pbox[i].y2 - y;
484
485 BEGIN_RING(7);
486
487 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
488 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
489 R128_GMC_DST_PITCH_OFFSET_CNTL |
490 R128_GMC_BRUSH_NONE |
491 (dev_priv->color_fmt << 8) |
492 R128_GMC_SRC_DATATYPE_COLOR |
493 R128_ROP3_S |
494 R128_DP_SRC_SOURCE_MEMORY |
495 R128_GMC_CLR_CMP_CNTL_DIS |
496 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
497
498 /* Make this work even if front & back are flipped:
499 */
500 if (dev_priv->current_page == 0) {
501 OUT_RING(dev_priv->back_pitch_offset_c);
502 OUT_RING(dev_priv->front_pitch_offset_c);
503 } else {
504 OUT_RING(dev_priv->front_pitch_offset_c);
505 OUT_RING(dev_priv->back_pitch_offset_c);
506 }
507
508 OUT_RING((x << 16) | y);
509 OUT_RING((x << 16) | y);
510 OUT_RING((w << 16) | h);
511
512 ADVANCE_RING();
513 }
514
515 /* Increment the frame counter. The client-side 3D driver must
516 * throttle the framerate by waiting for this value before
517 * performing the swapbuffer ioctl.
518 */
519 dev_priv->sarea_priv->last_frame++;
520
521 BEGIN_RING(2);
522
523 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
524 OUT_RING(dev_priv->sarea_priv->last_frame);
525
526 ADVANCE_RING();
527 }
528
529 static void r128_cce_dispatch_flip(struct drm_device * dev)
530 {
531 drm_r128_private_t *dev_priv = dev->dev_private;
532 RING_LOCALS;
533 DRM_DEBUG("page=%d pfCurrentPage=%d\n",
534 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
535
536 #if R128_PERFORMANCE_BOXES
537 /* Do some trivial performance monitoring...
538 */
539 r128_cce_performance_boxes(dev_priv);
540 #endif
541
542 BEGIN_RING(4);
543
544 R128_WAIT_UNTIL_PAGE_FLIPPED();
545 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
546
547 if (dev_priv->current_page == 0) {
548 OUT_RING(dev_priv->back_offset);
549 } else {
550 OUT_RING(dev_priv->front_offset);
551 }
552
553 ADVANCE_RING();
554
555 /* Increment the frame counter. The client-side 3D driver must
556 * throttle the framerate by waiting for this value before
557 * performing the swapbuffer ioctl.
558 */
559 dev_priv->sarea_priv->last_frame++;
560 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
561 1 - dev_priv->current_page;
562
563 BEGIN_RING(2);
564
565 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
566 OUT_RING(dev_priv->sarea_priv->last_frame);
567
568 ADVANCE_RING();
569 }
570
571 static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
572 {
573 drm_r128_private_t *dev_priv = dev->dev_private;
574 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
575 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
576 int format = sarea_priv->vc_format;
577 int offset = buf->bus_address;
578 int size = buf->used;
579 int prim = buf_priv->prim;
580 int i = 0;
581 RING_LOCALS;
582 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
583
584 if (0)
585 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
586
587 if (buf->used) {
588 buf_priv->dispatched = 1;
589
590 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
591 r128_emit_state(dev_priv);
592 }
593
594 do {
595 /* Emit the next set of up to three cliprects */
596 if (i < sarea_priv->nbox) {
597 r128_emit_clip_rects(dev_priv,
598 &sarea_priv->boxes[i],
599 sarea_priv->nbox - i);
600 }
601
602 /* Emit the vertex buffer rendering commands */
603 BEGIN_RING(5);
604
605 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
606 OUT_RING(offset);
607 OUT_RING(size);
608 OUT_RING(format);
609 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
610 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
611
612 ADVANCE_RING();
613
614 i += 3;
615 } while (i < sarea_priv->nbox);
616 }
617
618 if (buf_priv->discard) {
619 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
620
621 /* Emit the vertex buffer age */
622 BEGIN_RING(2);
623
624 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
625 OUT_RING(buf_priv->age);
626
627 ADVANCE_RING();
628
629 buf->pending = 1;
630 buf->used = 0;
631 /* FIXME: Check dispatched field */
632 buf_priv->dispatched = 0;
633 }
634
635 dev_priv->sarea_priv->last_dispatch++;
636
637 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
638 sarea_priv->nbox = 0;
639 }
640
641 static void r128_cce_dispatch_indirect(struct drm_device * dev,
642 struct drm_buf * buf, int start, int end)
643 {
644 drm_r128_private_t *dev_priv = dev->dev_private;
645 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
646 RING_LOCALS;
647 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
648
649 if (start != end) {
650 int offset = buf->bus_address + start;
651 int dwords = (end - start + 3) / sizeof(u32);
652
653 /* Indirect buffer data must be an even number of
654 * dwords, so if we've been given an odd number we must
655 * pad the data with a Type-2 CCE packet.
656 */
657 if (dwords & 1) {
658 u32 *data = (u32 *)
659 ((char *)dev->agp_buffer_map->handle
660 + buf->offset + start);
661 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
662 }
663
664 buf_priv->dispatched = 1;
665
666 /* Fire off the indirect buffer */
667 BEGIN_RING(3);
668
669 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
670 OUT_RING(offset);
671 OUT_RING(dwords);
672
673 ADVANCE_RING();
674 }
675
676 if (buf_priv->discard) {
677 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
678
679 /* Emit the indirect buffer age */
680 BEGIN_RING(2);
681
682 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
683 OUT_RING(buf_priv->age);
684
685 ADVANCE_RING();
686
687 buf->pending = 1;
688 buf->used = 0;
689 /* FIXME: Check dispatched field */
690 buf_priv->dispatched = 0;
691 }
692
693 dev_priv->sarea_priv->last_dispatch++;
694 }
695
696 static void r128_cce_dispatch_indices(struct drm_device * dev,
697 struct drm_buf * buf,
698 int start, int end, int count)
699 {
700 drm_r128_private_t *dev_priv = dev->dev_private;
701 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
702 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
703 int format = sarea_priv->vc_format;
704 int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
705 int prim = buf_priv->prim;
706 u32 *data;
707 int dwords;
708 int i = 0;
709 RING_LOCALS;
710 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
711
712 if (0)
713 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
714
715 if (start != end) {
716 buf_priv->dispatched = 1;
717
718 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
719 r128_emit_state(dev_priv);
720 }
721
722 dwords = (end - start + 3) / sizeof(u32);
723
724 data = (u32 *) ((char *)dev->agp_buffer_map->handle
725 + buf->offset + start);
726
727 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
728 dwords - 2));
729
730 data[1] = cpu_to_le32(offset);
731 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
732 data[3] = cpu_to_le32(format);
733 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
734 (count << 16)));
735
736 if (count & 0x1) {
737 #ifdef __LITTLE_ENDIAN
738 data[dwords - 1] &= 0x0000ffff;
739 #else
740 data[dwords - 1] &= 0xffff0000;
741 #endif
742 }
743
744 do {
745 /* Emit the next set of up to three cliprects */
746 if (i < sarea_priv->nbox) {
747 r128_emit_clip_rects(dev_priv,
748 &sarea_priv->boxes[i],
749 sarea_priv->nbox - i);
750 }
751
752 r128_cce_dispatch_indirect(dev, buf, start, end);
753
754 i += 3;
755 } while (i < sarea_priv->nbox);
756 }
757
758 if (buf_priv->discard) {
759 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
760
761 /* Emit the vertex buffer age */
762 BEGIN_RING(2);
763
764 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
765 OUT_RING(buf_priv->age);
766
767 ADVANCE_RING();
768
769 buf->pending = 1;
770 /* FIXME: Check dispatched field */
771 buf_priv->dispatched = 0;
772 }
773
774 dev_priv->sarea_priv->last_dispatch++;
775
776 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
777 sarea_priv->nbox = 0;
778 }
779
780 static int r128_cce_dispatch_blit(struct drm_device * dev,
781 struct drm_file *file_priv,
782 drm_r128_blit_t * blit)
783 {
784 drm_r128_private_t *dev_priv = dev->dev_private;
785 struct drm_device_dma *dma = dev->dma;
786 struct drm_buf *buf;
787 drm_r128_buf_priv_t *buf_priv;
788 u32 *data;
789 int dword_shift, dwords;
790 RING_LOCALS;
791 DRM_DEBUG("\n");
792
793 /* The compiler won't optimize away a division by a variable,
794 * even if the only legal values are powers of two. Thus, we'll
795 * use a shift instead.
796 */
797 switch (blit->format) {
798 case R128_DATATYPE_ARGB8888:
799 dword_shift = 0;
800 break;
801 case R128_DATATYPE_ARGB1555:
802 case R128_DATATYPE_RGB565:
803 case R128_DATATYPE_ARGB4444:
804 case R128_DATATYPE_YVYU422:
805 case R128_DATATYPE_VYUY422:
806 dword_shift = 1;
807 break;
808 case R128_DATATYPE_CI8:
809 case R128_DATATYPE_RGB8:
810 dword_shift = 2;
811 break;
812 default:
813 DRM_ERROR("invalid blit format %d\n", blit->format);
814 return -EINVAL;
815 }
816
817 /* Flush the pixel cache, and mark the contents as Read Invalid.
818 * This ensures no pixel data gets mixed up with the texture
819 * data from the host data blit, otherwise part of the texture
820 * image may be corrupted.
821 */
822 BEGIN_RING(2);
823
824 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
825 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
826
827 ADVANCE_RING();
828
829 /* Dispatch the indirect buffer.
830 */
831 buf = dma->buflist[blit->idx];
832 buf_priv = buf->dev_private;
833
834 if (buf->file_priv != file_priv) {
835 DRM_ERROR("process %d using buffer owned by %p\n",
836 DRM_CURRENTPID, buf->file_priv);
837 return -EINVAL;
838 }
839 if (buf->pending) {
840 DRM_ERROR("sending pending buffer %d\n", blit->idx);
841 return -EINVAL;
842 }
843
844 buf_priv->discard = 1;
845
846 dwords = (blit->width * blit->height) >> dword_shift;
847
848 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
849
850 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
851 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
852 R128_GMC_BRUSH_NONE |
853 (blit->format << 8) |
854 R128_GMC_SRC_DATATYPE_COLOR |
855 R128_ROP3_S |
856 R128_DP_SRC_SOURCE_HOST_DATA |
857 R128_GMC_CLR_CMP_CNTL_DIS |
858 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
859
860 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
861 data[3] = cpu_to_le32(0xffffffff);
862 data[4] = cpu_to_le32(0xffffffff);
863 data[5] = cpu_to_le32((blit->y << 16) | blit->x);
864 data[6] = cpu_to_le32((blit->height << 16) | blit->width);
865 data[7] = cpu_to_le32(dwords);
866
867 buf->used = (dwords + 8) * sizeof(u32);
868
869 r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
870
871 /* Flush the pixel cache after the blit completes. This ensures
872 * the texture data is written out to memory before rendering
873 * continues.
874 */
875 BEGIN_RING(2);
876
877 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
878 OUT_RING(R128_PC_FLUSH_GUI);
879
880 ADVANCE_RING();
881
882 return 0;
883 }
884
885 /* ================================================================
886 * Tiled depth buffer management
887 *
888 * FIXME: These should all set the destination write mask for when we
889 * have hardware stencil support.
890 */
891
892 static int r128_cce_dispatch_write_span(struct drm_device * dev,
893 drm_r128_depth_t * depth)
894 {
895 drm_r128_private_t *dev_priv = dev->dev_private;
896 int count, x, y;
897 u32 *buffer;
898 u8 *mask;
899 int i, buffer_size, mask_size;
900 RING_LOCALS;
901 DRM_DEBUG("\n");
902
903 count = depth->n;
904 if (count > 4096 || count <= 0)
905 return -EMSGSIZE;
906
907 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
908 return -EFAULT;
909 }
910 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
911 return -EFAULT;
912 }
913
914 buffer_size = depth->n * sizeof(u32);
915 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
916 if (buffer == NULL)
917 return -ENOMEM;
918 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
919 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
920 return -EFAULT;
921 }
922
923 mask_size = depth->n * sizeof(u8);
924 if (depth->mask) {
925 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
926 if (mask == NULL) {
927 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
928 return -ENOMEM;
929 }
930 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
931 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
932 drm_free(mask, mask_size, DRM_MEM_BUFS);
933 return -EFAULT;
934 }
935
936 for (i = 0; i < count; i++, x++) {
937 if (mask[i]) {
938 BEGIN_RING(6);
939
940 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
941 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
942 R128_GMC_BRUSH_SOLID_COLOR |
943 (dev_priv->depth_fmt << 8) |
944 R128_GMC_SRC_DATATYPE_COLOR |
945 R128_ROP3_P |
946 R128_GMC_CLR_CMP_CNTL_DIS |
947 R128_GMC_WR_MSK_DIS);
948
949 OUT_RING(dev_priv->depth_pitch_offset_c);
950 OUT_RING(buffer[i]);
951
952 OUT_RING((x << 16) | y);
953 OUT_RING((1 << 16) | 1);
954
955 ADVANCE_RING();
956 }
957 }
958
959 drm_free(mask, mask_size, DRM_MEM_BUFS);
960 } else {
961 for (i = 0; i < count; i++, x++) {
962 BEGIN_RING(6);
963
964 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
965 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
966 R128_GMC_BRUSH_SOLID_COLOR |
967 (dev_priv->depth_fmt << 8) |
968 R128_GMC_SRC_DATATYPE_COLOR |
969 R128_ROP3_P |
970 R128_GMC_CLR_CMP_CNTL_DIS |
971 R128_GMC_WR_MSK_DIS);
972
973 OUT_RING(dev_priv->depth_pitch_offset_c);
974 OUT_RING(buffer[i]);
975
976 OUT_RING((x << 16) | y);
977 OUT_RING((1 << 16) | 1);
978
979 ADVANCE_RING();
980 }
981 }
982
983 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
984
985 return 0;
986 }
987
988 static int r128_cce_dispatch_write_pixels(struct drm_device * dev,
989 drm_r128_depth_t * depth)
990 {
991 drm_r128_private_t *dev_priv = dev->dev_private;
992 int count, *x, *y;
993 u32 *buffer;
994 u8 *mask;
995 int i, xbuf_size, ybuf_size, buffer_size, mask_size;
996 RING_LOCALS;
997 DRM_DEBUG("\n");
998
999 count = depth->n;
1000 if (count > 4096 || count <= 0)
1001 return -EMSGSIZE;
1002
1003 xbuf_size = count * sizeof(*x);
1004 ybuf_size = count * sizeof(*y);
1005 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1006 if (x == NULL) {
1007 return -ENOMEM;
1008 }
1009 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1010 if (y == NULL) {
1011 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1012 return -ENOMEM;
1013 }
1014 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1015 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1016 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1017 return -EFAULT;
1018 }
1019 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1020 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1021 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1022 return -EFAULT;
1023 }
1024
1025 buffer_size = depth->n * sizeof(u32);
1026 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1027 if (buffer == NULL) {
1028 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1029 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1030 return -ENOMEM;
1031 }
1032 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1033 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1034 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1035 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1036 return -EFAULT;
1037 }
1038
1039 if (depth->mask) {
1040 mask_size = depth->n * sizeof(u8);
1041 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1042 if (mask == NULL) {
1043 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1044 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1045 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1046 return -ENOMEM;
1047 }
1048 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1049 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1050 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1051 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1052 drm_free(mask, mask_size, DRM_MEM_BUFS);
1053 return -EFAULT;
1054 }
1055
1056 for (i = 0; i < count; i++) {
1057 if (mask[i]) {
1058 BEGIN_RING(6);
1059
1060 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1061 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1062 R128_GMC_BRUSH_SOLID_COLOR |
1063 (dev_priv->depth_fmt << 8) |
1064 R128_GMC_SRC_DATATYPE_COLOR |
1065 R128_ROP3_P |
1066 R128_GMC_CLR_CMP_CNTL_DIS |
1067 R128_GMC_WR_MSK_DIS);
1068
1069 OUT_RING(dev_priv->depth_pitch_offset_c);
1070 OUT_RING(buffer[i]);
1071
1072 OUT_RING((x[i] << 16) | y[i]);
1073 OUT_RING((1 << 16) | 1);
1074
1075 ADVANCE_RING();
1076 }
1077 }
1078
1079 drm_free(mask, mask_size, DRM_MEM_BUFS);
1080 } else {
1081 for (i = 0; i < count; i++) {
1082 BEGIN_RING(6);
1083
1084 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1085 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1086 R128_GMC_BRUSH_SOLID_COLOR |
1087 (dev_priv->depth_fmt << 8) |
1088 R128_GMC_SRC_DATATYPE_COLOR |
1089 R128_ROP3_P |
1090 R128_GMC_CLR_CMP_CNTL_DIS |
1091 R128_GMC_WR_MSK_DIS);
1092
1093 OUT_RING(dev_priv->depth_pitch_offset_c);
1094 OUT_RING(buffer[i]);
1095
1096 OUT_RING((x[i] << 16) | y[i]);
1097 OUT_RING((1 << 16) | 1);
1098
1099 ADVANCE_RING();
1100 }
1101 }
1102
1103 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1104 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1105 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1106
1107 return 0;
1108 }
1109
1110 static int r128_cce_dispatch_read_span(struct drm_device * dev,
1111 drm_r128_depth_t * depth)
1112 {
1113 drm_r128_private_t *dev_priv = dev->dev_private;
1114 int count, x, y;
1115 RING_LOCALS;
1116 DRM_DEBUG("\n");
1117
1118 count = depth->n;
1119 if (count > 4096 || count <= 0)
1120 return -EMSGSIZE;
1121
1122 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1123 return -EFAULT;
1124 }
1125 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1126 return -EFAULT;
1127 }
1128
1129 BEGIN_RING(7);
1130
1131 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1132 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1133 R128_GMC_DST_PITCH_OFFSET_CNTL |
1134 R128_GMC_BRUSH_NONE |
1135 (dev_priv->depth_fmt << 8) |
1136 R128_GMC_SRC_DATATYPE_COLOR |
1137 R128_ROP3_S |
1138 R128_DP_SRC_SOURCE_MEMORY |
1139 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1140
1141 OUT_RING(dev_priv->depth_pitch_offset_c);
1142 OUT_RING(dev_priv->span_pitch_offset_c);
1143
1144 OUT_RING((x << 16) | y);
1145 OUT_RING((0 << 16) | 0);
1146 OUT_RING((count << 16) | 1);
1147
1148 ADVANCE_RING();
1149
1150 return 0;
1151 }
1152
1153 static int r128_cce_dispatch_read_pixels(struct drm_device * dev,
1154 drm_r128_depth_t * depth)
1155 {
1156 drm_r128_private_t *dev_priv = dev->dev_private;
1157 int count, *x, *y;
1158 int i, xbuf_size, ybuf_size;
1159 RING_LOCALS;
1160 DRM_DEBUG("\n");
1161
1162 count = depth->n;
1163 if (count > 4096 || count <= 0)
1164 return -EMSGSIZE;
1165
1166 if (count > dev_priv->depth_pitch) {
1167 count = dev_priv->depth_pitch;
1168 }
1169
1170 xbuf_size = count * sizeof(*x);
1171 ybuf_size = count * sizeof(*y);
1172 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1173 if (x == NULL) {
1174 return -ENOMEM;
1175 }
1176 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1177 if (y == NULL) {
1178 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1179 return -ENOMEM;
1180 }
1181 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1182 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1183 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1184 return -EFAULT;
1185 }
1186 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1187 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1188 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1189 return -EFAULT;
1190 }
1191
1192 for (i = 0; i < count; i++) {
1193 BEGIN_RING(7);
1194
1195 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1196 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1197 R128_GMC_DST_PITCH_OFFSET_CNTL |
1198 R128_GMC_BRUSH_NONE |
1199 (dev_priv->depth_fmt << 8) |
1200 R128_GMC_SRC_DATATYPE_COLOR |
1201 R128_ROP3_S |
1202 R128_DP_SRC_SOURCE_MEMORY |
1203 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1204
1205 OUT_RING(dev_priv->depth_pitch_offset_c);
1206 OUT_RING(dev_priv->span_pitch_offset_c);
1207
1208 OUT_RING((x[i] << 16) | y[i]);
1209 OUT_RING((i << 16) | 0);
1210 OUT_RING((1 << 16) | 1);
1211
1212 ADVANCE_RING();
1213 }
1214
1215 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1216 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1217
1218 return 0;
1219 }
1220
1221 /* ================================================================
1222 * Polygon stipple
1223 */
1224
1225 static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1226 {
1227 drm_r128_private_t *dev_priv = dev->dev_private;
1228 int i;
1229 RING_LOCALS;
1230 DRM_DEBUG("\n");
1231
1232 BEGIN_RING(33);
1233
1234 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1235 for (i = 0; i < 32; i++) {
1236 OUT_RING(stipple[i]);
1237 }
1238
1239 ADVANCE_RING();
1240 }
1241
1242 /* ================================================================
1243 * IOCTL functions
1244 */
1245
1246 static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
1247 {
1248 drm_r128_private_t *dev_priv = dev->dev_private;
1249 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1250 drm_r128_clear_t *clear = data;
1251 DRM_DEBUG("\n");
1252
1253 LOCK_TEST_WITH_RETURN(dev, file_priv);
1254
1255 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1256
1257 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1258 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1259
1260 r128_cce_dispatch_clear(dev, clear);
1261 COMMIT_RING();
1262
1263 /* Make sure we restore the 3D state next time.
1264 */
1265 dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
1266
1267 return 0;
1268 }
1269
1270 static int r128_do_init_pageflip(struct drm_device * dev)
1271 {
1272 drm_r128_private_t *dev_priv = dev->dev_private;
1273 DRM_DEBUG("\n");
1274
1275 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1276 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1277
1278 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1279 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1280 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1281
1282 dev_priv->page_flipping = 1;
1283 dev_priv->current_page = 0;
1284 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1285
1286 return 0;
1287 }
1288
1289 static int r128_do_cleanup_pageflip(struct drm_device * dev)
1290 {
1291 drm_r128_private_t *dev_priv = dev->dev_private;
1292 DRM_DEBUG("\n");
1293
1294 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1295 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1296
1297 if (dev_priv->current_page != 0) {
1298 r128_cce_dispatch_flip(dev);
1299 COMMIT_RING();
1300 }
1301
1302 dev_priv->page_flipping = 0;
1303 return 0;
1304 }
1305
1306 /* Swapping and flipping are different operations, need different ioctls.
1307 * They can & should be intermixed to support multiple 3d windows.
1308 */
1309
1310 static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
1311 {
1312 drm_r128_private_t *dev_priv = dev->dev_private;
1313 DRM_DEBUG("\n");
1314
1315 LOCK_TEST_WITH_RETURN(dev, file_priv);
1316
1317 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1318
1319 if (!dev_priv->page_flipping)
1320 r128_do_init_pageflip(dev);
1321
1322 r128_cce_dispatch_flip(dev);
1323
1324 COMMIT_RING();
1325 return 0;
1326 }
1327
1328 static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
1329 {
1330 drm_r128_private_t *dev_priv = dev->dev_private;
1331 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1332 DRM_DEBUG("\n");
1333
1334 LOCK_TEST_WITH_RETURN(dev, file_priv);
1335
1336 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1337
1338 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1339 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1340
1341 r128_cce_dispatch_swap(dev);
1342 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1343 R128_UPLOAD_MASKS);
1344
1345 COMMIT_RING();
1346 return 0;
1347 }
1348
1349 static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
1350 {
1351 drm_r128_private_t *dev_priv = dev->dev_private;
1352 struct drm_device_dma *dma = dev->dma;
1353 struct drm_buf *buf;
1354 drm_r128_buf_priv_t *buf_priv;
1355 drm_r128_vertex_t *vertex = data;
1356
1357 LOCK_TEST_WITH_RETURN(dev, file_priv);
1358
1359 if (!dev_priv) {
1360 DRM_ERROR("called with no initialization\n");
1361 return -EINVAL;
1362 }
1363
1364 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1365 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
1366
1367 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
1368 DRM_ERROR("buffer index %d (of %d max)\n",
1369 vertex->idx, dma->buf_count - 1);
1370 return -EINVAL;
1371 }
1372 if (vertex->prim < 0 ||
1373 vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1374 DRM_ERROR("buffer prim %d\n", vertex->prim);
1375 return -EINVAL;
1376 }
1377
1378 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1379 VB_AGE_TEST_WITH_RETURN(dev_priv);
1380
1381 buf = dma->buflist[vertex->idx];
1382 buf_priv = buf->dev_private;
1383
1384 if (buf->file_priv != file_priv) {
1385 DRM_ERROR("process %d using buffer owned by %p\n",
1386 DRM_CURRENTPID, buf->file_priv);
1387 return -EINVAL;
1388 }
1389 if (buf->pending) {
1390 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
1391 return -EINVAL;
1392 }
1393
1394 buf->used = vertex->count;
1395 buf_priv->prim = vertex->prim;
1396 buf_priv->discard = vertex->discard;
1397
1398 r128_cce_dispatch_vertex(dev, buf);
1399
1400 COMMIT_RING();
1401 return 0;
1402 }
1403
1404 static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
1405 {
1406 drm_r128_private_t *dev_priv = dev->dev_private;
1407 struct drm_device_dma *dma = dev->dma;
1408 struct drm_buf *buf;
1409 drm_r128_buf_priv_t *buf_priv;
1410 drm_r128_indices_t *elts = data;
1411 int count;
1412
1413 LOCK_TEST_WITH_RETURN(dev, file_priv);
1414
1415 if (!dev_priv) {
1416 DRM_ERROR("called with no initialization\n");
1417 return -EINVAL;
1418 }
1419
1420 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1421 elts->idx, elts->start, elts->end, elts->discard);
1422
1423 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
1424 DRM_ERROR("buffer index %d (of %d max)\n",
1425 elts->idx, dma->buf_count - 1);
1426 return -EINVAL;
1427 }
1428 if (elts->prim < 0 ||
1429 elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1430 DRM_ERROR("buffer prim %d\n", elts->prim);
1431 return -EINVAL;
1432 }
1433
1434 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1435 VB_AGE_TEST_WITH_RETURN(dev_priv);
1436
1437 buf = dma->buflist[elts->idx];
1438 buf_priv = buf->dev_private;
1439
1440 if (buf->file_priv != file_priv) {
1441 DRM_ERROR("process %d using buffer owned by %p\n",
1442 DRM_CURRENTPID, buf->file_priv);
1443 return -EINVAL;
1444 }
1445 if (buf->pending) {
1446 DRM_ERROR("sending pending buffer %d\n", elts->idx);
1447 return -EINVAL;
1448 }
1449
1450 count = (elts->end - elts->start) / sizeof(u16);
1451 elts->start -= R128_INDEX_PRIM_OFFSET;
1452
1453 if (elts->start & 0x7) {
1454 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
1455 return -EINVAL;
1456 }
1457 if (elts->start < buf->used) {
1458 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
1459 return -EINVAL;
1460 }
1461
1462 buf->used = elts->end;
1463 buf_priv->prim = elts->prim;
1464 buf_priv->discard = elts->discard;
1465
1466 r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count);
1467
1468 COMMIT_RING();
1469 return 0;
1470 }
1471
1472 static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1473 {
1474 struct drm_device_dma *dma = dev->dma;
1475 drm_r128_private_t *dev_priv = dev->dev_private;
1476 drm_r128_blit_t *blit = data;
1477 int ret;
1478
1479 LOCK_TEST_WITH_RETURN(dev, file_priv);
1480
1481 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
1482
1483 if (blit->idx < 0 || blit->idx >= dma->buf_count) {
1484 DRM_ERROR("buffer index %d (of %d max)\n",
1485 blit->idx, dma->buf_count - 1);
1486 return -EINVAL;
1487 }
1488
1489 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1490 VB_AGE_TEST_WITH_RETURN(dev_priv);
1491
1492 ret = r128_cce_dispatch_blit(dev, file_priv, blit);
1493
1494 COMMIT_RING();
1495 return ret;
1496 }
1497
1498 static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv)
1499 {
1500 drm_r128_private_t *dev_priv = dev->dev_private;
1501 drm_r128_depth_t *depth = data;
1502 int ret;
1503
1504 LOCK_TEST_WITH_RETURN(dev, file_priv);
1505
1506 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1507
1508 ret = -EINVAL;
1509 switch (depth->func) {
1510 case R128_WRITE_SPAN:
1511 ret = r128_cce_dispatch_write_span(dev, depth);
1512 break;
1513 case R128_WRITE_PIXELS:
1514 ret = r128_cce_dispatch_write_pixels(dev, depth);
1515 break;
1516 case R128_READ_SPAN:
1517 ret = r128_cce_dispatch_read_span(dev, depth);
1518 break;
1519 case R128_READ_PIXELS:
1520 ret = r128_cce_dispatch_read_pixels(dev, depth);
1521 break;
1522 }
1523
1524 COMMIT_RING();
1525 return ret;
1526 }
1527
1528 static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
1529 {
1530 drm_r128_private_t *dev_priv = dev->dev_private;
1531 drm_r128_stipple_t *stipple = data;
1532 u32 mask[32];
1533
1534 LOCK_TEST_WITH_RETURN(dev, file_priv);
1535
1536 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
1537 return -EFAULT;
1538
1539 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1540
1541 r128_cce_dispatch_stipple(dev, mask);
1542
1543 COMMIT_RING();
1544 return 0;
1545 }
1546
1547 static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
1548 {
1549 drm_r128_private_t *dev_priv = dev->dev_private;
1550 struct drm_device_dma *dma = dev->dma;
1551 struct drm_buf *buf;
1552 drm_r128_buf_priv_t *buf_priv;
1553 drm_r128_indirect_t *indirect = data;
1554 #if 0
1555 RING_LOCALS;
1556 #endif
1557
1558 LOCK_TEST_WITH_RETURN(dev, file_priv);
1559
1560 if (!dev_priv) {
1561 DRM_ERROR("called with no initialization\n");
1562 return -EINVAL;
1563 }
1564
1565 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
1566 indirect->idx, indirect->start, indirect->end,
1567 indirect->discard);
1568
1569 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
1570 DRM_ERROR("buffer index %d (of %d max)\n",
1571 indirect->idx, dma->buf_count - 1);
1572 return -EINVAL;
1573 }
1574
1575 buf = dma->buflist[indirect->idx];
1576 buf_priv = buf->dev_private;
1577
1578 if (buf->file_priv != file_priv) {
1579 DRM_ERROR("process %d using buffer owned by %p\n",
1580 DRM_CURRENTPID, buf->file_priv);
1581 return -EINVAL;
1582 }
1583 if (buf->pending) {
1584 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
1585 return -EINVAL;
1586 }
1587
1588 if (indirect->start < buf->used) {
1589 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1590 indirect->start, buf->used);
1591 return -EINVAL;
1592 }
1593
1594 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1595 VB_AGE_TEST_WITH_RETURN(dev_priv);
1596
1597 buf->used = indirect->end;
1598 buf_priv->discard = indirect->discard;
1599
1600 #if 0
1601 /* Wait for the 3D stream to idle before the indirect buffer
1602 * containing 2D acceleration commands is processed.
1603 */
1604 BEGIN_RING(2);
1605 RADEON_WAIT_UNTIL_3D_IDLE();
1606 ADVANCE_RING();
1607 #endif
1608
1609 /* Dispatch the indirect buffer full of commands from the
1610 * X server. This is insecure and is thus only available to
1611 * privileged clients.
1612 */
1613 r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end);
1614
1615 COMMIT_RING();
1616 return 0;
1617 }
1618
1619 static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1620 {
1621 drm_r128_private_t *dev_priv = dev->dev_private;
1622 drm_r128_getparam_t *param = data;
1623 int value;
1624
1625 if (!dev_priv) {
1626 DRM_ERROR("called with no initialization\n");
1627 return -EINVAL;
1628 }
1629
1630 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1631
1632 switch (param->param) {
1633 case R128_PARAM_IRQ_NR:
1634 value = dev->irq;
1635 break;
1636 default:
1637 return -EINVAL;
1638 }
1639
1640 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1641 DRM_ERROR("copy_to_user\n");
1642 return -EFAULT;
1643 }
1644
1645 return 0;
1646 }
1647
1648 void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1649 {
1650 if (dev->dev_private) {
1651 drm_r128_private_t *dev_priv = dev->dev_private;
1652 if (dev_priv->page_flipping) {
1653 r128_do_cleanup_pageflip(dev);
1654 }
1655 }
1656 }
1657
1658 void r128_driver_lastclose(struct drm_device * dev)
1659 {
1660 r128_do_cleanup_cce(dev);
1661 }
1662
1663 struct drm_ioctl_desc r128_ioctls[] = {
1664 DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1665 DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1666 DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1667 DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1668 DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH),
1669 DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH),
1670 DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH),
1671 DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH),
1672 DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH),
1673 DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH),
1674 DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH),
1675 DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH),
1676 DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH),
1677 DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH),
1678 DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH),
1679 DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1680 DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH),
1681 };
1682
1683 int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
DragonFly BSD