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Reduce ifnet.if_serializer contention on output path:
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
bloba577138ebe8b48818476c1ba52e227ebee52f5cc
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.91 2008/05/14 11:59:18 sephe Exp $
35 *
36 */
37
38 /*
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 *
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
43 */
44
45 /*
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
56 * into the driver.
57 *
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
60 *
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
64 *
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
67 *
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
72 * ring.
73 */
74
75 #include "opt_polling.h"
76 #include <sys/param.h>
77 #include <sys/bus.h>
78 #include <sys/endian.h>
79 #include <sys/kernel.h>
80 #include <sys/ktr.h>
81 #include <sys/interrupt.h>
82 #include <sys/mbuf.h>
83 #include <sys/malloc.h>
84 #include <sys/queue.h>
85 #include <sys/rman.h>
86 #include <sys/serialize.h>
87 #include <sys/socket.h>
88 #include <sys/sockio.h>
89 #include <sys/sysctl.h>
90
91 #include <net/bpf.h>
92 #include <net/ethernet.h>
93 #include <net/if.h>
94 #include <net/if_arp.h>
95 #include <net/if_dl.h>
96 #include <net/if_media.h>
97 #include <net/if_types.h>
98 #include <net/ifq_var.h>
99 #include <net/vlan/if_vlan_var.h>
100 #include <net/vlan/if_vlan_ether.h>
101
102 #include <dev/netif/mii_layer/mii.h>
103 #include <dev/netif/mii_layer/miivar.h>
104 #include <dev/netif/mii_layer/brgphyreg.h>
105
106 #include <bus/pci/pcidevs.h>
107 #include <bus/pci/pcireg.h>
108 #include <bus/pci/pcivar.h>
109
110 #include <dev/netif/bge/if_bgereg.h>
111
112 /* "device miibus" required. See GENERIC if you get errors here. */
113 #include "miibus_if.h"
114
115 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
116 #define BGE_MIN_FRAME 60
117
118 /*
119 * Various supported device vendors/types and their names. Note: the
120 * spec seems to indicate that the hardware still has Alteon's vendor
121 * ID burned into it, though it will always be overriden by the vendor
122 * ID in the EEPROM. Just to be safe, we cover all possibilities.
123 */
124 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
125
126 static struct bge_type bge_devs[] = {
127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
128 "3COM 3C996 Gigabit Ethernet" },
129
130 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
131 "Alteon BCM5700 Gigabit Ethernet" },
132 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
133 "Alteon BCM5701 Gigabit Ethernet" },
134
135 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
136 "Altima AC1000 Gigabit Ethernet" },
137 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
138 "Altima AC1002 Gigabit Ethernet" },
139 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
140 "Altima AC9100 Gigabit Ethernet" },
141
142 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
143 "Apple BCM5701 Gigabit Ethernet" },
144
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
146 "Broadcom BCM5700 Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
148 "Broadcom BCM5701 Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
150 "Broadcom BCM5702 Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
152 "Broadcom BCM5702X Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
154 "Broadcom BCM5702 Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
156 "Broadcom BCM5703 Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
158 "Broadcom BCM5703X Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
160 "Broadcom BCM5703 Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
162 "Broadcom BCM5704C Dual Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
164 "Broadcom BCM5704S Dual Gigabit Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
166 "Broadcom BCM5704S Dual Gigabit Ethernet" },
167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
168 "Broadcom BCM5705 Gigabit Ethernet" },
169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
170 "Broadcom BCM5705F Gigabit Ethernet" },
171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
172 "Broadcom BCM5705K Gigabit Ethernet" },
173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
174 "Broadcom BCM5705M Gigabit Ethernet" },
175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
176 "Broadcom BCM5705M Gigabit Ethernet" },
177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
178 "Broadcom BCM5714C Gigabit Ethernet" },
179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
180 "Broadcom BCM5714S Gigabit Ethernet" },
181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
182 "Broadcom BCM5715 Gigabit Ethernet" },
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
184 "Broadcom BCM5715S Gigabit Ethernet" },
185 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
186 "Broadcom BCM5720 Gigabit Ethernet" },
187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
188 "Broadcom BCM5721 Gigabit Ethernet" },
189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
190 "Broadcom BCM5722 Gigabit Ethernet" },
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
192 "Broadcom BCM5750 Gigabit Ethernet" },
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
194 "Broadcom BCM5750M Gigabit Ethernet" },
195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
196 "Broadcom BCM5751 Gigabit Ethernet" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
198 "Broadcom BCM5751F Gigabit Ethernet" },
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
200 "Broadcom BCM5751M Gigabit Ethernet" },
201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
202 "Broadcom BCM5752 Gigabit Ethernet" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
204 "Broadcom BCM5752M Gigabit Ethernet" },
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
206 "Broadcom BCM5753 Gigabit Ethernet" },
207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
208 "Broadcom BCM5753F Gigabit Ethernet" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
210 "Broadcom BCM5753M Gigabit Ethernet" },
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
212 "Broadcom BCM5754 Gigabit Ethernet" },
213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
214 "Broadcom BCM5754M Gigabit Ethernet" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
216 "Broadcom BCM5755 Gigabit Ethernet" },
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
218 "Broadcom BCM5755M Gigabit Ethernet" },
219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
220 "Broadcom BCM5756 Gigabit Ethernet" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
222 "Broadcom BCM5780 Gigabit Ethernet" },
223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
224 "Broadcom BCM5780S Gigabit Ethernet" },
225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
226 "Broadcom BCM5781 Gigabit Ethernet" },
227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
228 "Broadcom BCM5782 Gigabit Ethernet" },
229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
230 "Broadcom BCM5786 Gigabit Ethernet" },
231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
232 "Broadcom BCM5787 Gigabit Ethernet" },
233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
234 "Broadcom BCM5787F Gigabit Ethernet" },
235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
236 "Broadcom BCM5787M Gigabit Ethernet" },
237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
238 "Broadcom BCM5788 Gigabit Ethernet" },
239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
240 "Broadcom BCM5789 Gigabit Ethernet" },
241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
242 "Broadcom BCM5901 Fast Ethernet" },
243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
244 "Broadcom BCM5901A2 Fast Ethernet" },
245 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
246 "Broadcom BCM5903M Fast Ethernet" },
247
248 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
249 "SysKonnect Gigabit Ethernet" },
250
251 { 0, 0, NULL }
252 };
253
254 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
255 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
256 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
257 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
258 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
259
260 static int bge_probe(device_t);
261 static int bge_attach(device_t);
262 static int bge_detach(device_t);
263 static void bge_txeof(struct bge_softc *);
264 static void bge_rxeof(struct bge_softc *);
265
266 static void bge_tick(void *);
267 static void bge_stats_update(struct bge_softc *);
268 static void bge_stats_update_regs(struct bge_softc *);
269 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
270
271 #ifdef DEVICE_POLLING
272 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
273 #endif
274 static void bge_intr(void *);
275 static void bge_enable_intr(struct bge_softc *);
276 static void bge_disable_intr(struct bge_softc *);
277 static void bge_start(struct ifnet *);
278 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
279 static void bge_init(void *);
280 static void bge_stop(struct bge_softc *);
281 static void bge_watchdog(struct ifnet *);
282 static void bge_shutdown(device_t);
283 static int bge_suspend(device_t);
284 static int bge_resume(device_t);
285 static int bge_ifmedia_upd(struct ifnet *);
286 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
287
288 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
289 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
290
291 static void bge_setmulti(struct bge_softc *);
292 static void bge_setpromisc(struct bge_softc *);
293
294 static int bge_alloc_jumbo_mem(struct bge_softc *);
295 static void bge_free_jumbo_mem(struct bge_softc *);
296 static struct bge_jslot
297 *bge_jalloc(struct bge_softc *);
298 static void bge_jfree(void *);
299 static void bge_jref(void *);
300 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
301 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
302 static int bge_init_rx_ring_std(struct bge_softc *);
303 static void bge_free_rx_ring_std(struct bge_softc *);
304 static int bge_init_rx_ring_jumbo(struct bge_softc *);
305 static void bge_free_rx_ring_jumbo(struct bge_softc *);
306 static void bge_free_tx_ring(struct bge_softc *);
307 static int bge_init_tx_ring(struct bge_softc *);
308
309 static int bge_chipinit(struct bge_softc *);
310 static int bge_blockinit(struct bge_softc *);
311
312 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
313 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
314 #ifdef notdef
315 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
316 #endif
317 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
318 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
319
320 static int bge_miibus_readreg(device_t, int, int);
321 static int bge_miibus_writereg(device_t, int, int, int);
322 static void bge_miibus_statchg(device_t);
323 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
324 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
325 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
326
327 static void bge_reset(struct bge_softc *);
328
329 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
330 static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
331 bus_size_t, int);
332 static int bge_dma_alloc(struct bge_softc *);
333 static void bge_dma_free(struct bge_softc *);
334 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
335 bus_dma_tag_t *, bus_dmamap_t *,
336 void **, bus_addr_t *);
337 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
338
339 static void bge_coal_change(struct bge_softc *);
340 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
341 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
342 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
343 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
344 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
345
346 /*
347 * Set following tunable to 1 for some IBM blade servers with the DNLK
348 * switch module. Auto negotiation is broken for those configurations.
349 */
350 static int bge_fake_autoneg = 0;
351 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
352
353 /* Interrupt moderation control variables. */
354 static int bge_rx_coal_ticks = 150; /* usec */
355 static int bge_tx_coal_ticks = 1000000; /* usec */
356 static int bge_rx_max_coal_bds = 16;
357 static int bge_tx_max_coal_bds = 32;
358
359 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
360 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
361 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
362 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
363
364 #if !defined(KTR_IF_BGE)
365 #define KTR_IF_BGE KTR_ALL
366 #endif
367 KTR_INFO_MASTER(if_bge);
368 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
369 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
370 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
371 #define logif(name) KTR_LOG(if_bge_ ## name)
372
373 static device_method_t bge_methods[] = {
374 /* Device interface */
375 DEVMETHOD(device_probe, bge_probe),
376 DEVMETHOD(device_attach, bge_attach),
377 DEVMETHOD(device_detach, bge_detach),
378 DEVMETHOD(device_shutdown, bge_shutdown),
379 DEVMETHOD(device_suspend, bge_suspend),
380 DEVMETHOD(device_resume, bge_resume),
381
382 /* bus interface */
383 DEVMETHOD(bus_print_child, bus_generic_print_child),
384 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
385
386 /* MII interface */
387 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
388 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
389 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
390
391 { 0, 0 }
392 };
393
394 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
395 static devclass_t bge_devclass;
396
397 DECLARE_DUMMY_MODULE(if_bge);
398 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
399 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
400
401 static uint32_t
402 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
403 {
404 device_t dev = sc->bge_dev;
405 uint32_t val;
406
407 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
408 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
409 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
410 return (val);
411 }
412
413 static void
414 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
415 {
416 device_t dev = sc->bge_dev;
417
418 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
419 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
420 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
421 }
422
423 #ifdef notdef
424 static uint32_t
425 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
426 {
427 device_t dev = sc->bge_dev;
428
429 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
430 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
431 }
432 #endif
433
434 static void
435 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
436 {
437 device_t dev = sc->bge_dev;
438
439 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
440 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
441 }
442
443 static void
444 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
445 {
446 CSR_WRITE_4(sc, off, val);
447 }
448
449 /*
450 * Read a byte of data stored in the EEPROM at address 'addr.' The
451 * BCM570x supports both the traditional bitbang interface and an
452 * auto access interface for reading the EEPROM. We use the auto
453 * access method.
454 */
455 static uint8_t
456 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
457 {
458 int i;
459 uint32_t byte = 0;
460
461 /*
462 * Enable use of auto EEPROM access so we can avoid
463 * having to use the bitbang method.
464 */
465 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
466
467 /* Reset the EEPROM, load the clock period. */
468 CSR_WRITE_4(sc, BGE_EE_ADDR,
469 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
470 DELAY(20);
471
472 /* Issue the read EEPROM command. */
473 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
474
475 /* Wait for completion */
476 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
477 DELAY(10);
478 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
479 break;
480 }
481
482 if (i == BGE_TIMEOUT) {
483 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
484 return(1);
485 }
486
487 /* Get result. */
488 byte = CSR_READ_4(sc, BGE_EE_DATA);
489
490 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
491
492 return(0);
493 }
494
495 /*
496 * Read a sequence of bytes from the EEPROM.
497 */
498 static int
499 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
500 {
501 size_t i;
502 int err;
503 uint8_t byte;
504
505 for (byte = 0, err = 0, i = 0; i < len; i++) {
506 err = bge_eeprom_getbyte(sc, off + i, &byte);
507 if (err)
508 break;
509 *(dest + i) = byte;
510 }
511
512 return(err ? 1 : 0);
513 }
514
515 static int
516 bge_miibus_readreg(device_t dev, int phy, int reg)
517 {
518 struct bge_softc *sc;
519 struct ifnet *ifp;
520 uint32_t val, autopoll;
521 int i;
522
523 sc = device_get_softc(dev);
524 ifp = &sc->arpcom.ac_if;
525
526 /*
527 * Broadcom's own driver always assumes the internal
528 * PHY is at GMII address 1. On some chips, the PHY responds
529 * to accesses at all addresses, which could cause us to
530 * bogusly attach the PHY 32 times at probe type. Always
531 * restricting the lookup to address 1 is simpler than
532 * trying to figure out which chips revisions should be
533 * special-cased.
534 */
535 if (phy != 1)
536 return(0);
537
538 /* Reading with autopolling on may trigger PCI errors */
539 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
540 if (autopoll & BGE_MIMODE_AUTOPOLL) {
541 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
542 DELAY(40);
543 }
544
545 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
546 BGE_MIPHY(phy)|BGE_MIREG(reg));
547
548 for (i = 0; i < BGE_TIMEOUT; i++) {
549 val = CSR_READ_4(sc, BGE_MI_COMM);
550 if (!(val & BGE_MICOMM_BUSY))
551 break;
552 }
553
554 if (i == BGE_TIMEOUT) {
555 if_printf(ifp, "PHY read timed out\n");
556 val = 0;
557 goto done;
558 }
559
560 val = CSR_READ_4(sc, BGE_MI_COMM);
561
562 done:
563 if (autopoll & BGE_MIMODE_AUTOPOLL) {
564 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
565 DELAY(40);
566 }
567
568 if (val & BGE_MICOMM_READFAIL)
569 return(0);
570
571 return(val & 0xFFFF);
572 }
573
574 static int
575 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
576 {
577 struct bge_softc *sc;
578 uint32_t autopoll;
579 int i;
580
581 sc = device_get_softc(dev);
582
583 /* Reading with autopolling on may trigger PCI errors */
584 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
585 if (autopoll & BGE_MIMODE_AUTOPOLL) {
586 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
587 DELAY(40);
588 }
589
590 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
591 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
592
593 for (i = 0; i < BGE_TIMEOUT; i++) {
594 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
595 break;
596 }
597
598 if (autopoll & BGE_MIMODE_AUTOPOLL) {
599 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
600 DELAY(40);
601 }
602
603 if (i == BGE_TIMEOUT) {
604 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
605 return(0);
606 }
607
608 return(0);
609 }
610
611 static void
612 bge_miibus_statchg(device_t dev)
613 {
614 struct bge_softc *sc;
615 struct mii_data *mii;
616
617 sc = device_get_softc(dev);
618 mii = device_get_softc(sc->bge_miibus);
619
620 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
621 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
622 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
623 } else {
624 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
625 }
626
627 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
628 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
629 } else {
630 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
631 }
632 }
633
634 /*
635 * Memory management for jumbo frames.
636 */
637 static int
638 bge_alloc_jumbo_mem(struct bge_softc *sc)
639 {
640 struct ifnet *ifp = &sc->arpcom.ac_if;
641 struct bge_jslot *entry;
642 uint8_t *ptr;
643 bus_addr_t paddr;
644 int i, error;
645
646 /*
647 * Create tag for jumbo mbufs.
648 * This is really a bit of a kludge. We allocate a special
649 * jumbo buffer pool which (thanks to the way our DMA
650 * memory allocation works) will consist of contiguous
651 * pages. This means that even though a jumbo buffer might
652 * be larger than a page size, we don't really need to
653 * map it into more than one DMA segment. However, the
654 * default mbuf tag will result in multi-segment mappings,
655 * so we have to create a special jumbo mbuf tag that
656 * lets us get away with mapping the jumbo buffers as
657 * a single segment. I think eventually the driver should
658 * be changed so that it uses ordinary mbufs and cluster
659 * buffers, i.e. jumbo frames can span multiple DMA
660 * descriptors. But that's a project for another day.
661 */
662
663 /*
664 * Create DMA stuffs for jumbo RX ring.
665 */
666 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
667 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
668 &sc->bge_cdata.bge_rx_jumbo_ring_map,
669 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
670 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
671 if (error) {
672 if_printf(ifp, "could not create jumbo RX ring\n");
673 return error;
674 }
675
676 /*
677 * Create DMA stuffs for jumbo buffer block.
678 */
679 error = bge_dma_block_alloc(sc, BGE_JMEM,
680 &sc->bge_cdata.bge_jumbo_tag,
681 &sc->bge_cdata.bge_jumbo_map,
682 (void **)&sc->bge_ldata.bge_jumbo_buf,
683 &paddr);
684 if (error) {
685 if_printf(ifp, "could not create jumbo buffer\n");
686 return error;
687 }
688
689 SLIST_INIT(&sc->bge_jfree_listhead);
690
691 /*
692 * Now divide it up into 9K pieces and save the addresses
693 * in an array. Note that we play an evil trick here by using
694 * the first few bytes in the buffer to hold the the address
695 * of the softc structure for this interface. This is because
696 * bge_jfree() needs it, but it is called by the mbuf management
697 * code which will not pass it to us explicitly.
698 */
699 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
700 entry = &sc->bge_cdata.bge_jslots[i];
701 entry->bge_sc = sc;
702 entry->bge_buf = ptr;
703 entry->bge_paddr = paddr;
704 entry->bge_inuse = 0;
705 entry->bge_slot = i;
706 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
707
708 ptr += BGE_JLEN;
709 paddr += BGE_JLEN;
710 }
711 return 0;
712 }
713
714 static void
715 bge_free_jumbo_mem(struct bge_softc *sc)
716 {
717 /* Destroy jumbo RX ring. */
718 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
719 sc->bge_cdata.bge_rx_jumbo_ring_map,
720 sc->bge_ldata.bge_rx_jumbo_ring);
721
722 /* Destroy jumbo buffer block. */
723 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
724 sc->bge_cdata.bge_jumbo_map,
725 sc->bge_ldata.bge_jumbo_buf);
726 }
727
728 /*
729 * Allocate a jumbo buffer.
730 */
731 static struct bge_jslot *
732 bge_jalloc(struct bge_softc *sc)
733 {
734 struct bge_jslot *entry;
735
736 lwkt_serialize_enter(&sc->bge_jslot_serializer);
737 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
738 if (entry) {
739 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
740 entry->bge_inuse = 1;
741 } else {
742 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
743 }
744 lwkt_serialize_exit(&sc->bge_jslot_serializer);
745 return(entry);
746 }
747
748 /*
749 * Adjust usage count on a jumbo buffer.
750 */
751 static void
752 bge_jref(void *arg)
753 {
754 struct bge_jslot *entry = (struct bge_jslot *)arg;
755 struct bge_softc *sc = entry->bge_sc;
756
757 if (sc == NULL)
758 panic("bge_jref: can't find softc pointer!");
759
760 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
761 panic("bge_jref: asked to reference buffer "
762 "that we don't manage!");
763 } else if (entry->bge_inuse == 0) {
764 panic("bge_jref: buffer already free!");
765 } else {
766 atomic_add_int(&entry->bge_inuse, 1);
767 }
768 }
769
770 /*
771 * Release a jumbo buffer.
772 */
773 static void
774 bge_jfree(void *arg)
775 {
776 struct bge_jslot *entry = (struct bge_jslot *)arg;
777 struct bge_softc *sc = entry->bge_sc;
778
779 if (sc == NULL)
780 panic("bge_jfree: can't find softc pointer!");
781
782 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
783 panic("bge_jfree: asked to free buffer that we don't manage!");
784 } else if (entry->bge_inuse == 0) {
785 panic("bge_jfree: buffer already free!");
786 } else {
787 /*
788 * Possible MP race to 0, use the serializer. The atomic insn
789 * is still needed for races against bge_jref().
790 */
791 lwkt_serialize_enter(&sc->bge_jslot_serializer);
792 atomic_subtract_int(&entry->bge_inuse, 1);
793 if (entry->bge_inuse == 0) {
794 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
795 entry, jslot_link);
796 }
797 lwkt_serialize_exit(&sc->bge_jslot_serializer);
798 }
799 }
800
801
802 /*
803 * Intialize a standard receive ring descriptor.
804 */
805 static int
806 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
807 {
808 struct mbuf *m_new = NULL;
809 struct bge_dmamap_arg ctx;
810 bus_dma_segment_t seg;
811 struct bge_rx_bd *r;
812 int error;
813
814 if (m == NULL) {
815 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
816 if (m_new == NULL)
817 return ENOBUFS;
818 } else {
819 m_new = m;
820 m_new->m_data = m_new->m_ext.ext_buf;
821 }
822 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
823
824 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
825 m_adj(m_new, ETHER_ALIGN);
826
827 ctx.bge_maxsegs = 1;
828 ctx.bge_segs = &seg;
829 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
830 sc->bge_cdata.bge_rx_std_dmamap[i],
831 m_new, bge_dma_map_mbuf, &ctx,
832 BUS_DMA_NOWAIT);
833 if (error || ctx.bge_maxsegs == 0) {
834 if (m == NULL)
835 m_freem(m_new);
836 return ENOMEM;
837 }
838
839 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
840
841 r = &sc->bge_ldata.bge_rx_std_ring[i];
842 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
843 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
844 r->bge_flags = BGE_RXBDFLAG_END;
845 r->bge_len = m_new->m_len;
846 r->bge_idx = i;
847
848 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
849 sc->bge_cdata.bge_rx_std_dmamap[i],
850 BUS_DMASYNC_PREREAD);
851 return 0;
852 }
853
854 /*
855 * Initialize a jumbo receive ring descriptor. This allocates
856 * a jumbo buffer from the pool managed internally by the driver.
857 */
858 static int
859 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
860 {
861 struct mbuf *m_new = NULL;
862 struct bge_jslot *buf;
863 struct bge_rx_bd *r;
864 bus_addr_t paddr;
865
866 if (m == NULL) {
867 /* Allocate the mbuf. */
868 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
869 if (m_new == NULL)
870 return(ENOBUFS);
871
872 /* Allocate the jumbo buffer */
873 buf = bge_jalloc(sc);
874 if (buf == NULL) {
875 m_freem(m_new);
876 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
877 "-- packet dropped!\n");
878 return ENOBUFS;
879 }
880
881 /* Attach the buffer to the mbuf. */
882 m_new->m_ext.ext_arg = buf;
883 m_new->m_ext.ext_buf = buf->bge_buf;
884 m_new->m_ext.ext_free = bge_jfree;
885 m_new->m_ext.ext_ref = bge_jref;
886 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
887
888 m_new->m_flags |= M_EXT;
889 } else {
890 KKASSERT(m->m_flags & M_EXT);
891 m_new = m;
892 buf = m_new->m_ext.ext_arg;
893 }
894 m_new->m_data = m_new->m_ext.ext_buf;
895 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
896
897 paddr = buf->bge_paddr;
898 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
899 m_adj(m_new, ETHER_ALIGN);
900 paddr += ETHER_ALIGN;
901 }
902
903 /* Set up the descriptor. */
904 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
905
906 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
907 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
908 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
909 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
910 r->bge_len = m_new->m_len;
911 r->bge_idx = i;
912
913 return 0;
914 }
915
916 /*
917 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
918 * that's 1MB or memory, which is a lot. For now, we fill only the first
919 * 256 ring entries and hope that our CPU is fast enough to keep up with
920 * the NIC.
921 */
922 static int
923 bge_init_rx_ring_std(struct bge_softc *sc)
924 {
925 int i;
926
927 for (i = 0; i < BGE_SSLOTS; i++) {
928 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
929 return(ENOBUFS);
930 };
931
932 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
933 sc->bge_cdata.bge_rx_std_ring_map,
934 BUS_DMASYNC_PREWRITE);
935
936 sc->bge_std = i - 1;
937 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
938
939 return(0);
940 }
941
942 static void
943 bge_free_rx_ring_std(struct bge_softc *sc)
944 {
945 int i;
946
947 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
948 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
949 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
950 sc->bge_cdata.bge_rx_std_dmamap[i]);
951 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
952 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
953 }
954 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
955 sizeof(struct bge_rx_bd));
956 }
957 }
958
959 static int
960 bge_init_rx_ring_jumbo(struct bge_softc *sc)
961 {
962 int i;
963 struct bge_rcb *rcb;
964
965 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
966 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
967 return(ENOBUFS);
968 };
969
970 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
971 sc->bge_cdata.bge_rx_jumbo_ring_map,
972 BUS_DMASYNC_PREWRITE);
973
974 sc->bge_jumbo = i - 1;
975
976 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
977 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
978 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
979
980 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
981
982 return(0);
983 }
984
985 static void
986 bge_free_rx_ring_jumbo(struct bge_softc *sc)
987 {
988 int i;
989
990 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
991 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
992 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
993 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
994 }
995 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
996 sizeof(struct bge_rx_bd));
997 }
998 }
999
1000 static void
1001 bge_free_tx_ring(struct bge_softc *sc)
1002 {
1003 int i;
1004
1005 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1006 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1007 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1008 sc->bge_cdata.bge_tx_dmamap[i]);
1009 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1010 sc->bge_cdata.bge_tx_chain[i] = NULL;
1011 }
1012 bzero(&sc->bge_ldata.bge_tx_ring[i],
1013 sizeof(struct bge_tx_bd));
1014 }
1015 }
1016
1017 static int
1018 bge_init_tx_ring(struct bge_softc *sc)
1019 {
1020 sc->bge_txcnt = 0;
1021 sc->bge_tx_saved_considx = 0;
1022 sc->bge_tx_prodidx = 0;
1023
1024 /* Initialize transmit producer index for host-memory send ring. */
1025 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1026
1027 /* 5700 b2 errata */
1028 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1029 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1030
1031 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1032 /* 5700 b2 errata */
1033 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1034 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1035
1036 return(0);
1037 }
1038
1039 static void
1040 bge_setmulti(struct bge_softc *sc)
1041 {
1042 struct ifnet *ifp;
1043 struct ifmultiaddr *ifma;
1044 uint32_t hashes[4] = { 0, 0, 0, 0 };
1045 int h, i;
1046
1047 ifp = &sc->arpcom.ac_if;
1048
1049 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1050 for (i = 0; i < 4; i++)
1051 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1052 return;
1053 }
1054
1055 /* First, zot all the existing filters. */
1056 for (i = 0; i < 4; i++)
1057 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1058
1059 /* Now program new ones. */
1060 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1061 if (ifma->ifma_addr->sa_family != AF_LINK)
1062 continue;
1063 h = ether_crc32_le(
1064 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1065 ETHER_ADDR_LEN) & 0x7f;
1066 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1067 }
1068
1069 for (i = 0; i < 4; i++)
1070 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1071 }
1072
1073 /*
1074 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1075 * self-test results.
1076 */
1077 static int
1078 bge_chipinit(struct bge_softc *sc)
1079 {
1080 int i;
1081 uint32_t dma_rw_ctl;
1082
1083 /* Set endian type before we access any non-PCI registers. */
1084 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1085
1086 /*
1087 * Check the 'ROM failed' bit on the RX CPU to see if
1088 * self-tests passed.
1089 */
1090 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1091 if_printf(&sc->arpcom.ac_if,
1092 "RX CPU self-diagnostics failed!\n");
1093 return(ENODEV);
1094 }
1095
1096 /* Clear the MAC control register */
1097 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1098
1099 /*
1100 * Clear the MAC statistics block in the NIC's
1101 * internal memory.
1102 */
1103 for (i = BGE_STATS_BLOCK;
1104 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1105 BGE_MEMWIN_WRITE(sc, i, 0);
1106
1107 for (i = BGE_STATUS_BLOCK;
1108 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1109 BGE_MEMWIN_WRITE(sc, i, 0);
1110
1111 /* Set up the PCI DMA control register. */
1112 if (sc->bge_flags & BGE_FLAG_PCIE) {
1113 /* PCI Express */
1114 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1115 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1116 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1117 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1118 /* PCI-X bus */
1119 if (BGE_IS_5714_FAMILY(sc)) {
1120 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1121 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1122 /* XXX magic values, Broadcom-supplied Linux driver */
1123 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1124 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1125 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1126 } else {
1127 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1128 }
1129 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1130 /*
1131 * The 5704 uses a different encoding of read/write
1132 * watermarks.
1133 */
1134 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1135 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1136 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1137 } else {
1138 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1139 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1140 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1141 (0x0F);
1142 }
1143
1144 /*
1145 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1146 * for hardware bugs.
1147 */
1148 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1149 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1150 uint32_t tmp;
1151
1152 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1153 if (tmp == 0x6 || tmp == 0x7)
1154 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1155 }
1156 } else {
1157 /* Conventional PCI bus */
1158 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1159 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1160 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1161 (0x0F);
1162 }
1163
1164 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1165 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1166 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1167 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1168 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1169
1170 /*
1171 * Set up general mode register.
1172 */
1173 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1174 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1175 BGE_MODECTL_TX_NO_PHDR_CSUM);
1176
1177 /*
1178 * Disable memory write invalidate. Apparently it is not supported
1179 * properly by these devices.
1180 */
1181 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1182
1183 /* Set the timer prescaler (always 66Mhz) */
1184 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1185
1186 return(0);
1187 }
1188
1189 static int
1190 bge_blockinit(struct bge_softc *sc)
1191 {
1192 struct bge_rcb *rcb;
1193 bus_size_t vrcb;
1194 bge_hostaddr taddr;
1195 uint32_t val;
1196 int i;
1197
1198 /*
1199 * Initialize the memory window pointer register so that
1200 * we can access the first 32K of internal NIC RAM. This will
1201 * allow us to set up the TX send ring RCBs and the RX return
1202 * ring RCBs, plus other things which live in NIC memory.
1203 */
1204 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1205
1206 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1207
1208 if (!BGE_IS_5705_PLUS(sc)) {
1209 /* Configure mbuf memory pool */
1210 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1211 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1212 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1213 else
1214 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1215
1216 /* Configure DMA resource pool */
1217 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1218 BGE_DMA_DESCRIPTORS);
1219 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1220 }
1221
1222 /* Configure mbuf pool watermarks */
1223 if (BGE_IS_5705_PLUS(sc)) {
1224 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1225 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1226 } else {
1227 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1228 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1229 }
1230 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1231
1232 /* Configure DMA resource watermarks */
1233 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1234 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1235
1236 /* Enable buffer manager */
1237 if (!BGE_IS_5705_PLUS(sc)) {
1238 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1239 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1240
1241 /* Poll for buffer manager start indication */
1242 for (i = 0; i < BGE_TIMEOUT; i++) {
1243 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1244 break;
1245 DELAY(10);
1246 }
1247
1248 if (i == BGE_TIMEOUT) {
1249 if_printf(&sc->arpcom.ac_if,
1250 "buffer manager failed to start\n");
1251 return(ENXIO);
1252 }
1253 }
1254
1255 /* Enable flow-through queues */
1256 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1257 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1258
1259 /* Wait until queue initialization is complete */
1260 for (i = 0; i < BGE_TIMEOUT; i++) {
1261 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1262 break;
1263 DELAY(10);
1264 }
1265
1266 if (i == BGE_TIMEOUT) {
1267 if_printf(&sc->arpcom.ac_if,
1268 "flow-through queue init failed\n");
1269 return(ENXIO);
1270 }
1271
1272 /* Initialize the standard RX ring control block */
1273 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1274 rcb->bge_hostaddr.bge_addr_lo =
1275 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1276 rcb->bge_hostaddr.bge_addr_hi =
1277 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1278 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1279 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1280 if (BGE_IS_5705_PLUS(sc))
1281 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1282 else
1283 rcb->bge_maxlen_flags =
1284 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1285 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1286 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1287 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1288 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1289 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1290
1291 /*
1292 * Initialize the jumbo RX ring control block
1293 * We set the 'ring disabled' bit in the flags
1294 * field until we're actually ready to start
1295 * using this ring (i.e. once we set the MTU
1296 * high enough to require it).
1297 */
1298 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1299 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1300
1301 rcb->bge_hostaddr.bge_addr_lo =
1302 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1303 rcb->bge_hostaddr.bge_addr_hi =
1304 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1305 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1306 sc->bge_cdata.bge_rx_jumbo_ring_map,
1307 BUS_DMASYNC_PREREAD);
1308 rcb->bge_maxlen_flags =
1309 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1310 BGE_RCB_FLAG_RING_DISABLED);
1311 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1312 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1313 rcb->bge_hostaddr.bge_addr_hi);
1314 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1315 rcb->bge_hostaddr.bge_addr_lo);
1316 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1317 rcb->bge_maxlen_flags);
1318 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1319
1320 /* Set up dummy disabled mini ring RCB */
1321 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1322 rcb->bge_maxlen_flags =
1323 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1324 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1325 rcb->bge_maxlen_flags);
1326 }
1327
1328 /*
1329 * Set the BD ring replentish thresholds. The recommended
1330 * values are 1/8th the number of descriptors allocated to
1331 * each ring.
1332 */
1333 if (BGE_IS_5705_PLUS(sc))
1334 val = 8;
1335 else
1336 val = BGE_STD_RX_RING_CNT / 8;
1337 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1338 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1339
1340 /*
1341 * Disable all unused send rings by setting the 'ring disabled'
1342 * bit in the flags field of all the TX send ring control blocks.
1343 * These are located in NIC memory.
1344 */
1345 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1346 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1347 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1348 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1349 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1350 vrcb += sizeof(struct bge_rcb);
1351 }
1352
1353 /* Configure TX RCB 0 (we use only the first ring) */
1354 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1355 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1356 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1357 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1358 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1359 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1360 if (!BGE_IS_5705_PLUS(sc)) {
1361 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1362 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1363 }
1364
1365 /* Disable all unused RX return rings */
1366 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1367 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1368 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1369 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1370 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1371 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1372 BGE_RCB_FLAG_RING_DISABLED));
1373 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1374 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1375 (i * (sizeof(uint64_t))), 0);
1376 vrcb += sizeof(struct bge_rcb);
1377 }
1378
1379 /* Initialize RX ring indexes */
1380 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1381 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1382 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1383
1384 /*
1385 * Set up RX return ring 0
1386 * Note that the NIC address for RX return rings is 0x00000000.
1387 * The return rings live entirely within the host, so the
1388 * nicaddr field in the RCB isn't used.
1389 */
1390 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1391 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1392 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1393 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1394 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1395 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1396 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1397
1398 /* Set random backoff seed for TX */
1399 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1400 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1401 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1402 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1403 BGE_TX_BACKOFF_SEED_MASK);
1404
1405 /* Set inter-packet gap */
1406 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1407
1408 /*
1409 * Specify which ring to use for packets that don't match
1410 * any RX rules.
1411 */
1412 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1413
1414 /*
1415 * Configure number of RX lists. One interrupt distribution
1416 * list, sixteen active lists, one bad frames class.
1417 */
1418 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1419
1420 /* Inialize RX list placement stats mask. */
1421 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1422 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1423
1424 /* Disable host coalescing until we get it set up */
1425 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1426
1427 /* Poll to make sure it's shut down. */
1428 for (i = 0; i < BGE_TIMEOUT; i++) {
1429 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1430 break;
1431 DELAY(10);
1432 }
1433
1434 if (i == BGE_TIMEOUT) {
1435 if_printf(&sc->arpcom.ac_if,
1436 "host coalescing engine failed to idle\n");
1437 return(ENXIO);
1438 }
1439
1440 /* Set up host coalescing defaults */
1441 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1442 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1443 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1444 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1445 if (!BGE_IS_5705_PLUS(sc)) {
1446 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1447 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1448 }
1449 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1450 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1451
1452 /* Set up address of statistics block */
1453 if (!BGE_IS_5705_PLUS(sc)) {
1454 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1455 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1456 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1457 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1458
1459 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1460 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1461 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1462 }
1463
1464 /* Set up address of status block */
1465 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1466 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1467 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1468 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1469 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1470 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1471
1472 /* Turn on host coalescing state machine */
1473 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1474
1475 /* Turn on RX BD completion state machine and enable attentions */
1476 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1477 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1478
1479 /* Turn on RX list placement state machine */
1480 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1481
1482 /* Turn on RX list selector state machine. */
1483 if (!BGE_IS_5705_PLUS(sc))
1484 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1485
1486 /* Turn on DMA, clear stats */
1487 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1488 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1489 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1490 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1491 ((sc->bge_flags & BGE_FLAG_TBI) ?
1492 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1493
1494 /* Set misc. local control, enable interrupts on attentions */
1495 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1496
1497 #ifdef notdef
1498 /* Assert GPIO pins for PHY reset */
1499 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1500 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1501 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1502 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1503 #endif
1504
1505 /* Turn on DMA completion state machine */
1506 if (!BGE_IS_5705_PLUS(sc))
1507 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1508
1509 /* Turn on write DMA state machine */
1510 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1511 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1512 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1513 val |= (1 << 29); /* Enable host coalescing bug fix. */
1514 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1515
1516 /* Turn on read DMA state machine */
1517 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1518 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1519
1520 /* Turn on RX data completion state machine */
1521 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1522
1523 /* Turn on RX BD initiator state machine */
1524 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1525
1526 /* Turn on RX data and RX BD initiator state machine */
1527 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1528
1529 /* Turn on Mbuf cluster free state machine */
1530 if (!BGE_IS_5705_PLUS(sc))
1531 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1532
1533 /* Turn on send BD completion state machine */
1534 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1535
1536 /* Turn on send data completion state machine */
1537 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1538
1539 /* Turn on send data initiator state machine */
1540 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1541
1542 /* Turn on send BD initiator state machine */
1543 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1544
1545 /* Turn on send BD selector state machine */
1546 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1547
1548 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1549 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1550 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1551
1552 /* ack/clear link change events */
1553 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1554 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1555 BGE_MACSTAT_LINK_CHANGED);
1556 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1557
1558 /* Enable PHY auto polling (for MII/GMII only) */
1559 if (sc->bge_flags & BGE_FLAG_TBI) {
1560 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1561 } else {
1562 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1563 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1564 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1565 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1566 BGE_EVTENB_MI_INTERRUPT);
1567 }
1568 }
1569
1570 /*
1571 * Clear any pending link state attention.
1572 * Otherwise some link state change events may be lost until attention
1573 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1574 * It's not necessary on newer BCM chips - perhaps enabling link
1575 * state change attentions implies clearing pending attention.
1576 */
1577 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1578 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1579 BGE_MACSTAT_LINK_CHANGED);
1580
1581 /* Enable link state change attentions. */
1582 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1583
1584 return(0);
1585 }
1586
1587 /*
1588 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1589 * against our list and return its name if we find a match. Note
1590 * that since the Broadcom controller contains VPD support, we
1591 * can get the device name string from the controller itself instead
1592 * of the compiled-in string. This is a little slow, but it guarantees
1593 * we'll always announce the right product name.
1594 */
1595 static int
1596 bge_probe(device_t dev)
1597 {
1598 struct bge_softc *sc;
1599 struct bge_type *t;
1600 char *descbuf;
1601 uint16_t product, vendor;
1602
1603 product = pci_get_device(dev);
1604 vendor = pci_get_vendor(dev);
1605
1606 for (t = bge_devs; t->bge_name != NULL; t++) {
1607 if (vendor == t->bge_vid && product == t->bge_did)
1608 break;
1609 }
1610
1611 if (t->bge_name == NULL)
1612 return(ENXIO);
1613
1614 sc = device_get_softc(dev);
1615 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1616 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1617 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1618 device_set_desc_copy(dev, descbuf);
1619 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1620 sc->bge_flags |= BGE_FLAG_NO_3LED;
1621 kfree(descbuf, M_TEMP);
1622 return(0);
1623 }
1624
1625 static int
1626 bge_attach(device_t dev)
1627 {
1628 struct ifnet *ifp;
1629 struct bge_softc *sc;
1630 uint32_t hwcfg = 0;
1631 uint32_t mac_addr = 0;
1632 int error = 0, rid;
1633 uint8_t ether_addr[ETHER_ADDR_LEN];
1634
1635 sc = device_get_softc(dev);
1636 sc->bge_dev = dev;
1637 callout_init(&sc->bge_stat_timer);
1638 lwkt_serialize_init(&sc->bge_jslot_serializer);
1639
1640 /*
1641 * Map control/status registers.
1642 */
1643 pci_enable_busmaster(dev);
1644
1645 rid = BGE_PCI_BAR0;
1646 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1647 RF_ACTIVE);
1648
1649 if (sc->bge_res == NULL) {
1650 device_printf(dev, "couldn't map memory\n");
1651 return ENXIO;
1652 }
1653
1654 sc->bge_btag = rman_get_bustag(sc->bge_res);
1655 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1656
1657 /* Save ASIC rev. */
1658 sc->bge_chipid =
1659 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1660 BGE_PCIMISCCTL_ASICREV;
1661 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1662 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1663
1664 /* Save chipset family. */
1665 switch (sc->bge_asicrev) {
1666 case BGE_ASICREV_BCM5700:
1667 case BGE_ASICREV_BCM5701:
1668 case BGE_ASICREV_BCM5703:
1669 case BGE_ASICREV_BCM5704:
1670 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1671 break;
1672
1673 case BGE_ASICREV_BCM5714_A0:
1674 case BGE_ASICREV_BCM5780:
1675 case BGE_ASICREV_BCM5714:
1676 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1677 /* Fall through */
1678
1679 case BGE_ASICREV_BCM5750:
1680 case BGE_ASICREV_BCM5752:
1681 case BGE_ASICREV_BCM5755:
1682 case BGE_ASICREV_BCM5787:
1683 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1684 /* Fall through */
1685
1686 case BGE_ASICREV_BCM5705:
1687 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1688 break;
1689 }
1690
1691 /*
1692 * Set various quirk flags.
1693 */
1694
1695 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1696 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1697 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1698 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1699 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1700 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1701 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1702
1703 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1704 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1705 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1706
1707 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1708 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1709 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1710
1711 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1712 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1713
1714 if (BGE_IS_5705_PLUS(sc)) {
1715 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1716 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1717 uint32_t product = pci_get_device(dev);
1718
1719 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1720 product != PCI_PRODUCT_BROADCOM_BCM5756)
1721 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1722 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1723 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1724 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1725 sc->bge_flags |= BGE_FLAG_BER_BUG;
1726 }
1727 }
1728
1729 /* Allocate interrupt */
1730 rid = 0;
1731
1732 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1733 RF_SHAREABLE | RF_ACTIVE);
1734
1735 if (sc->bge_irq == NULL) {
1736 device_printf(dev, "couldn't map interrupt\n");
1737 error = ENXIO;
1738 goto fail;
1739 }
1740
1741 /*
1742 * Check if this is a PCI-X or PCI Express device.
1743 */
1744 if (BGE_IS_5705_PLUS(sc)) {
1745 uint32_t reg;
1746
1747 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1748 if ((reg & 0xff) == BGE_PCIE_CAPID)
1749 sc->bge_flags |= BGE_FLAG_PCIE;
1750 } else {
1751 /*
1752 * Check if the device is in PCI-X Mode.
1753 * (This bit is not valid on PCI Express controllers.)
1754 */
1755 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1756 BGE_PCISTATE_PCI_BUSMODE) == 0)
1757 sc->bge_flags |= BGE_FLAG_PCIX;
1758 }
1759
1760 ifp = &sc->arpcom.ac_if;
1761 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1762
1763 /* Try to reset the chip. */
1764 bge_reset(sc);
1765
1766 if (bge_chipinit(sc)) {
1767 device_printf(dev, "chip initialization failed\n");
1768 error = ENXIO;
1769 goto fail;
1770 }
1771
1772 /*
1773 * Get station address from the EEPROM.
1774 */
1775 mac_addr = bge_readmem_ind(sc, 0x0c14);
1776 if ((mac_addr >> 16) == 0x484b) {
1777 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1778 ether_addr[1] = (uint8_t)mac_addr;
1779 mac_addr = bge_readmem_ind(sc, 0x0c18);
1780 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1781 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1782 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1783 ether_addr[5] = (uint8_t)mac_addr;
1784 } else if (bge_read_eeprom(sc, ether_addr,
1785 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1786 device_printf(dev, "failed to read station address\n");
1787 error = ENXIO;
1788 goto fail;
1789 }
1790
1791 /* 5705/5750 limits RX return ring to 512 entries. */
1792 if (BGE_IS_5705_PLUS(sc))
1793 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1794 else
1795 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1796
1797 error = bge_dma_alloc(sc);
1798 if (error)
1799 goto fail;
1800
1801 /* Set default tuneable values. */
1802 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1803 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1804 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1805 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1806 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1807
1808 /* Set up ifnet structure */
1809 ifp->if_softc = sc;
1810 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1811 ifp->if_ioctl = bge_ioctl;
1812 ifp->if_start = bge_start;
1813 #ifdef DEVICE_POLLING
1814 ifp->if_poll = bge_poll;
1815 #endif
1816 ifp->if_watchdog = bge_watchdog;
1817 ifp->if_init = bge_init;
1818 ifp->if_mtu = ETHERMTU;
1819 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1820 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1821 ifq_set_ready(&ifp->if_snd);
1822
1823 /*
1824 * 5700 B0 chips do not support checksumming correctly due
1825 * to hardware bugs.
1826 */
1827 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1828 ifp->if_capabilities |= IFCAP_HWCSUM;
1829 ifp->if_hwassist = BGE_CSUM_FEATURES;
1830 }
1831 ifp->if_capenable = ifp->if_capabilities;
1832
1833 /*
1834 * Figure out what sort of media we have by checking the
1835 * hardware config word in the first 32k of NIC internal memory,
1836 * or fall back to examining the EEPROM if necessary.
1837 * Note: on some BCM5700 cards, this value appears to be unset.
1838 * If that's the case, we have to rely on identifying the NIC
1839 * by its PCI subsystem ID, as we do below for the SysKonnect
1840 * SK-9D41.
1841 */
1842 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1843 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1844 else {
1845 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1846 sizeof(hwcfg))) {
1847 device_printf(dev, "failed to read EEPROM\n");
1848 error = ENXIO;
1849 goto fail;
1850 }
1851 hwcfg = ntohl(hwcfg);
1852 }
1853
1854 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1855 sc->bge_flags |= BGE_FLAG_TBI;
1856
1857 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1858 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1859 sc->bge_flags |= BGE_FLAG_TBI;
1860
1861 if (sc->bge_flags & BGE_FLAG_TBI) {
1862 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1863 bge_ifmedia_upd, bge_ifmedia_sts);
1864 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1865 ifmedia_add(&sc->bge_ifmedia,
1866 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1867 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1868 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1869 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1870 } else {
1871 /*
1872 * Do transceiver setup.
1873 */
1874 if (mii_phy_probe(dev, &sc->bge_miibus,
1875 bge_ifmedia_upd, bge_ifmedia_sts)) {
1876 device_printf(dev, "MII without any PHY!\n");
1877 error = ENXIO;
1878 goto fail;
1879 }
1880 }
1881
1882 /*
1883 * When using the BCM5701 in PCI-X mode, data corruption has
1884 * been observed in the first few bytes of some received packets.
1885 * Aligning the packet buffer in memory eliminates the corruption.
1886 * Unfortunately, this misaligns the packet payloads. On platforms
1887 * which do not support unaligned accesses, we will realign the
1888 * payloads by copying the received packets.
1889 */
1890 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1891 (sc->bge_flags & BGE_FLAG_PCIX))
1892 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1893
1894 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1895 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1896 sc->bge_link_upd = bge_bcm5700_link_upd;
1897 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1898 } else if (sc->bge_flags & BGE_FLAG_TBI) {
1899 sc->bge_link_upd = bge_tbi_link_upd;
1900 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1901 } else {
1902 sc->bge_link_upd = bge_copper_link_upd;
1903 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1904 }
1905
1906 /*
1907 * Create sysctl nodes.
1908 */
1909 sysctl_ctx_init(&sc->bge_sysctl_ctx);
1910 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1911 SYSCTL_STATIC_CHILDREN(_hw),
1912 OID_AUTO,
1913 device_get_nameunit(dev),
1914 CTLFLAG_RD, 0, "");
1915 if (sc->bge_sysctl_tree == NULL) {
1916 device_printf(dev, "can't add sysctl node\n");
1917 error = ENXIO;
1918 goto fail;
1919 }
1920
1921 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1922 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1923 OID_AUTO, "rx_coal_ticks",
1924 CTLTYPE_INT | CTLFLAG_RW,
1925 sc, 0, bge_sysctl_rx_coal_ticks, "I",
1926 "Receive coalescing ticks (usec).");
1927 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1928 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1929 OID_AUTO, "tx_coal_ticks",
1930 CTLTYPE_INT | CTLFLAG_RW,
1931 sc, 0, bge_sysctl_tx_coal_ticks, "I",
1932 "Transmit coalescing ticks (usec).");
1933 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1934 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1935 OID_AUTO, "rx_max_coal_bds",
1936 CTLTYPE_INT | CTLFLAG_RW,
1937 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1938 "Receive max coalesced BD count.");
1939 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1940 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1941 OID_AUTO, "tx_max_coal_bds",
1942 CTLTYPE_INT | CTLFLAG_RW,
1943 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1944 "Transmit max coalesced BD count.");
1945
1946 /*
1947 * Call MI attach routine.
1948 */
1949 ether_ifattach(ifp, ether_addr, NULL);
1950
1951 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1952 bge_intr, sc, &sc->bge_intrhand,
1953 ifp->if_serializer);
1954 if (error) {
1955 ether_ifdetach(ifp);
1956 device_printf(dev, "couldn't set up irq\n");
1957 goto fail;
1958 }
1959
1960 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
1961 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1962
1963 return(0);
1964 fail:
1965 bge_detach(dev);
1966 return(error);
1967 }
1968
1969 static int
1970 bge_detach(device_t dev)
1971 {
1972 struct bge_softc *sc = device_get_softc(dev);
1973
1974 if (device_is_attached(dev)) {
1975 struct ifnet *ifp = &sc->arpcom.ac_if;
1976
1977 lwkt_serialize_enter(ifp->if_serializer);
1978 bge_stop(sc);
1979 bge_reset(sc);
1980 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1981 lwkt_serialize_exit(ifp->if_serializer);
1982
1983 ether_ifdetach(ifp);
1984 }
1985
1986 if (sc->bge_flags & BGE_FLAG_TBI)
1987 ifmedia_removeall(&sc->bge_ifmedia);
1988 if (sc->bge_miibus)
1989 device_delete_child(dev, sc->bge_miibus);
1990 bus_generic_detach(dev);
1991
1992 if (sc->bge_irq != NULL)
1993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1994
1995 if (sc->bge_res != NULL)
1996 bus_release_resource(dev, SYS_RES_MEMORY,
1997 BGE_PCI_BAR0, sc->bge_res);
1998
1999 if (sc->bge_sysctl_tree != NULL)
2000 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2001
2002 bge_dma_free(sc);
2003
2004 return 0;
2005 }
2006
2007 static void
2008 bge_reset(struct bge_softc *sc)
2009 {
2010 device_t dev;
2011 uint32_t cachesize, command, pcistate, reset;
2012 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2013 int i, val = 0;
2014
2015 dev = sc->bge_dev;
2016
2017 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2018 if (sc->bge_flags & BGE_FLAG_PCIE)
2019 write_op = bge_writemem_direct;
2020 else
2021 write_op = bge_writemem_ind;
2022 } else {
2023 write_op = bge_writereg_ind;
2024 }
2025
2026 /* Save some important PCI state. */
2027 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2028 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2029 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2030
2031 pci_write_config(dev, BGE_PCI_MISC_CTL,
2032 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2033 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2034
2035 /* Disable fastboot on controllers that support it. */
2036 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2037 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2038 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2039 if (bootverbose)
2040 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2041 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2042 }
2043
2044 /*
2045 * Write the magic number to SRAM at offset 0xB50.
2046 * When firmware finishes its initialization it will
2047 * write ~BGE_MAGIC_NUMBER to the same location.
2048 */
2049 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2050
2051 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2052
2053 /* XXX: Broadcom Linux driver. */
2054 if (sc->bge_flags & BGE_FLAG_PCIE) {
2055 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2056 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2057 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2058 /* Prevent PCIE link training during global reset */
2059 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2060 reset |= (1<<29);
2061 }
2062 }
2063
2064 /*
2065 * Set GPHY Power Down Override to leave GPHY
2066 * powered up in D0 uninitialized.
2067 */
2068 if (BGE_IS_5705_PLUS(sc))
2069 reset |= 0x04000000;
2070
2071 /* Issue global reset */
2072 write_op(sc, BGE_MISC_CFG, reset);
2073
2074 DELAY(1000);
2075
2076 /* XXX: Broadcom Linux driver. */
2077 if (sc->bge_flags & BGE_FLAG_PCIE) {
2078 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2079 uint32_t v;
2080
2081 DELAY(500000); /* wait for link training to complete */
2082 v = pci_read_config(dev, 0xc4, 4);
2083 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2084 }
2085 /*
2086 * Set PCIE max payload size to 128 bytes and
2087 * clear error status.
2088 */
2089 pci_write_config(dev, 0xd8, 0xf5000, 4);
2090 }
2091
2092 /* Reset some of the PCI state that got zapped by reset */
2093 pci_write_config(dev, BGE_PCI_MISC_CTL,
2094 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2095 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2096 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2097 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2098 write_op(sc, BGE_MISC_CFG, (65 << 1));
2099
2100 /* Enable memory arbiter. */
2101 if (BGE_IS_5714_FAMILY(sc)) {
2102 uint32_t val;
2103
2104 val = CSR_READ_4(sc, BGE_MARB_MODE);
2105 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2106 } else {
2107 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2108 }
2109
2110 /*
2111 * Poll until we see the 1's complement of the magic number.
2112 * This indicates that the firmware initialization
2113 * is complete.
2114 */
2115 for (i = 0; i < BGE_TIMEOUT; i++) {
2116 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2117 if (val == ~BGE_MAGIC_NUMBER)
2118 break;
2119 DELAY(10);
2120 }
2121
2122 if (i == BGE_TIMEOUT) {
2123 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2124 "found 0x%08x\n", val);
2125 return;
2126 }
2127
2128 /*
2129 * XXX Wait for the value of the PCISTATE register to
2130 * return to its original pre-reset state. This is a
2131 * fairly good indicator of reset completion. If we don't
2132 * wait for the reset to fully complete, trying to read
2133 * from the device's non-PCI registers may yield garbage
2134 * results.
2135 */
2136 for (i = 0; i < BGE_TIMEOUT; i++) {
2137 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2138 break;
2139 DELAY(10);
2140 }
2141
2142 if (sc->bge_flags & BGE_FLAG_PCIE) {
2143 reset = bge_readmem_ind(sc, 0x7c00);
2144 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2145 }
2146
2147 /* Fix up byte swapping */
2148 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2149 BGE_MODECTL_BYTESWAP_DATA);
2150
2151 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2152
2153 /*
2154 * The 5704 in TBI mode apparently needs some special
2155 * adjustment to insure the SERDES drive level is set
2156 * to 1.2V.
2157 */
2158 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2159 (sc->bge_flags & BGE_FLAG_TBI)) {
2160 uint32_t serdescfg;
2161
2162 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2163 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2164 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2165 }
2166
2167 /* XXX: Broadcom Linux driver. */
2168 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2169 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2170 uint32_t v;
2171
2172 v = CSR_READ_4(sc, 0x7c00);
2173 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2174 }
2175
2176 DELAY(10000);
2177 }
2178
2179 /*
2180 * Frame reception handling. This is called if there's a frame
2181 * on the receive return list.
2182 *
2183 * Note: we have to be able to handle two possibilities here:
2184 * 1) the frame is from the jumbo recieve ring
2185 * 2) the frame is from the standard receive ring
2186 */
2187
2188 static void
2189 bge_rxeof(struct bge_softc *sc)
2190 {
2191 struct ifnet *ifp;
2192 int stdcnt = 0, jumbocnt = 0;
2193
2194 if (sc->bge_rx_saved_considx ==
2195 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2196 return;
2197
2198 ifp = &sc->arpcom.ac_if;
2199
2200 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2201 sc->bge_cdata.bge_rx_return_ring_map,
2202 BUS_DMASYNC_POSTREAD);
2203 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2204 sc->bge_cdata.bge_rx_std_ring_map,
2205 BUS_DMASYNC_POSTREAD);
2206 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2207 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2208 sc->bge_cdata.bge_rx_jumbo_ring_map,
2209 BUS_DMASYNC_POSTREAD);
2210 }
2211
2212 while (sc->bge_rx_saved_considx !=
2213 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2214 struct bge_rx_bd *cur_rx;
2215 uint32_t rxidx;
2216 struct mbuf *m = NULL;
2217 uint16_t vlan_tag = 0;
2218 int have_tag = 0;
2219
2220 cur_rx =
2221 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2222
2223 rxidx = cur_rx->bge_idx;
2224 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2225 logif(rx_pkt);
2226
2227 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2228 have_tag = 1;
2229 vlan_tag = cur_rx->bge_vlan_tag;
2230 }
2231
2232 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2233 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2234 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2235 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2236 jumbocnt++;
2237 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2238 ifp->if_ierrors++;
2239 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2240 continue;
2241 }
2242 if (bge_newbuf_jumbo(sc,
2243 sc->bge_jumbo, NULL) == ENOBUFS) {
2244 ifp->if_ierrors++;
2245 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2246 continue;
2247 }
2248 } else {
2249 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2250 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2251 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2252 BUS_DMASYNC_POSTREAD);
2253 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2254 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2255 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2256 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2257 stdcnt++;
2258 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2259 ifp->if_ierrors++;
2260 bge_newbuf_std(sc, sc->bge_std, m);
2261 continue;
2262 }
2263 if (bge_newbuf_std(sc, sc->bge_std,
2264 NULL) == ENOBUFS) {
2265 ifp->if_ierrors++;
2266 bge_newbuf_std(sc, sc->bge_std, m);
2267 continue;
2268 }
2269 }
2270
2271 ifp->if_ipackets++;
2272 #ifndef __i386__
2273 /*
2274 * The i386 allows unaligned accesses, but for other
2275 * platforms we must make sure the payload is aligned.
2276 */
2277 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2278 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2279 cur_rx->bge_len);
2280 m->m_data += ETHER_ALIGN;
2281 }
2282 #endif
2283 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2284 m->m_pkthdr.rcvif = ifp;
2285
2286 if (ifp->if_capenable & IFCAP_RXCSUM) {
2287 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2288 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2289 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2290 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2291 }
2292 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2293 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2294 m->m_pkthdr.csum_data =
2295 cur_rx->bge_tcp_udp_csum;
2296 m->m_pkthdr.csum_flags |=
2297 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2298 }
2299 }
2300
2301 /*
2302 * If we received a packet with a vlan tag, pass it
2303 * to vlan_input() instead of ether_input().
2304 */
2305 if (have_tag) {
2306 VLAN_INPUT_TAG(m, vlan_tag);
2307 have_tag = vlan_tag = 0;
2308 } else {
2309 ifp->if_input(ifp, m);
2310 }
2311 }
2312
2313 if (stdcnt > 0) {
2314 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2315 sc->bge_cdata.bge_rx_std_ring_map,
2316 BUS_DMASYNC_PREWRITE);
2317 }
2318
2319 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2320 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2321 sc->bge_cdata.bge_rx_jumbo_ring_map,
2322 BUS_DMASYNC_PREWRITE);
2323 }
2324
2325 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2326 if (stdcnt)
2327 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2328 if (jumbocnt)
2329 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2330 }
2331
2332 static void
2333 bge_txeof(struct bge_softc *sc)
2334 {
2335 struct bge_tx_bd *cur_tx = NULL;
2336 struct ifnet *ifp;
2337
2338 if (sc->bge_tx_saved_considx ==
2339 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2340 return;
2341
2342 ifp = &sc->arpcom.ac_if;
2343
2344 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2345 sc->bge_cdata.bge_tx_ring_map,
2346 BUS_DMASYNC_POSTREAD);
2347
2348 /*
2349 * Go through our tx ring and free mbufs for those
2350 * frames that have been sent.
2351 */
2352 while (sc->bge_tx_saved_considx !=
2353 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2354 uint32_t idx = 0;
2355
2356 idx = sc->bge_tx_saved_considx;
2357 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2358 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2359 ifp->if_opackets++;
2360 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2361 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2362 sc->bge_cdata.bge_tx_dmamap[idx],
2363 BUS_DMASYNC_POSTWRITE);
2364 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2365 sc->bge_cdata.bge_tx_dmamap[idx]);
2366 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2367 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2368 }
2369 sc->bge_txcnt--;
2370 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2371 logif(tx_pkt);
2372 }
2373
2374 if (cur_tx != NULL &&
2375 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2376 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2377 ifp->if_flags &= ~IFF_OACTIVE;
2378
2379 if (sc->bge_txcnt == 0)
2380 ifp->if_timer = 0;
2381
2382 if (!ifq_is_empty(&ifp->if_snd))
2383 if_devstart(ifp);
2384 }
2385
2386 #ifdef DEVICE_POLLING
2387
2388 static void
2389 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2390 {
2391 struct bge_softc *sc = ifp->if_softc;
2392 uint32_t status;
2393
2394 switch(cmd) {
2395 case POLL_REGISTER:
2396 bge_disable_intr(sc);
2397 break;
2398 case POLL_DEREGISTER:
2399 bge_enable_intr(sc);
2400 break;
2401 case POLL_AND_CHECK_STATUS:
2402 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2403 sc->bge_cdata.bge_status_map,
2404 BUS_DMASYNC_POSTREAD);
2405
2406 /*
2407 * Process link state changes.
2408 */
2409 status = CSR_READ_4(sc, BGE_MAC_STS);
2410 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2411 sc->bge_link_evt = 0;
2412 sc->bge_link_upd(sc, status);
2413 }
2414 /* fall through */
2415 case POLL_ONLY:
2416 if (ifp->if_flags & IFF_RUNNING) {
2417 bge_rxeof(sc);
2418 bge_txeof(sc);
2419 }
2420 break;
2421 }
2422 }
2423
2424 #endif
2425
2426 static void
2427 bge_intr(void *xsc)
2428 {
2429 struct bge_softc *sc = xsc;
2430 struct ifnet *ifp = &sc->arpcom.ac_if;
2431 uint32_t status;
2432
2433 logif(intr);
2434
2435 /*
2436 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2437 * disable interrupts by writing nonzero like we used to, since with
2438 * our current organization this just gives complications and
2439 * pessimizations for re-enabling interrupts. We used to have races
2440 * instead of the necessary complications. Disabling interrupts
2441 * would just reduce the chance of a status update while we are
2442 * running (by switching to the interrupt-mode coalescence
2443 * parameters), but this chance is already very low so it is more
2444 * efficient to get another interrupt than prevent it.
2445 *
2446 * We do the ack first to ensure another interrupt if there is a
2447 * status update after the ack. We don't check for the status
2448 * changing later because it is more efficient to get another
2449 * interrupt than prevent it, not quite as above (not checking is
2450 * a smaller optimization than not toggling the interrupt enable,
2451 * since checking doesn't involve PCI accesses and toggling require
2452 * the status check). So toggling would probably be a pessimization
2453 * even with MSI. It would only be needed for using a task queue.
2454 */
2455 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2456
2457 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2458 sc->bge_cdata.bge_status_map,
2459 BUS_DMASYNC_POSTREAD);
2460
2461 /*
2462 * Process link state changes.
2463 */
2464 status = CSR_READ_4(sc, BGE_MAC_STS);
2465 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2466 sc->bge_link_evt = 0;
2467 sc->bge_link_upd(sc, status);
2468 }
2469
2470 if (ifp->if_flags & IFF_RUNNING) {
2471 /* Check RX return ring producer/consumer */
2472 bge_rxeof(sc);
2473
2474 /* Check TX ring producer/consumer */
2475 bge_txeof(sc);
2476 }
2477
2478 if (sc->bge_coal_chg)
2479 bge_coal_change(sc);
2480 }
2481
2482 static void
2483 bge_tick(void *xsc)
2484 {
2485 struct bge_softc *sc = xsc;
2486 struct ifnet *ifp = &sc->arpcom.ac_if;
2487
2488 lwkt_serialize_enter(ifp->if_serializer);
2489
2490 if (BGE_IS_5705_PLUS(sc))
2491 bge_stats_update_regs(sc);
2492 else
2493 bge_stats_update(sc);
2494
2495 if (sc->bge_flags & BGE_FLAG_TBI) {
2496 /*
2497 * Since in TBI mode auto-polling can't be used we should poll
2498 * link status manually. Here we register pending link event
2499 * and trigger interrupt.
2500 */
2501 sc->bge_link_evt++;
2502 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2503 } else if (!sc->bge_link) {
2504 mii_tick(device_get_softc(sc->bge_miibus));
2505 }
2506
2507 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2508
2509 lwkt_serialize_exit(ifp->if_serializer);
2510 }
2511
2512 static void
2513 bge_stats_update_regs(struct bge_softc *sc)
2514 {
2515 struct ifnet *ifp = &sc->arpcom.ac_if;
2516 struct bge_mac_stats_regs stats;
2517 uint32_t *s;
2518 int i;
2519
2520 s = (uint32_t *)&stats;
2521 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2522 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2523 s++;
2524 }
2525
2526 ifp->if_collisions +=
2527 (stats.dot3StatsSingleCollisionFrames +
2528 stats.dot3StatsMultipleCollisionFrames +
2529 stats.dot3StatsExcessiveCollisions +
2530 stats.dot3StatsLateCollisions) -
2531 ifp->if_collisions;
2532 }
2533
2534 static void
2535 bge_stats_update(struct bge_softc *sc)
2536 {
2537 struct ifnet *ifp = &sc->arpcom.ac_if;
2538 bus_size_t stats;
2539
2540 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2541
2542 #define READ_STAT(sc, stats, stat) \
2543 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2544
2545 ifp->if_collisions +=
2546 (READ_STAT(sc, stats,
2547 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2548 READ_STAT(sc, stats,
2549 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2550 READ_STAT(sc, stats,
2551 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2552 READ_STAT(sc, stats,
2553 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2554 ifp->if_collisions;
2555
2556 #undef READ_STAT
2557
2558 #ifdef notdef
2559 ifp->if_collisions +=
2560 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2561 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2562 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2563 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2564 ifp->if_collisions;
2565 #endif
2566 }
2567
2568 /*
2569 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2570 * pointers to descriptors.
2571 */
2572 static int
2573 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2574 {
2575 struct bge_tx_bd *d = NULL;
2576 uint16_t csum_flags = 0;
2577 struct bge_dmamap_arg ctx;
2578 bus_dma_segment_t segs[BGE_NSEG_NEW];
2579 bus_dmamap_t map;
2580 int error, maxsegs, idx, i;
2581 struct mbuf *m_head = *m_head0;
2582
2583 if (m_head->m_pkthdr.csum_flags) {
2584 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2585 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2586 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2587 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2588 if (m_head->m_flags & M_LASTFRAG)
2589 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2590 else if (m_head->m_flags & M_FRAG)
2591 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2592 }
2593
2594 idx = *txidx;
2595 map = sc->bge_cdata.bge_tx_dmamap[idx];
2596
2597 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2598 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2599 ("not enough segments %d\n", maxsegs));
2600
2601 if (maxsegs > BGE_NSEG_NEW)
2602 maxsegs = BGE_NSEG_NEW;
2603
2604 /*
2605 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2606 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2607 * but when such padded frames employ the bge IP/TCP checksum
2608 * offload, the hardware checksum assist gives incorrect results
2609 * (possibly from incorporating its own padding into the UDP/TCP
2610 * checksum; who knows). If we pad such runts with zeros, the
2611 * onboard checksum comes out correct. We do this by pretending
2612 * the mbuf chain has too many fragments so the coalescing code
2613 * below can assemble the packet into a single buffer that's
2614 * padded out to the mininum frame size.
2615 */
2616 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2617 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2618 error = EFBIG;
2619 } else {
2620 ctx.bge_segs = segs;
2621 ctx.bge_maxsegs = maxsegs;
2622 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2623 m_head, bge_dma_map_mbuf, &ctx,
2624 BUS_DMA_NOWAIT);
2625 }
2626 if (error == EFBIG || ctx.bge_maxsegs == 0) {
2627 struct mbuf *m_new;
2628
2629 m_new = m_defrag(m_head, MB_DONTWAIT);
2630 if (m_new == NULL) {
2631 if_printf(&sc->arpcom.ac_if,
2632 "could not defrag TX mbuf\n");
2633 error = ENOBUFS;
2634 goto back;
2635 } else {
2636 m_head = m_new;
2637 *m_head0 = m_head;
2638 }
2639
2640 /*
2641 * Manually pad short frames, and zero the pad space
2642 * to avoid leaking data.
2643 */
2644 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2645 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2646 int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2647
2648 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2649 pad_len);
2650 m_head->m_pkthdr.len += pad_len;
2651 m_head->m_len = m_head->m_pkthdr.len;
2652 }
2653
2654 ctx.bge_segs = segs;
2655 ctx.bge_maxsegs = maxsegs;
2656 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2657 m_head, bge_dma_map_mbuf, &ctx,
2658 BUS_DMA_NOWAIT);
2659 if (error || ctx.bge_maxsegs == 0) {
2660 if_printf(&sc->arpcom.ac_if,
2661 "could not defrag TX mbuf\n");
2662 if (error == 0)
2663 error = EFBIG;
2664 goto back;
2665 }
2666 } else if (error) {
2667 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2668 goto back;
2669 }
2670
2671 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2672
2673 for (i = 0; ; i++) {
2674 d = &sc->bge_ldata.bge_tx_ring[idx];
2675
2676 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2677 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2678 d->bge_len = segs[i].ds_len;
2679 d->bge_flags = csum_flags;
2680
2681 if (i == ctx.bge_maxsegs - 1)
2682 break;
2683 BGE_INC(idx, BGE_TX_RING_CNT);
2684 }
2685 /* Mark the last segment as end of packet... */
2686 d->bge_flags |= BGE_TXBDFLAG_END;
2687
2688 /* Set vlan tag to the first segment of the packet. */
2689 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2690 if (m_head->m_flags & M_VLANTAG) {
2691 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2692 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2693 } else {
2694 d->bge_vlan_tag = 0;
2695 }
2696
2697 /*
2698 * Insure that the map for this transmission is placed at
2699 * the array index of the last descriptor in this chain.
2700 */
2701 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2702 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2703 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2704 sc->bge_txcnt += ctx.bge_maxsegs;
2705
2706 BGE_INC(idx, BGE_TX_RING_CNT);
2707 *txidx = idx;
2708 back:
2709 if (error) {
2710 m_freem(m_head);
2711 *m_head0 = NULL;
2712 }
2713 return error;
2714 }
2715
2716 /*
2717 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2718 * to the mbuf data regions directly in the transmit descriptors.
2719 */
2720 static void
2721 bge_start(struct ifnet *ifp)
2722 {
2723 struct bge_softc *sc = ifp->if_softc;
2724 struct mbuf *m_head = NULL;
2725 uint32_t prodidx;
2726 int need_trans;
2727
2728 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2729 return;
2730
2731 prodidx = sc->bge_tx_prodidx;
2732
2733 need_trans = 0;
2734 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2735 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2736 if (m_head == NULL)
2737 break;
2738
2739 /*
2740 * XXX
2741 * The code inside the if() block is never reached since we
2742 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2743 * requests to checksum TCP/UDP in a fragmented packet.
2744 *
2745 * XXX
2746 * safety overkill. If this is a fragmented packet chain
2747 * with delayed TCP/UDP checksums, then only encapsulate
2748 * it if we have enough descriptors to handle the entire
2749 * chain at once.
2750 * (paranoia -- may not actually be needed)
2751 */
2752 if ((m_head->m_flags & M_FIRSTFRAG) &&
2753 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2754 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2755 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2756 ifp->if_flags |= IFF_OACTIVE;
2757 ifq_prepend(&ifp->if_snd, m_head);
2758 break;
2759 }
2760 }
2761
2762 /*
2763 * Sanity check: avoid coming within BGE_NSEG_RSVD
2764 * descriptors of the end of the ring. Also make
2765 * sure there are BGE_NSEG_SPARE descriptors for
2766 * jumbo buffers' defragmentation.
2767 */
2768 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2769 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2770 ifp->if_flags |= IFF_OACTIVE;
2771 ifq_prepend(&ifp->if_snd, m_head);
2772 break;
2773 }
2774
2775 /*
2776 * Pack the data into the transmit ring. If we
2777 * don't have room, set the OACTIVE flag and wait
2778 * for the NIC to drain the ring.
2779 */
2780 if (bge_encap(sc, &m_head, &prodidx)) {
2781 ifp->if_flags |= IFF_OACTIVE;
2782 break;
2783 }
2784 need_trans = 1;
2785
2786 ETHER_BPF_MTAP(ifp, m_head);
2787 }
2788
2789 if (!need_trans)
2790 return;
2791
2792 /* Transmit */
2793 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2794 /* 5700 b2 errata */
2795 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2796 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2797
2798 sc->bge_tx_prodidx = prodidx;
2799
2800 /*
2801 * Set a timeout in case the chip goes out to lunch.
2802 */
2803 ifp->if_timer = 5;
2804 }
2805
2806 static void
2807 bge_init(void *xsc)
2808 {
2809 struct bge_softc *sc = xsc;
2810 struct ifnet *ifp = &sc->arpcom.ac_if;
2811 uint16_t *m;
2812
2813 ASSERT_SERIALIZED(ifp->if_serializer);
2814
2815 if (ifp->if_flags & IFF_RUNNING)
2816 return;
2817
2818 /* Cancel pending I/O and flush buffers. */
2819 bge_stop(sc);
2820 bge_reset(sc);
2821 bge_chipinit(sc);
2822
2823 /*
2824 * Init the various state machines, ring
2825 * control blocks and firmware.
2826 */
2827 if (bge_blockinit(sc)) {
2828 if_printf(ifp, "initialization failure\n");
2829 return;
2830 }
2831
2832 /* Specify MTU. */
2833 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2834 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2835
2836 /* Load our MAC address. */
2837 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2838 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2839 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2840
2841 /* Enable or disable promiscuous mode as needed. */
2842 bge_setpromisc(sc);
2843
2844 /* Program multicast filter. */
2845 bge_setmulti(sc);
2846
2847 /* Init RX ring. */
2848 bge_init_rx_ring_std(sc);
2849
2850 /*
2851 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2852 * memory to insure that the chip has in fact read the first
2853 * entry of the ring.
2854 */
2855 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2856 uint32_t v, i;
2857 for (i = 0; i < 10; i++) {
2858 DELAY(20);
2859 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2860 if (v == (MCLBYTES - ETHER_ALIGN))
2861 break;
2862 }
2863 if (i == 10)
2864 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2865 }
2866
2867 /* Init jumbo RX ring. */
2868 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2869 bge_init_rx_ring_jumbo(sc);
2870
2871 /* Init our RX return ring index */
2872 sc->bge_rx_saved_considx = 0;
2873
2874 /* Init TX ring. */
2875 bge_init_tx_ring(sc);
2876
2877 /* Turn on transmitter */
2878 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2879
2880 /* Turn on receiver */
2881 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2882
2883 /* Tell firmware we're alive. */
2884 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2885
2886 /* Enable host interrupts if polling(4) is not enabled. */
2887 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2888 #ifdef DEVICE_POLLING
2889 if (ifp->if_flags & IFF_POLLING)
2890 bge_disable_intr(sc);
2891 else
2892 #endif
2893 bge_enable_intr(sc);
2894
2895 bge_ifmedia_upd(ifp);
2896
2897 ifp->if_flags |= IFF_RUNNING;
2898 ifp->if_flags &= ~IFF_OACTIVE;
2899
2900 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2901 }
2902
2903 /*
2904 * Set media options.
2905 */
2906 static int
2907 bge_ifmedia_upd(struct ifnet *ifp)
2908 {
2909 struct bge_softc *sc = ifp->if_softc;
2910
2911 /* If this is a 1000baseX NIC, enable the TBI port. */
2912 if (sc->bge_flags & BGE_FLAG_TBI) {
2913 struct ifmedia *ifm = &sc->bge_ifmedia;
2914
2915 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2916 return(EINVAL);
2917
2918 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2919 case IFM_AUTO:
2920 /*
2921 * The BCM5704 ASIC appears to have a special
2922 * mechanism for programming the autoneg
2923 * advertisement registers in TBI mode.
2924 */
2925 if (!bge_fake_autoneg &&
2926 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2927 uint32_t sgdig;
2928
2929 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2930 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2931 sgdig |= BGE_SGDIGCFG_AUTO |
2932 BGE_SGDIGCFG_PAUSE_CAP |
2933 BGE_SGDIGCFG_ASYM_PAUSE;
2934 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2935 sgdig | BGE_SGDIGCFG_SEND);
2936 DELAY(5);
2937 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2938 }
2939 break;
2940 case IFM_1000_SX:
2941 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2942 BGE_CLRBIT(sc, BGE_MAC_MODE,
2943 BGE_MACMODE_HALF_DUPLEX);
2944 } else {
2945 BGE_SETBIT(sc, BGE_MAC_MODE,
2946 BGE_MACMODE_HALF_DUPLEX);
2947 }
2948 break;
2949 default:
2950 return(EINVAL);
2951 }
2952 } else {
2953 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2954
2955 sc->bge_link_evt++;
2956 sc->bge_link = 0;
2957 if (mii->mii_instance) {
2958 struct mii_softc *miisc;
2959
2960 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2961 mii_phy_reset(miisc);
2962 }
2963 mii_mediachg(mii);
2964 }
2965 return(0);
2966 }
2967
2968 /*
2969 * Report current media status.
2970 */
2971 static void
2972 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2973 {
2974 struct bge_softc *sc = ifp->if_softc;
2975
2976 if (sc->bge_flags & BGE_FLAG_TBI) {
2977 ifmr->ifm_status = IFM_AVALID;
2978 ifmr->ifm_active = IFM_ETHER;
2979 if (CSR_READ_4(sc, BGE_MAC_STS) &
2980 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2981 ifmr->ifm_status |= IFM_ACTIVE;
2982 } else {
2983 ifmr->ifm_active |= IFM_NONE;
2984 return;
2985 }
2986
2987 ifmr->ifm_active |= IFM_1000_SX;
2988 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2989 ifmr->ifm_active |= IFM_HDX;
2990 else
2991 ifmr->ifm_active |= IFM_FDX;
2992 } else {
2993 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2994
2995 mii_pollstat(mii);
2996 ifmr->ifm_active = mii->mii_media_active;
2997 ifmr->ifm_status = mii->mii_media_status;
2998 }
2999 }
3000
3001 static int
3002 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3003 {
3004 struct bge_softc *sc = ifp->if_softc;
3005 struct ifreq *ifr = (struct ifreq *)data;
3006 int mask, error = 0;
3007
3008 ASSERT_SERIALIZED(ifp->if_serializer);
3009
3010 switch (command) {
3011 case SIOCSIFMTU:
3012 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3013 (BGE_IS_JUMBO_CAPABLE(sc) &&
3014 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3015 error = EINVAL;
3016 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3017 ifp->if_mtu = ifr->ifr_mtu;
3018 ifp->if_flags &= ~IFF_RUNNING;
3019 bge_init(sc);
3020 }
3021 break;
3022 case SIOCSIFFLAGS:
3023 if (ifp->if_flags & IFF_UP) {
3024 if (ifp->if_flags & IFF_RUNNING) {
3025 mask = ifp->if_flags ^ sc->bge_if_flags;
3026
3027 /*
3028 * If only the state of the PROMISC flag
3029 * changed, then just use the 'set promisc
3030 * mode' command instead of reinitializing
3031 * the entire NIC. Doing a full re-init
3032 * means reloading the firmware and waiting
3033 * for it to start up, which may take a
3034 * second or two. Similarly for ALLMULTI.
3035 */
3036 if (mask & IFF_PROMISC)
3037 bge_setpromisc(sc);
3038 if (mask & IFF_ALLMULTI)
3039 bge_setmulti(sc);
3040 } else {
3041 bge_init(sc);
3042 }
3043 } else {
3044 if (ifp->if_flags & IFF_RUNNING)
3045 bge_stop(sc);
3046 }
3047 sc->bge_if_flags = ifp->if_flags;
3048 break;
3049 case SIOCADDMULTI:
3050 case SIOCDELMULTI:
3051 if (ifp->if_flags & IFF_RUNNING)
3052 bge_setmulti(sc);
3053 break;
3054 case SIOCSIFMEDIA:
3055 case SIOCGIFMEDIA:
3056 if (sc->bge_flags & BGE_FLAG_TBI) {
3057 error = ifmedia_ioctl(ifp, ifr,
3058 &sc->bge_ifmedia, command);
3059 } else {
3060 struct mii_data *mii;
3061
3062 mii = device_get_softc(sc->bge_miibus);
3063 error = ifmedia_ioctl(ifp, ifr,
3064 &mii->mii_media, command);
3065 }
3066 break;
3067 case SIOCSIFCAP:
3068 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3069 if (mask & IFCAP_HWCSUM) {
3070 ifp->if_capenable ^= IFCAP_HWCSUM;
3071 if (IFCAP_HWCSUM & ifp->if_capenable)
3072 ifp->if_hwassist = BGE_CSUM_FEATURES;
3073 else
3074 ifp->if_hwassist = 0;
3075 }
3076 break;
3077 default:
3078 error = ether_ioctl(ifp, command, data);
3079 break;
3080 }
3081 return error;
3082 }
3083
3084 static void
3085 bge_watchdog(struct ifnet *ifp)
3086 {
3087 struct bge_softc *sc = ifp->if_softc;
3088
3089 if_printf(ifp, "watchdog timeout -- resetting\n");
3090
3091 ifp->if_flags &= ~IFF_RUNNING;
3092 bge_init(sc);
3093
3094 ifp->if_oerrors++;
3095
3096 if (!ifq_is_empty(&ifp->if_snd))
3097 if_devstart(ifp);
3098 }
3099
3100 /*
3101 * Stop the adapter and free any mbufs allocated to the
3102 * RX and TX lists.
3103 */
3104 static void
3105 bge_stop(struct bge_softc *sc)
3106 {
3107 struct ifnet *ifp = &sc->arpcom.ac_if;
3108 struct ifmedia_entry *ifm;
3109 struct mii_data *mii = NULL;
3110 int mtmp, itmp;
3111
3112 ASSERT_SERIALIZED(ifp->if_serializer);
3113
3114 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3115 mii = device_get_softc(sc->bge_miibus);
3116
3117 callout_stop(&sc->bge_stat_timer);
3118
3119 /*
3120 * Disable all of the receiver blocks
3121 */
3122 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3123 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3124 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3125 if (!BGE_IS_5705_PLUS(sc))
3126 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3127 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3128 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3129 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3130
3131 /*
3132 * Disable all of the transmit blocks
3133 */
3134 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3135 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3136 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3137 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3138 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3139 if (!BGE_IS_5705_PLUS(sc))
3140 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3141 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3142
3143 /*
3144 * Shut down all of the memory managers and related
3145 * state machines.
3146 */
3147 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3148 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3149 if (!BGE_IS_5705_PLUS(sc))
3150 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3151 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3152 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3153 if (!BGE_IS_5705_PLUS(sc)) {
3154 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3155 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3156 }
3157
3158 /* Disable host interrupts. */
3159 bge_disable_intr(sc);
3160
3161 /*
3162 * Tell firmware we're shutting down.
3163 */
3164 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3165
3166 /* Free the RX lists. */
3167 bge_free_rx_ring_std(sc);
3168
3169 /* Free jumbo RX list. */
3170 if (BGE_IS_JUMBO_CAPABLE(sc))
3171 bge_free_rx_ring_jumbo(sc);
3172
3173 /* Free TX buffers. */
3174 bge_free_tx_ring(sc);
3175
3176 /*
3177 * Isolate/power down the PHY, but leave the media selection
3178 * unchanged so that things will be put back to normal when
3179 * we bring the interface back up.
3180 *
3181 * 'mii' may be NULL in the following cases:
3182 * - The device uses TBI.
3183 * - bge_stop() is called by bge_detach().
3184 */
3185 if (mii != NULL) {
3186 itmp = ifp->if_flags;
3187 ifp->if_flags |= IFF_UP;
3188 ifm = mii->mii_media.ifm_cur;
3189 mtmp = ifm->ifm_media;
3190 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3191 mii_mediachg(mii);
3192 ifm->ifm_media = mtmp;
3193 ifp->if_flags = itmp;
3194 }
3195
3196 sc->bge_link = 0;
3197 sc->bge_coal_chg = 0;
3198
3199 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3200
3201 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3202 ifp->if_timer = 0;
3203 }
3204
3205 /*
3206 * Stop all chip I/O so that the kernel's probe routines don't
3207 * get confused by errant DMAs when rebooting.
3208 */
3209 static void
3210 bge_shutdown(device_t dev)
3211 {
3212 struct bge_softc *sc = device_get_softc(dev);
3213 struct ifnet *ifp = &sc->arpcom.ac_if;
3214
3215 lwkt_serialize_enter(ifp->if_serializer);
3216 bge_stop(sc);
3217 bge_reset(sc);
3218 lwkt_serialize_exit(ifp->if_serializer);
3219 }
3220
3221 static int
3222 bge_suspend(device_t dev)
3223 {
3224 struct bge_softc *sc = device_get_softc(dev);
3225 struct ifnet *ifp = &sc->arpcom.ac_if;
3226
3227 lwkt_serialize_enter(ifp->if_serializer);
3228 bge_stop(sc);
3229 lwkt_serialize_exit(ifp->if_serializer);
3230
3231 return 0;
3232 }
3233
3234 static int
3235 bge_resume(device_t dev)
3236 {
3237 struct bge_softc *sc = device_get_softc(dev);
3238 struct ifnet *ifp = &sc->arpcom.ac_if;
3239
3240 lwkt_serialize_enter(ifp->if_serializer);
3241
3242 if (ifp->if_flags & IFF_UP) {
3243 bge_init(sc);
3244
3245 if (!ifq_is_empty(&ifp->if_snd))
3246 if_devstart(ifp);
3247 }
3248
3249 lwkt_serialize_exit(ifp->if_serializer);
3250
3251 return 0;
3252 }
3253
3254 static void
3255 bge_setpromisc(struct bge_softc *sc)
3256 {
3257 struct ifnet *ifp = &sc->arpcom.ac_if;
3258
3259 if (ifp->if_flags & IFF_PROMISC)
3260 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3261 else
3262 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3263 }
3264
3265 static void
3266 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3267 {
3268 struct bge_dmamap_arg *ctx = arg;
3269
3270 if (error)
3271 return;
3272
3273 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3274 ("only one segment is allowed\n"));
3275
3276 ctx->bge_segs[0] = *segs;
3277 }
3278
3279 static void
3280 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3281 bus_size_t mapsz __unused, int error)
3282 {
3283 struct bge_dmamap_arg *ctx = arg;
3284 int i;
3285
3286 if (error)
3287 return;
3288
3289 if (nsegs > ctx->bge_maxsegs) {
3290 ctx->bge_maxsegs = 0;
3291 return;
3292 }
3293
3294 ctx->bge_maxsegs = nsegs;
3295 for (i = 0; i < nsegs; ++i)
3296 ctx->bge_segs[i] = segs[i];
3297 }
3298
3299 static void
3300 bge_dma_free(struct bge_softc *sc)
3301 {
3302 int i;
3303
3304 /* Destroy RX/TX mbuf DMA stuffs. */
3305 if (sc->bge_cdata.bge_mtag != NULL) {
3306 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3307 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3308 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3309 sc->bge_cdata.bge_rx_std_dmamap[i]);
3310 }
3311 }
3312
3313 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3314 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3315 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3316 sc->bge_cdata.bge_tx_dmamap[i]);
3317 }
3318 }
3319 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3320 }
3321
3322 /* Destroy standard RX ring */
3323 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3324 sc->bge_cdata.bge_rx_std_ring_map,
3325 sc->bge_ldata.bge_rx_std_ring);
3326
3327 if (BGE_IS_JUMBO_CAPABLE(sc))
3328 bge_free_jumbo_mem(sc);
3329
3330 /* Destroy RX return ring */
3331 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3332 sc->bge_cdata.bge_rx_return_ring_map,
3333 sc->bge_ldata.bge_rx_return_ring);
3334
3335 /* Destroy TX ring */
3336 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3337 sc->bge_cdata.bge_tx_ring_map,
3338 sc->bge_ldata.bge_tx_ring);
3339
3340 /* Destroy status block */
3341 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3342 sc->bge_cdata.bge_status_map,
3343 sc->bge_ldata.bge_status_block);
3344
3345 /* Destroy statistics block */
3346 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3347 sc->bge_cdata.bge_stats_map,
3348 sc->bge_ldata.bge_stats);
3349
3350 /* Destroy the parent tag */
3351 if (sc->bge_cdata.bge_parent_tag != NULL)
3352 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3353 }
3354
3355 static int
3356 bge_dma_alloc(struct bge_softc *sc)
3357 {
3358 struct ifnet *ifp = &sc->arpcom.ac_if;
3359 int nseg, i, error;
3360
3361 /*
3362 * Allocate the parent bus DMA tag appropriate for PCI.
3363 */
3364 error = bus_dma_tag_create(NULL, 1, 0,
3365 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3366 NULL, NULL,
3367 MAXBSIZE, BGE_NSEG_NEW,
3368 BUS_SPACE_MAXSIZE_32BIT,
3369 0, &sc->bge_cdata.bge_parent_tag);
3370 if (error) {
3371 if_printf(ifp, "could not allocate parent dma tag\n");
3372 return error;
3373 }
3374
3375 /*
3376 * Create DMA tag for mbufs.
3377 */
3378 nseg = BGE_NSEG_NEW;
3379 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3380 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3381 NULL, NULL,
3382 MCLBYTES * nseg, nseg, MCLBYTES,
3383 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3384 if (error) {
3385 if_printf(ifp, "could not allocate mbuf dma tag\n");
3386 return error;
3387 }
3388
3389 /*
3390 * Create DMA maps for TX/RX mbufs.
3391 */
3392 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3393 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3394 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3395 if (error) {
3396 int j;
3397
3398 for (j = 0; j < i; ++j) {
3399 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3400 sc->bge_cdata.bge_rx_std_dmamap[j]);
3401 }
3402 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3403 sc->bge_cdata.bge_mtag = NULL;
3404
3405 if_printf(ifp, "could not create DMA map for RX\n");
3406 return error;
3407 }
3408 }
3409
3410 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3411 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3412 &sc->bge_cdata.bge_tx_dmamap[i]);
3413 if (error) {
3414 int j;
3415
3416 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3417 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3418 sc->bge_cdata.bge_rx_std_dmamap[j]);
3419 }
3420 for (j = 0; j < i; ++j) {
3421 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3422 sc->bge_cdata.bge_tx_dmamap[j]);
3423 }
3424 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3425 sc->bge_cdata.bge_mtag = NULL;
3426
3427 if_printf(ifp, "could not create DMA map for TX\n");
3428 return error;
3429 }
3430 }
3431
3432 /*
3433 * Create DMA stuffs for standard RX ring.
3434 */
3435 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3436 &sc->bge_cdata.bge_rx_std_ring_tag,
3437 &sc->bge_cdata.bge_rx_std_ring_map,
3438 (void **)&sc->bge_ldata.bge_rx_std_ring,
3439 &sc->bge_ldata.bge_rx_std_ring_paddr);
3440 if (error) {
3441 if_printf(ifp, "could not create std RX ring\n");
3442 return error;
3443 }
3444
3445 /*
3446 * Create jumbo buffer pool.
3447 */
3448 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3449 error = bge_alloc_jumbo_mem(sc);
3450 if (error) {
3451 if_printf(ifp, "could not create jumbo buffer pool\n");
3452 return error;
3453 }
3454 }
3455
3456 /*
3457 * Create DMA stuffs for RX return ring.
3458 */
3459 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3460 &sc->bge_cdata.bge_rx_return_ring_tag,
3461 &sc->bge_cdata.bge_rx_return_ring_map,
3462 (void **)&sc->bge_ldata.bge_rx_return_ring,
3463 &sc->bge_ldata.bge_rx_return_ring_paddr);
3464 if (error) {
3465 if_printf(ifp, "could not create RX ret ring\n");
3466 return error;
3467 }
3468
3469 /*
3470 * Create DMA stuffs for TX ring.
3471 */
3472 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3473 &sc->bge_cdata.bge_tx_ring_tag,
3474 &sc->bge_cdata.bge_tx_ring_map,
3475 (void **)&sc->bge_ldata.bge_tx_ring,
3476 &sc->bge_ldata.bge_tx_ring_paddr);
3477 if (error) {
3478 if_printf(ifp, "could not create TX ring\n");
3479 return error;
3480 }
3481
3482 /*
3483 * Create DMA stuffs for status block.
3484 */
3485 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3486 &sc->bge_cdata.bge_status_tag,
3487 &sc->bge_cdata.bge_status_map,
3488 (void **)&sc->bge_ldata.bge_status_block,
3489 &sc->bge_ldata.bge_status_block_paddr);
3490 if (error) {
3491 if_printf(ifp, "could not create status block\n");
3492 return error;
3493 }
3494
3495 /*
3496 * Create DMA stuffs for statistics block.
3497 */
3498 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3499 &sc->bge_cdata.bge_stats_tag,
3500 &sc->bge_cdata.bge_stats_map,
3501 (void **)&sc->bge_ldata.bge_stats,
3502 &sc->bge_ldata.bge_stats_paddr);
3503 if (error) {
3504 if_printf(ifp, "could not create stats block\n");
3505 return error;
3506 }
3507 return 0;
3508 }
3509
3510 static int
3511 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3512 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3513 {
3514 struct ifnet *ifp = &sc->arpcom.ac_if;
3515 struct bge_dmamap_arg ctx;
3516 bus_dma_segment_t seg;
3517 int error;
3518
3519 /*
3520 * Create DMA tag
3521 */
3522 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3523 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3524 NULL, NULL, size, 1, size, 0, tag);
3525 if (error) {
3526 if_printf(ifp, "could not allocate dma tag\n");
3527 return error;
3528 }
3529
3530 /*
3531 * Allocate DMA'able memory
3532 */
3533 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3534 map);
3535 if (error) {
3536 if_printf(ifp, "could not allocate dma memory\n");
3537 bus_dma_tag_destroy(*tag);
3538 *tag = NULL;
3539 return error;
3540 }
3541
3542 /*
3543 * Load the DMA'able memory
3544 */
3545 ctx.bge_maxsegs = 1;
3546 ctx.bge_segs = &seg;
3547 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3548 BUS_DMA_WAITOK);
3549 if (error) {
3550 if_printf(ifp, "could not load dma memory\n");
3551 bus_dmamem_free(*tag, *addr, *map);
3552 bus_dma_tag_destroy(*tag);
3553 *tag = NULL;
3554 return error;
3555 }
3556 *paddr = ctx.bge_segs[0].ds_addr;
3557
3558 return 0;
3559 }
3560
3561 static void
3562 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3563 {
3564 if (tag != NULL) {
3565 bus_dmamap_unload(tag, map);
3566 bus_dmamem_free(tag, addr, map);
3567 bus_dma_tag_destroy(tag);
3568 }
3569 }
3570
3571 /*
3572 * Grrr. The link status word in the status block does
3573 * not work correctly on the BCM5700 rev AX and BX chips,
3574 * according to all available information. Hence, we have
3575 * to enable MII interrupts in order to properly obtain
3576 * async link changes. Unfortunately, this also means that
3577 * we have to read the MAC status register to detect link
3578 * changes, thereby adding an additional register access to
3579 * the interrupt handler.
3580 *
3581 * XXX: perhaps link state detection procedure used for
3582 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3583 */
3584 static void
3585 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3586 {
3587 struct ifnet *ifp = &sc->arpcom.ac_if;
3588 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3589
3590 mii_pollstat(mii);
3591
3592 if (!sc->bge_link &&
3593 (mii->mii_media_status & IFM_ACTIVE) &&
3594 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3595 sc->bge_link++;
3596 if (bootverbose)
3597 if_printf(ifp, "link UP\n");
3598 } else if (sc->bge_link &&
3599 (!(mii->mii_media_status & IFM_ACTIVE) ||
3600 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3601 sc->bge_link = 0;
3602 if (bootverbose)
3603 if_printf(ifp, "link DOWN\n");
3604 }
3605
3606 /* Clear the interrupt. */
3607 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3608 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3609 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3610 }
3611
3612 static void
3613 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3614 {
3615 struct ifnet *ifp = &sc->arpcom.ac_if;
3616
3617 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3618
3619 /*
3620 * Sometimes PCS encoding errors are detected in
3621 * TBI mode (on fiber NICs), and for some reason
3622 * the chip will signal them as link changes.
3623 * If we get a link change event, but the 'PCS
3624 * encoding error' bit in the MAC status register
3625 * is set, don't bother doing a link check.
3626 * This avoids spurious "gigabit link up" messages
3627 * that sometimes appear on fiber NICs during
3628 * periods of heavy traffic.
3629 */
3630 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3631 if (!sc->bge_link) {
3632 sc->bge_link++;
3633 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3634 BGE_CLRBIT(sc, BGE_MAC_MODE,
3635 BGE_MACMODE_TBI_SEND_CFGS);
3636 }
3637 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3638
3639 if (bootverbose)
3640 if_printf(ifp, "link UP\n");
3641
3642 ifp->if_link_state = LINK_STATE_UP;
3643 if_link_state_change(ifp);
3644 }
3645 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3646 if (sc->bge_link) {
3647 sc->bge_link = 0;
3648
3649 if (bootverbose)
3650 if_printf(ifp, "link DOWN\n");
3651
3652 ifp->if_link_state = LINK_STATE_DOWN;
3653 if_link_state_change(ifp);
3654 }
3655 }
3656
3657 #undef PCS_ENCODE_ERR
3658
3659 /* Clear the attention. */
3660 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3661 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3662 BGE_MACSTAT_LINK_CHANGED);
3663 }
3664
3665 static void
3666 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3667 {
3668 /*
3669 * Check that the AUTOPOLL bit is set before
3670 * processing the event as a real link change.
3671 * Turning AUTOPOLL on and off in the MII read/write
3672 * functions will often trigger a link status
3673 * interrupt for no reason.
3674 */
3675 if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3676 struct ifnet *ifp = &sc->arpcom.ac_if;
3677 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3678
3679 mii_pollstat(mii);
3680
3681 if (!sc->bge_link &&
3682 (mii->mii_media_status & IFM_ACTIVE) &&
3683 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3684 sc->bge_link++;
3685 if (bootverbose)
3686 if_printf(ifp, "link UP\n");
3687 } else if (sc->bge_link &&
3688 (!(mii->mii_media_status & IFM_ACTIVE) ||
3689 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3690 sc->bge_link = 0;
3691 if (bootverbose)
3692 if_printf(ifp, "link DOWN\n");
3693 }
3694 }
3695
3696 /* Clear the attention. */
3697 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3698 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3699 BGE_MACSTAT_LINK_CHANGED);
3700 }
3701
3702 static int
3703 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3704 {
3705 struct bge_softc *sc = arg1;
3706
3707 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3708 &sc->bge_rx_coal_ticks,
3709 BGE_RX_COAL_TICKS_CHG);
3710 }
3711
3712 static int
3713 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3714 {
3715 struct bge_softc *sc = arg1;
3716
3717 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3718 &sc->bge_tx_coal_ticks,
3719 BGE_TX_COAL_TICKS_CHG);
3720 }
3721
3722 static int
3723 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3724 {
3725 struct bge_softc *sc = arg1;
3726
3727 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3728 &sc->bge_rx_max_coal_bds,
3729 BGE_RX_MAX_COAL_BDS_CHG);
3730 }
3731
3732 static int
3733 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3734 {
3735 struct bge_softc *sc = arg1;
3736
3737 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3738 &sc->bge_tx_max_coal_bds,
3739 BGE_TX_MAX_COAL_BDS_CHG);
3740 }
3741
3742 static int
3743 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3744 uint32_t coal_chg_mask)
3745 {
3746 struct bge_softc *sc = arg1;
3747 struct ifnet *ifp = &sc->arpcom.ac_if;
3748 int error = 0, v;
3749
3750 lwkt_serialize_enter(ifp->if_serializer);
3751
3752 v = *coal;
3753 error = sysctl_handle_int(oidp, &v, 0, req);
3754 if (!error && req->newptr != NULL) {
3755 if (v < 0) {
3756 error = EINVAL;
3757 } else {
3758 *coal = v;
3759 sc->bge_coal_chg |= coal_chg_mask;
3760 }
3761 }
3762
3763 lwkt_serialize_exit(ifp->if_serializer);
3764 return error;
3765 }
3766
3767 static void
3768 bge_coal_change(struct bge_softc *sc)
3769 {
3770 struct ifnet *ifp = &sc->arpcom.ac_if;
3771 uint32_t val;
3772
3773 ASSERT_SERIALIZED(ifp->if_serializer);
3774
3775 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3776 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3777 sc->bge_rx_coal_ticks);
3778 DELAY(10);
3779 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3780
3781 if (bootverbose) {
3782 if_printf(ifp, "rx_coal_ticks -> %u\n",
3783 sc->bge_rx_coal_ticks);
3784 }
3785 }
3786
3787 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3788 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3789 sc->bge_tx_coal_ticks);
3790 DELAY(10);
3791 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3792
3793 if (bootverbose) {
3794 if_printf(ifp, "tx_coal_ticks -> %u\n",
3795 sc->bge_tx_coal_ticks);
3796 }
3797 }
3798
3799 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3800 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3801 sc->bge_rx_max_coal_bds);
3802 DELAY(10);
3803 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3804
3805 if (bootverbose) {
3806 if_printf(ifp, "rx_max_coal_bds -> %u\n",
3807 sc->bge_rx_max_coal_bds);
3808 }
3809 }
3810
3811 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3812 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3813 sc->bge_tx_max_coal_bds);
3814 DELAY(10);
3815 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3816
3817 if (bootverbose) {
3818 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3819 sc->bge_tx_max_coal_bds);
3820 }
3821 }
3822
3823 sc->bge_coal_chg = 0;
3824 }
3825
3826 static void
3827 bge_enable_intr(struct bge_softc *sc)
3828 {
3829 struct ifnet *ifp = &sc->arpcom.ac_if;
3830
3831 lwkt_serialize_handler_enable(ifp->if_serializer);
3832
3833 /*
3834 * Enable interrupt.
3835 */
3836 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3837
3838 /*
3839 * Unmask the interrupt when we stop polling.
3840 */
3841 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3842
3843 /*
3844 * Trigger another interrupt, since above writing
3845 * to interrupt mailbox0 may acknowledge pending
3846 * interrupt.
3847 */
3848 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3849 }
3850
3851 static void
3852 bge_disable_intr(struct bge_softc *sc)
3853 {
3854 struct ifnet *ifp = &sc->arpcom.ac_if;
3855
3856 /*
3857 * Mask the interrupt when we start polling.
3858 */
3859 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3860
3861 /*
3862 * Acknowledge possible asserted interrupt.
3863 */
3864 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3865
3866 lwkt_serialize_handler_disable(ifp->if_serializer);
3867 }
DragonFly BSD