sys/dev/netif/ep/if_epreg.h

   1 /*
   2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: 1. Redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer. 2. The name
   8  * of the author may not be used to endorse or promote products derived from
   9  * this software without specific prior written permission
  10  *
  11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
  14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  *
  22  * $FreeBSD: src/sys/dev/ep/if_epreg.h,v 1.29 2000/01/12 06:42:49 mdodd Exp $
  23  * $DragonFly: src/sys/dev/netif/ep/if_epreg.h,v 1.2 2003/06/17 04:28:25 dillon Exp $
  24  */
  25
  26 /*
  27  * DELAY_MULTIPLE: How much to boost "base" delays, except
  28  * for the inter-bit delays in get_eeprom_data.  A cyrix Media GX needed this.
  29  */
  30 #define DELAY_MULTIPLE 10
  31 #define BIT_DELAY_MULTIPLE 10
  32
  33 /*
  34  * Some global constants
  35  */
  36 #define TX_INIT_RATE         16
  37 #define TX_INIT_MAX_RATE     64
  38 #define RX_INIT_LATENCY      64
  39 #define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
  40 #define RX_NEXT_EARLY_THRESH 500
  41
  42 #define EEPROMSIZE      0x40
  43 #define MAX_EEPROMBUSY  1000
  44 #define EP_LAST_TAG     0xd7
  45 #define EP_MAX_BOARDS   16
  46 /*
  47  * This `ID' port is a mere hack.  There's currently no chance to register
  48  * it with config's idea of the ports that are in use.
  49  *
  50  * "After the automatic configuration is completed, the IDS is in its initial
  51  * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
  52  * 'x' is any hex digit.  If a zero is written to any one of these ports, then
  53  * that address is remembered and becomes the ID port.  A second zero written
  54  * to that port resets the ID sequence to its initial state.  The IDS watches
  55  * for the ID sequence to be written to the ID port."
  56  *
  57  * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
  58  * ports.
  59  */
  60 #define EP_ID_PORT      0x110
  61 #define EP_IOSIZE       16      /* 16 bytes of I/O space used. */
  62
  63 /*
  64  * some macros to acces long named fields
  65  */
  66 #define BASE    (sc->ep_io_addr)
  67
  68 /*
  69  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
  70  * Offset 0xa)
  71  */
  72 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
  73 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
  74 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
  75 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
  76
  77 #define EEPROM_BUSY             (1<<15)
  78 #define EEPROM_TST_MODE         (1<<14)
  79
  80 /*
  81  * Some short functions, worth to let them be a macro
  82  */
  83 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
  84 #define GO_WINDOW(x)      outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
  85
  86 /**************************************************************************
  87  *                                                                        *
  88  * These define the EEPROM data structure.  They are used in the probe
  89  * function to verify the existence of the adapter after having sent
  90  * the ID_Sequence.
  91  *
  92  **************************************************************************/
  93
  94 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
  95 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
  96 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
  97 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
  98 #define EEPROM_MFG_DATE         0x4     /* Manufacturing date */
  99 #define EEPROM_MFG_DIVSION      0x5     /* Manufacturing division */
 100 #define EEPROM_MFG_PRODUCT      0x6     /* Product code */
 101 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
 102 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
 103 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
 104 #define EEPROM_OEM_ADDR0        0xa
 105 #define EEPROM_OEM_ADDR1        0xb
 106 #define EEPROM_OEM_ADDR2        0xc
 107 #define EEPROM_SOFTINFO         0xd
 108 #define EEPROM_COMPAT           0xe
 109 #define EEPROM_SOFTINFO2        0xf
 110 #define EEPROM_CAP              0x10
 111 # define CAP_ISA                0x2083
 112 # define CAP_PCMCIA             0x2082
 113 #define EEPROM_INT_CONFIG_0     0x12
 114 #define EEPROM_INT_CONFIG_1     0x13
 115 /* RAM Partition TX FIFO/RX FIFO */
 116 # define ICW1_RAM_PART_MASK     0x03
 117 # define ICW1_RAM_PART_35       0x00    /* 2:5 (only legal if RAM size == 000b default power-up/reset */
 118 # define ICW1_RAM_PART_13       0x01    /* 1:3 (only legal if RAM size == 000b) */
 119 # define ICW1_RAM_PART_11       0x10    /* 1:1          */
 120 # define ICW1_RAM_PART_RESV     0x11    /* Reserved     */
 121 /* ISA Adapter Selection */
 122 # define ICW1_IAS_MASK          0x0c
 123 # define ICW1_IAS_DIS           0x00    /* Both mechanisms disabled (default) */
 124 # define ICW1_IAS_ISA           0x04    /* ISA contention only */
 125 # define ICW1_IAS_PNP           0x08    /* ISA Plug and Play only */
 126 # define ICW1_IAS_BOTH          0x0c    /* Both mechanisms enabled */
 127
 128 #define EEPROM_CHECKSUM_EL3     0x17
 129
 130 /**************************************************************************
 131  *                                                                                *
 132  * These are the registers for the 3Com 3c509 and their bit patterns when *
 133  * applicable.  They have been taken out the the "EtherLink III Parallel  *
 134  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
 135  * from 3com.                                                             *
 136  *                                                                                *
 137  **************************************************************************/
 138
 139 #define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a
 140                                          * command reg. */
 141 #define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status
 142                                          * reg. */
 143 #define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window
 144                                          * reg. */
 145 /*
 146  * Window 0 registers. Setup.
 147  */
 148 /* Write */
 149 #define EP_W0_EEPROM_DATA       0x0c
 150 #define EP_W0_EEPROM_COMMAND    0x0a
 151 #define EP_W0_RESOURCE_CFG      0x08
 152 #define EP_W0_ADDRESS_CFG       0x06
 153 #define EP_W0_CONFIG_CTRL       0x04
 154 /* Read */
 155 #define EP_W0_PRODUCT_ID        0x02
 156 #define EP_W0_MFG_ID            0x00
 157
 158 /*
 159  * Window 1 registers. Operating Set.
 160  */
 161 /* Write */
 162 #define EP_W1_TX_PIO_WR_2       0x02
 163 #define EP_W1_TX_PIO_WR_1       0x00
 164 /* Read */
 165 #define EP_W1_FREE_TX           0x0c
 166 #define EP_W1_TX_STATUS         0x0b    /* byte */
 167 #define EP_W1_TIMER             0x0a    /* byte */
 168 #define EP_W1_RX_STATUS         0x08
 169 #define EP_W1_RX_PIO_RD_2       0x02
 170 #define EP_W1_RX_PIO_RD_1       0x00
 171
 172 /*
 173  * Window 2 registers. Station Address Setup/Read
 174  */
 175 /* Read/Write */
 176 #define EP_W2_ADDR_5            0x05
 177 #define EP_W2_ADDR_4            0x04
 178 #define EP_W2_ADDR_3            0x03
 179 #define EP_W2_ADDR_2            0x02
 180 #define EP_W2_ADDR_1            0x01
 181 #define EP_W2_ADDR_0            0x00
 182
 183 /*
 184  * Window 3 registers.  FIFO Management.
 185  */
 186 /* Read */
 187 #define EP_W3_FREE_TX           0x0c
 188 #define EP_W3_FREE_RX           0x0a
 189 #define EP_W3_OPTIONS           0x08
 190
 191 /*
 192  * Window 4 registers. Diagnostics.
 193  */
 194 /* Read/Write */
 195 #define EP_W4_MEDIA_TYPE        0x0a
 196 #define EP_W4_CTRLR_STATUS      0x08
 197 #define EP_W4_NET_DIAG          0x06
 198 #define EP_W4_FIFO_DIAG         0x04
 199 #define EP_W4_HOST_DIAG         0x02
 200 #define EP_W4_TX_DIAG           0x00
 201
 202 /*
 203  * Window 5 Registers.  Results and Internal status.
 204  */
 205 /* Read */
 206 #define EP_W5_READ_0_MASK       0x0c
 207 #define EP_W5_INTR_MASK         0x0a
 208 #define EP_W5_RX_FILTER         0x08
 209 #define EP_W5_RX_EARLY_THRESH   0x06
 210 #define EP_W5_TX_AVAIL_THRESH   0x02
 211 #define EP_W5_TX_START_THRESH   0x00
 212
 213 /*
 214  * Window 6 registers. Statistics.
 215  */
 216 /* Read/Write */
 217 #define TX_TOTAL_OK             0x0c
 218 #define RX_TOTAL_OK             0x0a
 219 #define TX_DEFERRALS            0x08
 220 #define RX_FRAMES_OK            0x07
 221 #define TX_FRAMES_OK            0x06
 222 #define RX_OVERRUNS             0x05
 223 #define TX_COLLISIONS           0x04
 224 #define TX_AFTER_1_COLLISION    0x03
 225 #define TX_AFTER_X_COLLISIONS   0x02
 226 #define TX_NO_SQE               0x01
 227 #define TX_CD_LOST              0x00
 228
 229 /****************************************
 230  *
 231  * Register definitions.
 232  *
 233  ****************************************/
 234
 235 /*
 236  * Command parameter that disables threshold interrupts
 237  *   PIO (3c509) cards use 2044.  The fifo word-oriented and 2044--2047 work.
 238  *  "busmastering" cards need 8188.
 239  * The implicit two-bit upshift done by busmastering cards means
 240  * a value of 2047 disables threshold interrupts on both.
 241  */
 242 #define EP_THRESH_DISABLE    2047
 243
 244 /*
 245  * Command register. All windows.
 246  *
 247  * 16 bit register.
 248  *     15-11:  5-bit code for command to be executed.
 249  *     10-0:   11-bit arg if any. For commands with no args;
 250  *            this can be set to anything.
 251  */
 252 #define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
 253                                                          * after issuing */
 254 #define WINDOW_SELECT           (u_short) (0x1<<11)
 255 #define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
 256                                                          * determine whether
 257                                                          * this is needed. If
 258                                                          * so; wait 800 uSec
 259                                                          * before using trans-
 260                                                          * ceiver. */
 261 #define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
 262                                                          * power-up */
 263 #define RX_ENABLE               (u_short) (0x4<<11)
 264 #define RX_RESET                (u_short) (0x5<<11)
 265 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
 266 #define TX_ENABLE               (u_short) (0x9<<11)
 267 #define TX_DISABLE              (u_short) (0xa<<11)
 268 #define TX_RESET                (u_short) (0xb<<11)
 269 #define REQ_INTR                (u_short) (0xc<<11)
 270 #define SET_INTR_MASK           (u_short) (0xe<<11)
 271 #define SET_RD_0_MASK           (u_short) (0xf<<11)
 272 #define SET_RX_FILTER           (u_short) (0x10<<11)
 273 #define FIL_INDIVIDUAL          (u_short) (0x1)
 274 #define FIL_GROUP               (u_short) (0x2)
 275 #define FIL_BRDCST              (u_short) (0x4)
 276 #define FIL_ALL                 (u_short) (0x8)
 277 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
 278 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
 279 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
 280 #define STATS_ENABLE            (u_short) (0x15<<11)
 281 #define STATS_DISABLE           (u_short) (0x16<<11)
 282 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
 283 /*
 284  * The following C_* acknowledge the various interrupts. Some of them don't
 285  * do anything.  See the manual.
 286  */
 287 #define ACK_INTR                (u_short) (0x6800)
 288 #define C_INTR_LATCH    (u_short) (ACK_INTR|0x1)
 289 #define C_CARD_FAILURE  (u_short) (ACK_INTR|0x2)
 290 #define C_TX_COMPLETE   (u_short) (ACK_INTR|0x4)
 291 #define C_TX_AVAIL      (u_short) (ACK_INTR|0x8)
 292 #define C_RX_COMPLETE   (u_short) (ACK_INTR|0x10)
 293 #define C_RX_EARLY      (u_short) (ACK_INTR|0x20)
 294 #define C_INT_RQD               (u_short) (ACK_INTR|0x40)
 295 #define C_UPD_STATS     (u_short) (ACK_INTR|0x80)
 296 #define C_MASK  (u_short) 0xFF /* mask of C_* */
 297
 298 /*
 299  * Status register. All windows.
 300  *
 301  *     15-13:  Window number(0-7).
 302  *     12:     Command_in_progress.
 303  *     11:     reserved.
 304  *     10:     reserved.
 305  *     9:      reserved.
 306  *     8:      reserved.
 307  *     7:      Update Statistics.
 308  *     6:      Interrupt Requested.
 309  *     5:      RX Early.
 310  *     4:      RX Complete.
 311  *     3:      TX Available.
 312  *     2:      TX Complete.
 313  *     1:      Adapter Failure.
 314  *     0:      Interrupt Latch.
 315  */
 316 #define S_INTR_LATCH            (u_short) (0x1)
 317 #define S_CARD_FAILURE          (u_short) (0x2)
 318 #define S_TX_COMPLETE           (u_short) (0x4)
 319 #define S_TX_AVAIL              (u_short) (0x8)
 320 #define S_RX_COMPLETE           (u_short) (0x10)
 321 #define S_RX_EARLY              (u_short) (0x20)
 322 #define S_INT_RQD               (u_short) (0x40)
 323 #define S_UPD_STATS             (u_short) (0x80)
 324 #define S_MASK  (u_short) 0xFF /* mask of S_* */
 325 #define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
 326                                  S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
 327 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
 328
 329 /* Address Config. Register.
 330  * Window 0/Port 06
 331  */
 332
 333 #define ACF_CONNECTOR_BITS      14
 334 #define ACF_CONNECTOR_UTP       0
 335 #define ACF_CONNECTOR_AUI       1
 336 #define ACF_CONNECTOR_BNC       3
 337
 338 /* Resource configuration register.
 339  * Window 0/Port 08
 340  *
 341  */
 342
 343 #define SET_IRQ(base,irq)     outw((base) + EP_W0_RESOURCE_CFG, \
 344                               ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
 345                               ((u_short)(irq)<<12))  ) /* set IRQ i */
 346
 347 /*
 348  * FIFO Registers.
 349  * RX Status. Window 1/Port 08
 350  *
 351  *     15:     Incomplete or FIFO empty.
 352  *     14:     1: Error in RX Packet   0: Incomplete or no error.
 353  *     13-11:  Type of error.
 354  *            1000 = Overrun.
 355  *            1011 = Run Packet Error.
 356  *            1100 = Alignment Error.
 357  *            1101 = CRC Error.
 358  *            1001 = Oversize Packet Error (>1514 bytes)
 359  *            0010 = Dribble Bits.
 360  *            (all other error codes, no errors.)
 361  *
 362  *     10-0:   RX Bytes (0-1514)
 363  */
 364 #define ERR_RX_INCOMPLETE  (u_short) (0x1<<15)
 365 #define ERR_RX             (u_short) (0x1<<14)
 366 #define ERR_RX_OVERRUN     (u_short) (0x8<<11)
 367 #define ERR_RX_RUN_PKT     (u_short) (0xb<<11)
 368 #define ERR_RX_ALIGN       (u_short) (0xc<<11)
 369 #define ERR_RX_CRC         (u_short) (0xd<<11)
 370 #define ERR_RX_OVERSIZE    (u_short) (0x9<<11)
 371 #define ERR_RX_DRIBBLE     (u_short) (0x2<<11)
 372
 373 /*
 374  * FIFO Registers.
 375  * TX Status. Window 1/Port 0B
 376  *
 377  *   Reports the transmit status of a completed transmission. Writing this
 378  *   register pops the transmit completion stack.
 379  *
 380  *   Window 1/Port 0x0b.
 381  *
 382  *     7:      Complete
 383  *     6:      Interrupt on successful transmission requested.
 384  *     5:      Jabber Error (TP Only, TX Reset required. )
 385  *     4:      Underrun (TX Reset required. )
 386  *     3:      Maximum Collisions.
 387  *     2:      TX Status Overflow.
 388  *     1-0:    Undefined.
 389  *
 390  */
 391 #define TXS_COMPLETE            0x80
 392 #define TXS_SUCCES_INTR_REQ             0x40
 393 #define TXS_JABBER              0x20
 394 #define TXS_UNDERRUN            0x10
 395 #define TXS_MAX_COLLISION       0x8
 396 #define TXS_STATUS_OVERFLOW     0x4
 397
 398 /*
 399  * Configuration control register.
 400  * Window 0/Port 04
 401  */
 402 /* Read */
 403 #define IS_AUI                          (1<<13)
 404 #define IS_BNC                          (1<<12)
 405 #define IS_UTP                          (1<<9)
 406 /* Write */
 407 #define ENABLE_DRQ_IRQ                  0x0001
 408 #define W0_P4_CMD_RESET_ADAPTER       0x4
 409 #define W0_P4_CMD_ENABLE_ADAPTER      0x1
 410 /*
 411  * Media type and status.
 412  * Window 4/Port 0A
 413  */
 414 #define ENABLE_UTP                      0xc0
 415 #define DISABLE_UTP                     0x0
 416
 417 /*
 418  * Misc defines for various things.
 419  */
 420 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff /* to the id_port */
 421 #define MFG_ID                          0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
 422 #define PROD_ID                         0x9150
 423
 424 #define AUI                             0x1
 425 #define BNC                             0x2
 426 #define UTP                             0x4
 427
 428 #define RX_BYTES_MASK                   (u_short) (0x07ff)
 429
 430 /*
 431  * Config flags
 432  */
 433 #define EP_FLAGS_100TX                  0x1