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10Base-TX -> 10Base-T and 1000Base-TX -> 1000Base-T. Although 1000Base-TX
[dragonfly.git] / sys / dev / netif / ar / if_ar.c
bloba633a83915063ab9d99b97aeff10c825a3d55574
1 /*-
2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.66 2005/01/06 01:42:28 imp Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.23 2008/01/06 16:55:50 swildner Exp $
30 */
31
32 /*
33 * Programming assumptions and other issues.
34 *
35 * The descriptors of a DMA channel will fit in a 16K memory window.
36 *
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
38 *
39 * Only the ISA bus cards with X.21 and V.35 is tested.
40 *
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
43 *
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
46 */
47
48 #include "opt_netgraph.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/mbuf.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
58 #include <sys/bus.h>
59 #include <sys/serialize.h>
60 #include <sys/rman.h>
61 #include <sys/thread2.h>
62
63 #include <net/if.h>
64 #ifdef NETGRAPH
65 #include <netgraph/ng_message.h>
66 #include <netgraph/netgraph.h>
67 #include <sys/syslog.h>
68 #include <dev/netif/ar/if_ar.h>
69 #else /* NETGRAPH */
70 #include <net/sppp/if_sppp.h>
71 #include <net/bpf.h>
72 #endif /* NETGRAPH */
73
74 #include <machine/md_var.h>
75
76 #include <dev/netif/ic_layer/hd64570.h>
77 #include <dev/netif/ar/if_arregs.h>
78
79 #ifdef TRACE
80 #define TRC(x) x
81 #else
82 #define TRC(x)
83 #endif
84
85 #define TRCL(x) x
86
87 #define PPP_HEADER_LEN 4
88
89 devclass_t ar_devclass;
90
91 struct ar_softc {
92 #ifndef NETGRAPH
93 struct sppp ifsppp;
94 #endif /* NETGRAPH */
95 int unit; /* With regards to all ar devices */
96 int subunit; /* With regards to this card */
97 struct ar_hardc *hc;
98
99 struct buf_block {
100 u_int txdesc; /* On card address */
101 u_int txstart; /* On card address */
102 u_int txend; /* On card address */
103 u_int txtail; /* Index of first unused buffer */
104 u_int txmax; /* number of usable buffers/descriptors */
105 u_int txeda; /* Error descriptor addresses */
106 }block[AR_TX_BLOCKS];
107
108 char xmit_busy; /* Transmitter is busy */
109 char txb_inuse; /* Number of tx blocks currently in use */
110 u_char txb_new; /* Index to where new buffer will be added */
111 u_char txb_next_tx; /* Index to next block ready to tx */
112
113 u_int rxdesc; /* On card address */
114 u_int rxstart; /* On card address */
115 u_int rxend; /* On card address */
116 u_int rxhind; /* Index to the head of the rx buffers. */
117 u_int rxmax; /* number of usable buffers/descriptors */
118
119 int scano;
120 int scachan;
121 sca_regs *sca;
122 #ifdef NETGRAPH
123 int running; /* something is attached so we are running */
124 int dcd; /* do we have dcd? */
125 /* ---netgraph bits --- */
126 char nodename[NG_NODESIZ]; /* store our node name */
127 int datahooks; /* number of data hooks attached */
128 node_p node; /* netgraph node */
129 hook_p hook; /* data hook */
130 hook_p debug_hook;
131 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
132 struct ifqueue xmitq; /* transmit queue */
133 int flags; /* state */
134 #define SCF_RUNNING 0x01 /* board is active */
135 #define SCF_OACTIVE 0x02 /* output is active */
136 int out_dog; /* watchdog cycles output count-down */
137 struct callout timer; /* watchdog timer */
138 u_long inbytes, outbytes; /* stats */
139 u_long lastinbytes, lastoutbytes; /* a second ago */
140 u_long inrate, outrate; /* highest rate seen */
141 u_long inlast; /* last input N secs ago */
142 u_long out_deficit; /* output since last input */
143 u_long oerrors, ierrors[6];
144 u_long opackets, ipackets;
145 #endif /* NETGRAPH */
146 };
147
148 static int next_ar_unit = 0;
149 static struct lwkt_serialize ar_serializer;
150
151 #ifdef NETGRAPH
152 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
153 #define QUITE_A_WHILE 300 /* 5 MINUTES */
154 #define LOTS_OF_PACKETS 100
155 #endif /* NETGRAPH */
156
157 /*
158 * This translate from irq numbers to
159 * the value that the arnet card needs
160 * in the lower part of the AR_INT_SEL
161 * register.
162 */
163 static int irqtable[16] = {
164 0, /* 0 */
165 0, /* 1 */
166 0, /* 2 */
167 1, /* 3 */
168 0, /* 4 */
169 2, /* 5 */
170 0, /* 6 */
171 3, /* 7 */
172 0, /* 8 */
173 0, /* 9 */
174 4, /* 10 */
175 5, /* 11 */
176 6, /* 12 */
177 0, /* 13 */
178 0, /* 14 */
179 7 /* 15 */
180 };
181
182 #ifndef NETGRAPH
183 DECLARE_DUMMY_MODULE(if_ar);
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
185 #else
186 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
187 #endif
188
189 static void arintr(void *arg);
190 static void ar_xmit(struct ar_softc *sc);
191 #ifndef NETGRAPH
192 static void arstart(struct ifnet *ifp);
193 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *);
194 static void arwatchdog(struct ifnet *ifp);
195 #else /* NETGRAPH */
196 static void arstart(struct ar_softc *sc);
197 static void arwatchdog(struct ar_softc *sc);
198 #endif /* NETGRAPH */
199 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
200 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
201 static void ar_eat_packet(struct ar_softc *sc, int single);
202 static void ar_get_packets(struct ar_softc *sc);
203
204 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
205 static void ar_up(struct ar_softc *sc);
206 static void ar_down(struct ar_softc *sc);
207 static void arc_init(struct ar_hardc *hc);
208 static void ar_init_sca(struct ar_hardc *hc, int scano);
209 static void ar_init_msci(struct ar_softc *sc);
210 static void ar_init_rx_dmac(struct ar_softc *sc);
211 static void ar_init_tx_dmac(struct ar_softc *sc);
212 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
213 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
214 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
215
216 #ifdef NETGRAPH
217 static void ngar_watchdog_frame(void * arg);
218 static void ngar_init(void* ignored);
219
220 static ng_constructor_t ngar_constructor;
221 static ng_rcvmsg_t ngar_rcvmsg;
222 static ng_shutdown_t ngar_shutdown;
223 static ng_newhook_t ngar_newhook;
224 /*static ng_findhook_t ngar_findhook; */
225 static ng_connect_t ngar_connect;
226 static ng_rcvdata_t ngar_rcvdata;
227 static ng_disconnect_t ngar_disconnect;
228
229 static struct ng_type typestruct = {
230 NG_VERSION,
231 NG_AR_NODE_TYPE,
232 NULL,
233 ngar_constructor,
234 ngar_rcvmsg,
235 ngar_shutdown,
236 ngar_newhook,
237 NULL,
238 ngar_connect,
239 ngar_rcvdata,
240 ngar_rcvdata,
241 ngar_disconnect,
242 NULL
243 };
244
245 static int ngar_done_init = 0;
246 #endif /* NETGRAPH */
247
248 int
249 ar_attach(device_t device)
250 {
251 struct ar_hardc *hc;
252 struct ar_softc *sc;
253 #ifndef NETGRAPH
254 struct ifnet *ifp;
255 char *iface;
256 #endif /* NETGRAPH */
257 int unit;
258 int error;
259
260 hc = (struct ar_hardc *)device_get_softc(device);
261 lwkt_serialize_init(&ar_serializer);
262
263 kprintf("arc%d: %uK RAM, %u ports, rev %u.\n",
264 hc->cunit,
265 hc->memsize/1024,
266 hc->numports,
267 hc->revision);
268
269 arc_init(hc);
270
271 error = BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
272 0, arintr, hc,
273 &hc->intr_cookie, &ar_serializer);
274 if (error)
275 return (1);
276
277 sc = hc->sc;
278
279 for(unit=0;unit<hc->numports;unit+=NCHAN)
280 ar_init_sca(hc, unit / NCHAN);
281
282 /*
283 * Now configure each port on the card.
284 */
285 for(unit=0;unit<hc->numports;sc++,unit++) {
286 sc->hc = hc;
287 sc->subunit = unit;
288 sc->unit = next_ar_unit;
289 next_ar_unit++;
290 sc->scano = unit / NCHAN;
291 sc->scachan = unit%NCHAN;
292
293 ar_init_rx_dmac(sc);
294 ar_init_tx_dmac(sc);
295 ar_init_msci(sc);
296
297 #ifndef NETGRAPH
298 ifp = &sc->ifsppp.pp_if;
299
300 ifp->if_softc = sc;
301 if_initname(ifp, device_get_name(device), sc->unit);
302 ifp->if_mtu = PP_MTU;
303 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
304 ifp->if_ioctl = arioctl;
305 ifp->if_start = arstart;
306 ifp->if_watchdog = arwatchdog;
307
308 sc->ifsppp.pp_flags = PP_KEEPALIVE;
309
310 switch(hc->interface[unit]) {
311 default: iface = "UNKNOWN"; break;
312 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
313 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
314 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
315 case AR_IFACE_X_21: iface = "X.21"; break;
316 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
317 }
318
319 kprintf("ar%d: Adapter %d, port %d, interface %s.\n",
320 sc->unit,
321 hc->cunit,
322 sc->subunit,
323 iface);
324
325 sppp_attach((struct ifnet *)&sc->ifsppp);
326 if_attach(ifp, &ar_serializer);
327
328 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
329 #else /* NETGRAPH */
330 /*
331 * we have found a node, make sure our 'type' is availabe.
332 */
333 if (ngar_done_init == 0) ngar_init(NULL);
334 if (ng_make_node_common(&typestruct, &sc->node) != 0)
335 return (1);
336 ksprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
337 if (ng_name_node(sc->node, sc->nodename)) {
338 NG_NODE_UNREF(sc->node); /* drop it again */
339 return (1);
340 }
341 NG_NODE_SET_PRIVATE(sc->node, sc);
342 callout_init(&sc->timer);
343 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
344 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
345 sc->running = 0;
346 #endif /* NETGRAPH */
347 }
348
349 if(hc->bustype == AR_BUS_ISA)
350 ARC_SET_OFF(hc);
351
352 return (0);
353 }
354
355 int
356 ar_detach(device_t device)
357 {
358 device_t parent = device_get_parent(device);
359 struct ar_hardc *hc = device_get_softc(device);
360 int error;
361
362 lwkt_serialize_enter(&ar_serializer);
363
364 if (hc->intr_cookie != NULL) {
365 if (BUS_TEARDOWN_INTR(parent, device,
366 hc->res_irq, hc->intr_cookie) != 0) {
367 kprintf("intr teardown failed.. continuing\n");
368 }
369 hc->intr_cookie = NULL;
370 }
371
372 /*
373 * deallocate any system resources we may have
374 * allocated on behalf of this driver.
375 */
376 FREE(hc->sc, M_DEVBUF);
377 hc->sc = NULL;
378 hc->mem_start = NULL;
379 error = ar_deallocate_resources(device);
380 lwkt_serialize_exit(&ar_serializer);
381
382 return (error);
383 }
384
385 int
386 ar_allocate_ioport(device_t device, int rid, u_long size)
387 {
388 struct ar_hardc *hc = device_get_softc(device);
389
390 hc->rid_ioport = rid;
391 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
392 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
393 if (hc->res_ioport == NULL) {
394 goto errexit;
395 }
396 hc->bt = rman_get_bustag(hc->res_ioport);
397 hc->bh = rman_get_bushandle(hc->res_ioport);
398
399 return (0);
400
401 errexit:
402 ar_deallocate_resources(device);
403 return (ENXIO);
404 }
405
406 int
407 ar_allocate_irq(device_t device, int rid, u_long size)
408 {
409 struct ar_hardc *hc = device_get_softc(device);
410
411 hc->rid_irq = rid;
412 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
413 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
414 if (hc->res_irq == NULL) {
415 goto errexit;
416 }
417 return (0);
418
419 errexit:
420 ar_deallocate_resources(device);
421 return (ENXIO);
422 }
423
424 int
425 ar_allocate_memory(device_t device, int rid, u_long size)
426 {
427 struct ar_hardc *hc = device_get_softc(device);
428
429 hc->rid_memory = rid;
430 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
431 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
432 if (hc->res_memory == NULL) {
433 goto errexit;
434 }
435 return (0);
436
437 errexit:
438 ar_deallocate_resources(device);
439 return (ENXIO);
440 }
441
442 int
443 ar_allocate_plx_memory(device_t device, int rid, u_long size)
444 {
445 struct ar_hardc *hc = device_get_softc(device);
446
447 hc->rid_plx_memory = rid;
448 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
449 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
450 if (hc->res_plx_memory == NULL) {
451 goto errexit;
452 }
453 return (0);
454
455 errexit:
456 ar_deallocate_resources(device);
457 return (ENXIO);
458 }
459
460 int
461 ar_deallocate_resources(device_t device)
462 {
463 struct ar_hardc *hc = device_get_softc(device);
464
465 if (hc->res_irq != 0) {
466 bus_deactivate_resource(device, SYS_RES_IRQ,
467 hc->rid_irq, hc->res_irq);
468 bus_release_resource(device, SYS_RES_IRQ,
469 hc->rid_irq, hc->res_irq);
470 hc->res_irq = 0;
471 }
472 if (hc->res_ioport != 0) {
473 bus_deactivate_resource(device, SYS_RES_IOPORT,
474 hc->rid_ioport, hc->res_ioport);
475 bus_release_resource(device, SYS_RES_IOPORT,
476 hc->rid_ioport, hc->res_ioport);
477 hc->res_ioport = 0;
478 }
479 if (hc->res_memory != 0) {
480 bus_deactivate_resource(device, SYS_RES_MEMORY,
481 hc->rid_memory, hc->res_memory);
482 bus_release_resource(device, SYS_RES_MEMORY,
483 hc->rid_memory, hc->res_memory);
484 hc->res_memory = 0;
485 }
486 if (hc->res_plx_memory != 0) {
487 bus_deactivate_resource(device, SYS_RES_MEMORY,
488 hc->rid_plx_memory, hc->res_plx_memory);
489 bus_release_resource(device, SYS_RES_MEMORY,
490 hc->rid_plx_memory, hc->res_plx_memory);
491 hc->res_plx_memory = 0;
492 }
493 return (0);
494 }
495
496 /*
497 * First figure out which SCA gave the interrupt.
498 * Process it.
499 * See if there is other interrupts pending.
500 * Repeat until there is no more interrupts.
501 */
502 static void
503 arintr(void *arg)
504 {
505 struct ar_hardc *hc = (struct ar_hardc *)arg;
506 sca_regs *sca;
507 u_char isr0, isr1, isr2, arisr;
508 int scano;
509
510 /* XXX Use the PCI interrupt score board register later */
511 if(hc->bustype == AR_BUS_PCI)
512 arisr = hc->orbase[AR_ISTAT * 4];
513 else
514 arisr = ar_inb(hc, AR_ISTAT);
515
516 while(arisr & AR_BD_INT) {
517 TRC(kprintf("arisr = %x\n", arisr));
518 if(arisr & AR_INT_0)
519 scano = 0;
520 else if(arisr & AR_INT_1)
521 scano = 1;
522 else {
523 /* XXX Oops this shouldn't happen. */
524 kprintf("arc%d: Interrupted with no interrupt.\n",
525 hc->cunit);
526 return;
527 }
528 sca = hc->sca[scano];
529
530 if(hc->bustype == AR_BUS_ISA)
531 ARC_SET_SCA(hc, scano);
532
533 isr0 = sca->isr0;
534 isr1 = sca->isr1;
535 isr2 = sca->isr2;
536
537 TRC(kprintf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
538 hc->cunit,
539 isr0,
540 isr1,
541 isr2));
542 if(isr0)
543 ar_msci_intr(hc, scano, isr0);
544
545 if(isr1)
546 ar_dmac_intr(hc, scano, isr1);
547
548 if(isr2)
549 ar_timer_intr(hc, scano, isr2);
550
551 /*
552 * Proccess the second sca's interrupt if available.
553 * Else see if there are any new interrupts.
554 */
555 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
556 arisr &= ~AR_INT_0;
557 else {
558 if(hc->bustype == AR_BUS_PCI)
559 arisr = hc->orbase[AR_ISTAT * 4];
560 else
561 arisr = ar_inb(hc, AR_ISTAT);
562 }
563 }
564
565 if(hc->bustype == AR_BUS_ISA)
566 ARC_SET_OFF(hc);
567 }
568
569
570 /*
571 * This will only start the transmitter. It is assumed that the data
572 * is already there. It is normally called from arstart() or ar_dmac_intr().
573 *
574 */
575 static void
576 ar_xmit(struct ar_softc *sc)
577 {
578 #ifndef NETGRAPH
579 struct ifnet *ifp;
580 #endif /* NETGRAPH */
581 dmac_channel *dmac;
582
583 #ifndef NETGRAPH
584 ifp = &sc->ifsppp.pp_if;
585 #endif /* NETGRAPH */
586 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
587
588 if(sc->hc->bustype == AR_BUS_ISA)
589 ARC_SET_SCA(sc->hc, sc->scano);
590 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
591
592 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
593 dmac->dsr = SCA_DSR_DE;
594
595 sc->xmit_busy = 1;
596
597 sc->txb_next_tx++;
598 if(sc->txb_next_tx == AR_TX_BLOCKS)
599 sc->txb_next_tx = 0;
600
601 #ifndef NETGRAPH
602 ifp->if_timer = 2; /* Value in seconds. */
603 #else /* NETGRAPH */
604 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
605 #endif /* NETGRAPH */
606 if(sc->hc->bustype == AR_BUS_ISA)
607 ARC_SET_OFF(sc->hc);
608 }
609
610 /*
611 * This function will be called from the upper level when a user add a
612 * packet to be send, and from the interrupt handler after a finished
613 * transmit.
614 *
615 * This function only place the data in the oncard buffers. It does not
616 * start the transmition. ar_xmit() does that.
617 *
618 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
619 * that clears that should ensure that the transmitter and its DMA is
620 * in a "good" idle state.
621 */
622 #ifndef NETGRAPH
623 static void
624 arstart(struct ifnet *ifp)
625 {
626 struct ar_softc *sc = ifp->if_softc;
627 #else /* NETGRAPH */
628 static void
629 arstart(struct ar_softc *sc)
630 {
631 #endif /* NETGRAPH */
632 int i, len, tlen;
633 struct mbuf *mtx;
634 u_char *txdata;
635 sca_descriptor *txdesc;
636 struct buf_block *blkp;
637
638 #ifndef NETGRAPH
639 if(!(ifp->if_flags & IFF_RUNNING))
640 return;
641 #else /* NETGRAPH */
642 /* XXX */
643 #endif /* NETGRAPH */
644
645 top_arstart:
646
647 /*
648 * See if we have space for more packets.
649 */
650 if(sc->txb_inuse == AR_TX_BLOCKS) {
651 #ifndef NETGRAPH
652 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
653 #else /* NETGRAPH */
654 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
655 #endif /* NETGRAPH */
656 return;
657 }
658
659 #ifndef NETGRAPH
660 mtx = sppp_dequeue(ifp);
661 #else /* NETGRAPH */
662 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
663 if (mtx == NULL) {
664 IF_DEQUEUE(&sc->xmitq, mtx);
665 }
666 #endif /* NETGRAPH */
667 if(!mtx)
668 return;
669
670 /*
671 * It is OK to set the memory window outside the loop because
672 * all tx buffers and descriptors are assumed to be in the same
673 * 16K window.
674 */
675 if(sc->hc->bustype == AR_BUS_ISA)
676 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
677
678 /*
679 * We stay in this loop until there is nothing in the
680 * TX queue left or the tx buffer is full.
681 */
682 i = 0;
683 blkp = &sc->block[sc->txb_new];
684 txdesc = (sca_descriptor *)
685 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
686 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
687 for(;;) {
688 len = mtx->m_pkthdr.len;
689
690 TRC(kprintf("ar%d: ARstart len %u\n", sc->unit, len));
691
692 /*
693 * We can do this because the tx buffers don't wrap.
694 */
695 m_copydata(mtx, 0, len, txdata);
696 tlen = len;
697 while(tlen > AR_BUF_SIZ) {
698 txdesc->stat = 0;
699 txdesc->len = AR_BUF_SIZ;
700 tlen -= AR_BUF_SIZ;
701 txdesc++;
702 txdata += AR_BUF_SIZ;
703 i++;
704 }
705 /* XXX Move into the loop? */
706 txdesc->stat = SCA_DESC_EOM;
707 txdesc->len = tlen;
708 txdesc++;
709 txdata += AR_BUF_SIZ;
710 i++;
711
712 #ifndef NETGRAPH
713 BPF_MTAP(ifp, mtx);
714 m_freem(mtx);
715 ++sc->ifsppp.pp_if.if_opackets;
716 #else /* NETGRAPH */
717 m_freem(mtx);
718 sc->outbytes += len;
719 ++sc->opackets;
720 #endif /* NETGRAPH */
721
722 /*
723 * Check if we have space for another mbuf.
724 * XXX This is hardcoded. A packet won't be larger
725 * than 3 buffers (3 x 512).
726 */
727 if((i + 3) >= blkp->txmax)
728 break;
729
730 #ifndef NETGRAPH
731 mtx = sppp_dequeue(ifp);
732 #else /* NETGRAPH */
733 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
734 if (mtx == NULL) {
735 IF_DEQUEUE(&sc->xmitq, mtx);
736 }
737 #endif /* NETGRAPH */
738 if(!mtx)
739 break;
740 }
741
742 blkp->txtail = i;
743
744 /*
745 * Mark the last descriptor, so that the SCA know where
746 * to stop.
747 */
748 txdesc--;
749 txdesc->stat |= SCA_DESC_EOT;
750
751 txdesc = (sca_descriptor *)blkp->txdesc;
752 blkp->txeda = (u_short)((u_int)&txdesc[i]);
753
754 #if 0
755 kprintf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
756 kprintf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
757 kprintf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
758 kprintf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
759 kprintf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
760 #endif
761
762 sc->txb_inuse++;
763 sc->txb_new++;
764 if(sc->txb_new == AR_TX_BLOCKS)
765 sc->txb_new = 0;
766
767 if(sc->xmit_busy == 0)
768 ar_xmit(sc);
769
770 if(sc->hc->bustype == AR_BUS_ISA)
771 ARC_SET_OFF(sc->hc);
772
773 goto top_arstart;
774 }
775
776 #ifndef NETGRAPH
777 static int
778 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
779 {
780 int error;
781 int was_up, should_be_up;
782 struct ar_softc *sc = ifp->if_softc;
783
784 TRC(if_printf(ifp, "arioctl.\n");)
785
786 was_up = ifp->if_flags & IFF_RUNNING;
787
788 error = sppp_ioctl(ifp, cmd, data);
789 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
790 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
791 if(error)
792 return (error);
793
794 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
795 return (0);
796
797 TRC(if_printf(ifp, "arioctl %s.\n",
798 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
799
800 should_be_up = ifp->if_flags & IFF_RUNNING;
801
802 if(!was_up && should_be_up) {
803 /* Interface should be up -- start it. */
804 ar_up(sc);
805 arstart(ifp);
806 /* XXX Maybe clear the IFF_UP flag so that the link
807 * will only go up after sppp lcp and ipcp negotiation.
808 */
809 } else if(was_up && !should_be_up) {
810 /* Interface should be down -- stop it. */
811 ar_down(sc);
812 sppp_flush(ifp);
813 }
814 return (0);
815 }
816 #endif /* NETGRAPH */
817
818 /*
819 * This is to catch lost tx interrupts.
820 */
821 static void
822 #ifndef NETGRAPH
823 arwatchdog(struct ifnet *ifp)
824 {
825 struct ar_softc *sc = ifp->if_softc;
826 #else /* NETGRAPH */
827 arwatchdog(struct ar_softc *sc)
828 {
829 #endif /* NETGRAPH */
830 msci_channel *msci = &sc->sca->msci[sc->scachan];
831
832 #ifndef NETGRAPH
833 if(!(ifp->if_flags & IFF_RUNNING))
834 return;
835 #endif /* NETGRAPH */
836
837 if(sc->hc->bustype == AR_BUS_ISA)
838 ARC_SET_SCA(sc->hc, sc->scano);
839
840 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
841 kprintf("ar%d: transmit failed, "
842 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
843 sc->unit,
844 msci->st0,
845 msci->st1,
846 msci->st3,
847 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
848
849 if(msci->st1 & SCA_ST1_UDRN) {
850 msci->cmd = SCA_CMD_TXABORT;
851 msci->cmd = SCA_CMD_TXENABLE;
852 msci->st1 = SCA_ST1_UDRN;
853 }
854
855 sc->xmit_busy = 0;
856 #ifndef NETGRAPH
857 ifp->if_flags &= ~IFF_OACTIVE;
858 #else /* NETGRAPH */
859 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
860 #endif /* NETGRAPH */
861
862 if(sc->txb_inuse && --sc->txb_inuse)
863 ar_xmit(sc);
864
865 #ifndef NETGRAPH
866 arstart(ifp);
867 #else /* NETGRAPH */
868 arstart(sc);
869 #endif /* NETGRAPH */
870 }
871
872 static void
873 ar_up(struct ar_softc *sc)
874 {
875 sca_regs *sca;
876 msci_channel *msci;
877
878 sca = sc->sca;
879 msci = &sca->msci[sc->scachan];
880
881 TRC(kprintf("ar%d: sca %p, msci %p, ch %d\n",
882 sc->unit, sca, msci, sc->scachan));
883
884 /*
885 * Enable transmitter and receiver.
886 * Raise DTR and RTS.
887 * Enable interrupts.
888 */
889 if(sc->hc->bustype == AR_BUS_ISA)
890 ARC_SET_SCA(sc->hc, sc->scano);
891
892 /* XXX
893 * What about using AUTO mode in msci->md0 ???
894 * And what about CTS/DCD etc... ?
895 */
896 if(sc->hc->handshake & AR_SHSK_RTS)
897 msci->ctl &= ~SCA_CTL_RTS;
898 if(sc->hc->handshake & AR_SHSK_DTR) {
899 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
900 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
901 if(sc->hc->bustype == AR_BUS_PCI)
902 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
903 sc->hc->txc_dtr[sc->scano];
904 else
905 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
906 sc->hc->txc_dtr[sc->scano]);
907 }
908
909 if(sc->scachan == 0) {
910 sca->ier0 |= 0x0F;
911 sca->ier1 |= 0x0F;
912 } else {
913 sca->ier0 |= 0xF0;
914 sca->ier1 |= 0xF0;
915 }
916
917 msci->cmd = SCA_CMD_RXENABLE;
918 if(sc->hc->bustype == AR_BUS_ISA)
919 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
920 msci->cmd = SCA_CMD_TXENABLE;
921
922 if(sc->hc->bustype == AR_BUS_ISA)
923 ARC_SET_OFF(sc->hc);
924 #ifdef NETGRAPH
925 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
926 sc->running = 1;
927 #endif /* NETGRAPH */
928 }
929
930 static void
931 ar_down(struct ar_softc *sc)
932 {
933 sca_regs *sca;
934 msci_channel *msci;
935
936 sca = sc->sca;
937 msci = &sca->msci[sc->scachan];
938
939 #ifdef NETGRAPH
940 callout_stop(&sc->timer);
941 sc->running = 0;
942 #endif /* NETGRAPH */
943 /*
944 * Disable transmitter and receiver.
945 * Lower DTR and RTS.
946 * Disable interrupts.
947 */
948 if(sc->hc->bustype == AR_BUS_ISA)
949 ARC_SET_SCA(sc->hc, sc->scano);
950 msci->cmd = SCA_CMD_RXDISABLE;
951 if(sc->hc->bustype == AR_BUS_ISA)
952 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
953 msci->cmd = SCA_CMD_TXDISABLE;
954
955 if(sc->hc->handshake & AR_SHSK_RTS)
956 msci->ctl |= SCA_CTL_RTS;
957 if(sc->hc->handshake & AR_SHSK_DTR) {
958 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
959 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
960 if(sc->hc->bustype == AR_BUS_PCI)
961 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
962 sc->hc->txc_dtr[sc->scano];
963 else
964 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
965 sc->hc->txc_dtr[sc->scano]);
966 }
967
968 if(sc->scachan == 0) {
969 sca->ier0 &= ~0x0F;
970 sca->ier1 &= ~0x0F;
971 } else {
972 sca->ier0 &= ~0xF0;
973 sca->ier1 &= ~0xF0;
974 }
975
976 if(sc->hc->bustype == AR_BUS_ISA)
977 ARC_SET_OFF(sc->hc);
978 }
979
980 static int
981 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
982 {
983 int ctype, i, val, x;
984 volatile u_char *pimctrl;
985
986 ctype = 0;
987 val = 0;
988
989 pimctrl = hc->orbase + AR_PIMCTRL;
990
991 /* Reset the PIM */
992 *pimctrl = 0x00;
993 *pimctrl = AR_PIM_STROBE;
994
995 /* Check if there is a PIM */
996 *pimctrl = 0x00;
997 *pimctrl = AR_PIM_READ;
998 x = *pimctrl;
999 TRC(kprintf("x = %x", x));
1000 if(x & AR_PIM_DATA) {
1001 kprintf("No PIM installed\n");
1002 return (AR_IFACE_UNKNOWN);
1003 }
1004
1005 x = (x >> 1) & 0x01;
1006 val |= x << 0;
1007
1008 /* Now read the next 15 bits */
1009 for(i = 1; i < 16; i++) {
1010 *pimctrl = AR_PIM_READ;
1011 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1012 x = *pimctrl;
1013 TRC(kprintf(" %x ", x));
1014 x = (x >> 1) & 0x01;
1015 val |= x << i;
1016 if(i == 8 && (val & 0x000f) == 0x0004) {
1017 int ii;
1018
1019 /* Start bit */
1020 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1021 *pimctrl = AR_PIM_A2D_DOUT;
1022
1023 /* Mode bit */
1024 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1025 *pimctrl = AR_PIM_A2D_DOUT;
1026
1027 /* Sign bit */
1028 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1029 *pimctrl = AR_PIM_A2D_DOUT;
1030
1031 /* Select channel */
1032 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1033 *pimctrl = ((channel & 2) << 2);
1034 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1035 *pimctrl = ((channel & 1) << 3);
1036
1037 *pimctrl = AR_PIM_A2D_STROBE;
1038
1039 x = *pimctrl;
1040 if(x & AR_PIM_DATA)
1041 kprintf("\nOops A2D start bit not zero (%X)\n", x);
1042
1043 for(ii = 7; ii >= 0; ii--) {
1044 *pimctrl = 0x00;
1045 *pimctrl = AR_PIM_A2D_STROBE;
1046 x = *pimctrl;
1047 if(x & AR_PIM_DATA)
1048 ctype |= 1 << ii;
1049 }
1050 }
1051 }
1052 TRC(kprintf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1053 *pimctrl = AR_PIM_MODEG;
1054 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1055 if(ctype > 255)
1056 return (AR_IFACE_UNKNOWN);
1057 if(ctype > 239)
1058 return (AR_IFACE_V_35);
1059 if(ctype > 207)
1060 return (AR_IFACE_EIA_232);
1061 if(ctype > 178)
1062 return (AR_IFACE_X_21);
1063 if(ctype > 150)
1064 return (AR_IFACE_EIA_530);
1065 if(ctype > 25)
1066 return (AR_IFACE_UNKNOWN);
1067 if(ctype > 7)
1068 return (AR_IFACE_LOOPBACK);
1069 return (AR_IFACE_UNKNOWN);
1070 }
1071
1072 /*
1073 * Initialize the card, allocate memory for the ar_softc structures
1074 * and fill in the pointers.
1075 */
1076 static void
1077 arc_init(struct ar_hardc *hc)
1078 {
1079 struct ar_softc *sc;
1080 int x;
1081 u_int chanmem;
1082 u_int bufmem;
1083 u_int next;
1084 u_int descneeded;
1085 u_char isr, mar;
1086 u_long memst;
1087
1088 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1090 hc->sc = sc;
1091
1092 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1093 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1094 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1095 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1096 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1097 if(hc->bustype == AR_BUS_PCI) {
1098 hc->txc_dtr_off[0] *= 4;
1099 hc->txc_dtr_off[1] *= 4;
1100 }
1101
1102 /*
1103 * reset the card and wait at least 1uS.
1104 */
1105 if(hc->bustype == AR_BUS_PCI)
1106 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1107 hc->txc_dtr[0];
1108 else
1109 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1110 hc->txc_dtr[0]);
1111 DELAY(2);
1112 if(hc->bustype == AR_BUS_PCI)
1113 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1114 else
1115 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1116
1117 if(hc->bustype == AR_BUS_ISA) {
1118 /*
1119 * Configure the card.
1120 * Mem address, irq,
1121 */
1122 memst = rman_get_start(hc->res_memory);
1123 mar = memst >> 16;
1124 isr = irqtable[hc->isa_irq] << 1;
1125 if(isr == 0)
1126 kprintf("ar%d: Warning illegal interrupt %d\n",
1127 hc->cunit, hc->isa_irq);
1128 isr = isr | ((memst & 0xc000) >> 10);
1129
1130 hc->sca[0] = (sca_regs *)hc->mem_start;
1131 hc->sca[1] = (sca_regs *)hc->mem_start;
1132
1133 ar_outb(hc, AR_MEM_SEL, mar);
1134 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1135 }
1136
1137 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1138 for(x = 0; x < hc->numports; x++)
1139 hc->interface[x] = ar_read_pim_iface(hc, x);
1140
1141 /*
1142 * Set the TX clock direction and enable TX.
1143 */
1144 for(x=0;x<hc->numports;x++) {
1145 switch(hc->interface[x]) {
1146 case AR_IFACE_V_35:
1147 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1148 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1149 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1150 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1151 break;
1152 case AR_IFACE_EIA_530:
1153 case AR_IFACE_COMBO:
1154 case AR_IFACE_X_21:
1155 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1156 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1157 break;
1158 }
1159 }
1160
1161 if(hc->bustype == AR_BUS_PCI)
1162 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1163 else
1164 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1165 if(hc->numports > NCHAN) {
1166 if(hc->bustype == AR_BUS_PCI)
1167 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1168 else
1169 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1170 }
1171
1172 chanmem = hc->memsize / hc->numports;
1173 next = 0;
1174
1175 for(x=0;x<hc->numports;x++, sc++) {
1176 int blk;
1177
1178 sc->sca = hc->sca[x / NCHAN];
1179
1180 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1181 sc->block[blk].txdesc = next;
1182 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1183 descneeded = bufmem / AR_BUF_SIZ;
1184 sc->block[blk].txstart = sc->block[blk].txdesc +
1185 ((((descneeded * sizeof(sca_descriptor)) /
1186 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1187 sc->block[blk].txend = next + bufmem;
1188 sc->block[blk].txmax =
1189 (sc->block[blk].txend - sc->block[blk].txstart)
1190 / AR_BUF_SIZ;
1191 next += bufmem;
1192
1193 TRC(kprintf("ar%d: blk %d: txdesc %x, txstart %x, "
1194 "txend %x, txmax %d\n",
1195 x,
1196 blk,
1197 sc->block[blk].txdesc,
1198 sc->block[blk].txstart,
1199 sc->block[blk].txend,
1200 sc->block[blk].txmax));
1201 }
1202
1203 sc->rxdesc = next;
1204 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1205 descneeded = bufmem / AR_BUF_SIZ;
1206 sc->rxstart = sc->rxdesc +
1207 ((((descneeded * sizeof(sca_descriptor)) /
1208 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1209 sc->rxend = next + bufmem;
1210 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1211 next += bufmem;
1212 TRC(kprintf("ar%d: rxdesc %x, rxstart %x, "
1213 "rxend %x, rxmax %d\n",
1214 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1215 }
1216
1217 if(hc->bustype == AR_BUS_PCI)
1218 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1219 }
1220
1221
1222 /*
1223 * The things done here are channel independent.
1224 *
1225 * Configure the sca waitstates.
1226 * Configure the global interrupt registers.
1227 * Enable master dma enable.
1228 */
1229 static void
1230 ar_init_sca(struct ar_hardc *hc, int scano)
1231 {
1232 sca_regs *sca;
1233
1234 sca = hc->sca[scano];
1235 if(hc->bustype == AR_BUS_ISA)
1236 ARC_SET_SCA(hc, scano);
1237
1238 /*
1239 * Do the wait registers.
1240 * Set everything to 0 wait states.
1241 */
1242 sca->pabr0 = 0;
1243 sca->pabr1 = 0;
1244 sca->wcrl = 0;
1245 sca->wcrm = 0;
1246 sca->wcrh = 0;
1247
1248 /*
1249 * Configure the interrupt registers.
1250 * Most are cleared until the interface is configured.
1251 */
1252 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1253 sca->ier1 = 0x00; /* DMAC interrupts */
1254 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1255 sca->itcr = 0x00; /* Use ivr and no intr ack */
1256 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1257 sca->imvr = 0x40;
1258
1259 /*
1260 * Configure the timers.
1261 * XXX Later
1262 */
1263
1264
1265 /*
1266 * Set the DMA channel priority to rotate between
1267 * all four channels.
1268 *
1269 * Enable all dma channels.
1270 */
1271 if(hc->bustype == AR_BUS_PCI) {
1272 u_char *t;
1273
1274 /*
1275 * Stupid problem with the PCI interface chip that break
1276 * things.
1277 * XXX
1278 */
1279 t = (u_char *)sca;
1280 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1281 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1282 } else {
1283 sca->pcr = SCA_PCR_PR2;
1284 sca->dmer = SCA_DMER_EN;
1285 }
1286 }
1287
1288
1289 /*
1290 * Configure the msci
1291 *
1292 * NOTE: The serial port configuration is hardcoded at the moment.
1293 */
1294 static void
1295 ar_init_msci(struct ar_softc *sc)
1296 {
1297 msci_channel *msci;
1298
1299 msci = &sc->sca->msci[sc->scachan];
1300
1301 if(sc->hc->bustype == AR_BUS_ISA)
1302 ARC_SET_SCA(sc->hc, sc->scano);
1303
1304 msci->cmd = SCA_CMD_RESET;
1305
1306 msci->md0 = SCA_MD0_CRC_1 |
1307 SCA_MD0_CRC_CCITT |
1308 SCA_MD0_CRC_ENABLE |
1309 SCA_MD0_MODE_HDLC;
1310 msci->md1 = SCA_MD1_NOADDRCHK;
1311 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1312
1313 /*
1314 * Acording to the manual I should give a reset after changing the
1315 * mode registers.
1316 */
1317 msci->cmd = SCA_CMD_RXRESET;
1318 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1319
1320 /*
1321 * For now all interfaces are programmed to use the RX clock for
1322 * the TX clock.
1323 */
1324 switch(sc->hc->interface[sc->subunit]) {
1325 case AR_IFACE_V_35:
1326 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1327 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1328 break;
1329 case AR_IFACE_X_21:
1330 case AR_IFACE_EIA_530:
1331 case AR_IFACE_COMBO:
1332 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1333 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1334 }
1335
1336 msci->tmc = 153; /* This give 64k for loopback */
1337
1338 /* XXX
1339 * Disable all interrupts for now. I think if you are using
1340 * the dmac you don't use these interrupts.
1341 */
1342 msci->ie0 = 0;
1343 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1344 msci->ie2 = 0;
1345 msci->fie = 0;
1346
1347 msci->sa0 = 0;
1348 msci->sa1 = 0;
1349
1350 msci->idl = 0x7E; /* XXX This is what cisco does. */
1351
1352 /*
1353 * This is what the ARNET diags use.
1354 */
1355 msci->rrc = 0x0E;
1356 msci->trc0 = 0x12;
1357 msci->trc1 = 0x1F;
1358 }
1359
1360 /*
1361 * Configure the rx dma controller.
1362 */
1363 static void
1364 ar_init_rx_dmac(struct ar_softc *sc)
1365 {
1366 dmac_channel *dmac;
1367 sca_descriptor *rxd;
1368 u_int rxbuf;
1369 u_int rxda;
1370 u_int rxda_d;
1371 int x = 0;
1372
1373 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1374
1375 if(sc->hc->bustype == AR_BUS_ISA)
1376 ARC_SET_MEM(sc->hc, sc->rxdesc);
1377
1378 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1379 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1380
1381 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1382 rxda = (u_int)&rxd[1] - rxda_d;
1383 rxd->cp = (u_short)(rxda & 0xfffful);
1384
1385 x++;
1386 if(x < 6)
1387 TRC(kprintf("Descrp %p, data pt %x, data %x, ",
1388 rxd, rxda, rxbuf));
1389
1390 rxd->bp = (u_short)(rxbuf & 0xfffful);
1391 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1392 rxd->len = 0;
1393 rxd->stat = 0xff; /* The sca write here when it is finished. */
1394
1395 if(x < 6)
1396 TRC(kprintf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1397 }
1398 rxd--;
1399 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1400
1401 sc->rxhind = 0;
1402
1403 if(sc->hc->bustype == AR_BUS_ISA)
1404 ARC_SET_SCA(sc->hc, sc->scano);
1405
1406 dmac->dsr = 0; /* Disable DMA transfer */
1407 dmac->dcr = SCA_DCR_ABRT;
1408
1409 /* XXX maybe also SCA_DMR_CNTE */
1410 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1411 dmac->bfl = AR_BUF_SIZ;
1412
1413 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1414 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1415
1416 rxd = (sca_descriptor *)sc->rxstart;
1417 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1418
1419 dmac->dir = 0xF0;
1420
1421 dmac->dsr = SCA_DSR_DE;
1422 }
1423
1424 /*
1425 * Configure the TX DMA descriptors.
1426 * Initialize the needed values and chain the descriptors.
1427 */
1428 static void
1429 ar_init_tx_dmac(struct ar_softc *sc)
1430 {
1431 dmac_channel *dmac;
1432 struct buf_block *blkp;
1433 int blk;
1434 sca_descriptor *txd;
1435 u_int txbuf;
1436 u_int txda;
1437 u_int txda_d;
1438
1439 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1440
1441 if(sc->hc->bustype == AR_BUS_ISA)
1442 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1443
1444 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1445 blkp = &sc->block[blk];
1446 txd = (sca_descriptor *)(sc->hc->mem_start +
1447 (blkp->txdesc&sc->hc->winmsk));
1448 txda_d = (u_int)sc->hc->mem_start -
1449 (blkp->txdesc & ~sc->hc->winmsk);
1450
1451 txbuf=blkp->txstart;
1452 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1453 txda = (u_int)&txd[1] - txda_d;
1454 txd->cp = (u_short)(txda & 0xfffful);
1455
1456 txd->bp = (u_short)(txbuf & 0xfffful);
1457 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1458 TRC(kprintf("ar%d: txbuf %x, bpb %x, bp %x\n",
1459 sc->unit, txbuf, txd->bpb, txd->bp));
1460 txd->len = 0;
1461 txd->stat = 0;
1462 }
1463 txd--;
1464 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1465
1466 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1467 TRC(kprintf("TX Descriptors start %x, end %x.\n",
1468 blkp->txdesc,
1469 blkp->txtail));
1470 }
1471
1472 if(sc->hc->bustype == AR_BUS_ISA)
1473 ARC_SET_SCA(sc->hc, sc->scano);
1474
1475 dmac->dsr = 0; /* Disable DMA */
1476 dmac->dcr = SCA_DCR_ABRT;
1477 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1478 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1479
1480 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1481 }
1482
1483
1484 /*
1485 * Look through the descriptors to see if there is a complete packet
1486 * available. Stop if we get to where the sca is busy.
1487 *
1488 * Return the length and status of the packet.
1489 * Return nonzero if there is a packet available.
1490 *
1491 * NOTE:
1492 * It seems that we get the interrupt a bit early. The updateing of
1493 * descriptor values is not always completed when this is called.
1494 */
1495 static int
1496 ar_packet_avail(struct ar_softc *sc,
1497 int *len,
1498 u_char *rxstat)
1499 {
1500 dmac_channel *dmac;
1501 sca_descriptor *rxdesc;
1502 sca_descriptor *endp;
1503 sca_descriptor *cda;
1504
1505 if(sc->hc->bustype == AR_BUS_ISA)
1506 ARC_SET_SCA(sc->hc, sc->scano);
1507 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1508 cda = (sca_descriptor *)(sc->hc->mem_start +
1509 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1510
1511 if(sc->hc->bustype == AR_BUS_ISA)
1512 ARC_SET_MEM(sc->hc, sc->rxdesc);
1513 rxdesc = (sca_descriptor *)
1514 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1515 endp = rxdesc;
1516 rxdesc = &rxdesc[sc->rxhind];
1517 endp = &endp[sc->rxmax];
1518
1519 *len = 0;
1520
1521 while(rxdesc != cda) {
1522 *len += rxdesc->len;
1523
1524 if(rxdesc->stat & SCA_DESC_EOM) {
1525 *rxstat = rxdesc->stat;
1526 TRC(kprintf("ar%d: PKT AVAIL len %d, %x.\n",
1527 sc->unit, *len, *rxstat));
1528 return (1);
1529 }
1530
1531 rxdesc++;
1532 if(rxdesc == endp)
1533 rxdesc = (sca_descriptor *)
1534 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1535 }
1536
1537 *len = 0;
1538 *rxstat = 0;
1539 return (0);
1540 }
1541
1542
1543 /*
1544 * Copy a packet from the on card memory into a provided mbuf.
1545 * Take into account that buffers wrap and that a packet may
1546 * be larger than a buffer.
1547 */
1548 static void
1549 ar_copy_rxbuf(struct mbuf *m,
1550 struct ar_softc *sc,
1551 int len)
1552 {
1553 sca_descriptor *rxdesc;
1554 u_int rxdata;
1555 u_int rxmax;
1556 u_int off = 0;
1557 u_int tlen;
1558
1559 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1560 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1561
1562 rxdesc = (sca_descriptor *)
1563 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1564 rxdesc = &rxdesc[sc->rxhind];
1565
1566 while(len) {
1567 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1568 if(sc->hc->bustype == AR_BUS_ISA)
1569 ARC_SET_MEM(sc->hc, rxdata);
1570 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1571 mtod(m, caddr_t) + off,
1572 tlen);
1573
1574 off += tlen;
1575 len -= tlen;
1576
1577 if(sc->hc->bustype == AR_BUS_ISA)
1578 ARC_SET_MEM(sc->hc, sc->rxdesc);
1579 rxdesc->len = 0;
1580 rxdesc->stat = 0xff;
1581
1582 rxdata += AR_BUF_SIZ;
1583 rxdesc++;
1584 if(rxdata == rxmax) {
1585 rxdata = sc->rxstart;
1586 rxdesc = (sca_descriptor *)
1587 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1588 }
1589 }
1590 }
1591
1592 /*
1593 * If single is set, just eat a packet. Otherwise eat everything up to
1594 * where cda points. Update pointers to point to the next packet.
1595 */
1596 static void
1597 ar_eat_packet(struct ar_softc *sc, int single)
1598 {
1599 dmac_channel *dmac;
1600 sca_descriptor *rxdesc;
1601 sca_descriptor *endp;
1602 sca_descriptor *cda;
1603 int loopcnt = 0;
1604 u_char stat;
1605
1606 if(sc->hc->bustype == AR_BUS_ISA)
1607 ARC_SET_SCA(sc->hc, sc->scano);
1608 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1609 cda = (sca_descriptor *)(sc->hc->mem_start +
1610 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1611
1612 /*
1613 * Loop until desc->stat == (0xff || EOM)
1614 * Clear the status and length in the descriptor.
1615 * Increment the descriptor.
1616 */
1617 if(sc->hc->bustype == AR_BUS_ISA)
1618 ARC_SET_MEM(sc->hc, sc->rxdesc);
1619 rxdesc = (sca_descriptor *)
1620 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1621 endp = rxdesc;
1622 rxdesc = &rxdesc[sc->rxhind];
1623 endp = &endp[sc->rxmax];
1624
1625 while(rxdesc != cda) {
1626 loopcnt++;
1627 if(loopcnt > sc->rxmax) {
1628 kprintf("ar%d: eat pkt %d loop, cda %p, "
1629 "rxdesc %p, stat %x.\n",
1630 sc->unit,
1631 loopcnt,
1632 (void *)cda,
1633 (void *)rxdesc,
1634 rxdesc->stat);
1635 break;
1636 }
1637
1638 stat = rxdesc->stat;
1639
1640 rxdesc->len = 0;
1641 rxdesc->stat = 0xff;
1642
1643 rxdesc++;
1644 sc->rxhind++;
1645 if(rxdesc == endp) {
1646 rxdesc = (sca_descriptor *)
1647 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1648 sc->rxhind = 0;
1649 }
1650
1651 if(single && (stat == SCA_DESC_EOM))
1652 break;
1653 }
1654
1655 /*
1656 * Update the eda to the previous descriptor.
1657 */
1658 if(sc->hc->bustype == AR_BUS_ISA)
1659 ARC_SET_SCA(sc->hc, sc->scano);
1660
1661 rxdesc = (sca_descriptor *)sc->rxdesc;
1662 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1663
1664 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1665 (u_short)((u_int)rxdesc & 0xffff);
1666 }
1667
1668
1669 /*
1670 * While there is packets available in the rx buffer, read them out
1671 * into mbufs and ship them off.
1672 */
1673 static void
1674 ar_get_packets(struct ar_softc *sc)
1675 {
1676 sca_descriptor *rxdesc;
1677 struct mbuf *m = NULL;
1678 int i;
1679 int len;
1680 u_char rxstat;
1681 #ifdef NETGRAPH
1682 int error;
1683 #endif
1684
1685 while(ar_packet_avail(sc, &len, &rxstat)) {
1686 TRC(kprintf("apa: len %d, rxstat %x\n", len, rxstat));
1687 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1688 m = m_getl(len, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
1689 if(m == NULL) {
1690 /* eat packet if get mbuf fail!! */
1691 ar_eat_packet(sc, 1);
1692 continue;
1693 }
1694 #ifdef NETGRAPH
1695 m->m_pkthdr.rcvif = NULL;
1696 sc->inbytes += len;
1697 sc->inlast = 0;
1698 #else
1699 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1700 #endif
1701 m->m_pkthdr.len = m->m_len = len;
1702 ar_copy_rxbuf(m, sc, len);
1703 #ifdef NETGRAPH
1704 NG_SEND_DATA_ONLY(error, sc->hook, m);
1705 sc->ipackets++;
1706 #else
1707 BPF_MTAP(&sc->ifsppp.pp_if, m);
1708 sppp_input(&sc->ifsppp.pp_if, m);
1709 sc->ifsppp.pp_if.if_ipackets++;
1710 #endif
1711 /*
1712 * Update the eda to the previous descriptor.
1713 */
1714 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1715 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1716
1717 if(sc->hc->bustype == AR_BUS_ISA)
1718 ARC_SET_SCA(sc->hc, sc->scano);
1719
1720 rxdesc = (sca_descriptor *)sc->rxdesc;
1721 rxdesc =
1722 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1723
1724 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1725 (u_short)((u_int)rxdesc & 0xffff);
1726 } else {
1727 int tries = 5;
1728
1729 while((rxstat == 0xff) && --tries)
1730 ar_packet_avail(sc, &len, &rxstat);
1731
1732 /*
1733 * It look like we get an interrupt early
1734 * sometimes and then the status is not
1735 * filled in yet.
1736 */
1737 if(tries && (tries != 5))
1738 continue;
1739
1740 ar_eat_packet(sc, 1);
1741
1742 #ifndef NETGRAPH
1743 sc->ifsppp.pp_if.if_ierrors++;
1744 #else /* NETGRAPH */
1745 sc->ierrors[0]++;
1746 #endif /* NETGRAPH */
1747
1748 if(sc->hc->bustype == AR_BUS_ISA)
1749 ARC_SET_SCA(sc->hc, sc->scano);
1750
1751 TRCL(kprintf("ar%d: Receive error chan %d, "
1752 "stat %x, msci st3 %x,"
1753 "rxhind %d, cda %x, eda %x.\n",
1754 sc->unit,
1755 sc->scachan,
1756 rxstat,
1757 sc->sca->msci[sc->scachan].st3,
1758 sc->rxhind,
1759 sc->sca->dmac[
1760 DMAC_RXCH(sc->scachan)].cda,
1761 sc->sca->dmac[
1762 DMAC_RXCH(sc->scachan)].eda));
1763 }
1764 }
1765 }
1766
1767
1768 /*
1769 * All DMA interrupts come here.
1770 *
1771 * Each channel has two interrupts.
1772 * Interrupt A for errors and Interrupt B for normal stuff like end
1773 * of transmit or receive dmas.
1774 */
1775 static void
1776 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1777 {
1778 u_char dsr;
1779 u_char dotxstart = isr1;
1780 int mch;
1781 struct ar_softc *sc;
1782 sca_regs *sca;
1783 dmac_channel *dmac;
1784
1785 sca = hc->sca[scano];
1786 mch = 0;
1787 /*
1788 * Shortcut if there is no interrupts for dma channel 0 or 1
1789 */
1790 if((isr1 & 0x0F) == 0) {
1791 mch = 1;
1792 isr1 >>= 4;
1793 }
1794
1795 do {
1796 sc = &hc->sc[mch + (NCHAN * scano)];
1797
1798 /*
1799 * Transmit channel
1800 */
1801 if(isr1 & 0x0C) {
1802 dmac = &sca->dmac[DMAC_TXCH(mch)];
1803
1804 if(hc->bustype == AR_BUS_ISA)
1805 ARC_SET_SCA(hc, scano);
1806
1807 dsr = dmac->dsr;
1808 dmac->dsr = dsr;
1809
1810 /* Counter overflow */
1811 if(dsr & SCA_DSR_COF) {
1812 kprintf("ar%d: TX DMA Counter overflow, "
1813 "txpacket no %lu.\n",
1814 sc->unit,
1815 #ifndef NETGRAPH
1816 sc->ifsppp.pp_if.if_opackets);
1817 sc->ifsppp.pp_if.if_oerrors++;
1818 #else /* NETGRAPH */
1819 sc->opackets);
1820 sc->oerrors++;
1821 #endif /* NETGRAPH */
1822 }
1823
1824 /* Buffer overflow */
1825 if(dsr & SCA_DSR_BOF) {
1826 kprintf("ar%d: TX DMA Buffer overflow, "
1827 "txpacket no %lu, dsr %02x, "
1828 "cda %04x, eda %04x.\n",
1829 sc->unit,
1830 #ifndef NETGRAPH
1831 sc->ifsppp.pp_if.if_opackets,
1832 #else /* NETGRAPH */
1833 sc->opackets,
1834 #endif /* NETGRAPH */
1835 dsr,
1836 dmac->cda,
1837 dmac->eda);
1838 #ifndef NETGRAPH
1839 sc->ifsppp.pp_if.if_oerrors++;
1840 #else /* NETGRAPH */
1841 sc->oerrors++;
1842 #endif /* NETGRAPH */
1843 }
1844
1845 /* End of Transfer */
1846 if(dsr & SCA_DSR_EOT) {
1847 /*
1848 * This should be the most common case.
1849 *
1850 * Clear the IFF_OACTIVE flag.
1851 *
1852 * Call arstart to start a new transmit if
1853 * there is data to transmit.
1854 */
1855 sc->xmit_busy = 0;
1856 #ifndef NETGRAPH
1857 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1858 sc->ifsppp.pp_if.if_timer = 0;
1859 #else /* NETGRAPH */
1860 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1861 sc->out_dog = 0; /* XXX */
1862 #endif /* NETGRAPH */
1863
1864 if(sc->txb_inuse && --sc->txb_inuse)
1865 ar_xmit(sc);
1866 }
1867 }
1868
1869 /*
1870 * Receive channel
1871 */
1872 if(isr1 & 0x03) {
1873 dmac = &sca->dmac[DMAC_RXCH(mch)];
1874
1875 if(hc->bustype == AR_BUS_ISA)
1876 ARC_SET_SCA(hc, scano);
1877
1878 dsr = dmac->dsr;
1879 dmac->dsr = dsr;
1880
1881 TRC(kprintf("AR: RX DSR %x\n", dsr));
1882
1883 /* End of frame */
1884 if(dsr & SCA_DSR_EOM) {
1885 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1886 TRC(int ind = sc->rxhind;)
1887
1888 ar_get_packets(sc);
1889 #ifndef NETGRAPH
1890 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1891 #else /* NETGRAPH */
1892 #define IPACKETS sc->ipackets
1893 #endif /* NETGRAPH */
1894 TRC(if(tt == IPACKETS) {
1895 sca_descriptor *rxdesc;
1896 int i;
1897
1898 if(hc->bustype == AR_BUS_ISA)
1899 ARC_SET_SCA(hc, scano);
1900 kprintf("AR: RXINTR isr1 %x, dsr %x, "
1901 "no data %d pkts, orxhind %d.\n",
1902 dotxstart,
1903 dsr,
1904 tt,
1905 ind);
1906 kprintf("AR: rxdesc %x, rxstart %x, "
1907 "rxend %x, rxhind %d, "
1908 "rxmax %d.\n",
1909 sc->rxdesc,
1910 sc->rxstart,
1911 sc->rxend,
1912 sc->rxhind,
1913 sc->rxmax);
1914 kprintf("AR: cda %x, eda %x.\n",
1915 dmac->cda,
1916 dmac->eda);
1917
1918 if(sc->hc->bustype == AR_BUS_ISA)
1919 ARC_SET_MEM(sc->hc,
1920 sc->rxdesc);
1921 rxdesc = (sca_descriptor *)
1922 (sc->hc->mem_start +
1923 (sc->rxdesc & sc->hc->winmsk));
1924 rxdesc = &rxdesc[sc->rxhind];
1925 for(i=0;i<3;i++,rxdesc++)
1926 kprintf("AR: rxdesc->stat %x, "
1927 "len %d.\n",
1928 rxdesc->stat,
1929 rxdesc->len);
1930 })
1931 }
1932
1933 /* Counter overflow */
1934 if(dsr & SCA_DSR_COF) {
1935 kprintf("ar%d: RX DMA Counter overflow, "
1936 "rxpkts %lu.\n",
1937 sc->unit,
1938 #ifndef NETGRAPH
1939 sc->ifsppp.pp_if.if_ipackets);
1940 sc->ifsppp.pp_if.if_ierrors++;
1941 #else /* NETGRAPH */
1942 sc->ipackets);
1943 sc->ierrors[1]++;
1944 #endif /* NETGRAPH */
1945 }
1946
1947 /* Buffer overflow */
1948 if(dsr & SCA_DSR_BOF) {
1949 if(hc->bustype == AR_BUS_ISA)
1950 ARC_SET_SCA(hc, scano);
1951 kprintf("ar%d: RX DMA Buffer overflow, "
1952 "rxpkts %lu, rxind %d, "
1953 "cda %x, eda %x, dsr %x.\n",
1954 sc->unit,
1955 #ifndef NETGRAPH
1956 sc->ifsppp.pp_if.if_ipackets,
1957 #else /* NETGRAPH */
1958 sc->ipackets,
1959 #endif /* NETGRAPH */
1960 sc->rxhind,
1961 dmac->cda,
1962 dmac->eda,
1963 dsr);
1964 /*
1965 * Make sure we eat as many as possible.
1966 * Then get the system running again.
1967 */
1968 ar_eat_packet(sc, 0);
1969 #ifndef NETGRAPH
1970 sc->ifsppp.pp_if.if_ierrors++;
1971 #else /* NETGRAPH */
1972 sc->ierrors[2]++;
1973 #endif /* NETGRAPH */
1974 if(hc->bustype == AR_BUS_ISA)
1975 ARC_SET_SCA(hc, scano);
1976 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1977 dmac->dsr = SCA_DSR_DE;
1978
1979 TRC(kprintf("ar%d: RX DMA Buffer overflow, "
1980 "rxpkts %lu, rxind %d, "
1981 "cda %x, eda %x, dsr %x. After\n",
1982 sc->unit,
1983 sc->ifsppp.pp_if.if_ipackets,
1984 sc->rxhind,
1985 dmac->cda,
1986 dmac->eda,
1987 dmac->dsr);)
1988 }
1989
1990 /* End of Transfer */
1991 if(dsr & SCA_DSR_EOT) {
1992 /*
1993 * If this happen, it means that we are
1994 * receiving faster than what the processor
1995 * can handle.
1996 *
1997 * XXX We should enable the dma again.
1998 */
1999 kprintf("ar%d: RX End of transfer, rxpkts %lu.\n",
2000 sc->unit,
2001 #ifndef NETGRAPH
2002 sc->ifsppp.pp_if.if_ipackets);
2003 sc->ifsppp.pp_if.if_ierrors++;
2004 #else /* NETGRAPH */
2005 sc->ipackets);
2006 sc->ierrors[3]++;
2007 #endif /* NETGRAPH */
2008 }
2009 }
2010
2011 isr1 >>= 4;
2012
2013 mch++;
2014 }while((mch<NCHAN) && isr1);
2015
2016 /*
2017 * Now that we have done all the urgent things, see if we
2018 * can fill the transmit buffers.
2019 */
2020 for(mch = 0; mch < NCHAN; mch++) {
2021 if(dotxstart & 0x0C) {
2022 sc = &hc->sc[mch + (NCHAN * scano)];
2023 #ifndef NETGRAPH
2024 arstart(&sc->ifsppp.pp_if);
2025 #else /* NETGRAPH */
2026 arstart(sc);
2027 #endif /* NETGRAPH */
2028 }
2029 dotxstart >>= 4;
2030 }
2031 }
2032
2033 static void
2034 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2035 {
2036 kprintf("arc%d: ARINTR: MSCI\n", hc->cunit);
2037 }
2038
2039 static void
2040 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2041 {
2042 kprintf("arc%d: ARINTR: TIMER\n", hc->cunit);
2043 }
2044
2045
2046 #ifdef NETGRAPH
2047 /*****************************************
2048 * Device timeout/watchdog routine.
2049 * called once per second.
2050 * checks to see that if activity was expected, that it hapenned.
2051 * At present we only look to see if expected output was completed.
2052 */
2053 static void
2054 ngar_watchdog_frame(void * arg)
2055 {
2056 struct ar_softc * sc = arg;
2057 int speed;
2058
2059 if (sc->running == 0) {
2060 return; /* if we are not running let timeouts die */
2061 }
2062
2063 lwkt_serialize_enter(&ar_serializer);
2064
2065 /*
2066 * calculate the apparent throughputs
2067 * XXX a real hack
2068 */
2069 speed = sc->inbytes - sc->lastinbytes;
2070 sc->lastinbytes = sc->inbytes;
2071 if ( sc->inrate < speed )
2072 sc->inrate = speed;
2073 speed = sc->outbytes - sc->lastoutbytes;
2074 sc->lastoutbytes = sc->outbytes;
2075 if ( sc->outrate < speed )
2076 sc->outrate = speed;
2077 sc->inlast++;
2078
2079 if ((sc->inlast > QUITE_A_WHILE)
2080 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2081 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2082
2083 ar_down(sc);
2084 ar_up(sc);
2085 sc->inlast = sc->out_deficit = 0;
2086 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2087 if (sc->out_dog == 0) {
2088 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2089 sc->unit);
2090
2091 arwatchdog(sc);
2092 #if 0
2093 ar_down(sc);
2094 ar_up(sc);
2095 #endif
2096 sc->inlast = sc->out_deficit = 0;
2097 } else {
2098 sc->out_dog--;
2099 }
2100 }
2101 lwkt_serialize_exit(&ar_serializer);
2102 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
2103 }
2104
2105 /***********************************************************************
2106 * This section contains the methods for the Netgraph interface
2107 ***********************************************************************/
2108 /*
2109 * It is not possible or allowable to create a node of this type.
2110 * If the hardware exists, it will already have created it.
2111 */
2112 static int
2113 ngar_constructor(node_p *nodep)
2114 {
2115 return (EINVAL);
2116 }
2117
2118 /*
2119 * give our ok for a hook to be added...
2120 * If we are not running this should kick the device into life.
2121 * The hook's private info points to our stash of info about that
2122 * channel.
2123 */
2124 static int
2125 ngar_newhook(node_p node, hook_p hook, const char *name)
2126 {
2127 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2128
2129 /*
2130 * check if it's our friend the debug hook
2131 */
2132 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2133 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2134 sc->debug_hook = hook;
2135 return (0);
2136 }
2137
2138 /*
2139 * Check for raw mode hook.
2140 */
2141 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2142 return (EINVAL);
2143 }
2144 NG_HOOK_SET_PRIVATE(hook, sc);
2145 sc->hook = hook;
2146 sc->datahooks++;
2147 ar_up(sc);
2148 return (0);
2149 }
2150
2151 /*
2152 * incoming messages.
2153 * Just respond to the generic TEXT_STATUS message
2154 */
2155 static int
2156 ngar_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr,
2157 struct ng_mesg **rptr)
2158 {
2159 struct ar_softc *sc;
2160 int error = 0;
2161 struct ng_mesg *resp = NULL;
2162
2163 sc = NG_NODE_PRIVATE(node);
2164 switch (msg->header.typecookie) {
2165 case NG_AR_COOKIE:
2166 error = EINVAL;
2167 break;
2168 case NGM_GENERIC_COOKIE:
2169 switch(msg->header.cmd) {
2170 case NGM_TEXT_STATUS: {
2171 char *arg;
2172 int pos = 0;
2173
2174 int resplen = sizeof(struct ng_mesg) + 512;
2175 NG_MKRESPONSE(resp, msg, resplen, M_INTWAIT);
2176 if (resp == NULL) {
2177 error = ENOMEM;
2178 break;
2179 }
2180 arg = (resp)->data;
2181 pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n"
2182 "highest rate seen: %ld B/S in, %ld B/S out\n",
2183 sc->inbytes, sc->outbytes,
2184 sc->inrate, sc->outrate);
2185 pos += ksprintf(arg + pos,
2186 "%ld output errors\n",
2187 sc->oerrors);
2188 pos += ksprintf(arg + pos,
2189 "ierrors = %ld, %ld, %ld, %ld\n",
2190 sc->ierrors[0],
2191 sc->ierrors[1],
2192 sc->ierrors[2],
2193 sc->ierrors[3]);
2194
2195 (resp)->header.arglen = pos + 1;
2196 break;
2197 }
2198 default:
2199 error = EINVAL;
2200 break;
2201 }
2202 break;
2203 default:
2204 error = EINVAL;
2205 break;
2206 }
2207 /* Take care of synchronous response, if any */
2208 NG_RESPOND_MSG(error, node, retaddr, resp, rptr);
2209 NG_FREE_MSG(msg);
2210 return (error);
2211 }
2212
2213 /*
2214 * get data from another node and transmit it to the correct channel
2215 */
2216 static int
2217 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2218 {
2219 int error = 0;
2220 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2221 struct ifqueue *xmitq_p;
2222
2223 /*
2224 * data doesn't come in from just anywhere (e.g control hook)
2225 */
2226 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2227 error = ENETDOWN;
2228 goto bad;
2229 }
2230
2231 /*
2232 * Now queue the data for when it can be sent
2233 */
2234 if (meta && meta->priority > 0)
2235 xmitq_p = (&sc->xmitq_hipri);
2236 else
2237 xmitq_p = (&sc->xmitq);
2238
2239 if (IF_QFULL(xmitq_p)) {
2240 IF_DROP(xmitq_p);
2241
2242 error = ENOBUFS;
2243 goto bad;
2244 }
2245 IF_ENQUEUE(xmitq_p, m);
2246 arstart(sc);
2247
2248 return (0);
2249
2250 bad:
2251 /*
2252 * It was an error case.
2253 * check if we need to free the mbuf, and then return the error
2254 */
2255 NG_FREE_DATA(m, meta);
2256 return (error);
2257 }
2258
2259 /*
2260 * do local shutdown processing..
2261 * this node will refuse to go away, unless the hardware says to..
2262 * don't unref the node, or remove our name. just clear our links up.
2263 */
2264 static int
2265 ngar_shutdown(node_p node)
2266 {
2267 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2268
2269 ar_down(sc);
2270 NG_NODE_UNREF(node);
2271 /* XXX need to drain the output queues! */
2272
2273 /* The node is dead, long live the node! */
2274 /* stolen from the attach routine */
2275 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2276 return (0);
2277 ksprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2278 if (ng_name_node(sc->node, sc->nodename)) {
2279 sc->node = NULL;
2280 kprintf("node naming failed\n");
2281 NG_NODE_UNREF(sc->node); /* node dissappears */
2282 return (0);
2283 }
2284 NG_NODE_SET_PRIVATE(sc->node, sc);
2285 sc->running = 0;
2286 return (0);
2287 }
2288
2289 /* already linked */
2290 static int
2291 ngar_connect(hook_p hook)
2292 {
2293 /* be really amiable and just say "YUP that's OK by me! " */
2294 return (0);
2295 }
2296
2297 /*
2298 * notify on hook disconnection (destruction)
2299 *
2300 * Invalidate the private data associated with this dlci.
2301 * For this type, removal of the last link resets tries to destroy the node.
2302 * As the device still exists, the shutdown method will not actually
2303 * destroy the node, but reset the device and leave it 'fresh' :)
2304 *
2305 * The node removal code will remove all references except that owned by the
2306 * driver.
2307 */
2308 static int
2309 ngar_disconnect(hook_p hook)
2310 {
2311 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2312
2313 /*
2314 * If it's the data hook, then free resources etc.
2315 */
2316 if (NG_HOOK_PRIVATE(hook)) {
2317 sc->datahooks--;
2318 if (sc->datahooks == 0)
2319 ar_down(sc);
2320 } else {
2321 sc->debug_hook = NULL;
2322 }
2323 return (0);
2324 }
2325
2326 /*
2327 * called during bootup
2328 * or LKM loading to put this type into the list of known modules
2329 */
2330 static void
2331 ngar_init(void *ignored)
2332 {
2333 if (ng_newtype(&typestruct))
2334 kprintf("ngar install failed\n");
2335 ngar_done_init = 1;
2336 }
2337 #endif /* NETGRAPH */
2338
2339 /*
2340 ********************************* END ************************************
2341 */
DragonFly BSD