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HAMMER Utilities: MFC work to date.
[dragonfly.git] / sys / dev / netif / tl / if_tl.c
blobafe4cb1827b731da5be2cb69d5231dc7f9fb375a
1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.39 2008/05/14 11:59:22 sephe Exp $
34 */
35
36 /*
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
41 *
42 * Written using the following four documents:
43 *
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
48 *
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
52 */
53
54 /*
55 * Some notes about the ThunderLAN:
56 *
57 * The ThunderLAN controller is a single chip containing PCI controller
58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
62 * to act as a complete ethernet interface.
63 *
64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
66 * in full or half duplex. Some of the Compaq Deskpro machines use a
67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
69 * concert with the ThunderLAN's internal PHY to provide full 10/100
70 * support. This is cheaper than using a standalone external PHY for both
71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
72 * A serial EEPROM is also attached to the ThunderLAN chip to provide
73 * power-up default register settings and for storing the adapter's
74 * station address. Although not supported by this driver, the ThunderLAN
75 * chip can also be connected to token ring PHYs.
76 *
77 * The ThunderLAN has a set of registers which can be used to issue
78 * commands, acknowledge interrupts, and to manipulate other internal
79 * registers on its DIO bus. The primary registers can be accessed
80 * using either programmed I/O (inb/outb) or via PCI memory mapping,
81 * depending on how the card is configured during the PCI probing
82 * phase. It is even possible to have both PIO and memory mapped
83 * access turned on at the same time.
84 *
85 * Frame reception and transmission with the ThunderLAN chip is done
86 * using frame 'lists.' A list structure looks more or less like this:
87 *
88 * struct tl_frag {
89 * u_int32_t fragment_address;
90 * u_int32_t fragment_size;
91 * };
92 * struct tl_list {
93 * u_int32_t forward_pointer;
94 * u_int16_t cstat;
95 * u_int16_t frame_size;
96 * struct tl_frag fragments[10];
97 * };
98 *
99 * The forward pointer in the list header can be either a 0 or the address
100 * of another list, which allows several lists to be linked together. Each
101 * list contains up to 10 fragment descriptors. This means the chip allows
102 * ethernet frames to be broken up into up to 10 chunks for transfer to
103 * and from the SRAM. Note that the forward pointer and fragment buffer
104 * addresses are physical memory addresses, not virtual. Note also that
105 * a single ethernet frame can not span lists: if the host wants to
106 * transmit a frame and the frame data is split up over more than 10
107 * buffers, the frame has to collapsed before it can be transmitted.
108 *
109 * To receive frames, the driver sets up a number of lists and populates
110 * the fragment descriptors, then it sends an RX GO command to the chip.
111 * When a frame is received, the chip will DMA it into the memory regions
112 * specified by the fragment descriptors and then trigger an RX 'end of
113 * frame interrupt' when done. The driver may choose to use only one
114 * fragment per list; this may result is slighltly less efficient use
115 * of memory in exchange for improving performance.
116 *
117 * To transmit frames, the driver again sets up lists and fragment
118 * descriptors, only this time the buffers contain frame data that
119 * is to be DMA'ed into the chip instead of out of it. Once the chip
120 * has transfered the data into its on-board SRAM, it will trigger a
121 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
122 * interrupt when it reaches the end of the list.
123 */
124
125 /*
126 * Some notes about this driver:
127 *
128 * The ThunderLAN chip provides a couple of different ways to organize
129 * reception, transmission and interrupt handling. The simplest approach
130 * is to use one list each for transmission and reception. In this mode,
131 * the ThunderLAN will generate two interrupts for every received frame
132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
134 * performance to have to handle so many interrupts.
135 *
136 * Initially I wanted to create a circular list of receive buffers so
137 * that the ThunderLAN chip would think there was an infinitely long
138 * receive channel and never deliver an RXEOC interrupt. However this
139 * doesn't work correctly under heavy load: while the manual says the
140 * chip will trigger an RXEOF interrupt each time a frame is copied into
141 * memory, you can't count on the chip waiting around for you to acknowledge
142 * the interrupt before it starts trying to DMA the next frame. The result
143 * is that the chip might traverse the entire circular list and then wrap
144 * around before you have a chance to do anything about it. Consequently,
145 * the receive list is terminated (with a 0 in the forward pointer in the
146 * last element). Each time an RXEOF interrupt arrives, the used list
147 * is shifted to the end of the list. This gives the appearance of an
148 * infinitely large RX chain so long as the driver doesn't fall behind
149 * the chip and allow all of the lists to be filled up.
150 *
151 * If all the lists are filled, the adapter will deliver an RX 'end of
152 * channel' interrupt when it hits the 0 forward pointer at the end of
153 * the chain. The RXEOC handler then cleans out the RX chain and resets
154 * the list head pointer in the ch_parm register and restarts the receiver.
155 *
156 * For frame transmission, it is possible to program the ThunderLAN's
157 * transmit interrupt threshold so that the chip can acknowledge multiple
158 * lists with only a single TX EOF interrupt. This allows the driver to
159 * queue several frames in one shot, and only have to handle a total
160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
161 * are transmitted. Frame transmission is done directly out of the
162 * mbufs passed to the tl_start() routine via the interface send queue.
163 * The driver simply sets up the fragment descriptors in the transmit
164 * lists to point to the mbuf data regions and sends a TX GO command.
165 *
166 * Note that since the RX and TX lists themselves are always used
167 * only by the driver, the are malloc()ed once at driver initialization
168 * time and never free()ed.
169 *
170 * Also, in order to remain as platform independent as possible, this
171 * driver uses memory mapped register access to manipulate the card
172 * as opposed to programmed I/O. This avoids the use of the inb/outb
173 * (and related) instructions which are specific to the i386 platform.
174 *
175 * Using these techniques, this driver achieves very high performance
176 * by minimizing the amount of interrupts generated during large
177 * transfers and by completely avoiding buffer copies. Frame transfer
178 * to and from the ThunderLAN chip is performed entirely by the chip
179 * itself thereby reducing the load on the host CPU.
180 */
181
182 #include <sys/param.h>
183 #include <sys/systm.h>
184 #include <sys/sockio.h>
185 #include <sys/mbuf.h>
186 #include <sys/malloc.h>
187 #include <sys/kernel.h>
188 #include <sys/socket.h>
189 #include <sys/serialize.h>
190 #include <sys/bus.h>
191 #include <sys/rman.h>
192 #include <sys/thread2.h>
193 #include <sys/interrupt.h>
194
195 #include <net/if.h>
196 #include <net/ifq_var.h>
197 #include <net/if_arp.h>
198 #include <net/ethernet.h>
199 #include <net/if_dl.h>
200 #include <net/if_media.h>
201
202 #include <net/bpf.h>
203
204 #include <vm/vm.h> /* for vtophys */
205 #include <vm/pmap.h> /* for vtophys */
206
207 #include "../mii_layer/mii.h"
208 #include "../mii_layer/miivar.h"
209
210 #include <bus/pci/pcireg.h>
211 #include <bus/pci/pcivar.h>
212
213 /*
214 * Default to using PIO register access mode to pacify certain
215 * laptop docking stations with built-in ThunderLAN chips that
216 * don't seem to handle memory mapped mode properly.
217 */
218 #define TL_USEIOSPACE
219
220 #include "if_tlreg.h"
221
222 /* "controller miibus0" required. See GENERIC if you get errors here. */
223 #include "miibus_if.h"
224
225 /*
226 * Various supported device vendors/types and their names.
227 */
228
229 static struct tl_type tl_devs[] = {
230 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
231 "Texas Instruments ThunderLAN" },
232 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
233 "Compaq Netelligent 10" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
235 "Compaq Netelligent 10/100" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
237 "Compaq Netelligent 10/100 Proliant" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
239 "Compaq Netelligent 10/100 Dual Port" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
241 "Compaq NetFlex-3/P Integrated" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
243 "Compaq NetFlex-3/P" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
245 "Compaq NetFlex 3/P w/ BNC" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
247 "Compaq Netelligent 10/100 TX Embedded UTP" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
249 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
251 "Compaq Netelligent 10/100 TX UTP" },
252 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
253 "Olicom OC-2183/2185" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
255 "Olicom OC-2325" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
257 "Olicom OC-2326 10/100 TX UTP" },
258 { 0, 0, NULL }
259 };
260
261 static int tl_probe (device_t);
262 static int tl_attach (device_t);
263 static int tl_detach (device_t);
264 static int tl_intvec_rxeoc (void *, u_int32_t);
265 static int tl_intvec_txeoc (void *, u_int32_t);
266 static int tl_intvec_txeof (void *, u_int32_t);
267 static int tl_intvec_rxeof (void *, u_int32_t);
268 static int tl_intvec_adchk (void *, u_int32_t);
269 static int tl_intvec_netsts (void *, u_int32_t);
270
271 static int tl_newbuf (struct tl_softc *,
272 struct tl_chain_onefrag *);
273 static void tl_stats_update (void *);
274 static void tl_stats_update_serialized(void *);
275 static int tl_encap (struct tl_softc *, struct tl_chain *,
276 struct mbuf *);
277
278 static void tl_intr (void *);
279 static void tl_start (struct ifnet *);
280 static int tl_ioctl (struct ifnet *, u_long, caddr_t,
281 struct ucred *);
282 static void tl_init (void *);
283 static void tl_stop (struct tl_softc *);
284 static void tl_watchdog (struct ifnet *);
285 static void tl_shutdown (device_t);
286 static int tl_ifmedia_upd (struct ifnet *);
287 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
288
289 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
290 static u_int8_t tl_eeprom_getbyte (struct tl_softc *,
291 int, u_int8_t *);
292 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
293
294 static void tl_mii_sync (struct tl_softc *);
295 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
296 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
297 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
298 static int tl_miibus_readreg (device_t, int, int);
299 static int tl_miibus_writereg (device_t, int, int, int);
300 static void tl_miibus_statchg (device_t);
301
302 static void tl_setmode (struct tl_softc *, int);
303 static int tl_calchash (caddr_t);
304 static void tl_setmulti (struct tl_softc *);
305 static void tl_setfilt (struct tl_softc *, caddr_t, int);
306 static void tl_softreset (struct tl_softc *, int);
307 static void tl_hardreset (device_t);
308 static int tl_list_rx_init (struct tl_softc *);
309 static int tl_list_tx_init (struct tl_softc *);
310
311 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
312 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
313 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
314 static void tl_dio_write8 (struct tl_softc *, int, int);
315 static void tl_dio_write16 (struct tl_softc *, int, int);
316 static void tl_dio_write32 (struct tl_softc *, int, int);
317 static void tl_dio_setbit (struct tl_softc *, int, int);
318 static void tl_dio_clrbit (struct tl_softc *, int, int);
319 static void tl_dio_setbit16 (struct tl_softc *, int, int);
320 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
321
322 #ifdef TL_USEIOSPACE
323 #define TL_RES SYS_RES_IOPORT
324 #define TL_RID TL_PCI_LOIO
325 #else
326 #define TL_RES SYS_RES_MEMORY
327 #define TL_RID TL_PCI_LOMEM
328 #endif
329
330 static device_method_t tl_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, tl_probe),
333 DEVMETHOD(device_attach, tl_attach),
334 DEVMETHOD(device_detach, tl_detach),
335 DEVMETHOD(device_shutdown, tl_shutdown),
336
337 /* bus interface */
338 DEVMETHOD(bus_print_child, bus_generic_print_child),
339 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340
341 /* MII interface */
342 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
343 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
344 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
345
346 { 0, 0 }
347 };
348
349 static driver_t tl_driver = {
350 "tl",
351 tl_methods,
352 sizeof(struct tl_softc)
353 };
354
355 static devclass_t tl_devclass;
356
357 DECLARE_DUMMY_MODULE(if_tl);
358 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
359 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
360
361 static u_int8_t
362 tl_dio_read8(struct tl_softc *sc, int reg)
363 {
364 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
365 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
366 }
367
368 static u_int16_t
369 tl_dio_read16(struct tl_softc *sc, int reg)
370 {
371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
372 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
373 }
374
375 static u_int32_t
376 tl_dio_read32(struct tl_softc *sc, int reg)
377 {
378 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
379 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
380 }
381
382 static void
383 tl_dio_write8(struct tl_softc *sc, int reg, int val)
384 {
385 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
386 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
387 return;
388 }
389
390 static void
391 tl_dio_write16(struct tl_softc *sc, int reg, int val)
392 {
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
394 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
395 return;
396 }
397
398 static void
399 tl_dio_write32(struct tl_softc *sc, int reg, int val)
400 {
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
403 return;
404 }
405
406 static void
407 tl_dio_setbit(struct tl_softc *sc, int reg, int bit)
408 {
409 u_int8_t f;
410
411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
412 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
413 f |= bit;
414 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
415
416 return;
417 }
418
419 static void
420 tl_dio_clrbit(struct tl_softc *sc, int reg, int bit)
421 {
422 u_int8_t f;
423
424 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
425 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
426 f &= ~bit;
427 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
428
429 return;
430 }
431
432 static void
433 tl_dio_setbit16(struct tl_softc *sc, int reg, int bit)
434 {
435 u_int16_t f;
436
437 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
438 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
439 f |= bit;
440 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
441
442 return;
443 }
444
445 static void
446 tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit)
447 {
448 u_int16_t f;
449
450 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
451 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
452 f &= ~bit;
453 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
454
455 return;
456 }
457
458 /*
459 * Send an instruction or address to the EEPROM, check for ACK.
460 */
461 static u_int8_t
462 tl_eeprom_putbyte(struct tl_softc *sc, int byte)
463 {
464 int i, ack = 0;
465
466 /*
467 * Make sure we're in TX mode.
468 */
469 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
470
471 /*
472 * Feed in each bit and stobe the clock.
473 */
474 for (i = 0x80; i; i >>= 1) {
475 if (byte & i) {
476 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
477 } else {
478 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
479 }
480 DELAY(1);
481 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
482 DELAY(1);
483 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
484 }
485
486 /*
487 * Turn off TX mode.
488 */
489 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
490
491 /*
492 * Check for ack.
493 */
494 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
495 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
496 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
497
498 return(ack);
499 }
500
501 /*
502 * Read a byte of data stored in the EEPROM at address 'addr.'
503 */
504 static u_int8_t
505 tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest)
506 {
507 int i;
508 u_int8_t byte = 0;
509
510 tl_dio_write8(sc, TL_NETSIO, 0);
511
512 EEPROM_START;
513
514 /*
515 * Send write control code to EEPROM.
516 */
517 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
518 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
519 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
520 return(1);
521 }
522
523 /*
524 * Send address of byte we want to read.
525 */
526 if (tl_eeprom_putbyte(sc, addr)) {
527 if_printf(&sc->arpcom.ac_if, "failed to send address, "
528 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
529 return(1);
530 }
531
532 EEPROM_STOP;
533 EEPROM_START;
534 /*
535 * Send read control code to EEPROM.
536 */
537 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
538 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
539 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
540 return(1);
541 }
542
543 /*
544 * Start reading bits from EEPROM.
545 */
546 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
547 for (i = 0x80; i; i >>= 1) {
548 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
549 DELAY(1);
550 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
551 byte |= i;
552 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
553 DELAY(1);
554 }
555
556 EEPROM_STOP;
557
558 /*
559 * No ACK generated for read, so just return byte.
560 */
561
562 *dest = byte;
563
564 return(0);
565 }
566
567 /*
568 * Read a sequence of bytes from the EEPROM.
569 */
570 static int
571 tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt)
572 {
573 int err = 0, i;
574 u_int8_t byte = 0;
575
576 for (i = 0; i < cnt; i++) {
577 err = tl_eeprom_getbyte(sc, off + i, &byte);
578 if (err)
579 break;
580 *(dest + i) = byte;
581 }
582
583 return(err ? 1 : 0);
584 }
585
586 static void
587 tl_mii_sync(struct tl_softc *sc)
588 {
589 int i;
590
591 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
592
593 for (i = 0; i < 32; i++) {
594 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
595 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
596 }
597
598 return;
599 }
600
601 static void
602 tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt)
603 {
604 int i;
605
606 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
607 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
608 if (bits & i) {
609 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
610 } else {
611 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
612 }
613 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
614 }
615 }
616
617 static int
618 tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame)
619 {
620 int i, ack;
621 int minten = 0;
622
623 tl_mii_sync(sc);
624
625 /*
626 * Set up frame for RX.
627 */
628 frame->mii_stdelim = TL_MII_STARTDELIM;
629 frame->mii_opcode = TL_MII_READOP;
630 frame->mii_turnaround = 0;
631 frame->mii_data = 0;
632
633 /*
634 * Turn off MII interrupt by forcing MINTEN low.
635 */
636 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
637 if (minten) {
638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
639 }
640
641 /*
642 * Turn on data xmit.
643 */
644 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
645
646 /*
647 * Send command/address info.
648 */
649 tl_mii_send(sc, frame->mii_stdelim, 2);
650 tl_mii_send(sc, frame->mii_opcode, 2);
651 tl_mii_send(sc, frame->mii_phyaddr, 5);
652 tl_mii_send(sc, frame->mii_regaddr, 5);
653
654 /*
655 * Turn off xmit.
656 */
657 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
658
659 /* Idle bit */
660 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
661 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
662
663 /* Check for ack */
664 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
665 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
666
667 /* Complete the cycle */
668 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
669
670 /*
671 * Now try reading data bits. If the ack failed, we still
672 * need to clock through 16 cycles to keep the PHYs in sync.
673 */
674 if (ack) {
675 for(i = 0; i < 16; i++) {
676 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
677 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
678 }
679 goto fail;
680 }
681
682 for (i = 0x8000; i; i >>= 1) {
683 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
684 if (!ack) {
685 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
686 frame->mii_data |= i;
687 }
688 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
689 }
690
691 fail:
692
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
695
696 /* Reenable interrupts */
697 if (minten) {
698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
699 }
700
701 if (ack)
702 return(1);
703 return(0);
704 }
705
706 static int
707 tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame)
708 {
709 int minten;
710
711 tl_mii_sync(sc);
712
713 /*
714 * Set up frame for TX.
715 */
716
717 frame->mii_stdelim = TL_MII_STARTDELIM;
718 frame->mii_opcode = TL_MII_WRITEOP;
719 frame->mii_turnaround = TL_MII_TURNAROUND;
720
721 /*
722 * Turn off MII interrupt by forcing MINTEN low.
723 */
724 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
725 if (minten) {
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
727 }
728
729 /*
730 * Turn on data output.
731 */
732 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
733
734 tl_mii_send(sc, frame->mii_stdelim, 2);
735 tl_mii_send(sc, frame->mii_opcode, 2);
736 tl_mii_send(sc, frame->mii_phyaddr, 5);
737 tl_mii_send(sc, frame->mii_regaddr, 5);
738 tl_mii_send(sc, frame->mii_turnaround, 2);
739 tl_mii_send(sc, frame->mii_data, 16);
740
741 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
742 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
743
744 /*
745 * Turn off xmit.
746 */
747 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
748
749 /* Reenable interrupts */
750 if (minten)
751 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
752
753 return(0);
754 }
755
756 static int
757 tl_miibus_readreg(device_t dev, int phy, int reg)
758 {
759 struct tl_softc *sc;
760 struct tl_mii_frame frame;
761
762 sc = device_get_softc(dev);
763 bzero((char *)&frame, sizeof(frame));
764
765 frame.mii_phyaddr = phy;
766 frame.mii_regaddr = reg;
767 tl_mii_readreg(sc, &frame);
768
769 return(frame.mii_data);
770 }
771
772 static int
773 tl_miibus_writereg(device_t dev, int phy, int reg, int data)
774 {
775 struct tl_softc *sc;
776 struct tl_mii_frame frame;
777
778 sc = device_get_softc(dev);
779 bzero((char *)&frame, sizeof(frame));
780
781 frame.mii_phyaddr = phy;
782 frame.mii_regaddr = reg;
783 frame.mii_data = data;
784
785 tl_mii_writereg(sc, &frame);
786
787 return(0);
788 }
789
790 static void
791 tl_miibus_statchg(device_t dev)
792 {
793 struct tl_softc *sc;
794 struct mii_data *mii;
795
796 sc = device_get_softc(dev);
797 mii = device_get_softc(sc->tl_miibus);
798
799 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
800 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
801 } else {
802 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
803 }
804
805 return;
806 }
807
808 /*
809 * Set modes for bitrate devices.
810 */
811 static void
812 tl_setmode(struct tl_softc *sc, int media)
813 {
814 if (IFM_SUBTYPE(media) == IFM_10_5)
815 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
816 if (IFM_SUBTYPE(media) == IFM_10_T) {
817 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
818 if ((media & IFM_GMASK) == IFM_FDX) {
819 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
820 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
821 } else {
822 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
823 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
824 }
825 }
826
827 return;
828 }
829
830 /*
831 * Calculate the hash of a MAC address for programming the multicast hash
832 * table. This hash is simply the address split into 6-bit chunks
833 * XOR'd, e.g.
834 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
835 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
836 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
837 * the folded 24-bit value is split into 6-bit portions and XOR'd.
838 */
839 static int
840 tl_calchash(caddr_t addr)
841 {
842 int t;
843
844 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
845 (addr[2] ^ addr[5]);
846 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
847 }
848
849 /*
850 * The ThunderLAN has a perfect MAC address filter in addition to
851 * the multicast hash filter. The perfect filter can be programmed
852 * with up to four MAC addresses. The first one is always used to
853 * hold the station address, which leaves us free to use the other
854 * three for multicast addresses.
855 */
856 static void
857 tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot)
858 {
859 int i;
860 u_int16_t regaddr;
861
862 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
863
864 for (i = 0; i < ETHER_ADDR_LEN; i++)
865 tl_dio_write8(sc, regaddr + i, *(addr + i));
866
867 return;
868 }
869
870 /*
871 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
872 * linked list. This is fine, except addresses are added from the head
873 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
874 * group to always be in the perfect filter, but as more groups are added,
875 * the 224.0.0.1 entry (which is always added first) gets pushed down
876 * the list and ends up at the tail. So after 3 or 4 multicast groups
877 * are added, the all-hosts entry gets pushed out of the perfect filter
878 * and into the hash table.
879 *
880 * Because the multicast list is a doubly-linked list as opposed to a
881 * circular queue, we don't have the ability to just grab the tail of
882 * the list and traverse it backwards. Instead, we have to traverse
883 * the list once to find the tail, then traverse it again backwards to
884 * update the multicast filter.
885 */
886 static void
887 tl_setmulti(struct tl_softc *sc)
888 {
889 struct ifnet *ifp;
890 u_int32_t hashes[2] = { 0, 0 };
891 int h, i;
892 struct ifmultiaddr *ifma;
893 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
894 ifp = &sc->arpcom.ac_if;
895
896 /* First, zot all the existing filters. */
897 for (i = 1; i < 4; i++)
898 tl_setfilt(sc, (caddr_t)&dummy, i);
899 tl_dio_write32(sc, TL_HASH1, 0);
900 tl_dio_write32(sc, TL_HASH2, 0);
901
902 /* Now program new ones. */
903 if (ifp->if_flags & IFF_ALLMULTI) {
904 hashes[0] = 0xFFFFFFFF;
905 hashes[1] = 0xFFFFFFFF;
906 } else {
907 i = 1;
908 /* First find the tail of the list. */
909 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
910 ifma = ifma->ifma_link.le_next) {
911 if (ifma->ifma_link.le_next == NULL)
912 break;
913 }
914 /* Now traverse the list backwards. */
915 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
916 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
917 if (ifma->ifma_addr->sa_family != AF_LINK)
918 continue;
919 /*
920 * Program the first three multicast groups
921 * into the perfect filter. For all others,
922 * use the hash table.
923 */
924 if (i < 4) {
925 tl_setfilt(sc,
926 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
927 i++;
928 continue;
929 }
930
931 h = tl_calchash(
932 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
933 if (h < 32)
934 hashes[0] |= (1 << h);
935 else
936 hashes[1] |= (1 << (h - 32));
937 }
938 }
939
940 tl_dio_write32(sc, TL_HASH1, hashes[0]);
941 tl_dio_write32(sc, TL_HASH2, hashes[1]);
942
943 return;
944 }
945
946 /*
947 * This routine is recommended by the ThunderLAN manual to insure that
948 * the internal PHY is powered up correctly. It also recommends a one
949 * second pause at the end to 'wait for the clocks to start' but in my
950 * experience this isn't necessary.
951 */
952 static void
953 tl_hardreset(device_t dev)
954 {
955 struct tl_softc *sc;
956 int i;
957 u_int16_t flags;
958
959 sc = device_get_softc(dev);
960
961 tl_mii_sync(sc);
962
963 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
964
965 for (i = 0; i < MII_NPHY; i++)
966 tl_miibus_writereg(dev, i, MII_BMCR, flags);
967
968 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
969 DELAY(50000);
970 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
971 tl_mii_sync(sc);
972 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
973
974 DELAY(50000);
975 return;
976 }
977
978 static void
979 tl_softreset(struct tl_softc *sc, int internal)
980 {
981 u_int32_t cmd, dummy, i;
982
983 /* Assert the adapter reset bit. */
984 CMD_SET(sc, TL_CMD_ADRST);
985
986 /* Turn off interrupts */
987 CMD_SET(sc, TL_CMD_INTSOFF);
988
989 /* First, clear the stats registers. */
990 for (i = 0; i < 5; i++)
991 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
992
993 /* Clear Areg and Hash registers */
994 for (i = 0; i < 8; i++)
995 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
996
997 /*
998 * Set up Netconfig register. Enable one channel and
999 * one fragment mode.
1000 */
1001 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1002 if (internal && !sc->tl_bitrate) {
1003 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1004 } else {
1005 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1006 }
1007
1008 /* Handle cards with bitrate devices. */
1009 if (sc->tl_bitrate)
1010 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1011
1012 /*
1013 * Load adapter irq pacing timer and tx threshold.
1014 * We make the transmit threshold 1 initially but we may
1015 * change that later.
1016 */
1017 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1018 cmd |= TL_CMD_NES;
1019 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1020 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1021 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1022
1023 /* Unreset the MII */
1024 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1025
1026 /* Take the adapter out of reset */
1027 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1028
1029 /* Wait for things to settle down a little. */
1030 DELAY(500);
1031
1032 return;
1033 }
1034
1035 /*
1036 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1037 * against our list and return its name if we find a match.
1038 */
1039 static int
1040 tl_probe(device_t dev)
1041 {
1042 struct tl_type *t;
1043
1044 t = tl_devs;
1045
1046 while(t->tl_name != NULL) {
1047 if ((pci_get_vendor(dev) == t->tl_vid) &&
1048 (pci_get_device(dev) == t->tl_did)) {
1049 device_set_desc(dev, t->tl_name);
1050 return(0);
1051 }
1052 t++;
1053 }
1054
1055 return(ENXIO);
1056 }
1057
1058 static int
1059 tl_attach(device_t dev)
1060 {
1061 int i;
1062 u_int16_t did, vid;
1063 struct tl_type *t;
1064 struct ifnet *ifp;
1065 struct tl_softc *sc;
1066 int error = 0, rid;
1067 uint8_t eaddr[ETHER_ADDR_LEN];
1068
1069 vid = pci_get_vendor(dev);
1070 did = pci_get_device(dev);
1071 sc = device_get_softc(dev);
1072
1073 t = tl_devs;
1074 while(t->tl_name != NULL) {
1075 if (vid == t->tl_vid && did == t->tl_did)
1076 break;
1077 t++;
1078 }
1079
1080 KKASSERT(t->tl_name != NULL);
1081
1082 pci_enable_busmaster(dev);
1083
1084 #ifdef TL_USEIOSPACE
1085 rid = TL_PCI_LOIO;
1086 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1087 RF_ACTIVE);
1088
1089 /*
1090 * Some cards have the I/O and memory mapped address registers
1091 * reversed. Try both combinations before giving up.
1092 */
1093 if (sc->tl_res == NULL) {
1094 rid = TL_PCI_LOMEM;
1095 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1096 RF_ACTIVE);
1097 }
1098 #else
1099 rid = TL_PCI_LOMEM;
1100 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1101 RF_ACTIVE);
1102 if (sc->tl_res == NULL) {
1103 rid = TL_PCI_LOIO;
1104 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1105 RF_ACTIVE);
1106 }
1107 #endif
1108
1109 if (sc->tl_res == NULL) {
1110 device_printf(dev, "couldn't map ports/memory\n");
1111 error = ENXIO;
1112 return(error);
1113 }
1114
1115 sc->tl_btag = rman_get_bustag(sc->tl_res);
1116 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1117
1118 #ifdef notdef
1119 /*
1120 * The ThunderLAN manual suggests jacking the PCI latency
1121 * timer all the way up to its maximum value. I'm not sure
1122 * if this is really necessary, but what the manual wants,
1123 * the manual gets.
1124 */
1125 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1126 command |= 0x0000FF00;
1127 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1128 #endif
1129
1130 /* Allocate interrupt */
1131 rid = 0;
1132 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1133 RF_SHAREABLE | RF_ACTIVE);
1134
1135 if (sc->tl_irq == NULL) {
1136 device_printf(dev, "couldn't map interrupt\n");
1137 error = ENXIO;
1138 goto fail;
1139 }
1140
1141 /*
1142 * Now allocate memory for the TX and RX lists.
1143 */
1144 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1145 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
1146
1147 if (sc->tl_ldata == NULL) {
1148 device_printf(dev, "no memory for list buffers!\n");
1149 error = ENXIO;
1150 goto fail;
1151 }
1152
1153 sc->tl_dinfo = t;
1154 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1155 sc->tl_eeaddr = TL_EEPROM_EADDR;
1156 if (t->tl_vid == OLICOM_VENDORID)
1157 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1158
1159 /* Reset the adapter. */
1160 tl_softreset(sc, 1);
1161 tl_hardreset(dev);
1162 tl_softreset(sc, 1);
1163
1164 ifp = &sc->arpcom.ac_if;
1165 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1166
1167 /*
1168 * Get station address from the EEPROM.
1169 */
1170 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1171 device_printf(dev, "failed to read station address\n");
1172 error = ENXIO;
1173 goto fail;
1174 }
1175
1176 /*
1177 * XXX Olicom, in its desire to be different from the
1178 * rest of the world, has done strange things with the
1179 * encoding of the station address in the EEPROM. First
1180 * of all, they store the address at offset 0xF8 rather
1181 * than at 0x83 like the ThunderLAN manual suggests.
1182 * Second, they store the address in three 16-bit words in
1183 * network byte order, as opposed to storing it sequentially
1184 * like all the other ThunderLAN cards. In order to get
1185 * the station address in a form that matches what the Olicom
1186 * diagnostic utility specifies, we have to byte-swap each
1187 * word. To make things even more confusing, neither 00:00:28
1188 * nor 00:00:24 appear in the IEEE OUI database.
1189 */
1190 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1191 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1192 u_int16_t *p;
1193 p = (u_int16_t *)&eaddr[i];
1194 *p = ntohs(*p);
1195 }
1196 }
1197
1198 ifp->if_softc = sc;
1199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1200 ifp->if_ioctl = tl_ioctl;
1201 ifp->if_start = tl_start;
1202 ifp->if_watchdog = tl_watchdog;
1203 ifp->if_init = tl_init;
1204 ifp->if_mtu = ETHERMTU;
1205 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1206 ifq_set_ready(&ifp->if_snd);
1207 callout_init(&sc->tl_stat_timer);
1208
1209 /* Reset the adapter again. */
1210 tl_softreset(sc, 1);
1211 tl_hardreset(dev);
1212 tl_softreset(sc, 1);
1213
1214 /*
1215 * Do MII setup. If no PHYs are found, then this is a
1216 * bitrate ThunderLAN chip that only supports 10baseT
1217 * and AUI/BNC.
1218 */
1219 if (mii_phy_probe(dev, &sc->tl_miibus,
1220 tl_ifmedia_upd, tl_ifmedia_sts)) {
1221 struct ifmedia *ifm;
1222 sc->tl_bitrate = 1;
1223 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1224 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1225 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1226 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1227 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1228 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1229 /* Reset again, this time setting bitrate mode. */
1230 tl_softreset(sc, 1);
1231 ifm = &sc->ifmedia;
1232 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1233 tl_ifmedia_upd(ifp);
1234 }
1235
1236 /*
1237 * Call MI attach routine.
1238 */
1239 ether_ifattach(ifp, eaddr, NULL);
1240
1241 error = bus_setup_intr(dev, sc->tl_irq, INTR_NETSAFE,
1242 tl_intr, sc, &sc->tl_intrhand,
1243 ifp->if_serializer);
1244
1245 if (error) {
1246 ether_ifdetach(ifp);
1247 device_printf(dev, "couldn't set up irq\n");
1248 goto fail;
1249 }
1250
1251 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->tl_irq));
1252 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1253
1254 return(0);
1255
1256 fail:
1257 tl_detach(dev);
1258 return(error);
1259 }
1260
1261 static int
1262 tl_detach(device_t dev)
1263 {
1264 struct tl_softc *sc = device_get_softc(dev);
1265 struct ifnet *ifp = &sc->arpcom.ac_if;
1266
1267 if (device_is_attached(dev)) {
1268 lwkt_serialize_enter(ifp->if_serializer);
1269 tl_stop(sc);
1270 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1271 lwkt_serialize_exit(ifp->if_serializer);
1272
1273 ether_ifdetach(ifp);
1274 }
1275
1276 if (sc->tl_miibus)
1277 device_delete_child(dev, sc->tl_miibus);
1278 bus_generic_detach(dev);
1279
1280 if (sc->tl_ldata)
1281 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1282 if (sc->tl_bitrate)
1283 ifmedia_removeall(&sc->ifmedia);
1284 if (sc->tl_irq)
1285 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1286 if (sc->tl_res)
1287 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1288
1289 return(0);
1290 }
1291
1292 /*
1293 * Initialize the transmit lists.
1294 */
1295 static int
1296 tl_list_tx_init(struct tl_softc *sc)
1297 {
1298 struct tl_chain_data *cd;
1299 struct tl_list_data *ld;
1300 int i;
1301
1302 cd = &sc->tl_cdata;
1303 ld = sc->tl_ldata;
1304 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1305 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1306 if (i == (TL_TX_LIST_CNT - 1))
1307 cd->tl_tx_chain[i].tl_next = NULL;
1308 else
1309 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1310 }
1311
1312 cd->tl_tx_free = &cd->tl_tx_chain[0];
1313 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1314 sc->tl_txeoc = 1;
1315
1316 return(0);
1317 }
1318
1319 /*
1320 * Initialize the RX lists and allocate mbufs for them.
1321 */
1322 static int
1323 tl_list_rx_init(struct tl_softc *sc)
1324 {
1325 struct tl_chain_data *cd;
1326 struct tl_list_data *ld;
1327 int i;
1328
1329 cd = &sc->tl_cdata;
1330 ld = sc->tl_ldata;
1331
1332 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1333 cd->tl_rx_chain[i].tl_ptr =
1334 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1335 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1336 return(ENOBUFS);
1337 if (i == (TL_RX_LIST_CNT - 1)) {
1338 cd->tl_rx_chain[i].tl_next = NULL;
1339 ld->tl_rx_list[i].tlist_fptr = 0;
1340 } else {
1341 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1342 ld->tl_rx_list[i].tlist_fptr =
1343 vtophys(&ld->tl_rx_list[i + 1]);
1344 }
1345 }
1346
1347 cd->tl_rx_head = &cd->tl_rx_chain[0];
1348 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1349
1350 return(0);
1351 }
1352
1353 static int
1354 tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c)
1355 {
1356 struct mbuf *m_new;
1357
1358 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1359 if (m_new == NULL)
1360 return (ENOBUFS);
1361
1362 c->tl_mbuf = m_new;
1363 c->tl_next = NULL;
1364 c->tl_ptr->tlist_frsize = MCLBYTES;
1365 c->tl_ptr->tlist_fptr = 0;
1366 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1367 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1368 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1369
1370 return(0);
1371 }
1372
1373 /*
1374 * Interrupt handler for RX 'end of frame' condition (EOF). This
1375 * tells us that a full ethernet frame has been captured and we need
1376 * to handle it.
1377 *
1378 * Reception is done using 'lists' which consist of a header and a
1379 * series of 10 data count/data address pairs that point to buffers.
1380 * Initially you're supposed to create a list, populate it with pointers
1381 * to buffers, then load the physical address of the list into the
1382 * ch_parm register. The adapter is then supposed to DMA the received
1383 * frame into the buffers for you.
1384 *
1385 * To make things as fast as possible, we have the chip DMA directly
1386 * into mbufs. This saves us from having to do a buffer copy: we can
1387 * just hand the mbufs directly to ether_input(). Once the frame has
1388 * been sent on its way, the 'list' structure is assigned a new buffer
1389 * and moved to the end of the RX chain. As long we we stay ahead of
1390 * the chip, it will always think it has an endless receive channel.
1391 *
1392 * If we happen to fall behind and the chip manages to fill up all of
1393 * the buffers, it will generate an end of channel interrupt and wait
1394 * for us to empty the chain and restart the receiver.
1395 */
1396 static int
1397 tl_intvec_rxeof(void *xsc, u_int32_t type)
1398 {
1399 struct tl_softc *sc;
1400 int r = 0, total_len = 0;
1401 struct ether_header *eh;
1402 struct mbuf *m;
1403 struct ifnet *ifp;
1404 struct tl_chain_onefrag *cur_rx;
1405
1406 sc = xsc;
1407 ifp = &sc->arpcom.ac_if;
1408
1409 while(sc->tl_cdata.tl_rx_head != NULL) {
1410 cur_rx = sc->tl_cdata.tl_rx_head;
1411 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1412 break;
1413 r++;
1414 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1415 m = cur_rx->tl_mbuf;
1416 total_len = cur_rx->tl_ptr->tlist_frsize;
1417
1418 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1419 ifp->if_ierrors++;
1420 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1421 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1422 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1423 continue;
1424 }
1425
1426 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1427 vtophys(cur_rx->tl_ptr);
1428 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1429 sc->tl_cdata.tl_rx_tail = cur_rx;
1430
1431 eh = mtod(m, struct ether_header *);
1432 m->m_pkthdr.rcvif = ifp;
1433 m->m_pkthdr.len = m->m_len = total_len;
1434
1435 /*
1436 * Note: when the ThunderLAN chip is in 'capture all
1437 * frames' mode, it will receive its own transmissions.
1438 * We drop don't need to process our own transmissions,
1439 * so we drop them here and continue.
1440 */
1441 /*if (ifp->if_flags & IFF_PROMISC && */
1442 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1443 ETHER_ADDR_LEN)) {
1444 m_freem(m);
1445 continue;
1446 }
1447
1448 ifp->if_input(ifp, m);
1449 }
1450
1451 return(r);
1452 }
1453
1454 /*
1455 * The RX-EOC condition hits when the ch_parm address hasn't been
1456 * initialized or the adapter reached a list with a forward pointer
1457 * of 0 (which indicates the end of the chain). In our case, this means
1458 * the card has hit the end of the receive buffer chain and we need to
1459 * empty out the buffers and shift the pointer back to the beginning again.
1460 */
1461 static int
1462 tl_intvec_rxeoc(void *xsc, u_int32_t type)
1463 {
1464 struct tl_softc *sc;
1465 int r;
1466 struct tl_chain_data *cd;
1467
1468
1469 sc = xsc;
1470 cd = &sc->tl_cdata;
1471
1472 /* Flush out the receive queue and ack RXEOF interrupts. */
1473 r = tl_intvec_rxeof(xsc, type);
1474 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1475 r = 1;
1476 cd->tl_rx_head = &cd->tl_rx_chain[0];
1477 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1478 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1479 r |= (TL_CMD_GO|TL_CMD_RT);
1480 return(r);
1481 }
1482
1483 static int
1484 tl_intvec_txeof(void *xsc, u_int32_t type)
1485 {
1486 struct tl_softc *sc;
1487 int r = 0;
1488 struct tl_chain *cur_tx;
1489
1490 sc = xsc;
1491
1492 /*
1493 * Go through our tx list and free mbufs for those
1494 * frames that have been sent.
1495 */
1496 while (sc->tl_cdata.tl_tx_head != NULL) {
1497 cur_tx = sc->tl_cdata.tl_tx_head;
1498 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1499 break;
1500 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1501
1502 r++;
1503 m_freem(cur_tx->tl_mbuf);
1504 cur_tx->tl_mbuf = NULL;
1505
1506 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1507 sc->tl_cdata.tl_tx_free = cur_tx;
1508 if (!cur_tx->tl_ptr->tlist_fptr)
1509 break;
1510 }
1511
1512 return(r);
1513 }
1514
1515 /*
1516 * The transmit end of channel interrupt. The adapter triggers this
1517 * interrupt to tell us it hit the end of the current transmit list.
1518 *
1519 * A note about this: it's possible for a condition to arise where
1520 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1521 * You have to avoid this since the chip expects things to go in a
1522 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1523 * When the TXEOF handler is called, it will free all of the transmitted
1524 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1525 * interrupt should be received and acknowledged before any more frames
1526 * are queued for transmission. If tl_statrt() is called after TXEOF
1527 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1528 * it could attempt to issue a transmit command prematurely.
1529 *
1530 * To guard against this, tl_start() will only issue transmit commands
1531 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1532 * can set this flag once tl_start() has cleared it.
1533 */
1534 static int
1535 tl_intvec_txeoc(void *xsc, u_int32_t type)
1536 {
1537 struct tl_softc *sc;
1538 struct ifnet *ifp;
1539 u_int32_t cmd;
1540
1541 sc = xsc;
1542 ifp = &sc->arpcom.ac_if;
1543
1544 /* Clear the timeout timer. */
1545 ifp->if_timer = 0;
1546
1547 if (sc->tl_cdata.tl_tx_head == NULL) {
1548 ifp->if_flags &= ~IFF_OACTIVE;
1549 sc->tl_cdata.tl_tx_tail = NULL;
1550 sc->tl_txeoc = 1;
1551 } else {
1552 sc->tl_txeoc = 0;
1553 /* First we have to ack the EOC interrupt. */
1554 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1555 /* Then load the address of the next TX list. */
1556 CSR_WRITE_4(sc, TL_CH_PARM,
1557 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1558 /* Restart TX channel. */
1559 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1560 cmd &= ~TL_CMD_RT;
1561 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1562 CMD_PUT(sc, cmd);
1563 return(0);
1564 }
1565
1566 return(1);
1567 }
1568
1569 static int
1570 tl_intvec_adchk(void *xsc, u_int32_t type)
1571 {
1572 struct tl_softc *sc;
1573
1574 sc = xsc;
1575
1576 if (type) {
1577 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
1578 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1579 }
1580
1581 tl_softreset(sc, 1);
1582 tl_stop(sc);
1583 tl_init(sc);
1584 CMD_SET(sc, TL_CMD_INTSON);
1585
1586 return(0);
1587 }
1588
1589 static int
1590 tl_intvec_netsts(void *xsc, u_int32_t type)
1591 {
1592 struct tl_softc *sc;
1593 u_int16_t netsts;
1594
1595 sc = xsc;
1596
1597 netsts = tl_dio_read16(sc, TL_NETSTS);
1598 tl_dio_write16(sc, TL_NETSTS, netsts);
1599
1600 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
1601
1602 return(1);
1603 }
1604
1605 static void
1606 tl_intr(void *xsc)
1607 {
1608 struct tl_softc *sc;
1609 struct ifnet *ifp;
1610 int r = 0;
1611 u_int32_t type = 0;
1612 u_int16_t ints = 0;
1613 u_int8_t ivec = 0;
1614
1615 sc = xsc;
1616
1617 /* Disable interrupts */
1618 ints = CSR_READ_2(sc, TL_HOST_INT);
1619 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1620 type = (ints << 16) & 0xFFFF0000;
1621 ivec = (ints & TL_VEC_MASK) >> 5;
1622 ints = (ints & TL_INT_MASK) >> 2;
1623
1624 ifp = &sc->arpcom.ac_if;
1625
1626 switch(ints) {
1627 case (TL_INTR_INVALID):
1628 #ifdef DIAGNOSTIC
1629 if_printf(ifp, "got an invalid interrupt!\n");
1630 #endif
1631 /* Re-enable interrupts but don't ack this one. */
1632 CMD_PUT(sc, type);
1633 r = 0;
1634 break;
1635 case (TL_INTR_TXEOF):
1636 r = tl_intvec_txeof((void *)sc, type);
1637 break;
1638 case (TL_INTR_TXEOC):
1639 r = tl_intvec_txeoc((void *)sc, type);
1640 break;
1641 case (TL_INTR_STATOFLOW):
1642 tl_stats_update_serialized(sc);
1643 r = 1;
1644 break;
1645 case (TL_INTR_RXEOF):
1646 r = tl_intvec_rxeof((void *)sc, type);
1647 break;
1648 case (TL_INTR_DUMMY):
1649 if_printf(ifp, "got a dummy interrupt\n");
1650 r = 1;
1651 break;
1652 case (TL_INTR_ADCHK):
1653 if (ivec)
1654 r = tl_intvec_adchk((void *)sc, type);
1655 else
1656 r = tl_intvec_netsts((void *)sc, type);
1657 break;
1658 case (TL_INTR_RXEOC):
1659 r = tl_intvec_rxeoc((void *)sc, type);
1660 break;
1661 default:
1662 if_printf(ifp, "bogus interrupt type\n");
1663 break;
1664 }
1665
1666 /* Re-enable interrupts */
1667 if (r) {
1668 CMD_PUT(sc, TL_CMD_ACK | r | type);
1669 }
1670
1671 if (!ifq_is_empty(&ifp->if_snd))
1672 if_devstart(ifp);
1673 }
1674
1675 static
1676 void
1677 tl_stats_update(void *xsc)
1678 {
1679 struct tl_softc *sc = xsc;
1680 struct ifnet *ifp = &sc->arpcom.ac_if;
1681
1682 lwkt_serialize_enter(ifp->if_serializer);
1683 tl_stats_update_serialized(xsc);
1684 lwkt_serialize_exit(ifp->if_serializer);
1685 }
1686
1687 static
1688 void
1689 tl_stats_update_serialized(void *xsc)
1690 {
1691 struct tl_softc *sc;
1692 struct ifnet *ifp;
1693 struct tl_stats tl_stats;
1694 struct mii_data *mii;
1695 u_int32_t *p;
1696
1697 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1698
1699 sc = xsc;
1700 ifp = &sc->arpcom.ac_if;
1701
1702 p = (u_int32_t *)&tl_stats;
1703
1704 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1705 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1706 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1707 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1708 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1709 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1710
1711 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1712 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1713 tl_stats.tl_tx_multi_collision;
1714 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1715 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1716 tl_rx_overrun(tl_stats);
1717 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1718
1719 if (tl_tx_underrun(tl_stats)) {
1720 u_int8_t tx_thresh;
1721 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1722 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1723 tx_thresh >>= 4;
1724 tx_thresh++;
1725 if_printf(ifp, "tx underrun -- increasing "
1726 "tx threshold to %d bytes\n",
1727 (64 * (tx_thresh * 4)));
1728 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1729 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1730 }
1731 }
1732
1733 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1734
1735 if (!sc->tl_bitrate) {
1736 mii = device_get_softc(sc->tl_miibus);
1737 mii_tick(mii);
1738 }
1739 }
1740
1741 /*
1742 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1743 * pointers to the fragment pointers.
1744 */
1745 static int
1746 tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head)
1747 {
1748 int frag = 0;
1749 struct tl_frag *f = NULL;
1750 int total_len;
1751 struct mbuf *m;
1752
1753 /*
1754 * Start packing the mbufs in this chain into
1755 * the fragment pointers. Stop when we run out
1756 * of fragments or hit the end of the mbuf chain.
1757 */
1758 m = m_head;
1759 total_len = 0;
1760
1761 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1762 if (m->m_len != 0) {
1763 if (frag == TL_MAXFRAGS)
1764 break;
1765 total_len+= m->m_len;
1766 c->tl_ptr->tl_frag[frag].tlist_dadr =
1767 vtophys(mtod(m, vm_offset_t));
1768 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1769 frag++;
1770 }
1771 }
1772
1773 /*
1774 * Handle special cases.
1775 * Special case #1: we used up all 10 fragments, but
1776 * we have more mbufs left in the chain. Copy the
1777 * data into an mbuf cluster. Note that we don't
1778 * bother clearing the values in the other fragment
1779 * pointers/counters; it wouldn't gain us anything,
1780 * and would waste cycles.
1781 */
1782 if (m != NULL) {
1783 struct mbuf *m_new;
1784
1785 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA,
1786 M_PKTHDR, NULL);
1787 if (m_new == NULL) {
1788 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1789 return (1);
1790 }
1791 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1792 mtod(m_new, caddr_t));
1793 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1794 m_freem(m_head);
1795 m_head = m_new;
1796 f = &c->tl_ptr->tl_frag[0];
1797 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1798 f->tlist_dcnt = total_len = m_new->m_len;
1799 frag = 1;
1800 }
1801
1802 /*
1803 * Special case #2: the frame is smaller than the minimum
1804 * frame size. We have to pad it to make the chip happy.
1805 */
1806 if (total_len < TL_MIN_FRAMELEN) {
1807 if (frag == TL_MAXFRAGS) {
1808 if_printf(&sc->arpcom.ac_if, "all frags filled but "
1809 "frame still to small!\n");
1810 }
1811 f = &c->tl_ptr->tl_frag[frag];
1812 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1813 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1814 total_len += f->tlist_dcnt;
1815 frag++;
1816 }
1817
1818 c->tl_mbuf = m_head;
1819 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1820 c->tl_ptr->tlist_frsize = total_len;
1821 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1822 c->tl_ptr->tlist_fptr = 0;
1823
1824 return(0);
1825 }
1826
1827 /*
1828 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1829 * to the mbuf data regions directly in the transmit lists. We also save a
1830 * copy of the pointers since the transmit list fragment pointers are
1831 * physical addresses.
1832 */
1833 static void
1834 tl_start(struct ifnet *ifp)
1835 {
1836 struct tl_softc *sc;
1837 struct mbuf *m_head = NULL;
1838 u_int32_t cmd;
1839 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1840
1841 sc = ifp->if_softc;
1842
1843 /*
1844 * Check for an available queue slot. If there are none,
1845 * punt.
1846 */
1847 if (sc->tl_cdata.tl_tx_free == NULL) {
1848 ifp->if_flags |= IFF_OACTIVE;
1849 return;
1850 }
1851
1852 start_tx = sc->tl_cdata.tl_tx_free;
1853
1854 while(sc->tl_cdata.tl_tx_free != NULL) {
1855 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1856 if (m_head == NULL)
1857 break;
1858
1859 /* Pick a chain member off the free list. */
1860 cur_tx = sc->tl_cdata.tl_tx_free;
1861 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1862
1863 cur_tx->tl_next = NULL;
1864
1865 /* Pack the data into the list. */
1866 tl_encap(sc, cur_tx, m_head);
1867
1868 /* Chain it together */
1869 if (prev != NULL) {
1870 prev->tl_next = cur_tx;
1871 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1872 }
1873 prev = cur_tx;
1874
1875 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1876 }
1877
1878 /*
1879 * If there are no packets queued, bail.
1880 */
1881 if (cur_tx == NULL)
1882 return;
1883
1884 /*
1885 * That's all we can stands, we can't stands no more.
1886 * If there are no other transfers pending, then issue the
1887 * TX GO command to the adapter to start things moving.
1888 * Otherwise, just leave the data in the queue and let
1889 * the EOF/EOC interrupt handler send.
1890 */
1891 if (sc->tl_cdata.tl_tx_head == NULL) {
1892 sc->tl_cdata.tl_tx_head = start_tx;
1893 sc->tl_cdata.tl_tx_tail = cur_tx;
1894
1895 if (sc->tl_txeoc) {
1896 sc->tl_txeoc = 0;
1897 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1898 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1899 cmd &= ~TL_CMD_RT;
1900 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1901 CMD_PUT(sc, cmd);
1902 }
1903 } else {
1904 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1905 sc->tl_cdata.tl_tx_tail = cur_tx;
1906 }
1907
1908 /*
1909 * Set a timeout in case the chip goes out to lunch.
1910 */
1911 ifp->if_timer = 5;
1912
1913 return;
1914 }
1915
1916 static void
1917 tl_init(void *xsc)
1918 {
1919 struct tl_softc *sc = xsc;
1920 struct ifnet *ifp = &sc->arpcom.ac_if;
1921 struct mii_data *mii;
1922
1923 /*
1924 * Cancel pending I/O.
1925 */
1926 tl_stop(sc);
1927
1928 /* Initialize TX FIFO threshold */
1929 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1930 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1931
1932 /* Set PCI burst size */
1933 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1934
1935 /*
1936 * Set 'capture all frames' bit for promiscuous mode.
1937 */
1938 if (ifp->if_flags & IFF_PROMISC)
1939 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
1940 else
1941 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
1942
1943 /*
1944 * Set capture broadcast bit to capture broadcast frames.
1945 */
1946 if (ifp->if_flags & IFF_BROADCAST)
1947 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1948 else
1949 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1950
1951 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
1952
1953 /* Init our MAC address */
1954 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
1955
1956 /* Init multicast filter, if needed. */
1957 tl_setmulti(sc);
1958
1959 /* Init circular RX list. */
1960 if (tl_list_rx_init(sc) == ENOBUFS) {
1961 if_printf(ifp, "initialization failed: no "
1962 "memory for rx buffers\n");
1963 tl_stop(sc);
1964 return;
1965 }
1966
1967 /* Init TX pointers. */
1968 tl_list_tx_init(sc);
1969
1970 /* Enable PCI interrupts. */
1971 CMD_SET(sc, TL_CMD_INTSON);
1972
1973 /* Load the address of the rx list */
1974 CMD_SET(sc, TL_CMD_RT);
1975 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
1976
1977 if (!sc->tl_bitrate) {
1978 if (sc->tl_miibus != NULL) {
1979 mii = device_get_softc(sc->tl_miibus);
1980 mii_mediachg(mii);
1981 }
1982 }
1983
1984 /* Send the RX go command */
1985 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
1986
1987 ifp->if_flags |= IFF_RUNNING;
1988 ifp->if_flags &= ~IFF_OACTIVE;
1989
1990 /* Start the stats update counter */
1991 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1992 }
1993
1994 /*
1995 * Set media options.
1996 */
1997 static int
1998 tl_ifmedia_upd(struct ifnet *ifp)
1999 {
2000 struct tl_softc *sc;
2001 struct mii_data *mii = NULL;
2002
2003 sc = ifp->if_softc;
2004
2005 if (sc->tl_bitrate)
2006 tl_setmode(sc, sc->ifmedia.ifm_media);
2007 else {
2008 mii = device_get_softc(sc->tl_miibus);
2009 mii_mediachg(mii);
2010 }
2011
2012 return(0);
2013 }
2014
2015 /*
2016 * Report current media status.
2017 */
2018 static void
2019 tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2020 {
2021 struct tl_softc *sc;
2022 struct mii_data *mii;
2023
2024 sc = ifp->if_softc;
2025
2026 ifmr->ifm_active = IFM_ETHER;
2027
2028 if (sc->tl_bitrate) {
2029 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2030 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2031 else
2032 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2033 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2034 ifmr->ifm_active |= IFM_HDX;
2035 else
2036 ifmr->ifm_active |= IFM_FDX;
2037 return;
2038 } else {
2039 mii = device_get_softc(sc->tl_miibus);
2040 mii_pollstat(mii);
2041 ifmr->ifm_active = mii->mii_media_active;
2042 ifmr->ifm_status = mii->mii_media_status;
2043 }
2044
2045 return;
2046 }
2047
2048 static int
2049 tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2050 {
2051 struct tl_softc *sc = ifp->if_softc;
2052 struct ifreq *ifr = (struct ifreq *) data;
2053 int error = 0;
2054
2055 switch(command) {
2056 case SIOCSIFFLAGS:
2057 if (ifp->if_flags & IFF_UP) {
2058 if (ifp->if_flags & IFF_RUNNING &&
2059 ifp->if_flags & IFF_PROMISC &&
2060 !(sc->tl_if_flags & IFF_PROMISC)) {
2061 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2062 tl_setmulti(sc);
2063 } else if (ifp->if_flags & IFF_RUNNING &&
2064 !(ifp->if_flags & IFF_PROMISC) &&
2065 sc->tl_if_flags & IFF_PROMISC) {
2066 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2067 tl_setmulti(sc);
2068 } else
2069 tl_init(sc);
2070 } else {
2071 if (ifp->if_flags & IFF_RUNNING) {
2072 tl_stop(sc);
2073 }
2074 }
2075 sc->tl_if_flags = ifp->if_flags;
2076 error = 0;
2077 break;
2078 case SIOCADDMULTI:
2079 case SIOCDELMULTI:
2080 tl_setmulti(sc);
2081 error = 0;
2082 break;
2083 case SIOCSIFMEDIA:
2084 case SIOCGIFMEDIA:
2085 if (sc->tl_bitrate)
2086 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2087 else {
2088 struct mii_data *mii;
2089 mii = device_get_softc(sc->tl_miibus);
2090 error = ifmedia_ioctl(ifp, ifr,
2091 &mii->mii_media, command);
2092 }
2093 break;
2094 default:
2095 error = ether_ioctl(ifp, command, data);
2096 break;
2097 }
2098 return(error);
2099 }
2100
2101 static void
2102 tl_watchdog(struct ifnet *ifp)
2103 {
2104 struct tl_softc *sc;
2105
2106 sc = ifp->if_softc;
2107
2108 if_printf(ifp, "device timeout\n");
2109
2110 ifp->if_oerrors++;
2111
2112 tl_softreset(sc, 1);
2113 tl_init(sc);
2114
2115 return;
2116 }
2117
2118 /*
2119 * Stop the adapter and free any mbufs allocated to the
2120 * RX and TX lists.
2121 */
2122 static void
2123 tl_stop(struct tl_softc *sc)
2124 {
2125 int i;
2126 struct ifnet *ifp;
2127
2128 ifp = &sc->arpcom.ac_if;
2129
2130 /* Stop the stats updater. */
2131 callout_stop(&sc->tl_stat_timer);
2132
2133 /* Stop the transmitter */
2134 CMD_CLR(sc, TL_CMD_RT);
2135 CMD_SET(sc, TL_CMD_STOP);
2136 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2137
2138 /* Stop the receiver */
2139 CMD_SET(sc, TL_CMD_RT);
2140 CMD_SET(sc, TL_CMD_STOP);
2141 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2142
2143 /*
2144 * Disable host interrupts.
2145 */
2146 CMD_SET(sc, TL_CMD_INTSOFF);
2147
2148 /*
2149 * Clear list pointer.
2150 */
2151 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2152
2153 /*
2154 * Free the RX lists.
2155 */
2156 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2157 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2158 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2159 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2160 }
2161 }
2162 bzero((char *)&sc->tl_ldata->tl_rx_list,
2163 sizeof(sc->tl_ldata->tl_rx_list));
2164
2165 /*
2166 * Free the TX list buffers.
2167 */
2168 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2169 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2170 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2171 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2172 }
2173 }
2174 bzero((char *)&sc->tl_ldata->tl_tx_list,
2175 sizeof(sc->tl_ldata->tl_tx_list));
2176
2177 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2178
2179 return;
2180 }
2181
2182 /*
2183 * Stop all chip I/O so that the kernel's probe routines don't
2184 * get confused by errant DMAs when rebooting.
2185 */
2186 static void
2187 tl_shutdown(device_t dev)
2188 {
2189 struct tl_softc *sc;
2190
2191 sc = device_get_softc(dev);
2192
2193 tl_stop(sc);
2194
2195 return;
2196 }
DragonFly BSD