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HAMMER Utilities: MFC work to date.
[dragonfly.git] / sys / dev / netif / rtw / rtwreg.h
blobb444218a10326a43e0ed0e1bd4177bb751d9acbd
1 /*
2 * Copyright (c) 2004, 2005 David Young. All rights reserved.
3 *
4 * Programmed for NetBSD by David Young.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of David Young may not be used to endorse or promote
15 * products derived from this software without specific prior
16 * written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
22 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
29 * OF SUCH DAMAGE.
30 *
31 * $NetBSD: rtwreg.h,v 1.19 2006/03/10 23:37:35 dyoung Exp $
32 * $DragonFly: src/sys/dev/netif/rtw/rtwreg.h,v 1.3 2007/10/14 04:15:17 sephe Exp $
33 */
34
35 /* RTL8180L Host Control and Status Registers */
36
37 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes.
38 * Auto-loaded from EEPROM. Read by byte,
39 * by word, or by double word, but write
40 * only by double word.
41 */
42 #define RTW_IDR1 0x04
43
44 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */
45 #define RTW_MAR1 0x0c
46
47 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer
48 * Register, low word, 32b, read-only.
49 */
50 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */
51 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start
52 * Address, 32b, 256-byte alignment.
53 */
54 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start
55 * Address, 32b, 256-byte alignment.
56 */
57 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start
58 * Address, 32b, 256-byte alignment.
59 */
60
61 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */
62 #define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet,
63 * 0: use long PLCP header
64 */
65 #define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */
66 #define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK)
67 #define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK)
68 #define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK)
69 #define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK)
70
71 /* 8181 and 8180 docs conflict! */
72 #define RTW_BRSR_MBR8181_1MBPS __BIT(0)
73 #define RTW_BRSR_MBR8181_2MBPS __BIT(1)
74 #define RTW_BRSR_MBR8181_5MBPS __BIT(2)
75 #define RTW_BRSR_MBR8181_11MBPS __BIT(3)
76
77 #define RTW_BSSID 0x2e
78 /* BSSID, 6 bytes */
79 #define RTW_BSSID16 0x2e /* first two bytes */
80 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */
81 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */
82 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */
83 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */
84 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */
85 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */
86 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */
87
88 #define RTW_CR 0x37 /* Command Register, 8b */
89 #define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable
90 * transmitter & receiver, reinitialize FIFO.
91 * RTL8180L sets to 0 to signal completion.
92 */
93 #define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver
94 * by writing 1. RTL8180L indicates receiver
95 * is active with 1. After power-up, host
96 * must wait for reset before writing.
97 */
98 #define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter
99 * by writing 1. RTL8180L indicates transmitter
100 * is active with 1. After power-up, host
101 * must wait for reset before writing.
102 */
103 #define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables,
104 * 0 disables. XXX RTL8180, only?
105 */
106
107 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */
108 #define RTW_ISR 0x3e /* Interrupt status register, 16b */
109
110 #define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */
111 #define RTW_INTR_TIMEOUT __BIT(14) /* Time Out: 1 indicates
112 * RTW_TSFTR[0:31] = RTW_TINT
113 */
114 /* Beacon Time Out: time for host to prepare beacon:
115 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
116 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
117 */
118 #define RTW_INTR_BCNINT __BIT(13)
119 /* ATIM Time Out: ATIM interval will pass,
120 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
121 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
122 */
123 #define RTW_INTR_ATIMINT __BIT(12)
124 /* Tx Beacon Descriptor Error: beacon transmission aborted because frame Rx'd */
125 #define RTW_INTR_TBDER __BIT(11)
126 #define RTW_INTR_TBDOK __BIT(10) /* Tx Beacon Descriptor OK */
127 #define RTW_INTR_THPDER __BIT(9)/* Tx High Priority Descriptor Error:
128 * reached short/long retry limit
129 */
130 #define RTW_INTR_THPDOK __BIT(8)/* Tx High Priority Descriptor OK */
131 #define RTW_INTR_TNPDER __BIT(7)/* Tx Normal Priority Descriptor Error:
132 * reached short/long retry limit
133 */
134 #define RTW_INTR_TNPDOK __BIT(6)/* Tx Normal Priority Descriptor OK */
135 #define RTW_INTR_RXFOVW __BIT(5)/* Rx FIFO Overflow: either RDU (see below)
136 * or PCI bus too slow/busy
137 */
138 #define RTW_INTR_RDU __BIT(4)/* Rx Descriptor Unavailable */
139 #define RTW_INTR_TLPDER __BIT(3)/* Tx Normal Priority Descriptor Error
140 * reached short/long retry limit
141 */
142 #define RTW_INTR_TLPDOK __BIT(2)/* Tx Normal Priority Descriptor OK */
143 #define RTW_INTR_RER __BIT(1)/* Rx Error: CRC32 or ICV error */
144 #define RTW_INTR_ROK __BIT(0)/* Rx OK */
145
146 /* Convenient interrupt conjunctions. */
147 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK)
148 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
149 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\
150 RTW_INTR_TBDER|RTW_INTR_TBDOK)
151 #define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK)
152 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU)
153
154 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */
155 #define RTW_TCR_CWMIN __BIT(31)/* 1: CWmin = 8, 0: CWmin = 32. */
156 #define RTW_TCR_SWSEQ __BIT(30)/* 1: host assigns 802.11 sequence number,
157 * 0: hardware assigns sequence number
158 */
159 /* Hardware version ID, read-only */
160 #define RTW_TCR_HWVERID_MASK __BITS(29, 25)
161 #define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK)
162 #define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK)
163 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F
164
165 /* Set ACK/CTS Timeout (EIFS).
166 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
167 * 0: ACK rate = 1Mbps
168 */
169 #define RTW_TCR_SAT __BIT(24)
170 /* Max DMA Burst Size per Tx DMA Burst */
171 #define RTW_TCR_MXDMA_MASK __BITS(23,21)
172 #define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK)
173 #define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK)
174 #define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK)
175 #define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK)
176 #define RTW_TCR_MXDMA_256 __SHIFTIN(4, RTW_TCR_MXDMA_MASK)
177 #define RTW_TCR_MXDMA_512 __SHIFTIN(5, RTW_TCR_MXDMA_MASK)
178 #define RTW_TCR_MXDMA_1024 __SHIFTIN(6, RTW_TCR_MXDMA_MASK)
179 #define RTW_TCR_MXDMA_2048 __SHIFTIN(7, RTW_TCR_MXDMA_MASK)
180
181 /* disable 802.11 random backoff */
182 #define RTW_TCR_DISCW __BIT(20)
183
184 /* host lets RTL8180 append ICV to WEP packets */
185 #define RTW_TCR_ICV __BIT(19)
186
187 /* Loopback Test: disables TXI/TXQ outputs. */
188 #define RTW_TCR_LBK_MASK __BITS(18,17)
189 #define RTW_TCR_LBK_NORMAL __SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */
190 #define RTW_TCR_LBK_MAC __SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */
191 #define RTW_TCR_LBK_BBP __SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */
192 #define RTW_TCR_LBK_CONT __SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */
193
194 #define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32
195 * 1: host appends CRC32
196 *
197 * (I *think* this is right.
198 * The docs have a mysterious
199 * description in the
200 * passive voice.)
201 */
202 #define RTW_TCR_SRL_MASK __BITS(15,8) /* Short Retry Limit */
203 #define RTW_TCR_LRL_MASK __BITS(7,0) /* Long Retry Limit */
204
205 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */
206 /* only do Early Rx on packets longer than 1536 bytes */
207 #define RTW_RCR_ONLYERLPKT __BIT(31)
208 /* enable carrier sense method 2 */
209 #define RTW_RCR_ENCS2 __BIT(30)
210 /* enable carrier sense method 1 */
211 #define RTW_RCR_ENCS1 __BIT(29)
212 #define RTW_RCR_ENMARP __BIT(28) /* enable MAC auto-reset PHY */
213 /* Check BSSID/ToDS/FromDS: set "Link On" when received BSSID
214 * matches RTW_BSSID and received ToDS/FromDS are appropriate
215 * according to RTW_MSR_NETYPE.
216 */
217 #define RTW_RCR_CBSSID __BIT(23)
218 /* accept packets w/ PWRMGMT bit set */
219 #define RTW_RCR_APWRMGT __BIT(22)
220 /* when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept
221 * broadcast/multicast packets whose 3rd address matches RTL8180's MAC.
222 */
223 #define RTW_RCR_ADD3 __BIT(21)
224 #define RTW_RCR_AMF __BIT(20) /* accept management frames */
225 #define RTW_RCR_ACF __BIT(19) /* accept control frames */
226 #define RTW_RCR_ADF __BIT(18) /* accept data frames */
227 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
228 * bytes are received
229 */
230 #define RTW_RCR_RXFTH_MASK __BITS(15,13)
231 #define RTW_RCR_RXFTH_64 __SHIFTIN(2, RTW_RCR_RXFTH_MASK)
232 #define RTW_RCR_RXFTH_128 __SHIFTIN(3, RTW_RCR_RXFTH_MASK)
233 #define RTW_RCR_RXFTH_256 __SHIFTIN(4, RTW_RCR_RXFTH_MASK)
234 #define RTW_RCR_RXFTH_512 __SHIFTIN(5, RTW_RCR_RXFTH_MASK)
235 #define RTW_RCR_RXFTH_1024 __SHIFTIN(6, RTW_RCR_RXFTH_MASK)
236 #define RTW_RCR_RXFTH_WHOLE __SHIFTIN(7, RTW_RCR_RXFTH_MASK)
237
238 #define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */
239
240 /* Max DMA Burst Size per Rx DMA Burst */
241 #define RTW_RCR_MXDMA_MASK __BITS(10,8)
242 #define RTW_RCR_MXDMA_16 __SHIFTIN(0, RTW_RCR_MXDMA_MASK)
243 #define RTW_RCR_MXDMA_32 __SHIFTIN(1, RTW_RCR_MXDMA_MASK)
244 #define RTW_RCR_MXDMA_64 __SHIFTIN(2, RTW_RCR_MXDMA_MASK)
245 #define RTW_RCR_MXDMA_128 __SHIFTIN(3, RTW_RCR_MXDMA_MASK)
246 #define RTW_RCR_MXDMA_256 __SHIFTIN(4, RTW_RCR_MXDMA_MASK)
247 #define RTW_RCR_MXDMA_512 __SHIFTIN(5, RTW_RCR_MXDMA_MASK)
248 #define RTW_RCR_MXDMA_1024 __SHIFTIN(6, RTW_RCR_MXDMA_MASK)
249 #define RTW_RCR_MXDMA_UNLIMITED __SHIFTIN(7, RTW_RCR_MXDMA_MASK)
250
251 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */
252 #define RTW_RCR_9356SEL __BIT(6)
253
254 #define RTW_RCR_ACRC32 __BIT(5)/* accept frames w/ CRC32 errors */
255 #define RTW_RCR_AB __BIT(3)/* accept broadcast frames */
256 #define RTW_RCR_AM __BIT(2)/* accept multicast frames */
257 /* accept physical match frames. XXX means PLCP header ok? */
258 #define RTW_RCR_APM __BIT(1)
259 #define RTW_RCR_AAP __BIT(0)/* accept frames w/ destination */
260
261 /* Additional bits to set in monitor mode. */
262 #define RTW_RCR_MONITOR ( \
263 RTW_RCR_AAP | \
264 RTW_RCR_ACF | \
265 RTW_RCR_ACRC32 | \
266 RTW_RCR_AICV | \
267 0)
268
269 /* The packet filter bits. */
270 #define RTW_RCR_PKTFILTER_MASK (\
271 RTW_RCR_AAP | \
272 RTW_RCR_AB | \
273 RTW_RCR_ACF | \
274 RTW_RCR_ACRC32 | \
275 RTW_RCR_ADD3 | \
276 RTW_RCR_ADF | \
277 RTW_RCR_AICV | \
278 RTW_RCR_AM | \
279 RTW_RCR_AMF | \
280 RTW_RCR_APM | \
281 RTW_RCR_APWRMGT | \
282 0)
283
284 /* Receive power-management frames and mgmt/ctrl/data frames. */
285 #define RTW_RCR_PKTFILTER_DEFAULT ( \
286 RTW_RCR_ADF | \
287 RTW_RCR_AMF | \
288 RTW_RCR_APM | \
289 RTW_RCR_APWRMGT | \
290 0)
291
292 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */
293 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address,
294 * 32b, 256-byte alignment
295 */
296 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */
297 #define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */
298 #define RTW_9346CR_EEM_NORMAL __SHIFTIN(0, RTW_9346CR_EEM_MASK)
299 /* Load the EEPROM. Reset registers to defaults.
300 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
301 * XXX RTL8180 only?
302 */
303 #define RTW_9346CR_EEM_AUTOLOAD __SHIFTIN(1, RTW_9346CR_EEM_MASK)
304 /* Disable network & bus-master operations and enable
305 * _EECS, _EESK, _EEDI, _EEDO.
306 * XXX RTL8180 only?
307 */
308 #define RTW_9346CR_EEM_PROGRAM __SHIFTIN(2, RTW_9346CR_EEM_MASK)
309 /* Enable RTW_CONFIG[0123] registers. */
310 #define RTW_9346CR_EEM_CONFIG __SHIFTIN(3, RTW_9346CR_EEM_MASK)
311 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
312 * XXX RTL8180 only?
313 */
314 #define RTW_9346CR_EECS __BIT(3)
315 #define RTW_9346CR_EESK __BIT(2)
316 #define RTW_9346CR_EEDI __BIT(1)
317 #define RTW_9346CR_EEDO __BIT(0) /* read-only */
318
319 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */
320 #define RTW_CONFIG0_WEP40 __BIT(7)/* implements 40-bit WEP,
321 * XXX RTL8180 only?
322 */
323 #define RTW_CONFIG0_WEP104 __BIT(6)/* implements 104-bit WEP,
324 * from EEPROM, read-only
325 * XXX RTL8180 only?
326 */
327 #define RTW_CONFIG0_LEDGPOEN __BIT(4)/* 1: RTW_PSR_LEDGPO[01] control
328 * LED[01] pins.
329 * 0: LED behavior defined by
330 * RTW_CONFIG1_LEDS10_MASK
331 * XXX RTL8180 only?
332 */
333 /* auxiliary power is present, read-only */
334 #define RTW_CONFIG0_AUXPWR __BIT(3)
335 /* Geographic Location, read-only */
336 #define RTW_CONFIG0_GL_MASK __BITS(1,0)
337 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
338 * work.
339 */
340 #define _RTW_CONFIG0_GL_USA __SHIFTIN(3, RTW_CONFIG0_GL_MASK)
341 #define RTW_CONFIG0_GL_EUROPE __SHIFTIN(2, RTW_CONFIG0_GL_MASK)
342 #define RTW_CONFIG0_GL_JAPAN __SHIFTIN(1, RTW_CONFIG0_GL_MASK)
343 #define RTW_CONFIG0_GL_USA __SHIFTIN(0, RTW_CONFIG0_GL_MASK)
344 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
345
346 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */
347
348 /* LED configuration. From EEPROM. Read/write.
349 *
350 * Setting LED0 LED1
351 * ------- ---- ----
352 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
353 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link
354 * RTW_CONFIG1_LEDS_TX_RX Tx Rx
355 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure
356 */
357 #define RTW_CONFIG1_LEDS_MASK __BITS(7,6)
358 #define RTW_CONFIG1_LEDS_ACT_INFRA __SHIFTIN(0, RTW_CONFIG1_LEDS_MASK)
359 #define RTW_CONFIG1_LEDS_ACT_LINK __SHIFTIN(1, RTW_CONFIG1_LEDS_MASK)
360 #define RTW_CONFIG1_LEDS_TX_RX __SHIFTIN(2, RTW_CONFIG1_LEDS_MASK)
361 #define RTW_CONFIG1_LEDS_LINKACT_INFRA __SHIFTIN(3, RTW_CONFIG1_LEDS_MASK)
362
363 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
364 *
365 * RTW_CONFIG1_LWACT
366 * 0 1
367 * RTW_CONFIG4_LWPTN 0 active high active low
368 * 1 positive pulse negative pulse
369 */
370 #define RTW_CONFIG1_LWACT __BIT(4)
371
372 #define RTW_CONFIG1_MEMMAP __BIT(3)/* using PCI memory space, read-only */
373 #define RTW_CONFIG1_IOMAP __BIT(2)/* using PCI I/O space, read-only */
374 #define RTW_CONFIG1_VPD __BIT(1)/* if set, VPD from offsets
375 * 0x40-0x7f in EEPROM are at
376 * registers 0x60-0x67 of PCI
377 * Configuration Space (XXX huh?)
378 */
379 #define RTW_CONFIG1_PMEN __BIT(0)/* Power Management Enable: TBD */
380
381 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */
382 #define RTW_CONFIG2_LCK __BIT(7)/* clocks are locked, read-only:
383 * Tx frequency & symbol clocks
384 * are derived from the same OSC
385 */
386 #define RTW_CONFIG2_ANT __BIT(6) /* diversity enabled, read-only */
387 #define RTW_CONFIG2_DPS __BIT(3) /* Descriptor Polling State: enable
388 * test mode.
389 */
390 #define RTW_CONFIG2_PAPESIGN __BIT(2) /* TBD, from EEPROM */
391 #define RTW_CONFIG2_PAPETIME_MASK __BITS(1,0) /* TBD, from EEPROM */
392
393 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */
394 #define RTW_ANAPARM_RFPOW0_MASK __BITS(30,28) /* undocumented bits
395 * which appear to
396 * control the power
397 * state of the RF
398 * components
399 */
400 #define RTW_ANAPARM_RFPOW_MASK \
401 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK)
402
403 #define RTW_ANAPARM_TXDACOFF __BIT(27) /* 1: disable Tx DAC,
404 * 0: enable
405 */
406 #define RTW_ANAPARM_RFPOW1_MASK __BITS(26,20) /* undocumented bits
407 * which appear to
408 * control the power
409 * state of the RF
410 * components
411 */
412
413 /*
414 * Maxim On/Sleep/Off control
415 */
416 #define RTW_ANAPARM_RFPOW_MAXIM_ON __SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK)
417
418 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
419 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
420
421 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
422 #define RTW_ANAPARM_RFPOW_MAXIM_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
423
424 /*
425 * RFMD On/Sleep/Off control
426 */
427 #define RTW_ANAPARM_RFPOW_RFMD_ON __SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK)
428
429 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
430 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
431
432 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
433 #define RTW_ANAPARM_RFPOW_RFMD_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
434
435 /*
436 * Philips On/Sleep/Off control
437 */
438 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \
439 __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
440 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \
441 __SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK)
442
443 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
444 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
445 __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
446
447 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
448 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
449 __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
450
451 #define RTW_ANAPARM_RFPOW_PHILIPS_ON __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
452
453 #define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented
454 * card-specific
455 * bits from the
456 * EEPROM.
457 */
458
459 #define RTW_MSR 0x58 /* Media Status Register, 8b */
460 /* Network Type and Link Status */
461 #define RTW_MSR_NETYPE_MASK __BITS(3,2)
462 /* AP, XXX RTL8181 only? */
463 #define RTW_MSR_NETYPE_AP_OK __SHIFTIN(3, RTW_MSR_NETYPE_MASK)
464 /* infrastructure link ok */
465 #define RTW_MSR_NETYPE_INFRA_OK __SHIFTIN(2, RTW_MSR_NETYPE_MASK)
466 /* ad-hoc link ok */
467 #define RTW_MSR_NETYPE_ADHOC_OK __SHIFTIN(1, RTW_MSR_NETYPE_MASK)
468 /* no link */
469 #define RTW_MSR_NETYPE_NOLINK __SHIFTIN(0, RTW_MSR_NETYPE_MASK)
470
471 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */
472 #define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */
473 #define RTW_CONFIG3_PARMEN __BIT(6) /* Set RTW_CONFIG3_PARMEN and
474 * RTW_9346CR_EEM_CONFIG to
475 * allow RTW_ANAPARM writes.
476 */
477 #define RTW_CONFIG3_MAGIC __BIT(5)/* Valid when RTW_CONFIG1_PMEN is
478 * set. If set, RTL8180 wakes up
479 * OS when Magic Packet is Rx'd.
480 */
481 #define RTW_CONFIG3_CARDBEN __BIT(3)/* Cardbus-related registers
482 * and functions are enabled,
483 * read-only. XXX RTL8180 only.
484 */
485 #define RTW_CONFIG3_CLKRUNEN __BIT(2)/* CLKRUN enabled, read-only.
486 * XXX RTL8180 only.
487 */
488 #define RTW_CONFIG3_FUNCREGEN __BIT(1)/* Function Registers Enabled,
489 * read-only. XXX RTL8180 only.
490 */
491 #define RTW_CONFIG3_FBTBEN __BIT(0)/* Fast back-to-back enabled,
492 * read-only.
493 */
494 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */
495 #define RTW_CONFIG4_VCOPDN __BIT(7)/* VCO Power Down
496 * 0: normal operation
497 * (power-on default)
498 * 1: power-down VCO, RF front-end,
499 * and most RTL8180 components.
500 */
501 #define RTW_CONFIG4_PWROFF __BIT(6)/* Power Off
502 * 0: normal operation
503 * (power-on default)
504 * 1: power-down RF front-end,
505 * and most RTL8180 components,
506 * but leave VCO on.
507 *
508 * XXX RFMD front-end only?
509 */
510 #define RTW_CONFIG4_PWRMGT __BIT(5)/* Power Management
511 * 0: normal operation
512 * (power-on default)
513 * 1: set Tx packet's PWRMGMT bit.
514 */
515 #define RTW_CONFIG4_LWPME __BIT(4)/* LANWAKE vs. PMEB: Cardbus-only
516 * 0: LWAKE & PMEB asserted
517 * simultaneously
518 * 1: LWAKE asserted only if
519 * both PMEB is asserted and
520 * ISOLATEB is low.
521 * XXX RTL8180 only.
522 */
523 #define RTW_CONFIG4_LWPTN __BIT(2)/* see RTW_CONFIG1_LWACT
524 * XXX RTL8180 only.
525 */
526 /* Radio Front-End Programming Method */
527 #define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0)
528 #define RTW_CONFIG4_RFTYPE_INTERSIL __SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK)
529 #define RTW_CONFIG4_RFTYPE_RFMD __SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK)
530 #define RTW_CONFIG4_RFTYPE_PHILIPS __SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK)
531
532 #define RTW_TESTR 0x5B /* TEST mode register, 8b */
533
534 #define RTW_PSR 0x5e /* Page Select Register, 8b */
535 #define RTW_PSR_GPO __BIT(7)/* Control/status of pin 52. */
536 #define RTW_PSR_GPI __BIT(6)/* Status of pin 64. */
537 #define RTW_PSR_LEDGPO1 __BIT(5)/* Status/control of LED1 pin if
538 * RTW_CONFIG0_LEDGPOEN is set.
539 */
540 #define RTW_PSR_LEDGPO0 __BIT(4)/* Status/control of LED0 pin if
541 * RTW_CONFIG0_LEDGPOEN is set.
542 */
543 #define RTW_PSR_UWF __BIT(1)/* Enable Unicast Wakeup Frame */
544 #define RTW_PSR_PSEN __BIT(0)/* 1: page 1, 0: page 0 */
545
546 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */
547 #define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */
548 #define RTW_SCR_KM_WEP104 __SHIFTIN(1, RTW_SCR_KM_MASK)
549 #define RTW_SCR_KM_WEP40 __SHIFTIN(0, RTW_SCR_KM_MASK)
550 #define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if
551 * neither RTW_CONFIG0_WEP40 nor
552 * RTW_CONFIG0_WEP104 is set.
553 */
554 #define RTW_SCR_RXSECON __BIT(0)/* Enable Rx WEP. Invalid if
555 * neither RTW_CONFIG0_WEP40 nor
556 * RTW_CONFIG0_WEP104 is set.
557 */
558
559 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */
560 #define RTW_BCNITV_BCNITV_MASK __BITS(9,0) /* TU between TBTT, written
561 * by host.
562 */
563 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */
564 #define RTW_ATIMWND_ATIMWND __BITS(9,0) /* ATIM Window length in TU,
565 * written by host.
566 */
567
568 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */
569 #define RTW_BINTRITV_BINTRITV __BITS(9,0) /* RTL8180 wakes host with
570 * RTW_INTR_BCNINT at BINTRITV
571 * microseconds before TBTT
572 */
573 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */
574 #define RTW_ATIMTRITV_ATIMTRITV __BITS(9,0) /* RTL8180 wakes host with
575 * RTW_INTR_ATIMINT at ATIMTRITV
576 * microseconds before end of
577 * ATIM Window
578 */
579
580 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */
581 #define RTW_PHYDELAY_REVC_MAGIC __BIT(3) /* Rev. C magic from reference
582 * driver
583 */
584 #define RTW_PHYDELAY_PHYDELAY __BITS(2,0) /* microsecond Tx delay between
585 * MAC and RF front-end
586 */
587 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */
588 #define RTW_CRCOUNT_MAGIC 0x4c
589
590 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */
591
592 #define RTW_BB 0x7c /* Baseband interface, 32b */
593 /* used for writing RTL8180's integrated baseband processor */
594 #define RTW_BB_RD_MASK __BITS(23,16) /* data to read */
595 #define RTW_BB_WR_MASK __BITS(15,8) /* data to write */
596 #define RTW_BB_WREN __BIT(7) /* write enable */
597 #define RTW_BB_ADDR_MASK __BITS(6,0) /* address */
598
599 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */
600 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */
601 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */
602
603 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */
604 #define RTW_PHYCFG_MAC_POLL __BIT(31) /* if !RTW_PHYCFG_HST,
605 * host sets. MAC clears
606 * after banging bits.
607 */
608 #define RTW_PHYCFG_HST __BIT(30) /* 1: host bangs bits
609 * 0: MAC bangs bits
610 */
611 #define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28)
612 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL __SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
613 #define RTW_PHYCFG_MAC_RFTYPE_RFMD __SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
614 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD
615 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS __SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
616 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24)
617 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0)
618 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24)
619 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK __BITS(11,8)
620 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK __BITS(7,0)
621 #define RTW_PHYCFG_HST_EN __BIT(2)
622 #define RTW_PHYCFG_HST_CLK __BIT(1)
623 #define RTW_PHYCFG_HST_DATA __BIT(0)
624
625 #define RTW_MAXIM_HIDATA_MASK __BITS(11,4)
626 #define RTW_MAXIM_LODATA_MASK __BITS(3,0)
627
628 /**
629 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
630 **/
631
632 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */
633 #define RTW_WAKEUP0H 0x88 /* 32b */
634
635 #define RTW_WAKEUP1L 0x8c
636 #define RTW_WAKEUP1H 0x90
637
638 #define RTW_WAKEUP2LL 0x94
639 #define RTW_WAKEUP2LH 0x98
640
641 #define RTW_WAKEUP2HL 0x9c
642 #define RTW_WAKEUP2HH 0xa0
643
644 #define RTW_WAKEUP3LL 0xa4
645 #define RTW_WAKEUP3LH 0xa8
646
647 #define RTW_WAKEUP3HL 0xac
648 #define RTW_WAKEUP3HH 0xb0
649
650 #define RTW_WAKEUP4LL 0xb4
651 #define RTW_WAKEUP4LH 0xb8
652
653 #define RTW_WAKEUP4HL 0xbc
654 #define RTW_WAKEUP4HH 0xc0
655
656 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */
657 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */
658 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */
659 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */
660 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */
661
662 /**
663 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
664 **/
665
666 /* Default Key Registers, each 128b
667 *
668 * If RTW_SCR_KM_WEP104, 104 lsb are the key.
669 * If RTW_SCR_KM_WEP40, 40 lsb are the key.
670 */
671 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */
672 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */
673 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */
674 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */
675
676 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */
677 #define RTW_CONFIG5_TXFIFOOK __BIT(7)/* Tx FIFO self-test pass, read-only */
678 #define RTW_CONFIG5_RXFIFOOK __BIT(6)/* Rx FIFO self-test pass, read-only */
679 #define RTW_CONFIG5_CALON __BIT(5)/* 1: start calibration cycle
680 * and raise AGCRESET pin.
681 * 0: lower AGCRESET pin
682 */
683 #define RTW_CONFIG5_EACPI __BIT(2)/* Enable ACPI Wake up, default 0 */
684 #define RTW_CONFIG5_LANWAKE __BIT(1)/* Enable LAN Wake signal,
685 * from EEPROM
686 */
687 #define RTW_CONFIG5_PMESTS __BIT(0)/* 1: both software & PCI Reset
688 * reset PME_Status
689 * 0: only software resets PME_Status
690 *
691 * From EEPROM.
692 */
693
694 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b,
695 * write-only.
696 */
697 #define RTW_TPPOLL_BQ __BIT(7)/* RTL8180 clears to notify host of a beacon
698 * Tx. Host writes have no effect.
699 */
700 #define RTW_TPPOLL_HPQ __BIT(6)/* Host writes 1 to notify RTL8180 of
701 * high-priority Tx packets, RTL8180 clears
702 * to after high-priority Tx is complete.
703 */
704 #define RTW_TPPOLL_NPQ __BIT(5)/* If RTW_CONFIG2_DPS is set,
705 * host writes 1 to notify RTL8180 of
706 * normal-priority Tx packets, RTL8180 clears
707 * after normal-priority Tx is complete.
708 *
709 * If RTW_CONFIG2_DPS is clear, host writes
710 * have no effect. RTL8180 clears after
711 * normal-priority Tx is complete.
712 */
713 #define RTW_TPPOLL_LPQ __BIT(4)/* Host writes 1 to notify RTL8180 of
714 * low-priority Tx packets, RTL8180 clears
715 * after low-priority Tx is complete.
716 */
717 #define RTW_TPPOLL_SBQ __BIT(3)/* Host writes 1 to tell RTL8180 to
718 * stop beacon DMA. This bit is invalid
719 * when RTW_CONFIG2_DPS is set.
720 */
721 #define RTW_TPPOLL_SHPQ __BIT(2)/* Host writes 1 to tell RTL8180 to
722 * stop high-priority DMA.
723 */
724 #define RTW_TPPOLL_SNPQ __BIT(1)/* Host writes 1 to tell RTL8180 to
725 * stop normal-priority DMA. This bit is invalid
726 * when RTW_CONFIG2_DPS is set.
727 */
728 #define RTW_TPPOLL_SLPQ __BIT(0)/* Host writes 1 to tell RTL8180 to
729 * stop low-priority DMA.
730 */
731
732 /* Start all queues. */
733 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
734 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ)
735 /* Check all queues' activity. */
736 #define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL
737 /* Stop all queues. */
738 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
739 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ)
740
741 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */
742 /* Contention Window: indicates number of contention windows before Tx
743 */
744 #define RTW_CWR_CW __BITS(9,0)
745
746 /* Retry Count Register, 16b, read-only */
747 #define RTW_RETRYCTR 0xde
748 /* Retry Count: indicates number of retries after Tx */
749 #define RTW_RETRYCTR_RETRYCT __BITS(7,0)
750
751 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register,
752 * 32b, 256-byte alignment.
753 */
754 /* Function Event Register, 32b, Cardbus only. Only valid when
755 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
756 */
757 #define RTW_FER 0xf0
758 #define RTW_FER_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
759 #define RTW_FER_GWAKE __BIT(4) /* General Wakeup */
760 /* Function Event Mask Register, 32b, Cardbus only. Only valid when
761 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
762 */
763 #define RTW_FEMR 0xf4
764 #define RTW_FEMR_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
765 #define RTW_FEMR_WKUP __BIT(14) /* Wakeup Mask */
766 #define RTW_FEMR_GWAKE __BIT(4) /* General Wakeup */
767 /* Function Present State Register, 32b, read-only, Cardbus only.
768 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
769 * are set.
770 */
771 #define RTW_FPSR 0xf8
772 #define RTW_FPSR_INTR __BIT(15) /* TBD */
773 #define RTW_FPSR_GWAKE __BIT(4) /* General Wakeup: TBD */
774 /* Function Force Event Register, 32b, write-only, Cardbus only.
775 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
776 * are set.
777 */
778 #define RTW_FFER 0xfc
779 #define RTW_FFER_INTR __BIT(15) /* TBD */
780 #define RTW_FFER_GWAKE __BIT(4) /* General Wakeup: TBD */
781
782 /* Serial EEPROM offsets */
783 #define RTW_SR_ID 0x00 /* 16b */
784 #define RTW_SR_VID 0x02 /* 16b */
785 #define RTW_SR_DID 0x04 /* 16b */
786 #define RTW_SR_SVID 0x06 /* 16b */
787 #define RTW_SR_SMID 0x08 /* 16b */
788 #define RTW_SR_MNGNT 0x0a
789 #define RTW_SR_MXLAT 0x0b
790 #define RTW_SR_RFCHIPID 0x0c
791 #define RTW_SR_CONFIG3 0x0d
792 #define RTW_SR_MAC 0x0e /* 6 bytes */
793 #define RTW_SR_CONFIG0 0x14
794 #define RTW_SR_CONFIG1 0x15
795 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */
796 #define RTW_SR_CONFIG2 0x18
797 #define RTW_SR_CONFIG4 0x19
798 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */
799 #define RTW_SR_TESTR 0x1e
800 #define RTW_SR_CONFIG5 0x1f
801 #define RTW_SR_TXPOWER1 0x20
802 #define RTW_SR_TXPOWER2 0x21
803 #define RTW_SR_TXPOWER3 0x22
804 #define RTW_SR_TXPOWER4 0x23
805 #define RTW_SR_TXPOWER5 0x24
806 #define RTW_SR_TXPOWER6 0x25
807 #define RTW_SR_TXPOWER7 0x26
808 #define RTW_SR_TXPOWER8 0x27
809 #define RTW_SR_TXPOWER9 0x28
810 #define RTW_SR_TXPOWER10 0x29
811 #define RTW_SR_TXPOWER11 0x2a
812 #define RTW_SR_TXPOWER12 0x2b
813 #define RTW_SR_TXPOWER13 0x2c
814 #define RTW_SR_TXPOWER14 0x2d
815 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */
816 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */
817 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */
818 #define RTW_SR_CISPOINTER 0x30 /* 16b */
819 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */
820 #define RTW_SR_RFPARM_DIGPHY __BIT(0) /* 1: digital PHY */
821 #define RTW_SR_RFPARM_DFLANTB __BIT(1) /* 1: antenna B is default */
822 #define RTW_SR_RFPARM_CS_MASK __BITS(2,3) /* carrier-sense type */
823 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */
824 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */
825 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */
826 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/
827
828 /*
829 * RTL8180 Transmit/Receive Descriptors
830 */
831
832 /* the first descriptor in each ring must be on a 256-byte boundary */
833 #define RTW_DESC_ALIGNMENT 256
834
835 /* Tx descriptor */
836 struct rtw_txdesc {
837 uint32_t td_ctl0;
838 uint32_t td_ctl1;
839 uint32_t td_buf;
840 uint32_t td_len;
841 uint32_t td_next;
842 uint32_t td_rsvd[3];
843 };
844
845 #define td_stat td_ctl0
846
847 #define RTW_TXCTL0_OWN __BIT(31) /* 1: ready to Tx */
848 #define RTW_TXCTL0_RSVD0 __BIT(30) /* reserved */
849 #define RTW_TXCTL0_FS __BIT(29) /* first segment */
850 #define RTW_TXCTL0_LS __BIT(28) /* last segment */
851
852 #define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */
853 #define RTW_TXCTL0_RATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RATE_MASK)
854 #define RTW_TXCTL0_RATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RATE_MASK)
855 #define RTW_TXCTL0_RATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RATE_MASK)
856 #define RTW_TXCTL0_RATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RATE_MASK)
857
858 #define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */
859
860 #define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */
861 #define RTW_TXCTL0_RTSRATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK)
862 #define RTW_TXCTL0_RTSRATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK)
863 #define RTW_TXCTL0_RTSRATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK)
864 #define RTW_TXCTL0_RTSRATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK)
865
866 #define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */
867 #define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment
868 * follows
869 */
870 /* add short PLCP preamble and header */
871 #define RTW_TXCTL0_SPLCP __BIT(16)
872 #define RTW_TXCTL0_KEYID_MASK __BITS(15,14) /* default key id */
873 #define RTW_TXCTL0_RSVD1_MASK __BITS(13,12) /* reserved */
874 #define RTW_TXCTL0_TPKTSIZE_MASK __BITS(11,0) /* Tx packet size
875 * in bytes
876 */
877
878 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN
879 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0
880 #define RTW_TXSTAT_FS RTW_TXCTL0_FS
881 #define RTW_TXSTAT_LS RTW_TXCTL0_LS
882 #define RTW_TXSTAT_RSVD1_MASK __BITS(27,16)
883 #define RTW_TXSTAT_TOK __BIT(15)
884 #define RTW_TXSTAT_RTSRETRY_MASK __BITS(14,8) /* RTS retry count */
885 #define RTW_TXSTAT_DRC_MASK __BITS(7,0) /* Data retry count */
886
887 #define RTW_TXCTL1_LENGEXT __BIT(31) /* supplements _LENGTH
888 * in packets sent 5.5Mb/s or
889 * faster
890 */
891 #define RTW_TXCTL1_LENGTH_MASK __BITS(30,16) /* PLCP length (microseconds) */
892 #define RTW_TXCTL1_RTSDUR_MASK __BITS(15,0) /* RTS Duration
893 * (microseconds)
894 */
895
896 #define RTW_TXLEN_LENGTH_MASK __BITS(11,0) /* Tx buffer length in bytes */
897
898 /* Rx descriptor */
899 struct rtw_rxdesc {
900 uint32_t rd_ctl;
901 uint32_t rd_rsvd0;
902 uint32_t rd_buf;
903 uint32_t rd_rsvd1;
904 };
905
906 #define rd_stat rd_ctl
907 #define rd_rssi rd_rsvd0
908 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */
909 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */
910
911 #define RTW_RXCTL_OWN __BIT(31) /* 1: owned by NIC */
912 #define RTW_RXCTL_EOR __BIT(30) /* end of ring */
913 #define RTW_RXCTL_FS __BIT(29) /* first segment */
914 #define RTW_RXCTL_LS __BIT(28) /* last segment */
915 #define RTW_RXCTL_RSVD0_MASK __BITS(29,12) /* reserved */
916 #define RTW_RXCTL_LENGTH_MASK __BITS(11,0) /* Rx buffer length */
917
918 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN
919 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR
920 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */
921 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */
922 #define RTW_RXSTAT_DMAFAIL __BIT(27) /* DMA failure on this pkt */
923 #define RTW_RXSTAT_BOVF __BIT(26) /* buffer overflow XXX means
924 * FIFO exhausted?
925 */
926 #define RTW_RXSTAT_SPLCP __BIT(25) /* Rx'd with short preamble
927 * and PLCP header
928 */
929 #define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */
930 #define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */
931 #define RTW_RXSTAT_RATE_1MBPS __SHIFTIN(0, RTW_RXSTAT_RATE_MASK)
932 #define RTW_RXSTAT_RATE_2MBPS __SHIFTIN(1, RTW_RXSTAT_RATE_MASK)
933 #define RTW_RXSTAT_RATE_5MBPS __SHIFTIN(2, RTW_RXSTAT_RATE_MASK)
934 #define RTW_RXSTAT_RATE_11MBPS __SHIFTIN(3, RTW_RXSTAT_RATE_MASK)
935 #define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */
936 #define RTW_RXSTAT_MAR __BIT(18) /* is multicast */
937 #define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */
938 #define RTW_RXSTAT_BAR __BIT(16) /* is broadcast */
939 #define RTW_RXSTAT_RES __BIT(15) /* error summary. valid when
940 * RTW_RXSTAT_LS set. indicates
941 * that either RTW_RXSTAT_CRC32
942 * or RTW_RXSTAT_ICV is set.
943 */
944 #define RTW_RXSTAT_PWRMGT __BIT(14) /* 802.11 PWRMGMT bit is set */
945 #define RTW_RXSTAT_CRC16 __BIT(14) /* XXX CRC16 error, from
946 * reference driver
947 */
948 #define RTW_RXSTAT_CRC32 __BIT(13) /* CRC32 error */
949 #define RTW_RXSTAT_ICV __BIT(12) /* ICV error */
950 #define RTW_RXSTAT_LENGTH_MASK __BITS(11,0) /* frame length, including
951 * CRC32
952 */
953
954 /* Convenient status conjunction. */
955 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS)
956 /* Convenient status disjunctions. */
957 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
958 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
959 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\
960 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\
961 RTW_RXSTAT_ICV)
962
963
964 #define RTW_RXRSSI_VLAN __BITS(31,16) /* XXX from reference driver */
965 /* for Philips RF front-ends */
966 #define RTW_RXRSSI_RSSI __BITS(15,8) /* RF energy at the PHY */
967 /* for RF front-ends by Intersil, Maxim, RFMD */
968 #define RTW_RXRSSI_IMR_RSSI __BITS(15,9) /* RF energy at the PHY */
969 #define RTW_RXRSSI_IMR_LNA __BIT(8) /* 1: LNA activated */
970 #define RTW_RXRSSI_SQ __BITS(7,0) /* Barker code-lock quality */
971
972 #define RTW_READ8(regs, ofs) \
973 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs))
974
975 #define RTW_READ16(regs, ofs) \
976 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs))
977
978 #define RTW_READ(regs, ofs) \
979 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs))
980
981 #define RTW_WRITE8(regs, ofs, val) \
982 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val))
983
984 #define RTW_WRITE16(regs, ofs, val) \
985 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val))
986
987 #define RTW_WRITE(regs, ofs, val) \
988 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val))
989
990 #define RTW_ISSET(regs, reg, mask) \
991 (RTW_READ((regs), (reg)) & (mask))
992
993 #define RTW_CLR(regs, reg, mask) \
994 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
995
996 /* bus_space(9) lied? */
997 #ifndef BUS_SPACE_BARRIER_SYNC
998 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
999 #endif
1000
1001 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ
1002 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
1003 #endif
1004
1005 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE
1006 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
1007 #endif
1008
1009 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ
1010 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
1011 #endif
1012
1013 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE
1014 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
1015 #endif
1016
1017 /*
1018 * Bus barrier
1019 *
1020 * Complete outstanding read and/or write ops on [reg0, reg1]
1021 * ([reg1, reg0]) before starting new ops on the same region. See
1022 * acceptable bus_space_barrier(9) for the flag definitions.
1023 */
1024 #define RTW_BARRIER(regs, reg0, reg1, flags) \
1025 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \
1026 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
1027
1028 /*
1029 * Barrier convenience macros.
1030 */
1031 /* sync */
1032 #define RTW_SYNC(regs, reg0, reg1) \
1033 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
1034
1035 /* write-before-write */
1036 #define RTW_WBW(regs, reg0, reg1) \
1037 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1038
1039 /* write-before-read */
1040 #define RTW_WBR(regs, reg0, reg1) \
1041 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
1042
1043 /* read-before-read */
1044 #define RTW_RBR(regs, reg0, reg1) \
1045 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
1046
1047 /* read-before-read */
1048 #define RTW_RBW(regs, reg0, reg1) \
1049 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
1050
1051 #define RTW_WBRW(regs, reg0, reg1) \
1052 RTW_BARRIER(regs, reg0, reg1, \
1053 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \
1054 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1055
1056 /*
1057 * Registers for RTL8180L's built-in baseband modem.
1058 */
1059 #define RTW_BBP_SYS1 0x00
1060 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */
1061 #define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation
1062 * threshold
1063 */
1064 #define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF)
1065 * auto-gain control (AGC) initial value
1066 */
1067 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */
1068 #define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for
1069 * IF AGC loop
1070 */
1071
1072 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */
1073 #define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3
1074 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91
1075 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92
1076 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93
1077 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3
1078 #define RTW_BBP_ANTATTEN_DFLANTB 0x40
1079 #define RTW_BBP_ANTATTEN_CHAN14 0x0c
1080
1081 #define RTW_BBP_TRL 0x11 /* guess: transmit/receive
1082 * switch latency
1083 */
1084 #define RTW_BBP_SYS2 0x12
1085 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */
1086 #define RTW_BBP_SYS2_RATE_MASK __BITS(5,4) /* loopback rate?
1087 * 0: 1Mbps
1088 * 1: 2Mbps
1089 * 2: 5.5Mbps
1090 * 3: 11Mbps
1091 */
1092 #define RTW_BBP_SYS3 0x13
1093 /* carrier-sense threshold */
1094 #define RTW_BBP_SYS3_CSTHRESH_MASK __BITS(0,3)
1095 #define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect
1096 * threshold
1097 */
1098 #define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality
1099 * threshold
1100 */
1101
1102 #define RTW_NOISE_FLOOR -95 /* guess */
1103 #define RTW_RSSI_CORR 131 /* Linux driver (256 - 125) */
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