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HAMMER Utilities: MFC work to date.
[dragonfly.git] / sys / dev / netif / ral / rt2560reg.h
blob99accedfc37d7bab10dd25ef6359108776c3d4f7
1 /*
2 * Copyright (c) 2005, 2006
3 * Damien Bergamini <damien.bergamini@free.fr>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: src/sys/dev/ral/rt2560reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2560reg.h,v 1.7 2008/01/25 15:09:42 sephe Exp $
19 */
20
21 #define RT2560_DEFAULT_RSSI_CORR 0x79
22 #define RT2560_NOISE_FLOOR -95
23
24 #define RT2560_RXSNS_MAX 0x50 /* inclusive */
25 #define RT2560_RXSNS_DYNMAX 0x40 /* inclusive */
26
27 #define RT2560_DEFAULT_TXPOWER 24 /* dBm */
28
29 #define RT2560_TX_RING_COUNT 48
30 #define RT2560_ATIM_RING_COUNT 4
31 #define RT2560_PRIO_RING_COUNT 16
32 #define RT2560_BEACON_RING_COUNT 1
33 #define RT2560_RX_RING_COUNT 32
34
35 #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc))
36 #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc))
37
38 #define RT2560_MAX_SCATTER 1
39
40 /*
41 * Control and status registers.
42 */
43 #define RT2560_CSR0 0x0000 /* ASIC version number */
44 #define RT2560_CSR1 0x0004 /* System control */
45 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
46 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
47 #define RT2560_CSR5 0x0014 /* BSSID 0 */
48 #define RT2560_CSR6 0x0018 /* BSSID 1 */
49 #define RT2560_CSR7 0x001c /* Interrupt source */
50 #define RT2560_CSR8 0x0020 /* Interrupt mask */
51 #define RT2560_CSR9 0x0024 /* Maximum frame length */
52 #define RT2560_SECCSR0 0x0028 /* WEP control */
53 #define RT2560_CSR11 0x002c /* Back-off control */
54 #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
55 #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
56 #define RT2560_CSR14 0x0038 /* Synchronization control */
57 #define RT2560_CSR15 0x003c /* Synchronization status */
58 #define RT2560_CSR16 0x0040 /* TSF timer 0 */
59 #define RT2560_CSR17 0x0044 /* TSF timer 1 */
60 #define RT2560_CSR18 0x0048 /* IFS timer 0 */
61 #define RT2560_CSR19 0x004c /* IFS timer 1 */
62 #define RT2560_CSR20 0x0050 /* WAKEUP timer */
63 #define RT2560_CSR21 0x0054 /* EEPROM control */
64 #define RT2560_CSR22 0x0058 /* CFP control */
65 #define RT2560_TXCSR0 0x0060 /* TX control */
66 #define RT2560_TXCSR1 0x0064 /* TX configuration */
67 #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
68 #define RT2560_TXCSR3 0x006c /* TX ring base address */
69 #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
70 #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
71 #define RT2560_TXCSR6 0x0078 /* Beacon base address */
72 #define RT2560_TXCSR7 0x007c /* AutoResponder control */
73 #define RT2560_RXCSR0 0x0080 /* RX control */
74 #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
75 #define RT2560_RXCSR2 0x0088 /* RX ring base address */
76 #define RT2560_PCICSR 0x008c /* PCI control */
77 #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
78 #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
79 #define RT2560_TXCSR8 0x0098 /* CCK TX BBP */
80 #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
81 #define RT2560_CNT0 0x00a0 /* FCS error counter */
82 #define RT2560_CNT1 0x00ac /* PLCP error counter */
83 #define RT2560_CNT2 0x00b0 /* Long error counter */
84 #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
85 #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
86 #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
87 #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
88 #define RT2560_PSCSR0 0x00c8 /* Power state transition time */
89 #define RT2560_PSCSR1 0x00cc /* Power state transition time */
90 #define RT2560_PSCSR2 0x00d0 /* Power state transition time */
91 #define RT2560_PSCSR3 0x00d4 /* Power state transition time */
92 #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
93 #define RT2560_TIMECSR 0x00dc /* Timer control */
94 #define RT2560_MACCSR0 0x00e0 /* MAC configuration */
95 #define RT2560_MACCSR1 0x00e4 /* MAC configuration */
96 #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
97 #define RT2560_BCNCSR 0x00ec /* Beacon interval control */
98 #define RT2560_BBPCSR 0x00f0 /* BBP serial control */
99 #define RT2560_RFCSR 0x00f4 /* RF serial control */
100 #define RT2560_LEDCSR 0x00f8 /* LED control */
101 #define RT2560_SECCSR3 0x00fc /* XXX not documented */
102 #define RT2560_DMACSR0 0x0100 /* Current RX ring address */
103 #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
104 #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
105 #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
106 #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
107 #define RT2560_GPIOCSR 0x0120 /* */
108 #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
109 #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
110 #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
111 #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
112 #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
113 #define RT2560_TESTCSR 0x0138 /* Test Mode Select */
114 #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
115 #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
116 #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
117 #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
118 #define RT2560_ARTCSR0 0x014c /* ACK/CTS padload consume time
119 * @ 1/2/5.5/11M
120 */
121 #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time
122 * @ 18/12/9/6M
123 */
124 #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time
125 * @ 54/48/36/24M
126 */
127 #define RT2560_SECCSR1 0x0158 /* WEP control */
128 #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
129
130
131 /* possible flags for register RXCSR0 */
132 #define RT2560_DISABLE_RX (1 << 0)
133 #define RT2560_DROP_CRC_ERROR (1 << 1)
134 #define RT2560_DROP_PHY_ERROR (1 << 2)
135 #define RT2560_DROP_CTL (1 << 3)
136 #define RT2560_DROP_NOT_TO_ME (1 << 4)
137 #define RT2560_DROP_TODS (1 << 5)
138 #define RT2560_DROP_VERSION_ERROR (1 << 6)
139
140 /* possible flags for register CSR1 */
141 #define RT2560_RESET_ASIC (1 << 0)
142 #define RT2560_RESET_BBP (1 << 1)
143 #define RT2560_HOST_READY (1 << 2)
144
145 /* possible flags for register CSR14 */
146 #define RT2560_ENABLE_TSF (1 << 0)
147 #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
148 #define RT2560_ENABLE_TBCN (1 << 3)
149 #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6)
150
151 /* possible flags for register CSR21 */
152 #define RT2560_C (1 << 1)
153 #define RT2560_S (1 << 2)
154 #define RT2560_D (1 << 3)
155 #define RT2560_Q (1 << 4)
156 #define RT2560_93C46 (1 << 5)
157
158 #define RT2560_SHIFT_D 3
159 #define RT2560_SHIFT_Q 4
160
161 /* possible flags for register TXCSR0 */
162 #define RT2560_KICK_TX (1 << 0)
163 #define RT2560_KICK_ATIM (1 << 1)
164 #define RT2560_KICK_PRIO (1 << 2)
165 #define RT2560_ABORT_TX (1 << 3)
166
167 /* possible flags for register SECCSR0 */
168 #define RT2560_KICK_DECRYPT (1 << 0)
169
170 /* possible flags for register SECCSR1 */
171 #define RT2560_KICK_ENCRYPT (1 << 0)
172
173 /* possible flags for register CSR7 */
174 #define RT2560_BEACON_EXPIRE 0x00000001
175 #define RT2560_WAKEUP_EXPIRE 0x00000002
176 #define RT2560_ATIM_EXPIRE 0x00000004
177 #define RT2560_TX_DONE 0x00000008
178 #define RT2560_ATIM_DONE 0x00000010
179 #define RT2560_PRIO_DONE 0x00000020
180 #define RT2560_RX_DONE 0x00000040
181 #define RT2560_DECRYPTION_DONE 0x00000080
182 #define RT2560_ENCRYPTION_DONE 0x00000100
183
184 #define RT2560_INTR_MASK \
185 (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
186 RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \
187 RT2560_ENCRYPTION_DONE))
188
189 /* Tx descriptor */
190 struct rt2560_tx_desc {
191 uint32_t flags;
192 #define RT2560_TX_BUSY (1 << 0)
193 #define RT2560_TX_VALID (1 << 1)
194
195 #define RT2560_TX_RESULT_MASK 0x0000001c
196 #define RT2560_TX_SUCCESS (0 << 2)
197 #define RT2560_TX_SUCCESS_RETRY (1 << 2)
198 #define RT2560_TX_FAIL_RETRY (2 << 2)
199 #define RT2560_TX_FAIL_INVALID (3 << 2)
200 #define RT2560_TX_FAIL_OTHER (4 << 2)
201
202 #define RT2560_TX_MORE_FRAG (1 << 8)
203 #define RT2560_TX_ACK (1 << 9)
204 #define RT2560_TX_TIMESTAMP (1 << 10)
205 #define RT2560_TX_OFDM (1 << 11)
206 #define RT2560_TX_CIPHER_BUSY (1 << 12)
207
208 #define RT2560_TX_IFS_MASK 0x00006000
209 #define RT2560_TX_IFS_BACKOFF (0 << 13)
210 #define RT2560_TX_IFS_SIFS (1 << 13)
211 #define RT2560_TX_IFS_NEWBACKOFF (2 << 13)
212 #define RT2560_TX_IFS_NONE (3 << 13)
213
214 #define RT2560_TX_LONG_RETRY (1 << 15)
215
216 #define RT2560_TX_CIPHER_MASK 0xe0000000
217 #define RT2560_TX_CIPHER_NONE (0 << 29)
218 #define RT2560_TX_CIPHER_WEP40 (1 << 29)
219 #define RT2560_TX_CIPHER_WEP104 (2 << 29)
220 #define RT2560_TX_CIPHER_TKIP (3 << 29)
221 #define RT2560_TX_CIPHER_AES (4 << 29)
222
223 uint32_t physaddr;
224 uint16_t wme;
225 #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
226 #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
227 #define RT2560_AIFSN(x) (((x) & 0x3) << 6)
228 #define RT2560_IVOFFSET(x) (((x) & 0x3f))
229
230 uint16_t reserved1;
231 uint8_t plcp_signal;
232 uint8_t plcp_service;
233 #define RT2560_PLCP_LENGEXT 0x80
234
235 uint8_t plcp_length_lo;
236 uint8_t plcp_length_hi;
237 uint32_t iv;
238 uint32_t eiv;
239 uint8_t key[IEEE80211_KEYBUF_SIZE];
240 uint32_t reserved2[2];
241 } __packed;
242
243 /* Rx descriptor */
244 struct rt2560_rx_desc {
245 uint32_t flags;
246 #define RT2560_RX_BUSY (1 << 0)
247 #define RT2560_RX_CRC_ERROR (1 << 5)
248 #define RT2560_RX_OFDM (1 << 6)
249 #define RT2560_RX_PHY_ERROR (1 << 7)
250 #define RT2560_RX_CIPHER_BUSY (1 << 8)
251 #define RT2560_RX_ICV_ERROR (1 << 9)
252
253 #define RT2560_RX_CIPHER_MASK 0xe0000000
254 #define RT2560_RX_CIPHER_NONE (0 << 29)
255 #define RT2560_RX_CIPHER_WEP40 (1 << 29)
256 #define RT2560_RX_CIPHER_WEP104 (2 << 29)
257 #define RT2560_RX_CIPHER_TKIP (3 << 29)
258 #define RT2560_RX_CIPHER_AES (4 << 29)
259
260 uint32_t physaddr;
261 uint8_t rate;
262 uint8_t rssi;
263 uint8_t ta[IEEE80211_ADDR_LEN];
264 uint32_t iv;
265 uint32_t eiv;
266 uint8_t key[IEEE80211_KEYBUF_SIZE];
267 uint32_t reserved[2];
268 } __packed;
269
270 #define RAL_RF1 0
271 #define RAL_RF2 2
272 #define RAL_RF3 1
273 #define RAL_RF4 3
274
275 #define RT2560_RF1_AUTOTUNE 0x08000
276 #define RT2560_RF3_AUTOTUNE 0x00040
277
278 #define RT2560_BBP_BUSY (1 << 15)
279 #define RT2560_BBP_WRITE (1 << 16)
280 #define RT2560_RF_20BIT (20 << 24)
281 #define RT2560_RF_BUSY (1 << 31)
282
283 #define RT2560_RF_2522 0x00
284 #define RT2560_RF_2523 0x01
285 #define RT2560_RF_2524 0x02
286 #define RT2560_RF_2525 0x03
287 #define RT2560_RF_2525E 0x04
288 #define RT2560_RF_2526 0x05
289 /* dual-band RF */
290 #define RT2560_RF_5222 0x10
291
292 #define RT2560_BBP_VERSION 0
293 #define RT2560_BBP_TX 2
294 #define RT2560_BBP_RX 14
295
296 #define RT2560_BBP_ANTA 0x00
297 #define RT2560_BBP_DIVERSITY 0x01
298 #define RT2560_BBP_ANTB 0x02
299 #define RT2560_BBP_ANTMASK 0x03
300 #define RT2560_BBP_FLIPIQ 0x04
301
302 #define RT2560_LED_MODE_DEFAULT 0
303 #define RT2560_LED_MODE_TXRX_ACTIVITY 1
304 #define RT2560_LED_MODE_SINGLE 2
305 #define RT2560_LED_MODE_ASUS 3
306
307 #define RT2560_JAPAN_FILTER 0x8
308
309 #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
310
311 #define RT2560_EEPROM_CONFIG0 16
312 #define RT2560_EEPROM_CONFIG1 17
313 #define RT2560_EEPROM_BBP_BASE 19
314 #define RT2560_EEPROM_TXPOWER 35
315 #define RT2560_EEPROM_CALIBRATE 62
316
317 /*
318 * control and status registers access macros
319 */
320 #define RAL_READ(sc, reg) \
321 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
322
323 #define RAL_WRITE(sc, reg, val) \
324 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
325
326 /*
327 * EEPROM access macro
328 */
329 #define RT2560_EEPROM_CTL(sc, val) do { \
330 RAL_WRITE((sc), RT2560_CSR21, (val)); \
331 DELAY(RT2560_EEPROM_DELAY); \
332 } while (/* CONSTCOND */0)
333
334 /*
335 * Default values for MAC registers; values taken from the reference driver.
336 */
337 #define RT2560_DEF_MAC \
338 { RT2560_PSCSR0, 0x00020002 }, \
339 { RT2560_PSCSR1, 0x00000002 }, \
340 { RT2560_PSCSR2, 0x00020002 }, \
341 { RT2560_PSCSR3, 0x00000002 }, \
342 { RT2560_TIMECSR, 0x00003f21 }, \
343 { RT2560_CSR9, 0x00000780 }, \
344 { RT2560_CSR11, 0x07041483 }, \
345 { RT2560_CNT3, 0x00000000 }, \
346 { RT2560_TXCSR1, 0x07614562 }, \
347 { RT2560_TXCSR8, 0x8c8d8b8a }, \
348 { RT2560_ARTCSR0, 0x7038140a }, \
349 { RT2560_ARTCSR1, 0x21212929 }, \
350 { RT2560_ARTCSR2, 0x1d1d1d1d }, \
351 { RT2560_RXCSR0, 0xffffffff }, \
352 { RT2560_RXCSR3, 0xb3aab3af }, \
353 { RT2560_PCICSR, 0x000003b8 }, \
354 { RT2560_PWRCSR0, 0x3f3b3100 }, \
355 { RT2560_GPIOCSR, 0x0000ff00 }, \
356 { RT2560_TESTCSR, 0x000000f0 }, \
357 { RT2560_PWRCSR1, 0x000001ff }, \
358 { RT2560_MACCSR0, 0x00213223 }, \
359 { RT2560_MACCSR1, 0x00235518 }, \
360 { RT2560_RLPWCSR, 0x00000040 }, \
361 { RT2560_RALINKCSR, 0x9a009a11 }, \
362 { RT2560_CSR7, 0xffffffff }, \
363 { RT2560_BBPCSR1, 0x82188200 }, \
364 { RT2560_TXACKCSR0, 0x00000020 }, \
365 { RT2560_SECCSR3, 0x0000e78f }
366
367 /*
368 * Default values for BBP registers; values taken from the reference driver.
369 */
370 #define RT2560_DEF_BBP \
371 { 3, 0x02 }, \
372 { 4, 0x19 }, \
373 { 14, 0x1c }, \
374 { 15, 0x30 }, \
375 { 16, 0xac }, \
376 { 17, 0x48 }, \
377 { 18, 0x18 }, \
378 { 19, 0xff }, \
379 { 20, 0x1e }, \
380 { 21, 0x08 }, \
381 { 22, 0x08 }, \
382 { 23, 0x08 }, \
383 { 24, 0x80 }, \
384 { 25, 0x50 }, \
385 { 26, 0x08 }, \
386 { 27, 0x23 }, \
387 { 30, 0x10 }, \
388 { 31, 0x2b }, \
389 { 32, 0xb9 }, \
390 { 34, 0x12 }, \
391 { 35, 0x50 }, \
392 { 39, 0xc4 }, \
393 { 40, 0x02 }, \
394 { 41, 0x60 }, \
395 { 53, 0x10 }, \
396 { 54, 0x18 }, \
397 { 56, 0x08 }, \
398 { 57, 0x10 }, \
399 { 58, 0x08 }, \
400 { 61, 0x60 }, \
401 { 62, 0x10 }, \
402 { 75, 0xff }
403
404 /*
405 * Default values for RF register R2 indexed by channel numbers; values taken
406 * from the reference driver.
407 */
408 #define RT2560_RF2522_R2 \
409 { \
410 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
411 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
412 }
413
414 #define RT2560_RF2523_R2 \
415 { \
416 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
417 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
418 }
419
420 #define RT2560_RF2524_R2 \
421 { \
422 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
423 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
424 }
425
426 #define RT2560_RF2525_R2 \
427 { \
428 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
429 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
430 }
431
432 #define RT2560_RF2525_HI_R2 \
433 { \
434 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
435 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
436 }
437
438 #define RT2560_RF2525E_R2 \
439 { \
440 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
441 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
442 }
443
444 #define RT2560_RF2526_HI_R2 \
445 { \
446 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
447 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
448 }
449
450 #define RT2560_RF2526_R2 \
451 { \
452 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
453 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
454 }
455
456 /*
457 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
458 * values taken from the reference driver.
459 */
460 #define RT2560_RF5222 \
461 { 1, 0x08808, 0x0044d, 0x00282 }, \
462 { 2, 0x08808, 0x0044e, 0x00282 }, \
463 { 3, 0x08808, 0x0044f, 0x00282 }, \
464 { 4, 0x08808, 0x00460, 0x00282 }, \
465 { 5, 0x08808, 0x00461, 0x00282 }, \
466 { 6, 0x08808, 0x00462, 0x00282 }, \
467 { 7, 0x08808, 0x00463, 0x00282 }, \
468 { 8, 0x08808, 0x00464, 0x00282 }, \
469 { 9, 0x08808, 0x00465, 0x00282 }, \
470 { 10, 0x08808, 0x00466, 0x00282 }, \
471 { 11, 0x08808, 0x00467, 0x00282 }, \
472 { 12, 0x08808, 0x00468, 0x00282 }, \
473 { 13, 0x08808, 0x00469, 0x00282 }, \
474 { 14, 0x08808, 0x0046b, 0x00286 }, \
475 \
476 { 36, 0x08804, 0x06225, 0x00287 }, \
477 { 40, 0x08804, 0x06226, 0x00287 }, \
478 { 44, 0x08804, 0x06227, 0x00287 }, \
479 { 48, 0x08804, 0x06228, 0x00287 }, \
480 { 52, 0x08804, 0x06229, 0x00287 }, \
481 { 56, 0x08804, 0x0622a, 0x00287 }, \
482 { 60, 0x08804, 0x0622b, 0x00287 }, \
483 { 64, 0x08804, 0x0622c, 0x00287 }, \
484 \
485 { 100, 0x08804, 0x02200, 0x00283 }, \
486 { 104, 0x08804, 0x02201, 0x00283 }, \
487 { 108, 0x08804, 0x02202, 0x00283 }, \
488 { 112, 0x08804, 0x02203, 0x00283 }, \
489 { 116, 0x08804, 0x02204, 0x00283 }, \
490 { 120, 0x08804, 0x02205, 0x00283 }, \
491 { 124, 0x08804, 0x02206, 0x00283 }, \
492 { 128, 0x08804, 0x02207, 0x00283 }, \
493 { 132, 0x08804, 0x02208, 0x00283 }, \
494 { 136, 0x08804, 0x02209, 0x00283 }, \
495 { 140, 0x08804, 0x0220a, 0x00283 }, \
496 \
497 { 149, 0x08808, 0x02429, 0x00281 }, \
498 { 153, 0x08808, 0x0242b, 0x00281 }, \
499 { 157, 0x08808, 0x0242d, 0x00281 }, \
500 { 161, 0x08808, 0x0242f, 0x00281 }
DragonFly BSD