sys/dev/netif/lnc/lancereg.h

   1 /*      $NetBSD: lancereg.h,v 1.12 2005/12/11 12:21:27 christos Exp $   */
   2 /*      $FreeBSD: src/sys/dev/le/lancereg.h,v 1.2 2006/05/16 21:04:01 marius Exp $      */
   3 /*      $DragonFly: src/sys/dev/netif/lnc/lancereg.h,v 1.1 2006/07/07 14:16:29 sephe Exp $      */
   4
   5 /*-
   6  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software contributed to The NetBSD Foundation
  10  * by Charles M. Hannum and Jason R. Thorpe.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *        This product includes software developed by the NetBSD
  23  *        Foundation, Inc. and its contributors.
  24  * 4. Neither the name of The NetBSD Foundation nor the names of its
  25  *    contributors may be used to endorse or promote products derived
  26  *    from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /*-
  42  * Copyright (c) 1992, 1993
  43  *      The Regents of the University of California.  All rights reserved.
  44  *
  45  * This code is derived from software contributed to Berkeley by
  46  * Ralph Campbell and Rick Macklem.
  47  *
  48  * Redistribution and use in source and binary forms, with or without
  49  * modification, are permitted provided that the following conditions
  50  * are met:
  51  * 1. Redistributions of source code must retain the above copyright
  52  *    notice, this list of conditions and the following disclaimer.
  53  * 2. Redistributions in binary form must reproduce the above copyright
  54  *    notice, this list of conditions and the following disclaimer in the
  55  *    documentation and/or other materials provided with the distribution.
  56  * 3. Neither the name of the University nor the names of its contributors
  57  *    may be used to endorse or promote products derived from this software
  58  *    without specific prior written permission.
  59  *
  60  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  61  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  62  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  63  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  64  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  65  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  66  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  67  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  68  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  69  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  70  * SUCH DAMAGE.
  71  *
  72  *      @(#)if_lereg.h  8.1 (Berkeley) 6/10/93
  73  */
  74
  75 /*
  76  * Register description for the following Advanced Micro Devices
  77  * Ethernet chips:
  78  *
  79  *      - Am7990 Local Area Network Controller for Ethernet (LANCE)
  80  *        (and its descendent Am79c90 C-LANCE).
  81  *
  82  *      - Am79c900 Integrated Local Area Communications Controller (ILACC)
  83  *
  84  *      - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
  85  *
  86  *      - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
  87  *        for ISA
  88  *
  89  *      - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
  90  *        Ethernet Controller for ISA
  91  *
  92  *      - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
  93  *        (for VESA and 486 local busses)
  94  *
  95  *      - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
  96  *        Local Bus
  97  *
  98  *      - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
  99  *        for PCI Local Bus
 100  *
 101  *      - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
 102  *        Ethernet Controller for PCI Local Bus
 103  *
 104  *      - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
 105  *        with OnNow Support
 106  *
 107  *      - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
 108  *        Ethernet Controller with Integrated PHY
 109  *
 110  *      - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
 111  *        Networking Controller.
 112  *
 113  * Initialization block, transmit descriptor, and receive descriptor
 114  * formats are described in two separate files:
 115  *
 116  *      16-bit software model (LANCE)           am7990reg.h
 117  *
 118  *      32-bit software model (ILACC)           am79900reg.h
 119  *
 120  * Note that the vast majority of the registers described in this file
 121  * belong to follow-on chips to the original LANCE.  Only CSR0-CSR3 are
 122  * valid on the LANCE.
 123  */
 124
 125 #ifndef _DEV_LE_LANCEREG_H_
 126 #define _DEV_LE_LANCEREG_H_
 127
 128 #ifndef ETHER_VLAN_ENCAP_LEN
 129 #define ETHER_VLAN_ENCAP_LEN   4
 130 #endif
 131
 132 #define LEBLEN          (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
 133 /* LEMINSIZE should be ETHER_MIN_LEN when LE_MODE_DTCR is set. */
 134 #define LEMINSIZE       (ETHER_MIN_LEN - ETHER_CRC_LEN)
 135
 136 #define LE_INITADDR(sc)         (sc->sc_initaddr)
 137 #define LE_RMDADDR(sc, bix)     (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
 138 #define LE_TMDADDR(sc, bix)     (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
 139 #define LE_RBUFADDR(sc, bix)    (sc->sc_rbufaddr + LEBLEN * (bix))
 140 #define LE_TBUFADDR(sc, bix)    (sc->sc_tbufaddr + LEBLEN * (bix))
 141
 142 /*
 143  * The byte count fields in descriptors are in two's complement.
 144  * This macro does the conversion for us on unsigned numbers.
 145  */
 146 #define LE_BCNT(x)      (~(x) + 1)
 147
 148 /*
 149  * Control and Status Register addresses
 150  */
 151 #define LE_CSR0         0x0000          /* Control and status register */
 152 #define LE_CSR1         0x0001          /* low address of init block */
 153 #define LE_CSR2         0x0002          /* high address of init block */
 154 #define LE_CSR3         0x0003          /* Bus master and control */
 155 #define LE_CSR4         0x0004          /* Test and features control */
 156 #define LE_CSR5         0x0005          /* Extended control and Interrupt 1 */
 157 #define LE_CSR6         0x0006          /* Rx/Tx Descriptor table length */
 158 #define LE_CSR7         0x0007          /* Extended control and interrupt 2 */
 159 #define LE_CSR8         0x0008          /* Logical Address Filter 0 */
 160 #define LE_CSR9         0x0009          /* Logical Address Filter 1 */
 161 #define LE_CSR10        0x000a          /* Logical Address Filter 2 */
 162 #define LE_CSR11        0x000b          /* Logical Address Filter 3 */
 163 #define LE_CSR12        0x000c          /* Physical Address 0 */
 164 #define LE_CSR13        0x000d          /* Physical Address 1 */
 165 #define LE_CSR14        0x000e          /* Physical Address 2 */
 166 #define LE_CSR15        0x000f          /* Mode */
 167 #define LE_CSR16        0x0010          /* Initialization Block addr lower */
 168 #define LE_CSR17        0x0011          /* Initialization Block addr upper */
 169 #define LE_CSR18        0x0012          /* Current Rx Buffer addr lower */
 170 #define LE_CSR19        0x0013          /* Current Rx Buffer addr upper */
 171 #define LE_CSR20        0x0014          /* Current Tx Buffer addr lower */
 172 #define LE_CSR21        0x0015          /* Current Tx Buffer addr upper */
 173 #define LE_CSR22        0x0016          /* Next Rx Buffer addr lower */
 174 #define LE_CSR23        0x0017          /* Next Rx Buffer addr upper */
 175 #define LE_CSR24        0x0018          /* Base addr of Rx ring lower */
 176 #define LE_CSR25        0x0019          /* Base addr of Rx ring upper */
 177 #define LE_CSR26        0x001a          /* Next Rx Desc addr lower */
 178 #define LE_CSR27        0x001b          /* Next Rx Desc addr upper */
 179 #define LE_CSR28        0x001c          /* Current Rx Desc addr lower */
 180 #define LE_CSR29        0x001d          /* Current Rx Desc addr upper */
 181 #define LE_CSR30        0x001e          /* Base addr of Tx ring lower */
 182 #define LE_CSR31        0x001f          /* Base addr of Tx ring upper */
 183 #define LE_CSR32        0x0020          /* Next Tx Desc addr lower */
 184 #define LE_CSR33        0x0021          /* Next Tx Desc addr upper */
 185 #define LE_CSR34        0x0022          /* Current Tx Desc addr lower */
 186 #define LE_CSR35        0x0023          /* Current Tx Desc addr upper */
 187 #define LE_CSR36        0x0024          /* Next Next Rx Desc addr lower */
 188 #define LE_CSR37        0x0025          /* Next Next Rx Desc addr upper */
 189 #define LE_CSR38        0x0026          /* Next Next Tx Desc addr lower */
 190 #define LE_CSR39        0x0027          /* Next Next Tx Desc adddr upper */
 191 #define LE_CSR40        0x0028          /* Current Rx Byte Count */
 192 #define LE_CSR41        0x0029          /* Current Rx Status */
 193 #define LE_CSR42        0x002a          /* Current Tx Byte Count */
 194 #define LE_CSR43        0x002b          /* Current Tx Status */
 195 #define LE_CSR44        0x002c          /* Next Rx Byte Count */
 196 #define LE_CSR45        0x002d          /* Next Rx Status */
 197 #define LE_CSR46        0x002e          /* Tx Poll Time Counter */
 198 #define LE_CSR47        0x002f          /* Tx Polling Interval */
 199 #define LE_CSR48        0x0030          /* Rx Poll Time Counter */
 200 #define LE_CSR49        0x0031          /* Rx Polling Interval */
 201 #define LE_CSR58        0x003a          /* Software Style */
 202 #define LE_CSR60        0x003c          /* Previous Tx Desc addr lower */
 203 #define LE_CSR61        0x003d          /* Previous Tx Desc addr upper */
 204 #define LE_CSR62        0x003e          /* Previous Tx Byte Count */
 205 #define LE_CSR63        0x003f          /* Previous Tx Status */
 206 #define LE_CSR64        0x0040          /* Next Tx Buffer addr lower */
 207 #define LE_CSR65        0x0041          /* Next Tx Buffer addr upper */
 208 #define LE_CSR66        0x0042          /* Next Tx Byte Count */
 209 #define LE_CSR67        0x0043          /* Next Tx Status */
 210 #define LE_CSR72        0x0048          /* Receive Ring Counter */
 211 #define LE_CSR74        0x004a          /* Transmit Ring Counter */
 212 #define LE_CSR76        0x004c          /* Receive Ring Length */
 213 #define LE_CSR78        0x004e          /* Transmit Ring Length */
 214 #define LE_CSR80        0x0050          /* DMA Transfer Counter and FIFO
 215                                            Threshold Control */
 216 #define LE_CSR82        0x0052          /* Tx Desc addr Pointer lower */
 217 #define LE_CSR84        0x0054          /* DMA addr register lower */
 218 #define LE_CSR85        0x0055          /* DMA addr register upper */
 219 #define LE_CSR86        0x0056          /* Buffer Byte Counter */
 220 #define LE_CSR88        0x0058          /* Chip ID Register lower */
 221 #define LE_CSR89        0x0059          /* Chip ID Register upper */
 222 #define LE_CSR92        0x005c          /* Ring Length Conversion */
 223 #define LE_CSR100       0x0064          /* Bus Timeout */
 224 #define LE_CSR112       0x0070          /* Missed Frame Count */
 225 #define LE_CSR114       0x0072          /* Receive Collision Count */
 226 #define LE_CSR116       0x0074          /* OnNow Power Mode Register */
 227 #define LE_CSR122       0x007a          /* Advanced Feature Control */
 228 #define LE_CSR124       0x007c          /* Test Register 1 */
 229 #define LE_CSR125       0x007d          /* MAC Enhanced Configuration Control */
 230
 231 /*
 232  * Bus Configuration Register addresses
 233  */
 234 #define LE_BCR0         0x0000          /* Master Mode Read Active */
 235 #define LE_BCR1         0x0001          /* Master Mode Write Active */
 236 #define LE_BCR2         0x0002          /* Misc. Configuration */
 237 #define LE_BCR4         0x0004          /* LED0 Status */
 238 #define LE_BCR5         0x0005          /* LED1 Status */
 239 #define LE_BCR6         0x0006          /* LED2 Status */
 240 #define LE_BCR7         0x0007          /* LED3 Status */
 241 #define LE_BCR9         0x0009          /* Full-duplex Control */
 242 #define LE_BCR16        0x0010          /* I/O Base Address lower */
 243 #define LE_BCR17        0x0011          /* I/O Base Address upper */
 244 #define LE_BCR18        0x0012          /* Burst and Bus Control Register */
 245 #define LE_BCR19        0x0013          /* EEPROM Control and Status */
 246 #define LE_BCR20        0x0014          /* Software Style */
 247 #define LE_BCR22        0x0016          /* PCI Latency Register */
 248 #define LE_BCR23        0x0017          /* PCI Subsystem Vendor ID */
 249 #define LE_BCR24        0x0018          /* PCI Subsystem ID */
 250 #define LE_BCR25        0x0019          /* SRAM Size Register */
 251 #define LE_BCR26        0x001a          /* SRAM Boundary Register */
 252 #define LE_BCR27        0x001b          /* SRAM Interface Control Register */
 253 #define LE_BCR28        0x001c          /* Exp. Bus Port Addr lower */
 254 #define LE_BCR29        0x001d          /* Exp. Bus Port Addr upper */
 255 #define LE_BCR30        0x001e          /* Exp. Bus Data Port */
 256 #define LE_BCR31        0x001f          /* Software Timer Register */
 257 #define LE_BCR32        0x0020          /* PHY Control and Status Register */
 258 #define LE_BCR33        0x0021          /* PHY Address Register */
 259 #define LE_BCR34        0x0022          /* PHY Management Data Register */
 260 #define LE_BCR35        0x0023          /* PCI Vendor ID Register */
 261 #define LE_BCR36        0x0024          /* PCI Power Management Cap. Alias */
 262 #define LE_BCR37        0x0025          /* PCI DATA0 Alias */
 263 #define LE_BCR38        0x0026          /* PCI DATA1 Alias */
 264 #define LE_BCR39        0x0027          /* PCI DATA2 Alias */
 265 #define LE_BCR40        0x0028          /* PCI DATA3 Alias */
 266 #define LE_BCR41        0x0029          /* PCI DATA4 Alias */
 267 #define LE_BCR42        0x002a          /* PCI DATA5 Alias */
 268 #define LE_BCR43        0x002b          /* PCI DATA6 Alias */
 269 #define LE_BCR44        0x002c          /* PCI DATA7 Alias */
 270 #define LE_BCR45        0x002d          /* OnNow Pattern Matching 1 */
 271 #define LE_BCR46        0x002e          /* OnNow Pattern Matching 2 */
 272 #define LE_BCR47        0x002f          /* OnNow Pattern Matching 3 */
 273 #define LE_BCR48        0x0030          /* LED4 Status */
 274 #define LE_BCR49        0x0031          /* PHY Select */
 275
 276 /* Control and status register 0 (csr0) */
 277 #define LE_C0_ERR       0x8000          /* error summary */
 278 #define LE_C0_BABL      0x4000          /* transmitter timeout error */
 279 #define LE_C0_CERR      0x2000          /* collision */
 280 #define LE_C0_MISS      0x1000          /* missed a packet */
 281 #define LE_C0_MERR      0x0800          /* memory error */
 282 #define LE_C0_RINT      0x0400          /* receiver interrupt */
 283 #define LE_C0_TINT      0x0200          /* transmitter interrupt */
 284 #define LE_C0_IDON      0x0100          /* initialization done */
 285 #define LE_C0_INTR      0x0080          /* interrupt condition */
 286 #define LE_C0_INEA      0x0040          /* interrupt enable */
 287 #define LE_C0_RXON      0x0020          /* receiver on */
 288 #define LE_C0_TXON      0x0010          /* transmitter on */
 289 #define LE_C0_TDMD      0x0008          /* transmit demand */
 290 #define LE_C0_STOP      0x0004          /* disable all external activity */
 291 #define LE_C0_STRT      0x0002          /* enable external activity */
 292 #define LE_C0_INIT      0x0001          /* begin initialization */
 293
 294 #define LE_C0_BITS \
 295     "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
 296 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
 297
 298 /* Control and status register 3 (csr3) */
 299 #define LE_C3_BABLM     0x4000          /* babble mask */
 300 #define LE_C3_MISSM     0x1000          /* missed frame mask */
 301 #define LE_C3_MERRM     0x0800          /* memory error mask */
 302 #define LE_C3_RINTM     0x0400          /* receive interrupt mask */
 303 #define LE_C3_TINTM     0x0200          /* transmit interrupt mask */
 304 #define LE_C3_IDONM     0x0100          /* initialization done mask */
 305 #define LE_C3_DXSUFLO   0x0040          /* disable tx stop on underflow */
 306 #define LE_C3_LAPPEN    0x0020          /* look ahead packet processing enbl */
 307 #define LE_C3_DXMT2PD   0x0010          /* disable tx two part deferral */
 308 #define LE_C3_EMBA      0x0008          /* enable modified backoff algorithm */
 309 #define LE_C3_BSWP      0x0004          /* byte swap */
 310 #define LE_C3_ACON      0x0002          /* ALE control, eh? */
 311 #define LE_C3_BCON      0x0001          /* byte control */
 312
 313 /* Control and status register 4 (csr4) */
 314 #define LE_C4_EN124     0x8000          /* enable CSR124 */
 315 #define LE_C4_DMAPLUS   0x4000          /* always set (PCnet-PCI) */
 316 #define LE_C4_TIMER     0x2000          /* enable bus activity timer */
 317 #define LE_C4_TXDPOLL   0x1000          /* disable transmit polling */
 318 #define LE_C4_APAD_XMT  0x0800          /* auto pad transmit */
 319 #define LE_C4_ASTRP_RCV 0x0400          /* auto strip receive */
 320 #define LE_C4_MFCO      0x0200          /* missed frame counter overflow */
 321 #define LE_C4_MFCOM     0x0100          /* missed frame coutner overflow mask */
 322 #define LE_C4_UINTCMD   0x0080          /* user interrupt command */
 323 #define LE_C4_UINT      0x0040          /* user interrupt */
 324 #define LE_C4_RCVCCO    0x0020          /* receive collision counter overflow */
 325 #define LE_C4_RCVCCOM   0x0010          /* receive collision counter overflow
 326                                            mask */
 327 #define LE_C4_TXSTRT    0x0008          /* transmit start status */
 328 #define LE_C4_TXSTRTM   0x0004          /* transmit start mask */
 329
 330 /* Control and status register 5 (csr5) */
 331 #define LE_C5_TOKINTD   0x8000          /* transmit ok interrupt disable */
 332 #define LE_C5_LTINTEN   0x4000          /* last transmit interrupt enable */
 333 #define LE_C5_SINT      0x0800          /* system interrupt */
 334 #define LE_C5_SINTE     0x0400          /* system interrupt enable */
 335 #define LE_C5_EXDINT    0x0080          /* excessive deferral interrupt */
 336 #define LE_C5_EXDINTE   0x0040          /* excessive deferral interrupt enbl */
 337 #define LE_C5_MPPLBA    0x0020          /* magic packet physical logical
 338                                            broadcast accept */
 339 #define LE_C5_MPINT     0x0010          /* magic packet interrupt */
 340 #define LE_C5_MPINTE    0x0008          /* magic packet interrupt enable */
 341 #define LE_C5_MPEN      0x0004          /* magic packet enable */
 342 #define LE_C5_MPMODE    0x0002          /* magic packet mode */
 343 #define LE_C5_SPND      0x0001          /* suspend */
 344
 345 /* Control and status register 6 (csr6) */
 346 #define LE_C6_TLEN      0xf000          /* TLEN from init block */
 347 #define LE_C6_RLEN      0x0f00          /* RLEN from init block */
 348
 349 /* Control and status register 7 (csr7) */
 350 #define LE_C7_FASTSPNDE 0x8000          /* fast suspend enable */
 351 #define LE_C7_RDMD      0x2000          /* receive demand */
 352 #define LE_C7_RDXPOLL   0x1000          /* receive disable polling */
 353 #define LE_C7_STINT     0x0800          /* software timer interrupt */
 354 #define LE_C7_STINTE    0x0400          /* software timer interrupt enable */
 355 #define LE_C7_MREINT    0x0200          /* PHY management read error intr */
 356 #define LE_C7_MREINTE   0x0100          /* PHY management read error intr
 357                                            enable */
 358 #define LE_C7_MAPINT    0x0080          /* PHY management auto-poll intr */
 359 #define LE_C7_MAPINTE   0x0040          /* PHY management auto-poll intr
 360                                            enable */
 361 #define LE_C7_MCCINT    0x0020          /* PHY management command complete
 362                                            interrupt */
 363 #define LE_C7_MCCINTE   0x0010          /* PHY management command complete
 364                                            interrupt enable */
 365 #define LE_C7_MCCIINT   0x0008          /* PHY management command complete
 366                                            internal interrupt */
 367 #define LE_C7_MCCIINTE  0x0004          /* PHY management command complete
 368                                            internal interrupt enable */
 369 #define LE_C7_MIIPDTINT 0x0002          /* PHY management detect transition
 370                                            interrupt */
 371 #define LE_C7_MIIPDTINTE 0x0001         /* PHY management detect transition
 372                                            interrupt enable */
 373
 374 /* Control and status register 15 (csr15) */
 375 #define LE_C15_PROM     0x8000          /* promiscuous mode */
 376 #define LE_C15_DRCVBC   0x4000          /* disable Rx of broadcast */
 377 #define LE_C15_DRCVPA   0x2000          /* disable Rx of physical address */
 378 #define LE_C15_DLNKTST  0x1000          /* disable link status */
 379 #define LE_C15_DAPC     0x0800          /* disable auto-polarity correction */
 380 #define LE_C15_MENDECL  0x0400          /* MENDEC Loopback mode */
 381 #define LE_C15_LRT      0x0200          /* low receive threshold (TMAU) */
 382 #define LE_C15_TSEL     0x0200          /* transmit mode select (AUI) */
 383 #define LE_C15_PORTSEL(x) ((x) << 7)    /* port select */
 384 #define LE_C15_INTL     0x0040          /* internal loopback */
 385 #define LE_C15_DRTY     0x0020          /* disable retry */
 386 #define LE_C15_FCOLL    0x0010          /* force collision */
 387 #define LE_C15_DXMTFCS  0x0008          /* disable Tx FCS (ADD_FCS overrides) */
 388 #define LE_C15_LOOP     0x0004          /* loopback enable */
 389 #define LE_C15_DTX      0x0002          /* disable transmit */
 390 #define LE_C15_DRX      0x0001          /* disable receiver */
 391
 392 #define LE_PORTSEL_AUI  0
 393 #define LE_PORTSEL_10T  1
 394 #define LE_PORTSEL_GPSI 2
 395 #define LE_PORTSEL_MII  3
 396 #define LE_PORTSEL_MASK 3
 397
 398 /* control and status register 80 (csr80) */
 399 #define LE_C80_RCVFW(x) ((x) << 12)     /* Receive FIFO Watermark */
 400 #define LE_C80_RCVFW_MAX 3
 401 #define LE_C80_XMTSP(x) ((x) << 10)     /* Transmit Start Point */
 402 #define LE_C80_XMTSP_MAX 3
 403 #define LE_C80_XMTFW(x) ((x) << 8)      /* Transmit FIFO Watermark */
 404 #define LE_C80_XMTFW_MAX 3
 405 #define LE_C80_DMATC    0x00ff          /* DMA transfer counter */
 406
 407 /* control and status register 116 (csr116) */
 408 #define LE_C116_PME_EN_OVR 0x0400       /* PME_EN overwrite */
 409 #define LE_C116_LCDET      0x0200       /* link change detected */
 410 #define LE_C116_LCMODE     0x0100       /* link change wakeup mode */
 411 #define LE_C116_PMAT       0x0080       /* pattern matched */
 412 #define LE_C116_EMPPLBA    0x0040       /* magic packet physical logical
 413                                            broadcast accept */
 414 #define LE_C116_MPMAT      0x0020       /* magic packet match */
 415 #define LE_C116_MPPEN      0x0010       /* magic packet pin enable */
 416 #define LE_C116_RST_POL    0x0001       /* PHY_RST pin polarity */
 417
 418 /* control and status register 122 (csr122) */
 419 #define LE_C122_RCVALGN 0x0001          /* receive packet align */
 420
 421 /* control and status register 124 (csr124) */
 422 #define LE_C124_RPA     0x0008          /* runt packet accept */
 423
 424 /* control and status register 125 (csr125) */
 425 #define LE_C125_IPG     0xff00          /* inter-packet gap */
 426 #define LE_C125_IFS1    0x00ff          /* inter-frame spacing part 1 */
 427
 428 /* bus configuration register 0 (bcr0) */
 429 #define LE_B0_MSRDA     0xffff          /* reserved locations */
 430
 431 /* bus configuration register 1 (bcr1) */
 432 #define LE_B1_MSWRA     0xffff          /* reserved locations */
 433
 434 /* bus configuration register 2 (bcr2) */
 435 #define LE_B2_PHYSSELEN 0x2000          /* enable writes to BCR18[4:3] */
 436 #define LE_B2_LEDPE     0x1000          /* LED program enable */
 437 #define LE_B2_APROMWE   0x0100          /* Address PROM Write Enable */
 438 #define LE_B2_INTLEVEL  0x0080          /* 1 == edge triggered */
 439 #define LE_B2_DXCVRCTL  0x0020          /* DXCVR control */
 440 #define LE_B2_DXCVRPOL  0x0010          /* DXCVR polarity */
 441 #define LE_B2_EADISEL   0x0008          /* EADI select */
 442 #define LE_B2_AWAKE     0x0004          /* power saving mode select */
 443 #define LE_B2_ASEL      0x0002          /* auto-select PORTSEL */
 444 #define LE_B2_XMAUSEL   0x0001          /* reserved location */
 445
 446 /* bus configuration register 4 (bcr4) */
 447 /* bus configuration register 5 (bcr5) */
 448 /* bus configuration register 6 (bcr6) */
 449 /* bus configuration register 7 (bcr7) */
 450 /* bus configuration register 48 (bcr48) */
 451 #define LE_B4_LEDOUT    0x8000          /* LED output active */
 452 #define LE_B4_LEDPOL    0x4000          /* LED polarity */
 453 #define LE_B4_LEDDIS    0x2000          /* LED disable */
 454 #define LE_B4_100E      0x1000          /* 100Mb/s enable */
 455 #define LE_B4_MPSE      0x0200          /* magic packet status enable */
 456 #define LE_B4_FDLSE     0x0100          /* full-duplex link status enable */
 457 #define LE_B4_PSE       0x0080          /* pulse stretcher enable */
 458 #define LE_B4_LNKSE     0x0040          /* link status enable */
 459 #define LE_B4_RCVME     0x0020          /* receive match status enable */
 460 #define LE_B4_XMTE      0x0010          /* transmit status enable */
 461 #define LE_B4_POWER     0x0008          /* power enable */
 462 #define LE_B4_RCVE      0x0004          /* receive status enable */
 463 #define LE_B4_SPEED     0x0002          /* high speed enable */
 464 #define LE_B4_COLE      0x0001          /* collision status enable */
 465
 466 /* bus configuration register 9 (bcr9) */
 467 #define LE_B9_FDRPAD    0x0004          /* full-duplex runt packet accept
 468                                            disable */
 469 #define LE_B9_AUIFD     0x0002          /* AUI full-duplex */
 470 #define LE_B9_FDEN      0x0001          /* full-duplex enable */
 471
 472 /* bus configuration register 18 (bcr18) */
 473 #define LE_B18_ROMTMG   0xf000          /* expansion rom timing */
 474 #define LE_B18_NOUFLO   0x0800          /* no underflow on transmit */
 475 #define LE_B18_MEMCMD   0x0200          /* memory read multiple enable */
 476 #define LE_B18_EXTREQ   0x0100          /* extended request */
 477 #define LE_B18_DWIO     0x0080          /* double-word I/O */
 478 #define LE_B18_BREADE   0x0040          /* burst read enable */
 479 #define LE_B18_BWRITE   0x0020          /* burst write enable */
 480 #define LE_B18_PHYSEL1  0x0010          /* PHYSEL 1 */
 481 #define LE_B18_PHYSEL0  0x0008          /* PHYSEL 0 */
 482                                         /*      00      ex ROM/Flash    */
 483                                         /*      01      EADI/MII snoop  */
 484                                         /*      10      reserved        */
 485                                         /*      11      reserved        */
 486 #define LE_B18_LINBC    0x0007          /* reserved locations */
 487
 488 /* bus configuration register 19 (bcr19) */
 489 #define LE_B19_PVALID   0x8000          /* EEPROM status valid */
 490 #define LE_B19_PREAD    0x4000          /* EEPROM read command */
 491 #define LE_B19_EEDET    0x2000          /* EEPROM detect */
 492 #define LE_B19_EEN      0x0010          /* EEPROM port enable */
 493 #define LE_B19_ECS      0x0004          /* EEPROM chip select */
 494 #define LE_B19_ESK      0x0002          /* EEPROM serial clock */
 495 #define LE_B19_EDI      0x0001          /* EEPROM data in */
 496 #define LE_B19_EDO      0x0001          /* EEPROM data out */
 497
 498 /* bus configuration register 20 (bcr20) */
 499 #define LE_B20_APERREN  0x0400          /* Advanced parity error handling */
 500 #define LE_B20_CSRPCNET 0x0200          /* PCnet-style CSRs (0 = ILACC) */
 501 #define LE_B20_SSIZE32  0x0100          /* Software Size 32-bit */
 502 #define LE_B20_SSTYLE   0x0007          /* Software Style */
 503 #define LE_B20_SSTYLE_LANCE     0       /* LANCE/PCnet-ISA (16-bit) */
 504 #define LE_B20_SSTYLE_ILACC     1       /* ILACC (32-bit) */
 505 #define LE_B20_SSTYLE_PCNETPCI2 2       /* PCnet-PCI (32-bit) */
 506 #define LE_B20_SSTYLE_PCNETPCI3 3       /* PCnet-PCI II (32-bit) */
 507
 508 /* bus configuration register 25 (bcr25) */
 509 #define LE_B25_SRAM_SIZE  0x00ff        /* SRAM size */
 510
 511 /* bus configuration register 26 (bcr26) */
 512 #define LE_B26_SRAM_BND   0x00ff        /* SRAM boundary */
 513
 514 /* bus configuration register 27 (bcr27) */
 515 #define LE_B27_PTRTST   0x8000          /* reserved for manuf. tests */
 516 #define LE_B27_LOLATRX  0x4000          /* low latency receive */
 517 #define LE_B27_EBCS     0x0038          /* expansion bus clock source */
 518                                         /*      000     CLK pin         */
 519                                         /*      001     time base clock */
 520                                         /*      010     EBCLK pin       */
 521                                         /*      011     reserved        */
 522                                         /*      1xx     reserved        */
 523 #define LE_B27_CLK_FAC  0x0007          /* clock factor */
 524                                         /*      000     1               */
 525                                         /*      001     1/2             */
 526                                         /*      010     reserved        */
 527                                         /*      011     1/4             */
 528                                         /*      1xx     reserved        */
 529
 530 /* bus configuration register 28 (bcr28) */
 531 #define LE_B28_EADDRL   0xffff          /* expansion port address lower */
 532
 533 /* bus configuration register 29 (bcr29) */
 534 #define LE_B29_FLASH    0x8000          /* flash access */
 535 #define LE_B29_LAAINC   0x4000          /* lower address auto increment */
 536 #define LE_B29_EPADDRU  0x0007          /* expansion port address upper */
 537
 538 /* bus configuration register 30 (bcr30) */
 539 #define LE_B30_EBDATA   0xffff          /* expansion bus data port */
 540
 541 /* bus configuration register 31 (bcr31) */
 542 #define LE_B31_STVAL    0xffff          /* software timer value */
 543
 544 /* bus configuration register 32 (bcr32) */
 545 #define LE_B32_ANTST    0x8000          /* reserved for manuf. tests */
 546 #define LE_B32_MIIPD    0x4000          /* MII PHY Detect (manuf. tests) */
 547 #define LE_B32_FMDC     0x3000          /* fast management data clock */
 548 #define LE_B32_APEP     0x0800          /* auto-poll PHY */
 549 #define LE_B32_APDW     0x0700          /* auto-poll dwell time */
 550 #define LE_B32_DANAS    0x0080          /* disable autonegotiation */
 551 #define LE_B32_XPHYRST  0x0040          /* PHY reset */
 552 #define LE_B32_XPHYANE  0x0020          /* PHY autonegotiation enable */
 553 #define LE_B32_XPHYFD   0x0010          /* PHY full-duplex */
 554 #define LE_B32_XPHYSP   0x0008          /* PHY speed */
 555 #define LE_B32_MIIILP   0x0002          /* MII internal loopback */
 556
 557 /* bus configuration register 33 (bcr33) */
 558 #define LE_B33_SHADOW   0x8000          /* shadow enable */
 559 #define LE_B33_MII_SEL  0x4000          /* MII selected */
 560 #define LE_B33_ACOMP    0x2000          /* internal PHY autonegotiation comp */
 561 #define LE_B33_LINK     0x1000          /* link status */
 562 #define LE_B33_FDX      0x0800          /* full-duplex */
 563 #define LE_B33_SPEED    0x0400          /* 1 == high speed */
 564 #define LE_B33_PHYAD    0x03e0          /* PHY address */
 565 #define PHYAD_SHIFT     5
 566 #define LE_B33_REGAD    0x001f          /* register address */
 567
 568 /* bus configuration register 34 (bcr34) */
 569 #define LE_B34_MIIMD    0xffff          /* MII data */
 570
 571 /* bus configuration register 49 (bcr49) */
 572 #define LE_B49_PCNET    0x8000          /* PCnet mode - Must Be One */
 573 #define LE_B49_PHYSEL_D 0x0300          /* PHY_SEL_Default */
 574 #define LE_B49_PHYSEL_L 0x0010          /* PHY_SEL_Lock */
 575 #define LE_B49_PHYSEL   0x0003          /* PHYSEL */
 576                                         /*      00      10baseT PHY     */
 577                                         /*      01      HomePNA PHY     */
 578                                         /*      10      external PHY    */
 579                                         /*      11      reserved        */
 580
 581 /* Initialization block (mode) */
 582 #define LE_MODE_PROM    0x8000          /* promiscuous mode */
 583 /*                      0x7f80             reserved, must be zero */
 584 /* 0x4000 - 0x0080 are not available on LANCE 7990. */
 585 #define LE_MODE_DRCVBC  0x4000          /* disable receive brodcast */
 586 #define LE_MODE_DRCVPA  0x2000          /* disable physical address detection */
 587 #define LE_MODE_DLNKTST 0x1000          /* disable link status */
 588 #define LE_MODE_DAPC    0x0800          /* disable automatic polarity correction */
 589 #define LE_MODE_MENDECL 0x0400          /* MENDEC loopback mode */
 590 #define LE_MODE_LRTTSEL 0x0200          /* lower receive threshold /
 591                                            transmit mode selection */
 592 #define LE_MODE_PSEL1   0x0100          /* port selection bit1 */
 593 #define LE_MODE_PSEL0   0x0080          /* port selection bit0 */
 594 #define LE_MODE_INTL    0x0040          /* internal loopback */
 595 #define LE_MODE_DRTY    0x0020          /* disable retry */
 596 #define LE_MODE_COLL    0x0010          /* force a collision */
 597 #define LE_MODE_DTCR    0x0008          /* disable transmit CRC */
 598 #define LE_MODE_LOOP    0x0004          /* loopback mode */
 599 #define LE_MODE_DTX     0x0002          /* disable transmitter */
 600 #define LE_MODE_DRX     0x0001          /* disable receiver */
 601 #define LE_MODE_NORMAL  0               /* none of the above */
 602
 603 /*
 604  * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts
 605  */
 606 #define CHIPID_MANFID(x)        (((x) >> 1) & 0x3ff)
 607 #define CHIPID_PARTID(x)        (((x) >> 12) & 0xffff)
 608 #define CHIPID_VER(x)           (((x) >> 28) & 0x7)
 609
 610 #define PARTID_Am79c960         0x0003
 611 #define PARTID_Am79c961         0x2260
 612 #define PARTID_Am79c961A        0x2261
 613 #define PARTID_Am79c965         0x2430  /* yes, these... */
 614 #define PARTID_Am79c970         0x2430  /* ...are the same */
 615 #define PARTID_Am79c970A        0x2621
 616 #define PARTID_Am79c971         0x2623
 617 #define PARTID_Am79c972         0x2624
 618 #define PARTID_Am79c973         0x2625
 619 #define PARTID_Am79c978         0x2626
 620 #define PARTID_Am79c975         0x2627
 621 #define PARTID_Am79c976         0x2628
 622
 623 #endif  /* !_DEV_LE_LANCEREG_H_ */