2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
38 #include <sys/cpu_topology.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/lapic.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/acpica/acpi_md_cpu.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
68 #include <machine/clock.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <machine_base/icu/icu.h> /* IPIs */
72 #include <machine_base/icu/icu_var.h>
73 #include <machine_base/apic/ioapic_abi.h>
74 #include <machine/intr_machdep.h> /* IPIs */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
86 * this code MUST be enabled here and in mpboot.s.
87 * it follows the very early stages of AP boot by placing values in CMOS ram.
88 * it NORMALLY will never be needed and thus the primitive method for enabling.
91 #if defined(CHECK_POINTS)
92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
95 #define CHECK_INIT(D); \
96 CHECK_WRITE(0x34, (D)); \
97 CHECK_WRITE(0x35, (D)); \
98 CHECK_WRITE(0x36, (D)); \
99 CHECK_WRITE(0x37, (D)); \
100 CHECK_WRITE(0x38, (D)); \
101 CHECK_WRITE(0x39, (D));
103 #define CHECK_PRINT(S); \
104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
113 #else /* CHECK_POINTS */
115 #define CHECK_INIT(D)
116 #define CHECK_PRINT(S)
118 #endif /* CHECK_POINTS */
121 * Values to send to the POST hardware.
123 #define MP_BOOTADDRESS_POST 0x10
124 #define MP_PROBE_POST 0x11
125 #define MPTABLE_PASS1_POST 0x12
127 #define MP_START_POST 0x13
128 #define MP_ENABLE_POST 0x14
129 #define MPTABLE_PASS2_POST 0x15
131 #define START_ALL_APS_POST 0x16
132 #define INSTALL_AP_TRAMP_POST 0x17
133 #define START_AP_POST 0x18
135 #define MP_ANNOUNCE_POST 0x19
137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
138 int current_postcode
;
140 /** XXX FIXME: what system files declare these??? */
141 extern struct region_descriptor r_gdt
;
147 extern int64_t tsc_offsets
[];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs
[MAXCPU
];
155 extern inthand_t
IDTVEC(fast_syscall
), IDTVEC(fast_syscall32
);
158 * Local data and functions.
161 static u_int boot_address
;
162 static int mp_finish
;
163 static int mp_finish_lapic
;
165 static int start_all_aps(u_int boot_addr
);
167 static void install_ap_tramp(u_int boot_addr
);
169 static int start_ap(struct mdglobaldata
*gd
, u_int boot_addr
, int smibest
);
170 static int smitest(void);
171 static void mp_bsp_simple_setup(void);
173 /* which cpus have been started */
174 static cpumask_t smp_startup_mask
= CPUMASK_INITIALIZER_ONLYONE
;
175 /* which cpus have lapic been inited */
176 static cpumask_t smp_lapic_mask
= CPUMASK_INITIALIZER_ONLYONE
;
177 /* which cpus are ready for IPIs etc? */
178 cpumask_t smp_active_mask
= CPUMASK_INITIALIZER_ONLYONE
;
179 cpumask_t smp_finalize_mask
= CPUMASK_INITIALIZER_ONLYONE
;
181 SYSCTL_OPAQUE(_machdep
, OID_AUTO
, smp_active
, CTLFLAG_RD
,
182 &smp_active_mask
, sizeof(smp_active_mask
), "LU", "");
183 static u_int bootMP_size
;
184 static u_int report_invlpg_src
;
185 SYSCTL_INT(_machdep
, OID_AUTO
, report_invlpg_src
, CTLFLAG_RW
,
186 &report_invlpg_src
, 0, "");
187 static u_int report_invltlb_src
;
188 SYSCTL_INT(_machdep
, OID_AUTO
, report_invltlb_src
, CTLFLAG_RW
,
189 &report_invltlb_src
, 0, "");
190 static int optimized_invltlb
;
191 SYSCTL_INT(_machdep
, OID_AUTO
, optimized_invltlb
, CTLFLAG_RW
,
192 &optimized_invltlb
, 0, "");
193 static int all_but_self_ipi_enable
= 1;
194 SYSCTL_INT(_machdep
, OID_AUTO
, all_but_self_ipi_enable
, CTLFLAG_RW
,
195 &all_but_self_ipi_enable
, 0, "");
197 /* Local data for detecting CPU TOPOLOGY */
198 static int core_bits
= 0;
199 static int logical_CPU_bits
= 0;
203 * Calculate usable address in base memory for AP trampoline code.
206 mp_bootaddress(u_int basemem
)
208 POSTCODE(MP_BOOTADDRESS_POST
);
210 bootMP_size
= mptramp_end
- mptramp_start
;
211 boot_address
= trunc_page(basemem
* 1024); /* round down to 4k boundary */
212 if (((basemem
* 1024) - boot_address
) < bootMP_size
)
213 boot_address
-= PAGE_SIZE
; /* not enough, lower by 4k */
214 /* 3 levels of page table pages */
215 mptramp_pagetables
= boot_address
- (PAGE_SIZE
* 3);
217 return mptramp_pagetables
;
221 * Print various information about the SMP system hardware and setup.
228 POSTCODE(MP_ANNOUNCE_POST
);
230 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
231 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
232 for (x
= 1; x
<= naps
; ++x
)
233 kprintf(" cpu%d (AP): apic id: %2d\n", x
, CPUID_TO_APICID(x
));
236 kprintf(" Warning: APIC I/O disabled\n");
240 * AP cpu's call this to sync up protected mode.
242 * WARNING! %gs is not set up on entry. This routine sets up %gs.
248 int x
, myid
= bootAP
;
250 struct mdglobaldata
*md
;
251 struct privatespace
*ps
;
253 ps
= CPU_prvspace
[myid
];
255 gdt_segs
[GPROC0_SEL
].ssd_base
=
256 (long) &ps
->mdglobaldata
.gd_common_tss
;
257 ps
->mdglobaldata
.mi
.gd_prvspace
= ps
;
259 /* We fill the 32-bit segment descriptors */
260 for (x
= 0; x
< NGDT
; x
++) {
261 if (x
!= GPROC0_SEL
&& x
!= (GPROC0_SEL
+ 1))
262 ssdtosd(&gdt_segs
[x
], &gdt
[myid
* NGDT
+ x
]);
264 /* And now a 64-bit one */
265 ssdtosyssd(&gdt_segs
[GPROC0_SEL
],
266 (struct system_segment_descriptor
*)&gdt
[myid
* NGDT
+ GPROC0_SEL
]);
268 r_gdt
.rd_limit
= NGDT
* sizeof(gdt
[0]) - 1;
269 r_gdt
.rd_base
= (long) &gdt
[myid
* NGDT
];
270 lgdt(&r_gdt
); /* does magic intra-segment return */
272 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
273 wrmsr(MSR_FSBASE
, 0); /* User value */
274 wrmsr(MSR_GSBASE
, (u_int64_t
)ps
);
275 wrmsr(MSR_KGSBASE
, 0); /* XXX User value while we're in the kernel */
277 lidt(&r_idt_arr
[mdcpu
->mi
.gd_cpuid
]);
281 mdcpu
->gd_currentldt
= _default_ldt
;
284 gsel_tss
= GSEL(GPROC0_SEL
, SEL_KPL
);
285 gdt
[myid
* NGDT
+ GPROC0_SEL
].sd_type
= SDT_SYSTSS
;
287 md
= mdcpu
; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
289 md
->gd_common_tss
.tss_rsp0
= 0; /* not used until after switch */
291 md
->gd_common_tss
.tss_ioopt
= (sizeof md
->gd_common_tss
) << 16;
293 md
->gd_tss_gdt
= &gdt
[myid
* NGDT
+ GPROC0_SEL
];
294 md
->gd_common_tssd
= *md
->gd_tss_gdt
;
296 /* double fault stack */
297 md
->gd_common_tss
.tss_ist1
=
298 (long)&md
->mi
.gd_prvspace
->idlestack
[
299 sizeof(md
->mi
.gd_prvspace
->idlestack
)];
304 * Set to a known state:
305 * Set by mpboot.s: CR0_PG, CR0_PE
306 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
309 cr0
&= ~(CR0_CD
| CR0_NW
| CR0_EM
);
312 /* Set up the fast syscall stuff */
313 msr
= rdmsr(MSR_EFER
) | EFER_SCE
;
314 wrmsr(MSR_EFER
, msr
);
315 wrmsr(MSR_LSTAR
, (u_int64_t
)IDTVEC(fast_syscall
));
316 wrmsr(MSR_CSTAR
, (u_int64_t
)IDTVEC(fast_syscall32
));
317 msr
= ((u_int64_t
)GSEL(GCODE_SEL
, SEL_KPL
) << 32) |
318 ((u_int64_t
)GSEL(GUCODE32_SEL
, SEL_UPL
) << 48);
319 wrmsr(MSR_STAR
, msr
);
320 wrmsr(MSR_SF_MASK
, PSL_NT
|PSL_T
|PSL_I
|PSL_C
|PSL_D
|PSL_IOPL
);
322 pmap_set_opt(); /* PSE/4MB pages, etc */
323 pmap_init_pat(); /* Page Attribute Table */
325 /* set up CPU registers and state */
328 /* set up SSE/NX registers */
331 /* set up FPU state on the AP */
334 /* disable the APIC, just to be SURE */
335 lapic
->svr
&= ~APIC_SVR_ENABLE
;
338 /*******************************************************************
339 * local functions and data
343 * Start the SMP system
346 mp_start_aps(void *dummy __unused
)
349 /* start each Application Processor */
350 start_all_aps(boot_address
);
352 mp_bsp_simple_setup();
355 SYSINIT(startaps
, SI_BOOT2_START_APS
, SI_ORDER_FIRST
, mp_start_aps
, NULL
);
358 * start each AP in our list
361 start_all_aps(u_int boot_addr
)
363 vm_offset_t va
= boot_address
+ KERNBASE
;
364 u_int64_t
*pt4
, *pt3
, *pt2
;
372 u_long mpbioswarmvec
;
373 struct mdglobaldata
*gd
;
374 struct privatespace
*ps
;
377 POSTCODE(START_ALL_APS_POST
);
379 /* install the AP 1st level boot code */
380 pmap_kenter(va
, boot_address
);
381 cpu_invlpg((void *)va
); /* JG XXX */
382 bcopy(mptramp_start
, (void *)va
, bootMP_size
);
384 /* Locate the page tables, they'll be below the trampoline */
385 pt4
= (u_int64_t
*)(uintptr_t)(mptramp_pagetables
+ KERNBASE
);
386 pt3
= pt4
+ (PAGE_SIZE
) / sizeof(u_int64_t
);
387 pt2
= pt3
+ (PAGE_SIZE
) / sizeof(u_int64_t
);
389 /* Create the initial 1GB replicated page tables */
390 for (i
= 0; i
< 512; i
++) {
391 /* Each slot of the level 4 pages points to the same level 3 page */
392 pt4
[i
] = (u_int64_t
)(uintptr_t)(mptramp_pagetables
+ PAGE_SIZE
);
393 pt4
[i
] |= kernel_pmap
.pmap_bits
[PG_V_IDX
] |
394 kernel_pmap
.pmap_bits
[PG_RW_IDX
] |
395 kernel_pmap
.pmap_bits
[PG_U_IDX
];
397 /* Each slot of the level 3 pages points to the same level 2 page */
398 pt3
[i
] = (u_int64_t
)(uintptr_t)(mptramp_pagetables
+ (2 * PAGE_SIZE
));
399 pt3
[i
] |= kernel_pmap
.pmap_bits
[PG_V_IDX
] |
400 kernel_pmap
.pmap_bits
[PG_RW_IDX
] |
401 kernel_pmap
.pmap_bits
[PG_U_IDX
];
403 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
404 pt2
[i
] = i
* (2 * 1024 * 1024);
405 pt2
[i
] |= kernel_pmap
.pmap_bits
[PG_V_IDX
] |
406 kernel_pmap
.pmap_bits
[PG_RW_IDX
] |
407 kernel_pmap
.pmap_bits
[PG_PS_IDX
] |
408 kernel_pmap
.pmap_bits
[PG_U_IDX
];
411 /* save the current value of the warm-start vector */
412 mpbioswarmvec
= *((u_int32_t
*) WARMBOOT_OFF
);
413 outb(CMOS_REG
, BIOS_RESET
);
414 mpbiosreason
= inb(CMOS_DATA
);
416 /* setup a vector to our boot code */
417 *((volatile u_short
*) WARMBOOT_OFF
) = WARMBOOT_TARGET
;
418 *((volatile u_short
*) WARMBOOT_SEG
) = (boot_address
>> 4);
419 outb(CMOS_REG
, BIOS_RESET
);
420 outb(CMOS_DATA
, BIOS_WARM
); /* 'warm-start' */
423 * If we have a TSC we can figure out the SMI interrupt rate.
424 * The SMI does not necessarily use a constant rate. Spend
425 * up to 250ms trying to figure it out.
428 if (cpu_feature
& CPUID_TSC
) {
429 set_apic_timer(275000);
430 smilast
= read_apic_timer();
431 for (x
= 0; x
< 20 && read_apic_timer(); ++x
) {
432 smicount
= smitest();
433 if (smibest
== 0 || smilast
- smicount
< smibest
)
434 smibest
= smilast
- smicount
;
437 if (smibest
> 250000)
440 smibest
= smibest
* (int64_t)1000000 /
441 get_apic_timer_frequency();
445 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
446 1000000 / smibest
, smibest
);
449 for (x
= 1; x
<= naps
; ++x
) {
450 /* This is a bit verbose, it will go away soon. */
452 pssize
= sizeof(struct privatespace
);
453 ps
= (void *)kmem_alloc3(&kernel_map
, pssize
, VM_SUBSYS_GD
,
455 CPU_prvspace
[x
] = ps
;
457 kprintf("ps %d %p %d\n", x
, ps
, pssize
);
460 gd
= &ps
->mdglobaldata
;
461 gd
->mi
.gd_prvspace
= ps
;
463 /* prime data page for it to use */
464 mi_gdinit(&gd
->mi
, x
);
466 ipiq_size
= sizeof(struct lwkt_ipiq
) * (naps
+ 1);
467 gd
->mi
.gd_ipiq
= (void *)kmem_alloc3(&kernel_map
, ipiq_size
,
470 bzero(gd
->mi
.gd_ipiq
, ipiq_size
);
472 gd
->gd_acpi_id
= CPUID_TO_ACPIID(gd
->mi
.gd_cpuid
);
474 /* setup a vector to our boot code */
475 *((volatile u_short
*) WARMBOOT_OFF
) = WARMBOOT_TARGET
;
476 *((volatile u_short
*) WARMBOOT_SEG
) = (boot_addr
>> 4);
477 outb(CMOS_REG
, BIOS_RESET
);
478 outb(CMOS_DATA
, BIOS_WARM
); /* 'warm-start' */
481 * Setup the AP boot stack
483 bootSTK
= &ps
->idlestack
[UPAGES
* PAGE_SIZE
- PAGE_SIZE
];
486 /* attempt to start the Application Processor */
487 CHECK_INIT(99); /* setup checkpoints */
488 if (!start_ap(gd
, boot_addr
, smibest
)) {
489 kprintf("\nAP #%d (PHY# %d) failed!\n",
490 x
, CPUID_TO_APICID(x
));
491 CHECK_PRINT("trace"); /* show checkpoints */
492 /* better panic as the AP may be running loose */
493 kprintf("panic y/n? [y] ");
499 CHECK_PRINT("trace"); /* show checkpoints */
502 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
505 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
506 for (shift
= 0; (1 << shift
) <= ncpus
; ++shift
)
509 ncpus2_shift
= shift
;
511 ncpus2_mask
= ncpus2
- 1;
513 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
514 if ((1 << shift
) < ncpus
)
516 ncpus_fit
= 1 << shift
;
517 ncpus_fit_mask
= ncpus_fit
- 1;
519 /* build our map of 'other' CPUs */
520 mycpu
->gd_other_cpus
= smp_startup_mask
;
521 CPUMASK_NANDBIT(mycpu
->gd_other_cpus
, mycpu
->gd_cpuid
);
523 gd
= (struct mdglobaldata
*)mycpu
;
524 gd
->gd_acpi_id
= CPUID_TO_ACPIID(mycpu
->gd_cpuid
);
526 ipiq_size
= sizeof(struct lwkt_ipiq
) * ncpus
;
527 mycpu
->gd_ipiq
= (void *)kmem_alloc(&kernel_map
, ipiq_size
,
529 bzero(mycpu
->gd_ipiq
, ipiq_size
);
531 /* restore the warmstart vector */
532 *(u_long
*) WARMBOOT_OFF
= mpbioswarmvec
;
533 outb(CMOS_REG
, BIOS_RESET
);
534 outb(CMOS_DATA
, mpbiosreason
);
537 * NOTE! The idlestack for the BSP was setup by locore. Finish
538 * up, clean out the P==V mapping we did earlier.
543 * Wait all APs to finish initializing LAPIC
546 kprintf("SMP: Waiting APs LAPIC initialization\n");
547 if (cpu_feature
& CPUID_TSC
)
548 tsc0_offset
= rdtsc();
553 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask
, smp_startup_mask
)) {
556 if (cpu_feature
& CPUID_TSC
)
557 tsc0_offset
= rdtsc();
559 while (try_mplock() == 0) {
564 /* number of APs actually started */
570 * load the 1st level AP boot code into base memory.
573 /* targets for relocation */
574 extern void bigJump(void);
575 extern void bootCodeSeg(void);
576 extern void bootDataSeg(void);
577 extern void MPentry(void);
579 extern u_int mp_gdtbase
;
584 install_ap_tramp(u_int boot_addr
)
587 int size
= *(int *) ((u_long
) & bootMP_size
);
588 u_char
*src
= (u_char
*) ((u_long
) bootMP
);
589 u_char
*dst
= (u_char
*) boot_addr
+ KERNBASE
;
590 u_int boot_base
= (u_int
) bootMP
;
595 POSTCODE(INSTALL_AP_TRAMP_POST
);
597 for (x
= 0; x
< size
; ++x
)
601 * modify addresses in code we just moved to basemem. unfortunately we
602 * need fairly detailed info about mpboot.s for this to work. changes
603 * to mpboot.s might require changes here.
606 /* boot code is located in KERNEL space */
607 dst
= (u_char
*) boot_addr
+ KERNBASE
;
609 /* modify the lgdt arg */
610 dst32
= (u_int32_t
*) (dst
+ ((u_int
) & mp_gdtbase
- boot_base
));
611 *dst32
= boot_addr
+ ((u_int
) & MP_GDT
- boot_base
);
613 /* modify the ljmp target for MPentry() */
614 dst32
= (u_int32_t
*) (dst
+ ((u_int
) bigJump
- boot_base
) + 1);
615 *dst32
= ((u_int
) MPentry
- KERNBASE
);
617 /* modify the target for boot code segment */
618 dst16
= (u_int16_t
*) (dst
+ ((u_int
) bootCodeSeg
- boot_base
));
619 dst8
= (u_int8_t
*) (dst16
+ 1);
620 *dst16
= (u_int
) boot_addr
& 0xffff;
621 *dst8
= ((u_int
) boot_addr
>> 16) & 0xff;
623 /* modify the target for boot data segment */
624 dst16
= (u_int16_t
*) (dst
+ ((u_int
) bootDataSeg
- boot_base
));
625 dst8
= (u_int8_t
*) (dst16
+ 1);
626 *dst16
= (u_int
) boot_addr
& 0xffff;
627 *dst8
= ((u_int
) boot_addr
>> 16) & 0xff;
633 * This function starts the AP (application processor) identified
634 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
635 * to accomplish this. This is necessary because of the nuances
636 * of the different hardware we might encounter. It ain't pretty,
637 * but it seems to work.
639 * NOTE: eventually an AP gets to ap_init(), which is called just
640 * before the AP goes into the LWKT scheduler's idle loop.
643 start_ap(struct mdglobaldata
*gd
, u_int boot_addr
, int smibest
)
647 u_long icr_lo
, icr_hi
;
649 POSTCODE(START_AP_POST
);
651 /* get the PHYSICAL APIC ID# */
652 physical_cpu
= CPUID_TO_APICID(gd
->mi
.gd_cpuid
);
654 /* calculate the vector */
655 vector
= (boot_addr
>> 12) & 0xff;
657 /* We don't want anything interfering */
660 /* Make sure the target cpu sees everything */
664 * Try to detect when a SMI has occurred, wait up to 200ms.
666 * If a SMI occurs during an AP reset but before we issue
667 * the STARTUP command, the AP may brick. To work around
668 * this problem we hold off doing the AP startup until
669 * after we have detected the SMI. Hopefully another SMI
670 * will not occur before we finish the AP startup.
672 * Retries don't seem to help. SMIs have a window of opportunity
673 * and if USB->legacy keyboard emulation is enabled in the BIOS
674 * the interrupt rate can be quite high.
676 * NOTE: Don't worry about the L1 cache load, it might bloat
677 * ldelta a little but ndelta will be so huge when the SMI
678 * occurs the detection logic will still work fine.
681 set_apic_timer(200000);
686 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
687 * and running the target CPU. OR this INIT IPI might be latched (P5
688 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
691 * see apic/apicreg.h for icr bit definitions.
693 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
697 * Setup the address for the target AP. We can setup
698 * icr_hi once and then just trigger operations with
701 icr_hi
= lapic
->icr_hi
& ~APIC_ID_MASK
;
702 icr_hi
|= (physical_cpu
<< 24);
703 icr_lo
= lapic
->icr_lo
& 0xfff00000;
704 lapic
->icr_hi
= icr_hi
;
707 * Do an INIT IPI: assert RESET
709 * Use edge triggered mode to assert INIT
711 lapic
->icr_lo
= icr_lo
| 0x00004500;
712 while (lapic
->icr_lo
& APIC_DELSTAT_MASK
)
716 * The spec calls for a 10ms delay but we may have to use a
717 * MUCH lower delay to avoid bricking an AP due to a fast SMI
718 * interrupt. We have other loops here too and dividing by 2
719 * doesn't seem to be enough even after subtracting 350us,
722 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
723 * interrupt was detected we use the full 10ms.
727 else if (smibest
< 150 * 4 + 350)
729 else if ((smibest
- 350) / 4 < 10000)
730 u_sleep((smibest
- 350) / 4);
735 * Do an INIT IPI: deassert RESET
737 * Use level triggered mode to deassert. It is unclear
738 * why we need to do this.
740 lapic
->icr_lo
= icr_lo
| 0x00008500;
741 while (lapic
->icr_lo
& APIC_DELSTAT_MASK
)
743 u_sleep(150); /* wait 150us */
746 * Next we do a STARTUP IPI: the previous INIT IPI might still be
747 * latched, (P5 bug) this 1st STARTUP would then terminate
748 * immediately, and the previously started INIT IPI would continue. OR
749 * the previous INIT IPI has already run. and this STARTUP IPI will
750 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
753 lapic
->icr_lo
= icr_lo
| 0x00000600 | vector
;
754 while (lapic
->icr_lo
& APIC_DELSTAT_MASK
)
756 u_sleep(200); /* wait ~200uS */
759 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
760 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
761 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
762 * recognized after hardware RESET or INIT IPI.
764 lapic
->icr_lo
= icr_lo
| 0x00000600 | vector
;
765 while (lapic
->icr_lo
& APIC_DELSTAT_MASK
)
768 /* Resume normal operation */
771 /* wait for it to start, see ap_init() */
772 set_apic_timer(5000000);/* == 5 seconds */
773 while (read_apic_timer()) {
774 if (CPUMASK_TESTBIT(smp_startup_mask
, gd
->mi
.gd_cpuid
))
775 return 1; /* return SUCCESS */
778 return 0; /* return FAILURE */
793 while (read_apic_timer()) {
795 for (count
= 0; count
< 100; ++count
)
796 ntsc
= rdtsc(); /* force loop to occur */
798 ndelta
= ntsc
- ltsc
;
801 if (ndelta
> ldelta
* 2)
804 ldelta
= ntsc
- ltsc
;
807 return(read_apic_timer());
811 * Synchronously flush the TLB on all other CPU's. The current cpu's
812 * TLB is not flushed. If the caller wishes to flush the current cpu's
813 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
815 * This routine may be called concurrently from multiple cpus. When this
816 * happens, smp_invltlb() can wind up sticking around in the confirmation
817 * while() loop at the end as additional cpus are added to the global
818 * cpumask, until they are acknowledged by another IPI.
820 * NOTE: If for some reason we were unable to start all cpus we cannot
821 * safely use broadcast IPIs.
824 cpumask_t smp_smurf_mask
;
825 static cpumask_t smp_invltlb_mask
;
828 cpumask_t smp_in_mask
;
830 cpumask_t smp_invmask
;
831 extern cpumask_t smp_idleinvl_mask
;
832 extern cpumask_t smp_idleinvl_reqs
;
835 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove
836 * bits that do not need to be IPId. These bits are still part of the command,
837 * but the target cpus have already been signalled and do not need to be
840 #include <sys/spinlock.h>
841 #include <sys/spinlock2.h>
845 smp_smurf_fetchset(cpumask_t
*mask
)
853 while (i
< CPUMASK_ELEMENTS
) {
854 obits
= smp_smurf_mask
.ary
[i
];
856 nbits
= obits
| mask
->ary
[i
];
857 if (atomic_cmpset_long(&smp_smurf_mask
.ary
[i
], obits
, nbits
)) {
858 omask
.ary
[i
] = obits
;
862 CPUMASK_NANDMASK(*mask
, omask
);
866 * This is a mechanism which guarantees that cpu_invltlb() will be executed
867 * on idle cpus without having to signal or wake them up. The invltlb will be
868 * executed when they wake up, prior to any scheduling or interrupt thread.
870 * (*mask) is modified to remove the cpus we successfully negotiate this
871 * function with. This function may only be used with semi-synchronous
872 * commands (typically invltlb's or semi-synchronous invalidations which
873 * are usually associated only with kernel memory).
876 smp_smurf_idleinvlclr(cpumask_t
*mask
)
878 if (optimized_invltlb
) {
879 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs
, *mask
);
880 /* cpu_lfence() not needed */
881 CPUMASK_NANDMASK(*mask
, smp_idleinvl_mask
);
886 * Issue cpu_invltlb() across all cpus except the current cpu.
888 * This function will arrange to avoid idle cpus, but still gurantee that
889 * invltlb is run on them when they wake up prior to any scheduling or
895 struct mdglobaldata
*md
= mdcpu
;
897 unsigned long rflags
;
899 uint64_t tsc_base
= rdtsc();
903 if (report_invltlb_src
> 0) {
904 if (--report_invltlb_src
<= 0)
909 * Disallow normal interrupts, set all active cpus except our own
910 * in the global smp_invltlb_mask.
912 ++md
->mi
.gd_cnt
.v_smpinvltlb
;
913 crit_enter_gd(&md
->mi
);
916 * Bits we want to set in smp_invltlb_mask. We do not want to signal
917 * our own cpu. Also try to remove bits associated with idle cpus
918 * that we can flag for auto-invltlb.
920 mask
= smp_active_mask
;
921 CPUMASK_NANDBIT(mask
, md
->mi
.gd_cpuid
);
922 smp_smurf_idleinvlclr(&mask
);
924 rflags
= read_rflags();
926 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask
, mask
);
929 * IPI non-idle cpus represented by mask. The omask calculation
930 * removes cpus from the mask which already have a Xinvltlb IPI
931 * pending (avoid double-queueing the IPI).
933 * We must disable real interrupts when setting the smurf flags or
934 * we might race a XINVLTLB before we manage to send the ipi's for
937 * NOTE: We are not signalling ourselves, mask already does NOT
938 * include our own cpu.
940 smp_smurf_fetchset(&mask
);
943 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
944 * the critical section count on the target cpus.
946 CPUMASK_ORMASK(mask
, md
->mi
.gd_cpumask
);
947 if (all_but_self_ipi_enable
&&
948 CPUMASK_CMPMASKEQ(smp_startup_mask
, mask
)) {
949 all_but_self_ipi(XINVLTLB_OFFSET
);
951 CPUMASK_NANDMASK(mask
, md
->mi
.gd_cpumask
);
952 selected_apic_ipi(mask
, XINVLTLB_OFFSET
, APIC_DELMODE_FIXED
);
956 * Wait for acknowledgement by all cpus. smp_inval_intr() will
957 * temporarily enable interrupts to avoid deadlocking the lapic,
958 * and will also handle running cpu_invltlb() and remote invlpg
959 * command son our cpu if some other cpu requests it of us.
961 * WARNING! I originally tried to implement this as a hard loop
962 * checking only smp_invltlb_mask (and issuing a local
963 * cpu_invltlb() if requested), with interrupts enabled
964 * and without calling smp_inval_intr(). This DID NOT WORK.
965 * It resulted in weird races where smurf bits would get
966 * cleared without any action being taken.
969 CPUMASK_ASSZERO(mask
);
970 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask
, mask
)) {
974 if (tsc_frequency
&& rdtsc() - tsc_base
> tsc_frequency
) {
975 kprintf("smp_invltlb %d: waited too long %08jx "
978 smp_invltlb_mask
.ary
[0],
979 smp_idleinvl_mask
.ary
[0],
980 smp_idleinvl_reqs
.ary
[0]);
981 mdcpu
->gd_xinvaltlb
= 0;
982 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask
,
984 smp_invlpg(&smp_active_mask
);
986 if (++repeats
> 10) {
987 kprintf("smp_invltlb: giving up\n");
988 CPUMASK_ASSZERO(smp_invltlb_mask
);
993 write_rflags(rflags
);
994 crit_exit_gd(&md
->mi
);
998 * Called from a critical section with interrupts hard-disabled.
999 * This function issues an XINVLTLB IPI and then executes any pending
1000 * command on the current cpu before returning.
1003 smp_invlpg(cpumask_t
*cmdmask
)
1005 struct mdglobaldata
*md
= mdcpu
;
1008 if (report_invlpg_src
> 0) {
1009 if (--report_invlpg_src
<= 0)
1014 * Disallow normal interrupts, set all active cpus in the pmap,
1015 * plus our own for completion processing (it might or might not
1016 * be part of the set).
1018 mask
= smp_active_mask
;
1019 CPUMASK_ANDMASK(mask
, *cmdmask
);
1020 CPUMASK_ORMASK(mask
, md
->mi
.gd_cpumask
);
1023 * Avoid double-queuing IPIs, which can deadlock us. We must disable
1024 * real interrupts when setting the smurf flags or we might race a
1025 * XINVLTLB before we manage to send the ipi's for the bits we set.
1027 * NOTE: We might be including our own cpu in the smurf mask.
1029 smp_smurf_fetchset(&mask
);
1032 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
1033 * the critical section count on the target cpus.
1035 * We do not include our own cpu when issuing the IPI.
1037 if (all_but_self_ipi_enable
&&
1038 CPUMASK_CMPMASKEQ(smp_startup_mask
, mask
)) {
1039 all_but_self_ipi(XINVLTLB_OFFSET
);
1041 CPUMASK_NANDMASK(mask
, md
->mi
.gd_cpumask
);
1042 selected_apic_ipi(mask
, XINVLTLB_OFFSET
, APIC_DELMODE_FIXED
);
1046 * This will synchronously wait for our command to complete,
1047 * as well as process commands from other cpus. It also handles
1050 * (interrupts are disabled and we are in a critical section here)
1058 globaldata_t gd
= mycpu
;
1062 * Ignore all_but_self_ipi_enable here and just use it.
1064 all_but_self_ipi(XSNIFF_OFFSET
);
1065 gd
->gd_sample_pc
= smp_sniff
;
1066 gd
->gd_sample_sp
= &dummy
;
1070 * Called from Xinvltlb assembly with interrupts hard-disabled and in a
1071 * critical section. gd_intr_nesting_level may or may not be bumped
1072 * depending on entry.
1074 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT.
1075 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE
1076 * IS IN A CRITICAL SECTION.
1079 smp_inval_intr(void)
1081 struct mdglobaldata
*md
= mdcpu
;
1084 uint64_t tsc_base
= rdtsc();
1089 * The idle code is in a critical section, but that doesn't stop
1090 * Xinvltlb from executing, so deal with the race which can occur
1091 * in that situation. Otherwise r-m-w operations by pmap_inval_intr()
1092 * may have problems.
1094 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs
, md
->mi
.gd_cpuid
)) {
1095 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask
, md
->mi
.gd_cpuid
);
1102 * This is a real mess. I'd like to just leave interrupts disabled
1103 * but it can cause the lapic to deadlock if too many interrupts queue
1104 * to it, due to the idiotic design of the lapic. So instead we have
1105 * to enter a critical section so normal interrupts are made pending
1106 * and track whether this one was reentered.
1108 if (md
->gd_xinvaltlb
) { /* reentrant on cpu */
1109 md
->gd_xinvaltlb
= 2;
1112 md
->gd_xinvaltlb
= 1;
1115 * Check only those cpus with active Xinvl* commands pending.
1117 * We are going to enable interrupts so make sure we are in a
1118 * critical section. This is necessary to avoid deadlocking
1119 * the lapic and to ensure that we execute our commands prior to
1120 * any nominal interrupt or preemption.
1122 * WARNING! It is very important that we only clear out but in
1123 * smp_smurf_mask once for each interrupt we take. In
1124 * this case, we clear it on initial entry and only loop
1125 * on the reentrancy detect (caused by another interrupt).
1127 cpumask
= smp_invmask
;
1131 ATOMIC_CPUMASK_ORBIT(smp_in_mask
, md
->mi
.gd_cpuid
);
1133 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask
, md
->mi
.gd_cpuid
);
1136 * Specific page request(s), and we can't return until all bits
1143 * Also execute any pending full invalidation request in
1146 if (CPUMASK_TESTBIT(smp_invltlb_mask
, md
->mi
.gd_cpuid
)) {
1147 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask
,
1154 if (tsc_frequency
&& rdtsc() - tsc_base
> tsc_frequency
) {
1155 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx "
1156 "idle=%08jx/%08jx\n",
1159 smp_invltlb_mask
.ary
[0],
1160 smp_idleinvl_mask
.ary
[0],
1161 smp_idleinvl_reqs
.ary
[0]);
1172 * We can only add bits to the cpumask to test during the
1173 * loop because the smp_invmask bit is cleared once the
1174 * originator completes the command (the targets may still
1175 * be cycling their own completions in this loop, afterwords).
1177 * lfence required prior to all tests as this Xinvltlb
1178 * interrupt could race the originator (already be in progress
1179 * wnen the originator decides to issue, due to an issue by
1183 CPUMASK_ORMASK(cpumask
, smp_invmask
);
1184 /*cpumask = smp_active_mask;*/ /* XXX */
1186 if (pmap_inval_intr(&cpumask
, toolong
) == 0) {
1188 * Clear our smurf mask to allow new IPIs, but deal
1189 * with potential races.
1195 * Test if someone sent us another invalidation IPI, break
1196 * out so we can take it to avoid deadlocking the lapic
1197 * interrupt queue (? stupid intel, amd).
1199 if (md
->gd_xinvaltlb
== 2)
1202 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid))
1208 * Full invalidation request
1210 if (CPUMASK_TESTBIT(smp_invltlb_mask
, md
->mi
.gd_cpuid
)) {
1211 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask
,
1218 ATOMIC_CPUMASK_NANDBIT(smp_in_mask
, md
->mi
.gd_cpuid
);
1221 * Check to see if another Xinvltlb interrupt occurred and loop up
1225 if (md
->gd_xinvaltlb
== 2) {
1226 md
->gd_xinvaltlb
= 1;
1229 md
->gd_xinvaltlb
= 0;
1233 cpu_wbinvd_on_all_cpus_callback(void *arg
)
1239 * When called the executing CPU will send an IPI to all other CPUs
1240 * requesting that they halt execution.
1242 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1244 * - Signals all CPUs in map to stop.
1245 * - Waits for each to stop.
1252 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1253 * from executing at same time.
1256 stop_cpus(cpumask_t map
)
1260 CPUMASK_ANDMASK(map
, smp_active_mask
);
1262 /* send the Xcpustop IPI to all CPUs in map */
1263 selected_apic_ipi(map
, XCPUSTOP_OFFSET
, APIC_DELMODE_FIXED
);
1266 mask
= stopped_cpus
;
1267 CPUMASK_ANDMASK(mask
, map
);
1269 } while (CPUMASK_CMPMASKNEQ(mask
, map
));
1276 * Called by a CPU to restart stopped CPUs.
1278 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1280 * - Signals all CPUs in map to restart.
1281 * - Waits for each to restart.
1289 restart_cpus(cpumask_t map
)
1293 /* signal other cpus to restart */
1295 CPUMASK_ANDMASK(mask
, smp_active_mask
);
1297 started_cpus
= mask
;
1300 /* wait for each to clear its bit */
1301 while (CPUMASK_CMPMASKNEQ(stopped_cpus
, map
))
1308 * This is called once the mpboot code has gotten us properly relocated
1309 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1310 * and when it returns the scheduler will call the real cpu_idle() main
1311 * loop for the idlethread. Interrupts are disabled on entry and should
1312 * remain disabled at return.
1320 * Adjust smp_startup_mask to signal the BSP that we have started
1321 * up successfully. Note that we do not yet hold the BGL. The BSP
1322 * is waiting for our signal.
1324 * We can't set our bit in smp_active_mask yet because we are holding
1325 * interrupts physically disabled and remote cpus could deadlock
1326 * trying to send us an IPI.
1328 ATOMIC_CPUMASK_ORBIT(smp_startup_mask
, mycpu
->gd_cpuid
);
1332 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1333 * non-zero, then get the MP lock.
1335 * Note: We are in a critical section.
1337 * Note: we are the idle thread, we can only spin.
1339 * Note: The load fence is memory volatile and prevents the compiler
1340 * from improperly caching mp_finish_lapic, and the cpu from improperly
1343 while (mp_finish_lapic
== 0) {
1348 while (try_mplock() == 0) {
1354 if (cpu_feature
& CPUID_TSC
) {
1356 * The BSP is constantly updating tsc0_offset, figure out
1357 * the relative difference to synchronize ktrdump.
1359 tsc_offsets
[mycpu
->gd_cpuid
] = rdtsc() - tsc0_offset
;
1362 /* BSP may have changed PTD while we're waiting for the lock */
1365 /* Build our map of 'other' CPUs. */
1366 mycpu
->gd_other_cpus
= smp_startup_mask
;
1367 ATOMIC_CPUMASK_NANDBIT(mycpu
->gd_other_cpus
, mycpu
->gd_cpuid
);
1369 /* A quick check from sanity claus */
1370 cpu_id
= APICID_TO_CPUID((lapic
->id
& 0xff000000) >> 24);
1371 if (mycpu
->gd_cpuid
!= cpu_id
) {
1372 kprintf("SMP: assigned cpuid = %d\n", mycpu
->gd_cpuid
);
1373 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1374 cpu_id
, (lapic
->id
& 0xff000000) >> 24);
1376 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD
[MPPTDI
]);
1378 panic("cpuid mismatch! boom!!");
1381 /* Initialize AP's local APIC for irq's */
1384 /* LAPIC initialization is done */
1385 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask
, mycpu
->gd_cpuid
);
1389 /* Let BSP move onto the next initialization stage */
1394 * Interlock for finalization. Wait until mp_finish is non-zero,
1395 * then get the MP lock.
1397 * Note: We are in a critical section.
1399 * Note: we are the idle thread, we can only spin.
1401 * Note: The load fence is memory volatile and prevents the compiler
1402 * from improperly caching mp_finish, and the cpu from improperly
1405 while (mp_finish
== 0) {
1410 /* BSP may have changed PTD while we're waiting for the lock */
1413 /* Set memory range attributes for this CPU to match the BSP */
1414 mem_range_AP_init();
1417 * Once we go active we must process any IPIQ messages that may
1418 * have been queued, because no actual IPI will occur until we
1419 * set our bit in the smp_active_mask. If we don't the IPI
1420 * message interlock could be left set which would also prevent
1423 * The idle loop doesn't expect the BGL to be held and while
1424 * lwkt_switch() normally cleans things up this is a special case
1425 * because we returning almost directly into the idle loop.
1427 * The idle thread is never placed on the runq, make sure
1428 * nothing we've done put it there.
1432 * Hold a critical section and allow real interrupts to occur. Zero
1433 * any spurious interrupts which have accumulated, then set our
1434 * smp_active_mask indicating that we are fully operational.
1437 __asm
__volatile("sti; pause; pause"::);
1438 bzero(mdcpu
->gd_ipending
, sizeof(mdcpu
->gd_ipending
));
1439 ATOMIC_CPUMASK_ORBIT(smp_active_mask
, mycpu
->gd_cpuid
);
1442 * Wait until all cpus have set their smp_active_mask and have fully
1443 * operational interrupts before proceeding.
1445 * We need a final cpu_invltlb() because we would not have received
1446 * any until we set our bit in smp_active_mask.
1448 while (mp_finish
== 1) {
1455 * Initialize per-cpu clocks and do other per-cpu initialization.
1456 * At this point code is expected to be able to use the full kernel
1459 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1462 * Since we may have cleaned up the interrupt triggers, manually
1463 * process any pending IPIs before exiting our critical section.
1464 * Once the critical section has exited, normal interrupt processing
1467 atomic_swap_int(&mycpu
->gd_npoll
, 0);
1468 lwkt_process_ipiq();
1472 * Final final, allow the waiting BSP to resume the boot process,
1473 * return 'into' the idle thread bootstrap.
1475 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask
, mycpu
->gd_cpuid
);
1476 KKASSERT((curthread
->td_flags
& TDF_RUNQ
) == 0);
1480 * Get SMP fully working before we start initializing devices.
1487 kprintf("Finish MP startup\n");
1491 * Wait for the active mask to complete, after which all cpus will
1492 * be accepting interrupts.
1495 while (CPUMASK_CMPMASKNEQ(smp_active_mask
, smp_startup_mask
)) {
1501 * Wait for the finalization mask to complete, after which all cpus
1502 * have completely finished initializing and are entering or are in
1503 * their idle thread.
1505 * BSP should have received all required invltlbs but do another
1510 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask
, smp_startup_mask
)) {
1515 while (try_mplock() == 0) {
1521 kprintf("Active CPU Mask: %016jx\n",
1522 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask
));
1526 SYSINIT(finishsmp
, SI_BOOT2_FINISH_SMP
, SI_ORDER_FIRST
, ap_finish
, NULL
);
1529 cpu_send_ipiq(int dcpu
)
1531 if (CPUMASK_TESTBIT(smp_active_mask
, dcpu
))
1532 single_apic_ipi(dcpu
, XIPIQ_OFFSET
, APIC_DELMODE_FIXED
);
1535 #if 0 /* single_apic_ipi_passive() not working yet */
1537 * Returns 0 on failure, 1 on success
1540 cpu_send_ipiq_passive(int dcpu
)
1543 if (CPUMASK_TESTBIT(smp_active_mask
, dcpu
)) {
1544 r
= single_apic_ipi_passive(dcpu
, XIPIQ_OFFSET
,
1545 APIC_DELMODE_FIXED
);
1552 mp_bsp_simple_setup(void)
1554 struct mdglobaldata
*gd
;
1557 /* build our map of 'other' CPUs */
1558 mycpu
->gd_other_cpus
= smp_startup_mask
;
1559 CPUMASK_NANDBIT(mycpu
->gd_other_cpus
, mycpu
->gd_cpuid
);
1561 gd
= (struct mdglobaldata
*)mycpu
;
1562 gd
->gd_acpi_id
= CPUID_TO_ACPIID(mycpu
->gd_cpuid
);
1564 ipiq_size
= sizeof(struct lwkt_ipiq
) * ncpus
;
1565 mycpu
->gd_ipiq
= (void *)kmem_alloc(&kernel_map
, ipiq_size
,
1567 bzero(mycpu
->gd_ipiq
, ipiq_size
);
1571 if (cpu_feature
& CPUID_TSC
)
1572 tsc0_offset
= rdtsc();
1577 * CPU TOPOLOGY DETECTION FUNCTIONS
1580 /* Detect intel topology using CPUID
1581 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41
1584 detect_intel_topology(int count_htt_cores
)
1588 int core_plus_logical_bits
= 0;
1589 int cores_per_package
;
1590 int logical_per_package
;
1591 int logical_per_core
;
1594 if (cpu_high
>= 0xb) {
1597 } else if (cpu_high
>= 0x4) {
1602 for (shift
= 0; (1 << shift
) < count_htt_cores
; ++shift
)
1604 logical_CPU_bits
= 1 << shift
;
1609 cpuid_count(0xb, FUNC_B_THREAD_LEVEL
, p
);
1611 /* if 0xb not supported - fallback to 0x4 */
1612 if (p
[1] == 0 || (FUNC_B_TYPE(p
[2]) != FUNC_B_THREAD_TYPE
)) {
1616 logical_CPU_bits
= FUNC_B_BITS_SHIFT_NEXT_LEVEL(p
[0]);
1618 ecx_index
= FUNC_B_THREAD_LEVEL
+ 1;
1620 cpuid_count(0xb, ecx_index
, p
);
1622 /* Check for the Core type in the implemented sub leaves. */
1623 if (FUNC_B_TYPE(p
[2]) == FUNC_B_CORE_TYPE
) {
1624 core_plus_logical_bits
= FUNC_B_BITS_SHIFT_NEXT_LEVEL(p
[0]);
1630 } while (FUNC_B_TYPE(p
[2]) != FUNC_B_INVALID_TYPE
);
1632 core_bits
= core_plus_logical_bits
- logical_CPU_bits
;
1637 cpuid_count(0x4, 0, p
);
1638 cores_per_package
= FUNC_4_MAX_CORE_NO(p
[0]) + 1;
1640 logical_per_package
= count_htt_cores
;
1641 logical_per_core
= logical_per_package
/ cores_per_package
;
1643 for (shift
= 0; (1 << shift
) < logical_per_core
; ++shift
)
1645 logical_CPU_bits
= shift
;
1647 for (shift
= 0; (1 << shift
) < cores_per_package
; ++shift
)
1654 /* Detect AMD topology using CPUID
1655 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page
1658 detect_amd_topology(int count_htt_cores
)
1661 if ((cpu_feature
& CPUID_HTT
)
1662 && (amd_feature2
& AMDID2_CMP
)) {
1664 if (cpu_procinfo2
& AMDID_COREID_SIZE
) {
1665 core_bits
= (cpu_procinfo2
& AMDID_COREID_SIZE
)
1666 >> AMDID_COREID_SIZE_SHIFT
;
1668 core_bits
= (cpu_procinfo2
& AMDID_CMP_CORES
) + 1;
1669 for (shift
= 0; (1 << shift
) < core_bits
; ++shift
)
1674 logical_CPU_bits
= count_htt_cores
>> core_bits
;
1675 for (shift
= 0; (1 << shift
) < logical_CPU_bits
; ++shift
)
1677 logical_CPU_bits
= shift
;
1679 for (shift
= 0; (1 << shift
) < count_htt_cores
; ++shift
)
1682 logical_CPU_bits
= 0;
1687 amd_get_compute_unit_id(void *arg
)
1691 do_cpuid(0x8000001e, regs
);
1692 cpu_node_t
* mynode
= get_cpu_node_by_cpuid(mycpuid
);
1694 * AMD - CPUID Specification September 2010
1695 * page 34 - //ComputeUnitID = ebx[0:7]//
1697 mynode
->compute_unit_id
= regs
[1] & 0xff;
1701 fix_amd_topology(void)
1705 if (cpu_vendor_id
!= CPU_VENDOR_AMD
)
1707 if ((amd_feature2
& AMDID2_TOPOEXT
) == 0)
1710 CPUMASK_ASSALLONES(mask
);
1711 lwkt_cpusync_simple(mask
, amd_get_compute_unit_id
, NULL
);
1713 kprintf("Compute unit iDS:\n");
1715 for (i
= 0; i
< ncpus
; i
++) {
1716 kprintf("%d-%d; \n",
1717 i
, get_cpu_node_by_cpuid(i
)->compute_unit_id
);
1724 * - logical_CPU_bits
1726 * With the values above (for AMD or INTEL) we are able to generally
1727 * detect the CPU topology (number of cores for each level):
1728 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1729 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf
1732 detect_cpu_topology(void)
1734 static int topology_detected
= 0;
1737 if (topology_detected
)
1739 if ((cpu_feature
& CPUID_HTT
) == 0) {
1741 logical_CPU_bits
= 0;
1744 count
= (cpu_procinfo
& CPUID_HTT_CORES
) >> CPUID_HTT_CORE_SHIFT
;
1746 if (cpu_vendor_id
== CPU_VENDOR_INTEL
)
1747 detect_intel_topology(count
);
1748 else if (cpu_vendor_id
== CPU_VENDOR_AMD
)
1749 detect_amd_topology(count
);
1750 topology_detected
= 1;
1754 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n",
1755 logical_CPU_bits
, core_bits
);
1758 /* Interface functions to calculate chip_ID,
1759 * core_number and logical_number
1760 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1763 get_chip_ID(int cpuid
)
1765 return get_apicid_from_cpuid(cpuid
) >>
1766 (logical_CPU_bits
+ core_bits
);
1770 get_chip_ID_from_APICID(int apicid
)
1772 return apicid
>> (logical_CPU_bits
+ core_bits
);
1776 get_core_number_within_chip(int cpuid
)
1778 return (get_apicid_from_cpuid(cpuid
) >> logical_CPU_bits
) &
1779 ( (1 << core_bits
) -1);
1783 get_logical_CPU_number_within_core(int cpuid
)
1785 return get_apicid_from_cpuid(cpuid
) &
1786 ( (1 << logical_CPU_bits
) -1);