sys/bus/pci/pcivar.h

   1 /*
   2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $
  27  * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.12 2007/11/23 14:41:56 sephe Exp $
  28  *
  29  */
  30
  31 #ifndef _PCIVAR_H_
  32 #define _PCIVAR_H_
  33
  34 #include <sys/queue.h>
  35
  36 /* some PCI bus constants */
  37
  38 #define PCI_BUSMAX      255     /* highest supported bus number */
  39 #define PCI_SLOTMAX     31      /* highest supported slot number */
  40 #define PCI_FUNCMAX     7       /* highest supported function number */
  41 #define PCI_REGMAX      255     /* highest supported config register addr. */
  42
  43 #define PCI_MAXMAPS_0   6       /* max. no. of memory/port maps */
  44 #define PCI_MAXMAPS_1   2       /* max. no. of maps for PCI to PCI bridge */
  45 #define PCI_MAXMAPS_2   1       /* max. no. of maps for CardBus bridge */
  46
  47 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
  48
  49 #ifdef PCI_A64
  50 typedef u_int64_t pci_addr_t;   /* u_int64_t for system with 64bit addresses */
  51 #else
  52 typedef u_int32_t pci_addr_t;   /* u_int64_t for system with 64bit addresses */
  53 #endif
  54
  55 /* config values for PCI power management */
  56 struct pcicfg_pmgt {
  57     u_int16_t   pp_cap;         /* PCI power management capabilities */
  58     u_int8_t    pp_status;      /* config space address of PCI power status reg */
  59     u_int8_t    pp_pmcsr;       /* config space address of PMCSR reg */
  60     u_int8_t    pp_data;        /* config space address of PCI power data reg */
  61 };
  62
  63 /* config header information common to all header types */
  64
  65 typedef struct pcicfg {
  66     struct device *dev;         /* device which owns this */
  67     void        *hdrspec;       /* pointer to header type specific data */
  68
  69     u_int16_t   subvendor;      /* card vendor ID */
  70     u_int16_t   subdevice;      /* card device ID, assigned by card vendor */
  71     u_int16_t   vendor;         /* chip vendor ID */
  72     u_int16_t   device;         /* chip device ID, assigned by chip vendor */
  73
  74     u_int16_t   cmdreg;         /* disable/enable chip and PCI options */
  75     u_int16_t   statreg;        /* supported PCI features and error state */
  76
  77     u_int8_t    baseclass;      /* chip PCI class */
  78     u_int8_t    subclass;       /* chip PCI subclass */
  79     u_int8_t    progif;         /* chip PCI programming interface */
  80     u_int8_t    revid;          /* chip revision ID */
  81
  82     u_int8_t    hdrtype;        /* chip config header type */
  83     u_int8_t    cachelnsz;      /* cache line size in 4byte units */
  84     u_int8_t    intpin;         /* PCI interrupt pin */
  85     u_int8_t    intline;        /* interrupt line (IRQ for PC arch) */
  86
  87     u_int8_t    mingnt;         /* min. useful bus grant time in 250ns units */
  88     u_int8_t    maxlat;         /* max. tolerated bus grant latency in 250ns */
  89     u_int8_t    lattimer;       /* latency timer in units of 30ns bus cycles */
  90
  91     u_int8_t    mfdev;          /* multi-function device (from hdrtype reg) */
  92     u_int8_t    nummaps;        /* actual number of PCI maps used */
  93
  94     u_int8_t    bus;            /* config space bus address */
  95     u_int8_t    slot;           /* config space slot address */
  96     u_int8_t    func;           /* config space function number */
  97
  98     u_int8_t    secondarybus;   /* bus on secondary side of bridge, if any */
  99     u_int8_t    subordinatebus; /* topmost bus number behind bridge, if any */
 100
 101     struct pcicfg_pmgt pmgt;    /* power management */
 102 } pcicfgregs;
 103
 104 /* additional type 1 device config header information (PCI to PCI bridge) */
 105
 106 #ifdef PCI_A64
 107 #define PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
 108 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
 109 #else
 110 #define PCI_PPBMEMBASE(h,l)  (((l)<<16) & ~0xfffff)
 111 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
 112 #endif /* PCI_A64 */
 113
 114 #define PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
 115 #define PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
 116
 117 typedef struct {
 118     pci_addr_t  pmembase;       /* base address of prefetchable memory */
 119     pci_addr_t  pmemlimit;      /* topmost address of prefetchable memory */
 120     u_int32_t   membase;        /* base address of memory window */
 121     u_int32_t   memlimit;       /* topmost address of memory window */
 122     u_int32_t   iobase;         /* base address of port window */
 123     u_int32_t   iolimit;        /* topmost address of port window */
 124     u_int16_t   secstat;        /* secondary bus status register */
 125     u_int16_t   bridgectl;      /* bridge control register */
 126     u_int8_t    seclat;         /* CardBus latency timer */
 127 } pcih1cfgregs;
 128
 129 /* additional type 2 device config header information (CardBus bridge) */
 130
 131 typedef struct {
 132     u_int32_t   membase0;       /* base address of memory window */
 133     u_int32_t   memlimit0;      /* topmost address of memory window */
 134     u_int32_t   membase1;       /* base address of memory window */
 135     u_int32_t   memlimit1;      /* topmost address of memory window */
 136     u_int32_t   iobase0;        /* base address of port window */
 137     u_int32_t   iolimit0;       /* topmost address of port window */
 138     u_int32_t   iobase1;        /* base address of port window */
 139     u_int32_t   iolimit1;       /* topmost address of port window */
 140     u_int32_t   pccardif;       /* PC Card 16bit IF legacy more base addr. */
 141     u_int16_t   secstat;        /* secondary bus status register */
 142     u_int16_t   bridgectl;      /* bridge control register */
 143     u_int8_t    seclat;         /* CardBus latency timer */
 144 } pcih2cfgregs;
 145
 146 extern u_int32_t pci_numdevs;
 147 extern const char *pcib_owner;  /* arbitrate who owns the pci device arch */
 148
 149 /* Only if the prerequisites are present */
 150 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
 151 struct pci_devinfo {
 152         STAILQ_ENTRY(pci_devinfo) pci_links;
 153         struct resource_list resources;
 154         pcicfgregs              cfg;
 155         struct pci_conf         conf;
 156 };
 157 #endif
 158
 159 /* externally visible functions */
 160
 161 const char *pci_ata_match(struct device *dev);
 162 const char *pci_usb_match(struct device *dev);
 163 const char *pci_vga_match(struct device *dev);
 164 const char *pci_chip_match(struct device *dev);
 165
 166 /* low level PCI config register functions provided by pcibus.c */
 167
 168 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
 169 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
 170
 171 /* low level devlist operations for the 2.2 compatibility code in pci.c */
 172 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg);
 173
 174 #ifdef _SYS_BUS_H_
 175
 176 #include "pci_if.h"
 177
 178 /*
 179  * Define pci-specific resource flags for accessing memory via dense
 180  * or bwx memory spaces. These flags are ignored on i386.
 181  */
 182 #define PCI_RF_DENSE    0x10000
 183 #define PCI_RF_BWX      0x20000
 184
 185 enum pci_device_ivars {
 186         PCI_IVAR_SUBVENDOR,
 187         PCI_IVAR_SUBDEVICE,
 188         PCI_IVAR_VENDOR,
 189         PCI_IVAR_DEVICE,
 190         PCI_IVAR_DEVID,
 191         PCI_IVAR_CLASS,
 192         PCI_IVAR_SUBCLASS,
 193         PCI_IVAR_PROGIF,
 194         PCI_IVAR_REVID,
 195         PCI_IVAR_INTPIN,
 196         PCI_IVAR_IRQ,
 197         PCI_IVAR_BUS,
 198         PCI_IVAR_SLOT,
 199         PCI_IVAR_FUNCTION,
 200         PCI_IVAR_SECONDARYBUS,
 201         PCI_IVAR_SUBORDINATEBUS,
 202         PCI_IVAR_ETHADDR,
 203 };
 204
 205 /*
 206  * Simplified accessors for pci devices
 207  *
 208  * The PCI device passed in actually represents a PCI function number
 209  * for the current slot.  The parent of dev is the "pci" slot device.
 210  * Each function number has its own set of ivars.
 211  */
 212 #define PCI_ACCESSOR(A, B, T)                                           \
 213                                                                         \
 214 static __inline T pci_get_ ## A(device_t dev)                           \
 215 {                                                                       \
 216         uintptr_t v;                                                    \
 217         BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \
 218         return (T) v;                                                   \
 219 }                                                                       \
 220                                                                         \
 221 static __inline void pci_set_ ## A(device_t dev, T t)                   \
 222 {                                                                       \
 223         uintptr_t v = (uintptr_t) t;                                            \
 224         BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \
 225 }
 226
 227 PCI_ACCESSOR(subvendor,         SUBVENDOR,      u_int16_t)
 228 PCI_ACCESSOR(subdevice,         SUBDEVICE,      u_int16_t)
 229 PCI_ACCESSOR(vendor,            VENDOR,         u_int16_t)
 230 PCI_ACCESSOR(device,            DEVICE,         u_int16_t)
 231 PCI_ACCESSOR(devid,             DEVID,          u_int32_t)
 232 PCI_ACCESSOR(class,             CLASS,          u_int8_t)
 233 PCI_ACCESSOR(subclass,          SUBCLASS,       u_int8_t)
 234 PCI_ACCESSOR(progif,            PROGIF,         u_int8_t)
 235 PCI_ACCESSOR(revid,             REVID,          u_int8_t)
 236 PCI_ACCESSOR(intpin,            INTPIN,         u_int8_t)
 237 PCI_ACCESSOR(irq,               IRQ,            u_int8_t)
 238 PCI_ACCESSOR(bus,               BUS,            u_int8_t)
 239 PCI_ACCESSOR(slot,              SLOT,           u_int8_t)
 240 PCI_ACCESSOR(function,          FUNCTION,       u_int8_t)
 241 PCI_ACCESSOR(secondarybus,      SECONDARYBUS,   u_int8_t)
 242 PCI_ACCESSOR(subordinatebus,    SUBORDINATEBUS, u_int8_t)
 243 PCI_ACCESSOR(ether,             ETHADDR,        uint8_t *)
 244
 245 #undef PCI_ACCESSOR
 246
 247 static __inline u_int32_t
 248 pci_read_config(device_t dev, int reg, int width)
 249 {
 250     return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
 251 }
 252
 253 static __inline void
 254 pci_write_config(device_t dev, int reg, u_int32_t val, int width)
 255 {
 256     PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
 257 }
 258
 259 /*
 260  * Convenience functions.
 261  *
 262  * These should be used in preference to manually manipulating
 263  * configuration space.
 264  */
 265 static __inline void
 266 pci_enable_busmaster(device_t dev)
 267 {
 268     PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
 269 }
 270
 271 static __inline void
 272 pci_disable_busmaster(device_t dev)
 273 {
 274     PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
 275 }
 276
 277 static __inline void
 278 pci_enable_io(device_t dev, int space)
 279 {
 280     PCI_ENABLE_IO(device_get_parent(dev), dev, space);
 281 }
 282
 283 static __inline void
 284 pci_disable_io(device_t dev, int space)
 285 {
 286     PCI_DISABLE_IO(device_get_parent(dev), dev, space);
 287 }
 288
 289 /*
 290  * PCI power states are as defined by ACPI:
 291  *
 292  * D0   State in which device is on and running.  It is receiving full
 293  *      power from the system and delivering full functionality to the user.
 294  * D1   Class-specific low-power state in which device context may or may not
 295  *      be lost.  Buses in D1 cannot do anything to the bus that would force
 296  *      devices on that bus to loose context.
 297  * D2   Class-specific low-power state in which device context may or may
 298  *      not be lost.  Attains greater power savings than D1.  Buses in D2
 299  *      can cause devices on that bus to loose some context.  Devices in D2
 300  *      must be prepared for the bus to be in D2 or higher.
 301  * D3   State in which the device is off and not running.  Device context is
 302  *      lost.  Power can be removed from the device.
 303  */
 304 #define PCI_POWERSTATE_D0       0
 305 #define PCI_POWERSTATE_D1       1
 306 #define PCI_POWERSTATE_D2       2
 307 #define PCI_POWERSTATE_D3       3
 308 #define PCI_POWERSTATE_UNKNOWN  -1
 309
 310 static __inline int
 311 pci_set_powerstate(device_t dev, int state)
 312 {
 313     return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
 314 }
 315
 316 static __inline int
 317 pci_get_powerstate(device_t dev)
 318 {
 319     return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
 320 }
 321
 322 /*
 323  * Ivars for pci bridges.
 324  *
 325  * Whereas PCI devices are arranged [pciX]->[pciX.Y] with the pci driver
 326  * functions in [pciX] but the individual ivars in [pciX.Y], PCI bridges
 327  * are installed in [pciX.Y] and store their ivars in a softc.  This
 328  * is why the accessor functions for a bridge do not call device_get_parent().
 329  */
 330 /*typedef enum pci_device_ivars pcib_device_ivars;*/
 331 enum pcib_device_ivars {
 332         PCIB_IVAR_BUS,
 333 };
 334
 335 #define PCIB_ACCESSOR(A, B, T)                                           \
 336                                                                          \
 337 static __inline T pcib_get_ ## A(device_t dev)                           \
 338 {                                                                        \
 339         uintptr_t v;                                                     \
 340         BUS_READ_IVAR(dev, dev, PCIB_IVAR_ ## B, &v); \
 341         return (T) v;                                                    \
 342 }                                                                        \
 343                                                                          \
 344 static __inline void pcib_set_ ## A(device_t dev, T t)                   \
 345 {                                                                        \
 346         uintptr_t v = (uintptr_t) t;                                             \
 347         BUS_WRITE_IVAR(dev, dev, PCIB_IVAR_ ## B, v); \
 348 }
 349
 350 PCIB_ACCESSOR(bus,              BUS,            u_int32_t)
 351
 352 #undef PCIB_ACCESSOR
 353
 354 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
 355 device_t pci_find_device(u_int16_t, u_int16_t);
 356 #endif
 357
 358 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
 359
 360 #if defined(_KERNEL) && !defined(KLD_MODULE)
 361 #include "opt_compat_oldpci.h"
 362 #endif
 363
 364 #ifdef COMPAT_OLDPCI
 365 /* all this is going some day */
 366
 367 typedef pcicfgregs *pcici_t;
 368 typedef unsigned pcidi_t;
 369 typedef void pci_inthand_t(void *arg);
 370
 371 #define pci_max_burst_len (3)
 372
 373 /* just copied from old PCI code for now ... */
 374
 375 struct pci_device {
 376     char*    pd_name;
 377     const char*  (*pd_probe ) (pcici_t tag, pcidi_t type);
 378     void   (*pd_attach) (pcici_t tag, int     unit);
 379     u_long  *pd_count;
 380     int    (*pd_shutdown) (int, int);
 381 };
 382
 383 #ifdef __i386__
 384 typedef u_short pci_port_t;
 385 #else
 386 typedef u_int pci_port_t;
 387 #endif
 388
 389 u_long pci_conf_read (pcici_t tag, u_long reg);
 390 void pci_conf_write (pcici_t tag, u_long reg, u_long data);
 391 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
 392 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
 393 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg);
 394 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
 395                       u_int flags);
 396 int pci_unmap_int (pcici_t tag);
 397
 398 pcici_t pci_get_parent_from_tag(pcici_t tag);
 399 int     pci_get_bus_from_tag(pcici_t tag);
 400
 401 struct module;
 402 int compat_pci_handler (struct module *, int, void *);
 403 #define COMPAT_PCI_DRIVER(name, pcidata)                                \
 404 static moduledata_t name##_mod = {                                      \
 405         #name,                                                          \
 406         compat_pci_handler,                                             \
 407         &pcidata                                                        \
 408 };                                                                      \
 409 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
 410
 411
 412 #endif /* COMPAT_OLDPCI */
 413 #endif /* _PCIVAR_H_ */