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Nuke unused macro and comment
[dragonfly.git] / sys / dev / disk / sym / sym_fw2.h
blob7d12769482f200a6b15ab13246fc5b25a5dc95fa
1 /*
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58 /* $FreeBSD: src/sys/dev/sym/sym_fw2.h,v 1.2.2.4 2001/11/11 17:58:54 groudier Exp $ */
59 /* $DragonFly: src/sys/dev/disk/sym/sym_fw2.h,v 1.2 2003/06/17 04:28:31 dillon Exp $ */
60
61 /*
62 * Scripts for SYMBIOS-Processor
63 *
64 * We have to know the offsets of all labels before we reach
65 * them (for forward jumps). Therefore we declare a struct
66 * here. If you make changes inside the script,
67 *
68 * DONT FORGET TO CHANGE THE LENGTHS HERE!
69 */
70
71 /*
72 * Script fragments which are loaded into the on-chip RAM
73 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
74 * Must not exceed 4K bytes.
75 */
76 struct SYM_FWA_SCR {
77 u32 start [ 14];
78 u32 getjob_begin [ 4];
79 u32 getjob_end [ 4];
80 u32 select [ 8];
81 u32 wf_sel_done [ 2];
82 u32 sel_done [ 2];
83 u32 send_ident [ 2];
84 #ifdef SYM_CONF_IARB_SUPPORT
85 u32 select2 [ 8];
86 #else
87 u32 select2 [ 2];
88 #endif
89 u32 command [ 2];
90 u32 dispatch [ 28];
91 u32 sel_no_cmd [ 10];
92 u32 init [ 6];
93 u32 clrack [ 4];
94 u32 disp_status [ 4];
95 u32 datai_done [ 26];
96 u32 datao_done [ 12];
97 u32 datai_phase [ 2];
98 u32 datao_phase [ 4];
99 u32 msg_in [ 2];
100 u32 msg_in2 [ 10];
101 #ifdef SYM_CONF_IARB_SUPPORT
102 u32 status [ 14];
103 #else
104 u32 status [ 10];
105 #endif
106 u32 complete [ 8];
107 u32 complete2 [ 12];
108 u32 complete_error [ 4];
109 u32 done [ 14];
110 u32 done_end [ 2];
111 u32 save_dp [ 8];
112 u32 restore_dp [ 4];
113 u32 disconnect [ 20];
114 #ifdef SYM_CONF_IARB_SUPPORT
115 u32 idle [ 4];
116 #else
117 u32 idle [ 2];
118 #endif
119 #ifdef SYM_CONF_IARB_SUPPORT
120 u32 ungetjob [ 6];
121 #else
122 u32 ungetjob [ 4];
123 #endif
124 u32 reselect [ 4];
125 u32 reselected [ 22];
126 u32 resel_scntl4 [ 20];
127 u32 resel_lun0 [ 6];
128 #if SYM_CONF_MAX_TASK*4 > 512
129 u32 resel_tag [ 26];
130 #elif SYM_CONF_MAX_TASK*4 > 256
131 u32 resel_tag [ 20];
132 #else
133 u32 resel_tag [ 16];
134 #endif
135 u32 resel_dsa [ 2];
136 u32 resel_dsa1 [ 6];
137 u32 resel_no_tag [ 6];
138 u32 data_in [SYM_CONF_MAX_SG * 2];
139 u32 data_in2 [ 4];
140 u32 data_out [SYM_CONF_MAX_SG * 2];
141 u32 data_out2 [ 4];
142 u32 pm0_data [ 12];
143 u32 pm0_data_out [ 6];
144 u32 pm0_data_end [ 6];
145 u32 pm1_data [ 12];
146 u32 pm1_data_out [ 6];
147 u32 pm1_data_end [ 6];
148 };
149
150 /*
151 * Script fragments which stay in main memory for all chips
152 * except for chips that support 8K on-chip RAM.
153 */
154 struct SYM_FWB_SCR {
155 u32 start64 [ 2];
156 u32 no_data [ 2];
157 u32 sel_for_abort [ 18];
158 u32 sel_for_abort_1 [ 2];
159 u32 msg_in_etc [ 12];
160 u32 msg_received [ 4];
161 u32 msg_weird_seen [ 4];
162 u32 msg_extended [ 20];
163 u32 msg_bad [ 6];
164 u32 msg_weird [ 4];
165 u32 msg_weird1 [ 8];
166
167 u32 wdtr_resp [ 6];
168 u32 send_wdtr [ 4];
169 u32 sdtr_resp [ 6];
170 u32 send_sdtr [ 4];
171 u32 ppr_resp [ 6];
172 u32 send_ppr [ 4];
173 u32 nego_bad_phase [ 4];
174 u32 msg_out [ 4];
175 u32 msg_out_done [ 4];
176 u32 data_ovrun [ 2];
177 u32 data_ovrun1 [ 22];
178 u32 data_ovrun2 [ 8];
179 u32 abort_resel [ 16];
180 u32 resend_ident [ 4];
181 u32 ident_break [ 4];
182 u32 ident_break_atn [ 4];
183 u32 sdata_in [ 6];
184 u32 resel_bad_lun [ 4];
185 u32 bad_i_t_l [ 4];
186 u32 bad_i_t_l_q [ 4];
187 u32 bad_status [ 6];
188 u32 pm_handle [ 20];
189 u32 pm_handle1 [ 4];
190 u32 pm_save [ 4];
191 u32 pm0_save [ 14];
192 u32 pm1_save [ 14];
193
194 /* WSR handling */
195 u32 pm_wsr_handle [ 42];
196 u32 wsr_ma_helper [ 4];
197
198 /* Data area */
199 u32 zero [ 1];
200 u32 scratch [ 1];
201 u32 pm0_data_addr [ 1];
202 u32 pm1_data_addr [ 1];
203 u32 saved_dsa [ 1];
204 u32 saved_drs [ 1];
205 u32 done_pos [ 1];
206 u32 startpos [ 1];
207 u32 targtbl [ 1];
208 /* End of data area */
209
210 u32 snooptest [ 6];
211 u32 snoopend [ 2];
212 };
213
214 static struct SYM_FWA_SCR SYM_FWA_SCR = {
215 /*--------------------------< START >----------------------------*/ {
216 /*
217 * Switch the LED on.
218 * Will be patched with a NO_OP if LED
219 * not needed or not desired.
220 */
221 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
222 0,
223 /*
224 * Clear SIGP.
225 */
226 SCR_FROM_REG (ctest2),
227 0,
228 /*
229 * Stop here if the C code wants to perform
230 * some error recovery procedure manually.
231 * (Indicate this by setting SEM in ISTAT)
232 */
233 SCR_FROM_REG (istat),
234 0,
235 /*
236 * Report to the C code the next position in
237 * the start queue the SCRIPTS will schedule.
238 * The C code must not change SCRATCHA.
239 */
240 SCR_LOAD_ABS (scratcha, 4),
241 PADDR_B (startpos),
242 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
243 SIR_SCRIPT_STOPPED,
244 /*
245 * Start the next job.
246 *
247 * @DSA = start point for this job.
248 * SCRATCHA = address of this job in the start queue.
249 *
250 * We will restore startpos with SCRATCHA if we fails the
251 * arbitration or if it is the idle job.
252 *
253 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
254 * is a critical path. If it is partially executed, it then
255 * may happen that the job address is not yet in the DSA
256 * and the the next queue position points to the next JOB.
257 */
258 SCR_LOAD_ABS (dsa, 4),
259 PADDR_B (startpos),
260 SCR_LOAD_REL (temp, 4),
261 4,
262 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
263 SCR_STORE_ABS (temp, 4),
264 PADDR_B (startpos),
265 SCR_LOAD_REL (dsa, 4),
266 0,
267 }/*-------------------------< GETJOB_END >-----------------------*/,{
268 SCR_LOAD_REL (temp, 4),
269 0,
270 SCR_RETURN,
271 0,
272 }/*-------------------------< SELECT >---------------------------*/,{
273 /*
274 * DSA contains the address of a scheduled
275 * data structure.
276 *
277 * SCRATCHA contains the address of the start queue
278 * entry which points to the next job.
279 *
280 * Set Initiator mode.
281 *
282 * (Target mode is left as an exercise for the reader)
283 */
284 SCR_CLR (SCR_TRG),
285 0,
286 /*
287 * And try to select this target.
288 */
289 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
290 PADDR_A (ungetjob),
291 /*
292 * Now there are 4 possibilities:
293 *
294 * (1) The chip looses arbitration.
295 * This is ok, because it will try again,
296 * when the bus becomes idle.
297 * (But beware of the timeout function!)
298 *
299 * (2) The chip is reselected.
300 * Then the script processor takes the jump
301 * to the RESELECT label.
302 *
303 * (3) The chip wins arbitration.
304 * Then it will execute SCRIPTS instruction until
305 * the next instruction that checks SCSI phase.
306 * Then will stop and wait for selection to be
307 * complete or selection time-out to occur.
308 *
309 * After having won arbitration, the SCRIPTS
310 * processor is able to execute instructions while
311 * the SCSI core is performing SCSI selection.
312 */
313 /*
314 * load the savep (saved data pointer) into
315 * the actual data pointer.
316 */
317 SCR_LOAD_REL (temp, 4),
318 offsetof (struct sym_ccb, phys.head.savep),
319 /*
320 * Initialize the status registers
321 */
322 SCR_LOAD_REL (scr0, 4),
323 offsetof (struct sym_ccb, phys.head.status),
324 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
325 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
326 SIR_SEL_ATN_NO_MSG_OUT,
327 }/*-------------------------< SEL_DONE >-------------------------*/,{
328 /*
329 * C1010-33 errata work-around.
330 * Due to a race, the SCSI core may not have
331 * loaded SCNTL3 on SEL_TBL instruction.
332 * We reload it once phase is stable.
333 * Patched with a NOOP for other chips.
334 */
335 SCR_LOAD_REL (scntl3, 1),
336 offsetof(struct sym_dsb, select.sel_scntl3),
337 }/*-------------------------< SEND_IDENT >-----------------------*/,{
338 /*
339 * Selection complete.
340 * Send the IDENTIFY and possibly the TAG message
341 * and negotiation message if present.
342 */
343 SCR_MOVE_TBL ^ SCR_MSG_OUT,
344 offsetof (struct sym_dsb, smsg),
345 }/*-------------------------< SELECT2 >--------------------------*/,{
346 #ifdef SYM_CONF_IARB_SUPPORT
347 /*
348 * Set IMMEDIATE ARBITRATION if we have been given
349 * a hint to do so. (Some job to do after this one).
350 */
351 SCR_FROM_REG (HF_REG),
352 0,
353 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
354 8,
355 SCR_REG_REG (scntl1, SCR_OR, IARB),
356 0,
357 #endif
358 /*
359 * Anticipate the COMMAND phase.
360 * This is the PHASE we expect at this point.
361 */
362 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
363 PADDR_A (sel_no_cmd),
364 }/*-------------------------< COMMAND >--------------------------*/,{
365 /*
366 * ... and send the command
367 */
368 SCR_MOVE_TBL ^ SCR_COMMAND,
369 offsetof (struct sym_dsb, cmd),
370 }/*-------------------------< DISPATCH >-------------------------*/,{
371 /*
372 * MSG_IN is the only phase that shall be
373 * entered at least once for each (re)selection.
374 * So we test it first.
375 */
376 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
377 PADDR_A (msg_in),
378 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
379 PADDR_A (datao_phase),
380 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
381 PADDR_A (datai_phase),
382 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
383 PADDR_A (status),
384 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
385 PADDR_A (command),
386 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
387 PADDR_B (msg_out),
388 /*
389 * Discard as many illegal phases as
390 * required and tell the C code about.
391 */
392 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
393 16,
394 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
395 HADDR_1 (scratch),
396 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
397 -16,
398 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
399 16,
400 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
401 HADDR_1 (scratch),
402 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
403 -16,
404 SCR_INT,
405 SIR_BAD_PHASE,
406 SCR_JUMP,
407 PADDR_A (dispatch),
408 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
409 /*
410 * The target does not switch to command
411 * phase after IDENTIFY has been sent.
412 *
413 * If it stays in MSG OUT phase send it
414 * the IDENTIFY again.
415 */
416 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
417 PADDR_B (resend_ident),
418 /*
419 * If target does not switch to MSG IN phase
420 * and we sent a negotiation, assert the
421 * failure immediately.
422 */
423 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
424 PADDR_A (dispatch),
425 SCR_FROM_REG (HS_REG),
426 0,
427 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
428 SIR_NEGO_FAILED,
429 /*
430 * Jump to dispatcher.
431 */
432 SCR_JUMP,
433 PADDR_A (dispatch),
434 }/*-------------------------< INIT >-----------------------------*/,{
435 /*
436 * Wait for the SCSI RESET signal to be
437 * inactive before restarting operations,
438 * since the chip may hang on SEL_ATN
439 * if SCSI RESET is active.
440 */
441 SCR_FROM_REG (sstat0),
442 0,
443 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
444 -16,
445 SCR_JUMP,
446 PADDR_A (start),
447 }/*-------------------------< CLRACK >---------------------------*/,{
448 /*
449 * Terminate possible pending message phase.
450 */
451 SCR_CLR (SCR_ACK),
452 0,
453 SCR_JUMP,
454 PADDR_A (dispatch),
455 }/*-------------------------< DISP_STATUS >----------------------*/,{
456 /*
457 * Anticipate STATUS phase.
458 *
459 * Does spare 3 SCRIPTS instructions when we have
460 * completed the INPUT of the data.
461 */
462 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
463 PADDR_A (status),
464 SCR_JUMP,
465 PADDR_A (dispatch),
466 }/*-------------------------< DATAI_DONE >-----------------------*/,{
467 /*
468 * If the device still wants to send us data,
469 * we must count the extra bytes.
470 */
471 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)),
472 PADDR_B (data_ovrun),
473 /*
474 * If the SWIDE is not full, jump to dispatcher.
475 * We anticipate a STATUS phase.
476 */
477 SCR_FROM_REG (scntl2),
478 0,
479 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)),
480 PADDR_A (disp_status),
481 /*
482 * The SWIDE is full.
483 * Clear this condition.
484 */
485 SCR_REG_REG (scntl2, SCR_OR, WSR),
486 0,
487 /*
488 * We are expecting an IGNORE RESIDUE message
489 * from the device, otherwise we are in data
490 * overrun condition. Check against MSG_IN phase.
491 */
492 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
493 SIR_SWIDE_OVERRUN,
494 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
495 PADDR_A (disp_status),
496 /*
497 * We are in MSG_IN phase,
498 * Read the first byte of the message.
499 * If it is not an IGNORE RESIDUE message,
500 * signal overrun and jump to message
501 * processing.
502 */
503 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
504 HADDR_1 (msgin[0]),
505 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
506 SIR_SWIDE_OVERRUN,
507 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
508 PADDR_A (msg_in2),
509 /*
510 * We got the message we expected.
511 * Read the 2nd byte, and jump to dispatcher.
512 */
513 SCR_CLR (SCR_ACK),
514 0,
515 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
516 HADDR_1 (msgin[1]),
517 SCR_CLR (SCR_ACK),
518 0,
519 SCR_JUMP,
520 PADDR_A (disp_status),
521 }/*-------------------------< DATAO_DONE >-----------------------*/,{
522 /*
523 * If the device wants us to send more data,
524 * we must count the extra bytes.
525 */
526 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
527 PADDR_B (data_ovrun),
528 /*
529 * If the SODL is not full jump to dispatcher.
530 * We anticipate a STATUS phase.
531 */
532 SCR_FROM_REG (scntl2),
533 0,
534 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)),
535 PADDR_A (disp_status),
536 /*
537 * The SODL is full, clear this condition.
538 */
539 SCR_REG_REG (scntl2, SCR_OR, WSS),
540 0,
541 /*
542 * And signal a DATA UNDERRUN condition
543 * to the C code.
544 */
545 SCR_INT,
546 SIR_SODL_UNDERRUN,
547 SCR_JUMP,
548 PADDR_A (dispatch),
549 }/*-------------------------< DATAI_PHASE >----------------------*/,{
550 SCR_RETURN,
551 0,
552 }/*-------------------------< DATAO_PHASE >----------------------*/,{
553 /*
554 * C1010-66 errata work-around.
555 * Extra clocks of data hold must be inserted
556 * in DATA OUT phase on 33 MHz PCI BUS.
557 * Patched with a NOOP for other chips.
558 */
559 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
560 0,
561 SCR_RETURN,
562 0,
563 }/*-------------------------< MSG_IN >---------------------------*/,{
564 /*
565 * Get the first byte of the message.
566 *
567 * The script processor doesn't negate the
568 * ACK signal after this transfer.
569 */
570 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
571 HADDR_1 (msgin[0]),
572 }/*-------------------------< MSG_IN2 >--------------------------*/,{
573 /*
574 * Check first against 1 byte messages
575 * that we handle from SCRIPTS.
576 */
577 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
578 PADDR_A (complete),
579 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
580 PADDR_A (disconnect),
581 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
582 PADDR_A (save_dp),
583 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
584 PADDR_A (restore_dp),
585 /*
586 * We handle all other messages from the
587 * C code, so no need to waste on-chip RAM
588 * for those ones.
589 */
590 SCR_JUMP,
591 PADDR_B (msg_in_etc),
592 }/*-------------------------< STATUS >---------------------------*/,{
593 /*
594 * get the status
595 */
596 SCR_MOVE_ABS (1) ^ SCR_STATUS,
597 HADDR_1 (scratch),
598 #ifdef SYM_CONF_IARB_SUPPORT
599 /*
600 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
601 * since we may have to tamper the start queue from
602 * the C code.
603 */
604 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
605 8,
606 SCR_REG_REG (scntl1, SCR_AND, ~IARB),
607 0,
608 #endif
609 /*
610 * save status to scsi_status.
611 * mark as complete.
612 */
613 SCR_TO_REG (SS_REG),
614 0,
615 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
616 0,
617 /*
618 * Anticipate the MESSAGE PHASE for
619 * the TASK COMPLETE message.
620 */
621 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
622 PADDR_A (msg_in),
623 SCR_JUMP,
624 PADDR_A (dispatch),
625 }/*-------------------------< COMPLETE >-------------------------*/,{
626 /*
627 * Complete message.
628 *
629 * Copy the data pointer to LASTP.
630 */
631 SCR_STORE_REL (temp, 4),
632 offsetof (struct sym_ccb, phys.head.lastp),
633 /*
634 * When we terminate the cycle by clearing ACK,
635 * the target may disconnect immediately.
636 *
637 * We don't want to be told of an "unexpected disconnect",
638 * so we disable this feature.
639 */
640 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
641 0,
642 /*
643 * Terminate cycle ...
644 */
645 SCR_CLR (SCR_ACK|SCR_ATN),
646 0,
647 /*
648 * ... and wait for the disconnect.
649 */
650 SCR_WAIT_DISC,
651 0,
652 }/*-------------------------< COMPLETE2 >------------------------*/,{
653 /*
654 * Save host status.
655 */
656 SCR_STORE_REL (scr0, 4),
657 offsetof (struct sym_ccb, phys.head.status),
658 /*
659 * Some bridges may reorder DMA writes to memory.
660 * We donnot want the CPU to deal with completions
661 * without all the posted write having been flushed
662 * to memory. This DUMMY READ should flush posted
663 * buffers prior to the CPU having to deal with
664 * completions.
665 */
666 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */
667 offsetof (struct sym_ccb, phys.head.status),
668
669 /*
670 * If command resulted in not GOOD status,
671 * call the C code if needed.
672 */
673 SCR_FROM_REG (SS_REG),
674 0,
675 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
676 PADDR_B (bad_status),
677 /*
678 * If we performed an auto-sense, call
679 * the C code to synchronyze task aborts
680 * with UNIT ATTENTION conditions.
681 */
682 SCR_FROM_REG (HF_REG),
683 0,
684 SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
685 16,
686 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
687 SCR_LOAD_ABS (scratcha, 4),
688 PADDR_B (startpos),
689 SCR_INT,
690 SIR_COMPLETE_ERROR,
691 }/*-------------------------< DONE >-----------------------------*/,{
692 /*
693 * Copy the DSA to the DONE QUEUE and
694 * signal completion to the host.
695 * If we are interrupted between DONE
696 * and DONE_END, we must reset, otherwise
697 * the completed CCB may be lost.
698 */
699 SCR_STORE_ABS (dsa, 4),
700 PADDR_B (saved_dsa),
701 SCR_LOAD_ABS (dsa, 4),
702 PADDR_B (done_pos),
703 SCR_LOAD_ABS (scratcha, 4),
704 PADDR_B (saved_dsa),
705 SCR_STORE_REL (scratcha, 4),
706 0,
707 /*
708 * The instruction below reads the DONE QUEUE next
709 * free position from memory.
710 * In addition it ensures that all PCI posted writes
711 * are flushed and so the DSA value of the done
712 * CCB is visible by the CPU before INTFLY is raised.
713 */
714 SCR_LOAD_REL (temp, 4),
715 4,
716 SCR_INT_FLY,
717 0,
718 SCR_STORE_ABS (temp, 4),
719 PADDR_B (done_pos),
720 }/*-------------------------< DONE_END >-------------------------*/,{
721 SCR_JUMP,
722 PADDR_A (start),
723 }/*-------------------------< SAVE_DP >--------------------------*/,{
724 /*
725 * Clear ACK immediately.
726 * No need to delay it.
727 */
728 SCR_CLR (SCR_ACK),
729 0,
730 /*
731 * Keep track we received a SAVE DP, so
732 * we will switch to the other PM context
733 * on the next PM since the DP may point
734 * to the current PM context.
735 */
736 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
737 0,
738 /*
739 * SAVE_DP message:
740 * Copy the data pointer to SAVEP.
741 */
742 SCR_STORE_REL (temp, 4),
743 offsetof (struct sym_ccb, phys.head.savep),
744 SCR_JUMP,
745 PADDR_A (dispatch),
746 }/*-------------------------< RESTORE_DP >-----------------------*/,{
747 /*
748 * RESTORE_DP message:
749 * Copy SAVEP to actual data pointer.
750 */
751 SCR_LOAD_REL (temp, 4),
752 offsetof (struct sym_ccb, phys.head.savep),
753 SCR_JUMP,
754 PADDR_A (clrack),
755 }/*-------------------------< DISCONNECT >-----------------------*/,{
756 /*
757 * DISCONNECTing ...
758 *
759 * disable the "unexpected disconnect" feature,
760 * and remove the ACK signal.
761 */
762 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
763 0,
764 SCR_CLR (SCR_ACK|SCR_ATN),
765 0,
766 /*
767 * Wait for the disconnect.
768 */
769 SCR_WAIT_DISC,
770 0,
771 /*
772 * Status is: DISCONNECTED.
773 */
774 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
775 0,
776 /*
777 * Save host status.
778 */
779 SCR_STORE_REL (scr0, 4),
780 offsetof (struct sym_ccb, phys.head.status),
781 /*
782 * If QUIRK_AUTOSAVE is set,
783 * do an "save pointer" operation.
784 */
785 SCR_FROM_REG (QU_REG),
786 0,
787 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)),
788 PADDR_A (start),
789 /*
790 * like SAVE_DP message:
791 * Remember we saved the data pointer.
792 * Copy data pointer to SAVEP.
793 */
794 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
795 0,
796 SCR_STORE_REL (temp, 4),
797 offsetof (struct sym_ccb, phys.head.savep),
798 SCR_JUMP,
799 PADDR_A (start),
800 }/*-------------------------< IDLE >-----------------------------*/,{
801 /*
802 * Nothing to do?
803 * Switch the LED off and wait for reselect.
804 * Will be patched with a NO_OP if LED
805 * not needed or not desired.
806 */
807 SCR_REG_REG (gpreg, SCR_OR, 0x01),
808 0,
809 #ifdef SYM_CONF_IARB_SUPPORT
810 SCR_JUMPR,
811 8,
812 #endif
813 }/*-------------------------< UNGETJOB >-------------------------*/,{
814 #ifdef SYM_CONF_IARB_SUPPORT
815 /*
816 * Set IMMEDIATE ARBITRATION, for the next time.
817 * This will give us better chance to win arbitration
818 * for the job we just wanted to do.
819 */
820 SCR_REG_REG (scntl1, SCR_OR, IARB),
821 0,
822 #endif
823 /*
824 * We are not able to restart the SCRIPTS if we are
825 * interrupted and these instruction haven't been
826 * all executed. BTW, this is very unlikely to
827 * happen, but we check that from the C code.
828 */
829 SCR_LOAD_REG (dsa, 0xff),
830 0,
831 SCR_STORE_ABS (scratcha, 4),
832 PADDR_B (startpos),
833 }/*-------------------------< RESELECT >-------------------------*/,{
834 /*
835 * Make sure we are in initiator mode.
836 */
837 SCR_CLR (SCR_TRG),
838 0,
839 /*
840 * Sleep waiting for a reselection.
841 */
842 SCR_WAIT_RESEL,
843 PADDR_A(start),
844 }/*-------------------------< RESELECTED >-----------------------*/,{
845 /*
846 * Switch the LED on.
847 * Will be patched with a NO_OP if LED
848 * not needed or not desired.
849 */
850 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
851 0,
852 /*
853 * load the target id into the sdid
854 */
855 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
856 0,
857 SCR_TO_REG (sdid),
858 0,
859 /*
860 * Load the target control block address
861 */
862 SCR_LOAD_ABS (dsa, 4),
863 PADDR_B (targtbl),
864 SCR_SFBR_REG (dsa, SCR_SHL, 0),
865 0,
866 SCR_REG_REG (dsa, SCR_SHL, 0),
867 0,
868 SCR_REG_REG (dsa, SCR_AND, 0x3c),
869 0,
870 SCR_LOAD_REL (dsa, 4),
871 0,
872 /*
873 * We expect MESSAGE IN phase.
874 * If not, get help from the C code.
875 */
876 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
877 SIR_RESEL_NO_MSG_IN,
878 /*
879 * Load the legacy synchronous transfer registers.
880 */
881 SCR_LOAD_REL (scntl3, 1),
882 offsetof(struct sym_tcb, head.wval),
883 SCR_LOAD_REL (sxfer, 1),
884 offsetof(struct sym_tcb, head.sval),
885 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
886 /*
887 * The C1010 uses a new synchronous timing scheme.
888 * Will be patched with a NO_OP if not a C1010.
889 */
890 SCR_LOAD_REL (scntl4, 1),
891 offsetof(struct sym_tcb, head.uval),
892 /*
893 * Get the IDENTIFY message.
894 */
895 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
896 HADDR_1 (msgin),
897 /*
898 * If IDENTIFY LUN #0, use a faster path
899 * to find the LCB structure.
900 */
901 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
902 PADDR_A (resel_lun0),
903 /*
904 * If message isn't an IDENTIFY,
905 * tell the C code about.
906 */
907 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
908 SIR_RESEL_NO_IDENTIFY,
909 /*
910 * It is an IDENTIFY message,
911 * Load the LUN control block address.
912 */
913 SCR_LOAD_REL (dsa, 4),
914 offsetof(struct sym_tcb, head.luntbl_sa),
915 SCR_SFBR_REG (dsa, SCR_SHL, 0),
916 0,
917 SCR_REG_REG (dsa, SCR_SHL, 0),
918 0,
919 SCR_REG_REG (dsa, SCR_AND, 0xfc),
920 0,
921 SCR_LOAD_REL (dsa, 4),
922 0,
923 SCR_JUMPR,
924 8,
925 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
926 /*
927 * LUN 0 special case (but usual one :))
928 */
929 SCR_LOAD_REL (dsa, 4),
930 offsetof(struct sym_tcb, head.lun0_sa),
931 /*
932 * Jump indirectly to the reselect action for this LUN.
933 */
934 SCR_LOAD_REL (temp, 4),
935 offsetof(struct sym_lcb, head.resel_sa),
936 SCR_RETURN,
937 0,
938 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
939 }/*-------------------------< RESEL_TAG >------------------------*/,{
940 /*
941 * ACK the IDENTIFY previously received.
942 */
943 SCR_CLR (SCR_ACK),
944 0,
945 /*
946 * It shall be a tagged command.
947 * Read SIMPLE+TAG.
948 * The C code will deal with errors.
949 * Agressive optimization, is'nt it? :)
950 */
951 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
952 HADDR_1 (msgin),
953 /*
954 * Load the pointer to the tagged task
955 * table for this LUN.
956 */
957 SCR_LOAD_REL (dsa, 4),
958 offsetof(struct sym_lcb, head.itlq_tbl_sa),
959 /*
960 * The SIDL still contains the TAG value.
961 * Agressive optimization, isn't it? :):)
962 */
963 SCR_REG_SFBR (sidl, SCR_SHL, 0),
964 0,
965 #if SYM_CONF_MAX_TASK*4 > 512
966 SCR_JUMPR ^ IFFALSE (CARRYSET),
967 8,
968 SCR_REG_REG (dsa1, SCR_OR, 2),
969 0,
970 SCR_REG_REG (sfbr, SCR_SHL, 0),
971 0,
972 SCR_JUMPR ^ IFFALSE (CARRYSET),
973 8,
974 SCR_REG_REG (dsa1, SCR_OR, 1),
975 0,
976 #elif SYM_CONF_MAX_TASK*4 > 256
977 SCR_JUMPR ^ IFFALSE (CARRYSET),
978 8,
979 SCR_REG_REG (dsa1, SCR_OR, 1),
980 0,
981 #endif
982 /*
983 * Retrieve the DSA of this task.
984 * JUMP indirectly to the restart point of the CCB.
985 */
986 SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
987 0,
988 SCR_LOAD_REL (dsa, 4),
989 0,
990 SCR_LOAD_REL (temp, 4),
991 offsetof(struct sym_ccb, phys.head.go.restart),
992 SCR_RETURN,
993 0,
994 /* In normal situations we branch to RESEL_DSA */
995 }/*-------------------------< RESEL_DSA >------------------------*/,{
996 /*
997 * ACK the IDENTIFY or TAG previously received.
998 */
999 SCR_CLR (SCR_ACK),
1000 0,
1001 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1002 /*
1003 * load the savep (saved pointer) into
1004 * the actual data pointer.
1005 */
1006 SCR_LOAD_REL (temp, 4),
1007 offsetof (struct sym_ccb, phys.head.savep),
1008 /*
1009 * Initialize the status registers
1010 */
1011 SCR_LOAD_REL (scr0, 4),
1012 offsetof (struct sym_ccb, phys.head.status),
1013 /*
1014 * Jump to dispatcher.
1015 */
1016 SCR_JUMP,
1017 PADDR_A (dispatch),
1018 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1019 /*
1020 * Load the DSA with the unique ITL task.
1021 */
1022 SCR_LOAD_REL (dsa, 4),
1023 offsetof(struct sym_lcb, head.itl_task_sa),
1024 /*
1025 * JUMP indirectly to the restart point of the CCB.
1026 */
1027 SCR_LOAD_REL (temp, 4),
1028 offsetof(struct sym_ccb, phys.head.go.restart),
1029 SCR_RETURN,
1030 0,
1031 /* In normal situations we branch to RESEL_DSA */
1032 }/*-------------------------< DATA_IN >--------------------------*/,{
1033 /*
1034 * Because the size depends on the
1035 * #define SYM_CONF_MAX_SG parameter,
1036 * it is filled in at runtime.
1037 *
1038 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1039 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1040 * || offsetof (struct sym_dsb, data[ i]),
1041 * ##==========================================
1042 */
1043 0
1044 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1045 SCR_CALL,
1046 PADDR_A (datai_done),
1047 SCR_JUMP,
1048 PADDR_B (data_ovrun),
1049 }/*-------------------------< DATA_OUT >-------------------------*/,{
1050 /*
1051 * Because the size depends on the
1052 * #define SYM_CONF_MAX_SG parameter,
1053 * it is filled in at runtime.
1054 *
1055 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1056 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1057 * || offsetof (struct sym_dsb, data[ i]),
1058 * ##==========================================
1059 */
1060 0
1061 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1062 SCR_CALL,
1063 PADDR_A (datao_done),
1064 SCR_JUMP,
1065 PADDR_B (data_ovrun),
1066 }/*-------------------------< PM0_DATA >-------------------------*/,{
1067 /*
1068 * Read our host flags to SFBR, so we will be able
1069 * to check against the data direction we expect.
1070 */
1071 SCR_FROM_REG (HF_REG),
1072 0,
1073 /*
1074 * Check against actual DATA PHASE.
1075 */
1076 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1077 PADDR_A (pm0_data_out),
1078 /*
1079 * Actual phase is DATA IN.
1080 * Check against expected direction.
1081 */
1082 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1083 PADDR_B (data_ovrun),
1084 /*
1085 * Keep track we are moving data from the
1086 * PM0 DATA mini-script.
1087 */
1088 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1089 0,
1090 /*
1091 * Move the data to memory.
1092 */
1093 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1094 offsetof (struct sym_ccb, phys.pm0.sg),
1095 SCR_JUMP,
1096 PADDR_A (pm0_data_end),
1097 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1098 /*
1099 * Actual phase is DATA OUT.
1100 * Check against expected direction.
1101 */
1102 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1103 PADDR_B (data_ovrun),
1104 /*
1105 * Keep track we are moving data from the
1106 * PM0 DATA mini-script.
1107 */
1108 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1109 0,
1110 /*
1111 * Move the data from memory.
1112 */
1113 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1114 offsetof (struct sym_ccb, phys.pm0.sg),
1115 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1116 /*
1117 * Clear the flag that told we were moving
1118 * data from the PM0 DATA mini-script.
1119 */
1120 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1121 0,
1122 /*
1123 * Return to the previous DATA script which
1124 * is guaranteed by design (if no bug) to be
1125 * the main DATA script for this transfer.
1126 */
1127 SCR_LOAD_REL (temp, 4),
1128 offsetof (struct sym_ccb, phys.pm0.ret),
1129 SCR_RETURN,
1130 0,
1131 }/*-------------------------< PM1_DATA >-------------------------*/,{
1132 /*
1133 * Read our host flags to SFBR, so we will be able
1134 * to check against the data direction we expect.
1135 */
1136 SCR_FROM_REG (HF_REG),
1137 0,
1138 /*
1139 * Check against actual DATA PHASE.
1140 */
1141 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1142 PADDR_A (pm1_data_out),
1143 /*
1144 * Actual phase is DATA IN.
1145 * Check against expected direction.
1146 */
1147 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1148 PADDR_B (data_ovrun),
1149 /*
1150 * Keep track we are moving data from the
1151 * PM1 DATA mini-script.
1152 */
1153 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1154 0,
1155 /*
1156 * Move the data to memory.
1157 */
1158 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1159 offsetof (struct sym_ccb, phys.pm1.sg),
1160 SCR_JUMP,
1161 PADDR_A (pm1_data_end),
1162 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1163 /*
1164 * Actual phase is DATA OUT.
1165 * Check against expected direction.
1166 */
1167 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1168 PADDR_B (data_ovrun),
1169 /*
1170 * Keep track we are moving data from the
1171 * PM1 DATA mini-script.
1172 */
1173 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1174 0,
1175 /*
1176 * Move the data from memory.
1177 */
1178 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1179 offsetof (struct sym_ccb, phys.pm1.sg),
1180 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1181 /*
1182 * Clear the flag that told we were moving
1183 * data from the PM1 DATA mini-script.
1184 */
1185 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1186 0,
1187 /*
1188 * Return to the previous DATA script which
1189 * is guaranteed by design (if no bug) to be
1190 * the main DATA script for this transfer.
1191 */
1192 SCR_LOAD_REL (temp, 4),
1193 offsetof (struct sym_ccb, phys.pm1.ret),
1194 SCR_RETURN,
1195 0,
1196 }/*-------------------------<>-----------------------------------*/
1197 };
1198
1199 static struct SYM_FWB_SCR SYM_FWB_SCR = {
1200 /*--------------------------< START64 >--------------------------*/ {
1201 /*
1202 * SCRIPT entry point for the 895A, 896 and 1010.
1203 * For now, there is no specific stuff for those
1204 * chips at this point, but this may come.
1205 */
1206 SCR_JUMP,
1207 PADDR_A (init),
1208 }/*-------------------------< NO_DATA >--------------------------*/,{
1209 SCR_JUMP,
1210 PADDR_B (data_ovrun),
1211 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1212 /*
1213 * We are jumped here by the C code, if we have
1214 * some target to reset or some disconnected
1215 * job to abort. Since error recovery is a serious
1216 * busyness, we will really reset the SCSI BUS, if
1217 * case of a SCSI interrupt occuring in this path.
1218 */
1219
1220 /*
1221 * Set initiator mode.
1222 */
1223 SCR_CLR (SCR_TRG),
1224 0,
1225 /*
1226 * And try to select this target.
1227 */
1228 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1229 PADDR_A (reselect),
1230 /*
1231 * Wait for the selection to complete or
1232 * the selection to time out.
1233 */
1234 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1235 -8,
1236 /*
1237 * Call the C code.
1238 */
1239 SCR_INT,
1240 SIR_TARGET_SELECTED,
1241 /*
1242 * The C code should let us continue here.
1243 * Send the 'kiss of death' message.
1244 * We expect an immediate disconnect once
1245 * the target has eaten the message.
1246 */
1247 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1248 0,
1249 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1250 offsetof (struct sym_hcb, abrt_tbl),
1251 SCR_CLR (SCR_ACK|SCR_ATN),
1252 0,
1253 SCR_WAIT_DISC,
1254 0,
1255 /*
1256 * Tell the C code that we are done.
1257 */
1258 SCR_INT,
1259 SIR_ABORT_SENT,
1260 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1261 /*
1262 * Jump at scheduler.
1263 */
1264 SCR_JUMP,
1265 PADDR_A (start),
1266 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1267 /*
1268 * If it is an EXTENDED (variable size message)
1269 * Handle it.
1270 */
1271 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1272 PADDR_B (msg_extended),
1273 /*
1274 * Let the C code handle any other
1275 * 1 byte message.
1276 */
1277 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1278 PADDR_B (msg_received),
1279 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1280 PADDR_B (msg_received),
1281 /*
1282 * We donnot handle 2 bytes messages from SCRIPTS.
1283 * So, let the C code deal with these ones too.
1284 */
1285 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1286 PADDR_B (msg_weird_seen),
1287 SCR_CLR (SCR_ACK),
1288 0,
1289 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1290 HADDR_1 (msgin[1]),
1291 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1292 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1293 0,
1294 SCR_INT,
1295 SIR_MSG_RECEIVED,
1296 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1297 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1298 0,
1299 SCR_INT,
1300 SIR_MSG_WEIRD,
1301 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1302 /*
1303 * Clear ACK and get the next byte
1304 * assumed to be the message length.
1305 */
1306 SCR_CLR (SCR_ACK),
1307 0,
1308 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1309 HADDR_1 (msgin[1]),
1310 /*
1311 * Try to catch some unlikely situations as 0 length
1312 * or too large the length.
1313 */
1314 SCR_JUMP ^ IFTRUE (DATA (0)),
1315 PADDR_B (msg_weird_seen),
1316 SCR_TO_REG (scratcha),
1317 0,
1318 SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1319 0,
1320 SCR_JUMP ^ IFTRUE (CARRYSET),
1321 PADDR_B (msg_weird_seen),
1322 /*
1323 * We donnot handle extended messages from SCRIPTS.
1324 * Read the amount of data correponding to the
1325 * message length and call the C code.
1326 */
1327 SCR_STORE_REL (scratcha, 1),
1328 offsetof (struct sym_dsb, smsg_ext.size),
1329 SCR_CLR (SCR_ACK),
1330 0,
1331 SCR_MOVE_TBL ^ SCR_MSG_IN,
1332 offsetof (struct sym_dsb, smsg_ext),
1333 SCR_JUMP,
1334 PADDR_B (msg_received),
1335 }/*-------------------------< MSG_BAD >--------------------------*/,{
1336 /*
1337 * unimplemented message - reject it.
1338 */
1339 SCR_INT,
1340 SIR_REJECT_TO_SEND,
1341 SCR_SET (SCR_ATN),
1342 0,
1343 SCR_JUMP,
1344 PADDR_A (clrack),
1345 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1346 /*
1347 * weird message received
1348 * ignore all MSG IN phases and reject it.
1349 */
1350 SCR_INT,
1351 SIR_REJECT_TO_SEND,
1352 SCR_SET (SCR_ATN),
1353 0,
1354 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1355 SCR_CLR (SCR_ACK),
1356 0,
1357 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1358 PADDR_A (dispatch),
1359 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1360 HADDR_1 (scratch),
1361 SCR_JUMP,
1362 PADDR_B (msg_weird1),
1363 }/*-------------------------< WDTR_RESP >------------------------*/,{
1364 /*
1365 * let the target fetch our answer.
1366 */
1367 SCR_SET (SCR_ATN),
1368 0,
1369 SCR_CLR (SCR_ACK),
1370 0,
1371 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1372 PADDR_B (nego_bad_phase),
1373 }/*-------------------------< SEND_WDTR >------------------------*/,{
1374 /*
1375 * Send the M_X_WIDE_REQ
1376 */
1377 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1378 HADDR_1 (msgout),
1379 SCR_JUMP,
1380 PADDR_B (msg_out_done),
1381 }/*-------------------------< SDTR_RESP >------------------------*/,{
1382 /*
1383 * let the target fetch our answer.
1384 */
1385 SCR_SET (SCR_ATN),
1386 0,
1387 SCR_CLR (SCR_ACK),
1388 0,
1389 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1390 PADDR_B (nego_bad_phase),
1391 }/*-------------------------< SEND_SDTR >------------------------*/,{
1392 /*
1393 * Send the M_X_SYNC_REQ
1394 */
1395 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1396 HADDR_1 (msgout),
1397 SCR_JUMP,
1398 PADDR_B (msg_out_done),
1399 }/*-------------------------< PPR_RESP >-------------------------*/,{
1400 /*
1401 * let the target fetch our answer.
1402 */
1403 SCR_SET (SCR_ATN),
1404 0,
1405 SCR_CLR (SCR_ACK),
1406 0,
1407 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1408 PADDR_B (nego_bad_phase),
1409 }/*-------------------------< SEND_PPR >-------------------------*/,{
1410 /*
1411 * Send the M_X_PPR_REQ
1412 */
1413 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1414 HADDR_1 (msgout),
1415 SCR_JUMP,
1416 PADDR_B (msg_out_done),
1417 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1418 SCR_INT,
1419 SIR_NEGO_PROTO,
1420 SCR_JUMP,
1421 PADDR_A (dispatch),
1422 }/*-------------------------< MSG_OUT >--------------------------*/,{
1423 /*
1424 * The target requests a message.
1425 * We donnot send messages that may
1426 * require the device to go to bus free.
1427 */
1428 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1429 HADDR_1 (msgout),
1430 /*
1431 * ... wait for the next phase
1432 * if it's a message out, send it again, ...
1433 */
1434 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1435 PADDR_B (msg_out),
1436 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1437 /*
1438 * Let the C code be aware of the
1439 * sent message and clear the message.
1440 */
1441 SCR_INT,
1442 SIR_MSG_OUT_DONE,
1443 /*
1444 * ... and process the next phase
1445 */
1446 SCR_JUMP,
1447 PADDR_A (dispatch),
1448 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1449 /*
1450 * Use scratcha to count the extra bytes.
1451 */
1452 SCR_LOAD_ABS (scratcha, 4),
1453 PADDR_B (zero),
1454 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1455 /*
1456 * The target may want to transfer too much data.
1457 *
1458 * If phase is DATA OUT write 1 byte and count it.
1459 */
1460 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1461 16,
1462 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1463 HADDR_1 (scratch),
1464 SCR_JUMP,
1465 PADDR_B (data_ovrun2),
1466 /*
1467 * If WSR is set, clear this condition, and
1468 * count this byte.
1469 */
1470 SCR_FROM_REG (scntl2),
1471 0,
1472 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1473 16,
1474 SCR_REG_REG (scntl2, SCR_OR, WSR),
1475 0,
1476 SCR_JUMP,
1477 PADDR_B (data_ovrun2),
1478 /*
1479 * Finally check against DATA IN phase.
1480 * Signal data overrun to the C code
1481 * and jump to dispatcher if not so.
1482 * Read 1 byte otherwise and count it.
1483 */
1484 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1485 16,
1486 SCR_INT,
1487 SIR_DATA_OVERRUN,
1488 SCR_JUMP,
1489 PADDR_A (dispatch),
1490 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1491 HADDR_1 (scratch),
1492 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1493 /*
1494 * Count this byte.
1495 * This will allow to return a negative
1496 * residual to user.
1497 */
1498 SCR_REG_REG (scratcha, SCR_ADD, 0x01),
1499 0,
1500 SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1501 0,
1502 SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1503 0,
1504 /*
1505 * .. and repeat as required.
1506 */
1507 SCR_JUMP,
1508 PADDR_B (data_ovrun1),
1509 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1510 SCR_SET (SCR_ATN),
1511 0,
1512 SCR_CLR (SCR_ACK),
1513 0,
1514 /*
1515 * send the abort/abortag/reset message
1516 * we expect an immediate disconnect
1517 */
1518 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1519 0,
1520 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1521 HADDR_1 (msgout),
1522 SCR_CLR (SCR_ACK|SCR_ATN),
1523 0,
1524 SCR_WAIT_DISC,
1525 0,
1526 SCR_INT,
1527 SIR_RESEL_ABORTED,
1528 SCR_JUMP,
1529 PADDR_A (start),
1530 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1531 /*
1532 * The target stays in MSG OUT phase after having acked
1533 * Identify [+ Tag [+ Extended message ]]. Targets shall
1534 * behave this way on parity error.
1535 * We must send it again all the messages.
1536 */
1537 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
1538 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1539 SCR_JUMP,
1540 PADDR_A (send_ident),
1541 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1542 SCR_CLR (SCR_ATN),
1543 0,
1544 SCR_JUMP,
1545 PADDR_A (select2),
1546 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1547 SCR_SET (SCR_ATN),
1548 0,
1549 SCR_JUMP,
1550 PADDR_A (select2),
1551 }/*-------------------------< SDATA_IN >-------------------------*/,{
1552 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1553 offsetof (struct sym_dsb, sense),
1554 SCR_CALL,
1555 PADDR_A (datai_done),
1556 SCR_JUMP,
1557 PADDR_B (data_ovrun),
1558 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1559 /*
1560 * Message is an IDENTIFY, but lun is unknown.
1561 * Signal problem to C code for logging the event.
1562 * Send a M_ABORT to clear all pending tasks.
1563 */
1564 SCR_INT,
1565 SIR_RESEL_BAD_LUN,
1566 SCR_JUMP,
1567 PADDR_B (abort_resel),
1568 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1569 /*
1570 * We donnot have a task for that I_T_L.
1571 * Signal problem to C code for logging the event.
1572 * Send a M_ABORT message.
1573 */
1574 SCR_INT,
1575 SIR_RESEL_BAD_I_T_L,
1576 SCR_JUMP,
1577 PADDR_B (abort_resel),
1578 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1579 /*
1580 * We donnot have a task that matches the tag.
1581 * Signal problem to C code for logging the event.
1582 * Send a M_ABORTTAG message.
1583 */
1584 SCR_INT,
1585 SIR_RESEL_BAD_I_T_L_Q,
1586 SCR_JUMP,
1587 PADDR_B (abort_resel),
1588 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1589 /*
1590 * Anything different from INTERMEDIATE
1591 * CONDITION MET should be a bad SCSI status,
1592 * given that GOOD status has already been tested.
1593 * Call the C code.
1594 */
1595 SCR_LOAD_ABS (scratcha, 4),
1596 PADDR_B (startpos),
1597 SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1598 SIR_BAD_SCSI_STATUS,
1599 SCR_RETURN,
1600 0,
1601 }/*-------------------------< PM_HANDLE >------------------------*/,{
1602 /*
1603 * Phase mismatch handling.
1604 *
1605 * Since we have to deal with 2 SCSI data pointers
1606 * (current and saved), we need at least 2 contexts.
1607 * Each context (pm0 and pm1) has a saved area, a
1608 * SAVE mini-script and a DATA phase mini-script.
1609 */
1610 /*
1611 * Get the PM handling flags.
1612 */
1613 SCR_FROM_REG (HF_REG),
1614 0,
1615 /*
1616 * If no flags (1rst PM for example), avoid
1617 * all the below heavy flags testing.
1618 * This makes the normal case a bit faster.
1619 */
1620 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
1621 PADDR_B (pm_handle1),
1622 /*
1623 * If we received a SAVE DP, switch to the
1624 * other PM context since the savep may point
1625 * to the current PM context.
1626 */
1627 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
1628 8,
1629 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM),
1630 0,
1631 /*
1632 * If we have been interrupt in a PM DATA mini-script,
1633 * we take the return address from the corresponding
1634 * saved area.
1635 * This ensure the return address always points to the
1636 * main DATA script for this transfer.
1637 */
1638 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
1639 PADDR_B (pm_handle1),
1640 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
1641 16,
1642 SCR_LOAD_REL (ia, 4),
1643 offsetof(struct sym_ccb, phys.pm0.ret),
1644 SCR_JUMP,
1645 PADDR_B (pm_save),
1646 SCR_LOAD_REL (ia, 4),
1647 offsetof(struct sym_ccb, phys.pm1.ret),
1648 SCR_JUMP,
1649 PADDR_B (pm_save),
1650 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{
1651 /*
1652 * Normal case.
1653 * Update the return address so that it
1654 * will point after the interrupted MOVE.
1655 */
1656 SCR_REG_REG (ia, SCR_ADD, 8),
1657 0,
1658 SCR_REG_REG (ia1, SCR_ADDC, 0),
1659 0,
1660 }/*-------------------------< PM_SAVE >--------------------------*/,{
1661 /*
1662 * Clear all the flags that told us if we were
1663 * interrupted in a PM DATA mini-script and/or
1664 * we received a SAVE DP.
1665 */
1666 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))),
1667 0,
1668 /*
1669 * Choose the current PM context.
1670 */
1671 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
1672 PADDR_B (pm1_save),
1673 }/*-------------------------< PM0_SAVE >-------------------------*/,{
1674 SCR_STORE_REL (ia, 4),
1675 offsetof(struct sym_ccb, phys.pm0.ret),
1676 /*
1677 * If WSR bit is set, either UA and RBC may
1678 * have to be changed whether the device wants
1679 * to ignore this residue or not.
1680 */
1681 SCR_FROM_REG (scntl2),
1682 0,
1683 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1684 PADDR_B (pm_wsr_handle),
1685 /*
1686 * Save the remaining byte count, the updated
1687 * address and the return address.
1688 */
1689 SCR_STORE_REL (rbc, 4),
1690 offsetof(struct sym_ccb, phys.pm0.sg.size),
1691 SCR_STORE_REL (ua, 4),
1692 offsetof(struct sym_ccb, phys.pm0.sg.addr),
1693 /*
1694 * Set the current pointer at the PM0 DATA mini-script.
1695 */
1696 SCR_LOAD_ABS (temp, 4),
1697 PADDR_B (pm0_data_addr),
1698 SCR_JUMP,
1699 PADDR_A (dispatch),
1700 }/*-------------------------< PM1_SAVE >-------------------------*/,{
1701 SCR_STORE_REL (ia, 4),
1702 offsetof(struct sym_ccb, phys.pm1.ret),
1703 /*
1704 * If WSR bit is set, either UA and RBC may
1705 * have to be changed whether the device wants
1706 * to ignore this residue or not.
1707 */
1708 SCR_FROM_REG (scntl2),
1709 0,
1710 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1711 PADDR_B (pm_wsr_handle),
1712 /*
1713 * Save the remaining byte count, the updated
1714 * address and the return address.
1715 */
1716 SCR_STORE_REL (rbc, 4),
1717 offsetof(struct sym_ccb, phys.pm1.sg.size),
1718 SCR_STORE_REL (ua, 4),
1719 offsetof(struct sym_ccb, phys.pm1.sg.addr),
1720 /*
1721 * Set the current pointer at the PM1 DATA mini-script.
1722 */
1723 SCR_LOAD_ABS (temp, 4),
1724 PADDR_B (pm1_data_addr),
1725 SCR_JUMP,
1726 PADDR_A (dispatch),
1727 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
1728 /*
1729 * Phase mismatch handling from SCRIPT with WSR set.
1730 * Such a condition can occur if the chip wants to
1731 * execute a CHMOV(size > 1) when the WSR bit is
1732 * set and the target changes PHASE.
1733 *
1734 * We must move the residual byte to memory.
1735 *
1736 * UA contains bit 0..31 of the address to
1737 * move the residual byte.
1738 * Move it to the table indirect.
1739 */
1740 SCR_STORE_REL (ua, 4),
1741 offsetof (struct sym_ccb, phys.wresid.addr),
1742 /*
1743 * Increment UA (move address to next position).
1744 */
1745 SCR_REG_REG (ua, SCR_ADD, 1),
1746 0,
1747 SCR_REG_REG (ua1, SCR_ADDC, 0),
1748 0,
1749 SCR_REG_REG (ua2, SCR_ADDC, 0),
1750 0,
1751 SCR_REG_REG (ua3, SCR_ADDC, 0),
1752 0,
1753 /*
1754 * Compute SCRATCHA as:
1755 * - size to transfer = 1 byte.
1756 * - bit 24..31 = high address bit [32...39].
1757 */
1758 SCR_LOAD_ABS (scratcha, 4),
1759 PADDR_B (zero),
1760 SCR_REG_REG (scratcha, SCR_OR, 1),
1761 0,
1762 SCR_FROM_REG (rbc3),
1763 0,
1764 SCR_TO_REG (scratcha3),
1765 0,
1766 /*
1767 * Move this value to the table indirect.
1768 */
1769 SCR_STORE_REL (scratcha, 4),
1770 offsetof (struct sym_ccb, phys.wresid.size),
1771 /*
1772 * Wait for a valid phase.
1773 * While testing with bogus QUANTUM drives, the C1010
1774 * sometimes raised a spurious phase mismatch with
1775 * WSR and the CHMOV(1) triggered another PM.
1776 * Waiting explicitely for the PHASE seemed to avoid
1777 * the nested phase mismatch. Btw, this didn't happen
1778 * using my IBM drives.
1779 */
1780 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)),
1781 0,
1782 /*
1783 * Perform the move of the residual byte.
1784 */
1785 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1786 offsetof (struct sym_ccb, phys.wresid),
1787 /*
1788 * We can now handle the phase mismatch with UA fixed.
1789 * RBC[0..23]=0 is a special case that does not require
1790 * a PM context. The C code also checks against this.
1791 */
1792 SCR_FROM_REG (rbc),
1793 0,
1794 SCR_RETURN ^ IFFALSE (DATA (0)),
1795 0,
1796 SCR_FROM_REG (rbc1),
1797 0,
1798 SCR_RETURN ^ IFFALSE (DATA (0)),
1799 0,
1800 SCR_FROM_REG (rbc2),
1801 0,
1802 SCR_RETURN ^ IFFALSE (DATA (0)),
1803 0,
1804 /*
1805 * RBC[0..23]=0.
1806 * Not only we donnot need a PM context, but this would
1807 * lead to a bogus CHMOV(0). This condition means that
1808 * the residual was the last byte to move from this CHMOV.
1809 * So, we just have to move the current data script pointer
1810 * (i.e. TEMP) to the SCRIPTS address following the
1811 * interrupted CHMOV and jump to dispatcher.
1812 */
1813 SCR_STORE_ABS (ia, 4),
1814 PADDR_B (scratch),
1815 SCR_LOAD_ABS (temp, 4),
1816 PADDR_B (scratch),
1817 SCR_JUMP,
1818 PADDR_A (dispatch),
1819 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1820 /*
1821 * Helper for the C code when WSR bit is set.
1822 * Perform the move of the residual byte.
1823 */
1824 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1825 offsetof (struct sym_ccb, phys.wresid),
1826 SCR_JUMP,
1827 PADDR_A (dispatch),
1828 }/*-------------------------< ZERO >-----------------------------*/,{
1829 SCR_DATA_ZERO,
1830 }/*-------------------------< SCRATCH >--------------------------*/,{
1831 SCR_DATA_ZERO,
1832 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
1833 SCR_DATA_ZERO,
1834 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
1835 SCR_DATA_ZERO,
1836 }/*-------------------------< SAVED_DSA >------------------------*/,{
1837 SCR_DATA_ZERO,
1838 }/*-------------------------< SAVED_DRS >------------------------*/,{
1839 SCR_DATA_ZERO,
1840 }/*-------------------------< DONE_POS >-------------------------*/,{
1841 SCR_DATA_ZERO,
1842 }/*-------------------------< STARTPOS >-------------------------*/,{
1843 SCR_DATA_ZERO,
1844 }/*-------------------------< TARGTBL >--------------------------*/,{
1845 SCR_DATA_ZERO,
1846
1847 }/*-------------------------< SNOOPTEST >------------------------*/,{
1848 /*
1849 * Read the variable from memory.
1850 */
1851 SCR_LOAD_REL (scratcha, 4),
1852 offsetof(struct sym_hcb, cache),
1853 /*
1854 * Write the variable to memory.
1855 */
1856 SCR_STORE_REL (temp, 4),
1857 offsetof(struct sym_hcb, cache),
1858 /*
1859 * Read back the variable from memory.
1860 */
1861 SCR_LOAD_REL (temp, 4),
1862 offsetof(struct sym_hcb, cache),
1863 }/*-------------------------< SNOOPEND >-------------------------*/,{
1864 /*
1865 * And stop.
1866 */
1867 SCR_INT,
1868 99,
1869 }/*-------------------------<>-----------------------------------*/
1870 };
DragonFly BSD