sys/dev/disk/stg/tmc18c30reg.h

   1 /*      $FreeBSD: src/sys/dev/stg/tmc18c30reg.h,v 1.1.2.2 2001/07/22 00:21:40 non Exp $ */
   2 /*      $DragonFly: src/sys/dev/disk/stg/tmc18c30reg.h,v 1.2 2003/06/17 04:28:31 dillon Exp $   */
   3 /*      $NecBSD: tmc18c30reg.h,v 1.4 1998/03/14 07:05:23 kmatsuda Exp $ */
   4 /*      $NetBSD$        */
   5
   6 /*
   7  * [NetBSD for NEC PC-98 series]
   8  *  Copyright (c) 1996, 1997, 1998
   9  *      NetBSD/pc98 porting staff. All rights reserved.
  10  *  Copyright (c) 1996, 1997, 1998
  11  *      Kouichi Matsuda. All rights reserved.
  12  *
  13  *  Redistribution and use in source and binary forms, with or without
  14  *  modification, are permitted provided that the following conditions
  15  *  are met:
  16  *  1. Redistributions of source code must retain the above copyright
  17  *     notice, this list of conditions and the following disclaimer.
  18  *  2. Redistributions in binary form must reproduce the above copyright
  19  *     notice, this list of conditions and the following disclaimer in the
  20  *     documentation and/or other materials provided with the distribution.
  21  *  3. The name of the author may not be used to endorse or promote products
  22  *     derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  33  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #ifndef _TMC18C30REG_H_
  38 #define _TMC18C30REG_H_
  39
  40 #define tmc_wdata       0x00
  41 #define tmc_rdata       0x00
  42
  43 #define tmc_bctl        0x01
  44 #define         BCTL_BUSFREE    0x00
  45 #define         BCTL_RST        0x01
  46 #define         BCTL_SEL        0x02
  47 #define         BCTL_BSY        0x04
  48 #define         BCTL_ATN        0x08
  49 #define         BCTL_IO         0x10
  50 #define         BCTL_CD         0x20
  51 #define         BCTL_MSG        0x40
  52 #define         BCTL_BUSEN      0x80
  53 #define tmc_bstat       0x01
  54 #define         BSTAT_BSY       0x01
  55 #define         BSTAT_MSG       0x02
  56 #define         BSTAT_IO        0x04
  57 #define         BSTAT_CMD       0x08
  58 #define         BSTAT_REQ       0x10
  59 #define         BSTAT_SEL       0x20
  60 #define         BSTAT_ACK       0x40
  61
  62 #define tmc_ictl        0x02
  63 #define         ICTL_FIFO       0x10
  64 #define         ICTL_ARBIT      0x20
  65 #define         ICTL_SEL        0x40
  66 #define         ICTL_CD         0x80
  67 #define         ICTL_ALLINT     (ICTL_ARBIT | ICTL_CD | ICTL_SEL | ICTL_FIFO)
  68 #define tmc_astat       0x02
  69 #define         ASTAT_INT       0x01
  70 #define         ASTAT_ARBIT     0x02
  71 #define         ASTAT_PARERR    0x04
  72 #define         ASTAT_SCSIRST   0x08
  73 #define         ASTAT_STATMASK  0x0f
  74 #define         ASTAT_FIFODIR   0x10
  75 #define         ASTAT_FIFOEN    0x20
  76 #define         ASTAT_PARENB    0x40
  77 #define         ASTAT_BUSEN     0x80
  78
  79 #define tmc_ssctl       0x03
  80 #define         SSCTL_FSYNCHEN  0x40
  81 #define         SSCTL_SYNCHEN   0x80
  82 #define tmc_fstat       0x03
  83
  84 #define tmc_fctl        0x04
  85 #define         FCTL_CLRFIFO    0x01
  86 #define         FCTL_ARBIT      0x04
  87 #define         FCTL_PARENB     0x08
  88 #define         FCTL_INTEN      0x10
  89 #define         FCTL_CLRINT     0x20
  90 #define         FCTL_FIFOW      0x40
  91 #define         FCTL_FIFOEN     0x80
  92 #define tmc_icnd        0x04
  93
  94 #define tmc_mctl        0x05
  95 #define tmc_idlsb       0x05
  96
  97 #define tmc_idmsb       0x06
  98
  99 #define tmc_wlb         0x07
 100 #define tmc_rlb         0x07
 101
 102 #define tmc_scsiid      0x08
 103 #define tmc_sdna        0x08
 104
 105 #define tmc_istat       0x09
 106 #define         ISTAT_INTEN     0x08
 107 #define         ISTAT_FIFO      0x10
 108 #define         ISTAT_ARBIT     0x20
 109 #define         ISTAT_SEL       0x40
 110 #define         ISTAT_CD        0x80
 111
 112 #define tmc_cfg1        0x0a
 113
 114 #define tmc_ioctl       0x0b
 115 #define         IOCTL_IO32      0x80
 116 #define tmc_cfg2        0x0b
 117
 118 #define tmc_wfifo       0x0c
 119 #define tmc_rfifo       0x0c
 120
 121 #define tmc_fdcnt       0x0e
 122
 123 /* Information transfer phases */
 124 #define BUSFREE_PHASE           0x00
 125 #define DATA_OUT_PHASE          (BSTAT_BSY)
 126 #define DATA_IN_PHASE           (BSTAT_BSY|BSTAT_IO)
 127 #define COMMAND_PHASE           (BSTAT_CMD|BSTAT_BSY)
 128 #define STATUS_PHASE            (BSTAT_CMD|BSTAT_BSY|BSTAT_IO)
 129 #define MESSAGE_OUT_PHASE       (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY)
 130 #define MESSAGE_IN_PHASE        (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY|BSTAT_IO)
 131 #define PHASE_RESELECTED        (BSTAT_SEL|BSTAT_IO)
 132
 133 #define BSTAT_PHMASK            (BSTAT_MSG | BSTAT_IO | BSTAT_CMD)
 134 #define PHASE_MASK              (BSTAT_SEL | BSTAT_BSY | BSTAT_PHMASK)
 135 #define RESEL_PHASE_MASK        (BSTAT_SEL | BSTAT_PHMASK)
 136
 137 #define STG_IS_PHASE_DATA(st) \
 138         ((((st) & PHASE_MASK) & ~BSTAT_IO) == BSTAT_BSY)
 139
 140 /* chip type */
 141 #define TMCCHIP_UNK             0x00
 142 #define TMCCHIP_1800            0x01
 143 #define TMCCHIP_18C50           0x02
 144 #define TMCCHIP_18C30           0x03
 145
 146 #define STGIOSZ 0x10
 147
 148 #endif  /* !_TMC18C30REG_H_ */