contrib/gdb-6/include/opcode/i386.h

   1 /* opcode/i386.h -- Intel 80386 opcode macros
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
  23    ix86 Unix assemblers, generate floating point instructions with
  24    reversed source and destination registers in certain cases.
  25    Unfortunately, gcc and possibly many other programs use this
  26    reversed syntax, so we're stuck with it.
  27
  28    eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
  29    `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
  30    the expected st(3) = st(3) - st
  31
  32    This happens with all the non-commutative arithmetic floating point
  33    operations with two register operands, where the source register is
  34    %st, and destination register is %st(i).
  35
  36    The affected opcode map is dceX, dcfX, deeX, defX.  */
  37
  38 #ifndef SYSV386_COMPAT
  39 /* Set non-zero for broken, compatible instructions.  Set to zero for
  40    non-broken opcodes at your peril.  gcc generates SystemV/386
  41    compatible instructions.  */
  42 #define SYSV386_COMPAT 1
  43 #endif
  44 #ifndef OLDGCC_COMPAT
  45 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
  46    generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
  47    reversed.  */
  48 #define OLDGCC_COMPAT SYSV386_COMPAT
  49 #endif
  50
  51 #define MOV_AX_DISP32 0xa0
  52 #define POP_SEG_SHORT 0x07
  53 #define JUMP_PC_RELATIVE 0xeb
  54 #define INT_OPCODE  0xcd
  55 #define INT3_OPCODE 0xcc
  56 /* The opcode for the fwait instruction, which disassembler treats as a
  57    prefix when it can.  */
  58 #define FWAIT_OPCODE 0x9b
  59 #define ADDR_PREFIX_OPCODE 0x67
  60 #define DATA_PREFIX_OPCODE 0x66
  61 #define LOCK_PREFIX_OPCODE 0xf0
  62 #define CS_PREFIX_OPCODE 0x2e
  63 #define DS_PREFIX_OPCODE 0x3e
  64 #define ES_PREFIX_OPCODE 0x26
  65 #define FS_PREFIX_OPCODE 0x64
  66 #define GS_PREFIX_OPCODE 0x65
  67 #define SS_PREFIX_OPCODE 0x36
  68 #define REPNE_PREFIX_OPCODE 0xf2
  69 #define REPE_PREFIX_OPCODE  0xf3
  70
  71 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
  72 #define NOP_OPCODE (char) 0x90
  73
  74 /* register numbers */
  75 #define EBP_REG_NUM 5
  76 #define ESP_REG_NUM 4
  77
  78 /* modrm_byte.regmem for twobyte escape */
  79 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
  80 /* index_base_byte.index for no index register addressing */
  81 #define NO_INDEX_REGISTER ESP_REG_NUM
  82 /* index_base_byte.base for no base register addressing */
  83 #define NO_BASE_REGISTER EBP_REG_NUM
  84 #define NO_BASE_REGISTER_16 6
  85
  86 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
  87 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
  88 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
  89
  90 /* x86-64 extension prefix.  */
  91 #define REX_OPCODE      0x40
  92
  93 /* Indicates 64 bit operand size.  */
  94 #define REX_W   8
  95 /* High extension to reg field of modrm byte.  */
  96 #define REX_R   4
  97 /* High extension to SIB index field.  */
  98 #define REX_X   2
  99 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 100 #define REX_B   1
 101
 102 /* max operands per insn */
 103 #define MAX_OPERANDS 4
 104
 105 /* max immediates per insn (lcall, ljmp, insertq, extrq) */
 106 #define MAX_IMMEDIATE_OPERANDS 2
 107
 108 /* max memory refs per insn (string ops) */
 109 #define MAX_MEMORY_OPERANDS 2
 110
 111 /* max size of insn mnemonics.  */
 112 #define MAX_MNEM_SIZE 16
 113
 114 /* max size of register name in insn mnemonics.  */
 115 #define MAX_REG_NAME_SIZE 8