sys/platform/pc64/isa/intr_machdep.h

   1 /*-
   2  * Copyright (c) 1991 The Regents of the University of California.
   3  * Copyright (c) 2008 The DragonFly Project.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by the University of
  17  *      California, Berkeley and its contributors.
  18  * 4. Neither the name of the University nor the names of its contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
  35  * $DragonFly: src/sys/platform/pc64/isa/intr_machdep.h,v 1.1 2008/08/29 17:07:19 dillon Exp $
  36  */
  37
  38 #ifndef _ARCH_ISA_INTR_MACHDEP_H_
  39 #define _ARCH_ISA_INTR_MACHDEP_H_
  40
  41 #ifndef LOCORE
  42 #ifndef _SYS_INTERRUPT_H_
  43 #include <sys/interrupt.h>
  44 #endif
  45 #ifndef _SYS_SERIALIZE_H_
  46 #include <sys/serialize.h>
  47 #endif
  48 #endif
  49
  50 /*
  51  * Low level interrupt code.
  52  */
  53
  54 #ifdef _KERNEL
  55
  56 #define IDT_OFFSET      32
  57
  58 #if defined(SMP)
  59 /*
  60  * XXX FIXME: rethink location for all IPI vectors.
  61  */
  62
  63 /*
  64     APIC TPR priority vector levels:
  65
  66         0xff (255) +-------------+
  67                    |             | 15 (IPIs: Xspuriousint)
  68         0xf0 (240) +-------------+
  69                    |             | 14
  70         0xe0 (224) +-------------+
  71                    |             | 13
  72         0xd0 (208) +-------------+
  73                    |             | 12
  74         0xc0 (192) +-------------+
  75                    |             | 11
  76         0xb0 (176) +-------------+
  77                    |             | 10 (IPIs: Xcpustop)
  78         0xa0 (160) +-------------+
  79                    |             |  9 (IPIs: Xinvltlb)
  80         0x90 (144) +-------------+
  81                    |             |  8 (linux/BSD syscall, IGNORE FAST HW INTS)
  82         0x80 (128) +-------------+
  83                    |             |  7 (FAST_INTR 16-23)
  84         0x70 (112) +-------------+
  85                    |             |  6 (FAST_INTR 0-15)
  86         0x60 (96)  +-------------+
  87                    |             |  5 (IGNORE HW INTS)
  88         0x50 (80)  +-------------+
  89                    |             |  4 (2nd IO APIC)
  90         0x40 (64)  +------+------+
  91                    |      |      |  3 (upper APIC hardware INTs: PCI)
  92         0x30 (48)  +------+------+
  93                    |             |  2 (start of hardware INTs: ISA)
  94         0x20 (32)  +-------------+
  95                    |             |  1 (exceptions, traps, etc.)
  96         0x10 (16)  +-------------+
  97                    |             |  0 (exceptions, traps, etc.)
  98         0x00 (0)   +-------------+
  99  */
 100
 101 /* blocking values for local APIC Task Priority Register */
 102 #define TPR_BLOCK_HWI           0x4f            /* hardware INTs */
 103 #define TPR_IGNORE_HWI          0x5f            /* ignore INTs */
 104 #define TPR_BLOCK_FHWI          0x7f            /* hardware FAST INTs */
 105 #define TPR_IGNORE_FHWI         0x8f            /* ignore FAST INTs */
 106 #define TPR_IPI_ONLY            0x8f            /* ignore FAST INTs */
 107 #define TPR_BLOCK_XINVLTLB      0x9f            /*  */
 108 #define TPR_BLOCK_XCPUSTOP      0xaf            /*  */
 109 #define TPR_BLOCK_ALL           0xff            /* all INTs */
 110
 111
 112 /* TLB shootdowns */
 113 #define XINVLTLB_OFFSET         (IDT_OFFSET + 112)
 114
 115 /* unused/open (was inter-cpu clock handling) */
 116 #define XUNUSED113_OFFSET       (IDT_OFFSET + 113)
 117
 118 /* inter-CPU rendezvous */
 119 #define XUNUSED114_OFFSET       (IDT_OFFSET + 114)
 120
 121 /* IPIQ rendezvous */
 122 #define XIPIQ_OFFSET            (IDT_OFFSET + 115)
 123
 124 /* TIMER rendezvous */
 125 #define XTIMER_OFFSET           (IDT_OFFSET + 116)
 126
 127 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
 128 #define XCPUSTOP_OFFSET         (IDT_OFFSET + 128)
 129
 130 /*
 131  * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
 132  */
 133 #define XSPURIOUSINT_OFFSET     (IDT_OFFSET + 223)
 134
 135 #endif /* SMP */
 136
 137 #ifndef LOCORE
 138
 139 /*
 140  * Type of the first (asm) part of an interrupt handler.
 141  */
 142 #ifndef JG_defined_inthand_t
 143 #define JG_defined_inthand_t
 144 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
 145 typedef void unpendhand_t(void);
 146 #endif
 147
 148 #define IDTVEC(name)    __CONCAT(X,name)
 149
 150 #if defined(SMP)
 151 inthand_t
 152         Xinvltlb,       /* TLB shootdowns */
 153         Xcpuast,        /* Additional software trap on other cpu */
 154         Xforward_irq,   /* Forward irq to cpu holding ISR lock */
 155         Xcpustop,       /* CPU stops & waits for another CPU to restart it */
 156         Xspuriousint,   /* handle APIC "spurious INTs" */
 157         Xtimer,         /* handle LAPIC timer INT */
 158         Xipiq;          /* handle lwkt_send_ipiq() requests */
 159 #endif /* SMP */
 160
 161 void    call_fast_unpend(int irq);
 162 void    isa_defaultirq (void);
 163 int     isa_nmi (int cd);
 164 void    icu_reinit (void);
 165
 166 #endif /* LOCORE */
 167
 168 #endif /* _KERNEL */
 169
 170 #endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */