1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
39 #include "insn-config.h"
49 static void init_reg_sets_1 (void);
50 static void init_reg_autoinc (void);
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set
;
75 /* Data for initializing the above. */
77 static const char initial_fixed_regs
[] = FIXED_REGISTERS
;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set
;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set
;
94 /* Data for initializing the above. */
96 static const char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 #ifdef CALL_REALLY_USED_REGISTERS
104 char call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
107 #ifdef CALL_REALLY_USED_REGISTERS
108 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
110 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
114 /* Indexed by hard register number, contains 1 for registers that are
115 fixed use or call used registers that cannot hold quantities across
116 calls even if we are willing to save and restore them. call fixed
117 registers are a subset of call used registers. */
119 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
121 /* The same info as a HARD_REG_SET. */
123 HARD_REG_SET call_fixed_reg_set
;
125 /* Number of non-fixed registers. */
127 int n_non_fixed_regs
;
129 /* Indexed by hard register number, contains 1 for registers
130 that are being used for global register decls.
131 These must be exempt from ordinary flow analysis
132 and are also considered fixed. */
134 char global_regs
[FIRST_PSEUDO_REGISTER
];
136 /* Contains 1 for registers that are set or clobbered by calls. */
137 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
138 for someone's bright idea to have call_used_regs strictly include
139 fixed_regs. Which leaves us guessing as to the set of fixed_regs
140 that are actually preserved. We know for sure that those associated
141 with the local stack frame are safe, but scant others. */
143 HARD_REG_SET regs_invalidated_by_call
;
145 /* Table of register numbers in the order in which to try to use them. */
146 #ifdef REG_ALLOC_ORDER
147 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
149 /* The inverse of reg_alloc_order. */
150 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
153 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
155 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
157 /* The same information, but as an array of unsigned ints. We copy from
158 these unsigned ints to the table above. We do this so the tm.h files
159 do not have to be aware of the wordsize for machines with <= 64 regs.
160 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
163 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
165 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
166 = REG_CLASS_CONTENTS
;
168 /* For each reg class, number of regs it contains. */
170 unsigned int reg_class_size
[N_REG_CLASSES
];
172 /* For each reg class, table listing all the containing classes. */
174 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
176 /* For each reg class, table listing all the classes contained in it. */
178 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
180 /* For each pair of reg classes,
181 a largest reg class contained in their union. */
183 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
185 /* For each pair of reg classes,
186 the smallest reg class containing their union. */
188 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
190 /* Array containing all of the register names. */
192 const char * reg_names
[] = REGISTER_NAMES
;
194 /* For each hard register, the widest mode object that it can contain.
195 This will be a MODE_INT mode if the register can hold integers. Otherwise
196 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
199 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
201 /* 1 if class does contain register of given mode. */
203 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
205 /* Maximum cost of moving from a register in one class to a register in
206 another class. Based on REGISTER_MOVE_COST. */
208 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
210 /* Similar, but here we don't have to move if the first index is a subset
211 of the second so in that case the cost is zero. */
213 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
215 /* Similar, but here we don't have to move if the first index is a superset
216 of the second so in that case the cost is zero. */
218 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
220 #ifdef FORBIDDEN_INC_DEC_CLASSES
222 /* These are the classes that regs which are auto-incremented or decremented
225 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
227 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
230 static char *in_inc_dec
;
232 #endif /* FORBIDDEN_INC_DEC_CLASSES */
234 /* Sample MEM values for use by memory_move_secondary_cost. */
236 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
238 /* Linked list of reg_info structures allocated for reg_n_info array.
239 Grouping all of the allocated structures together in one lump
240 means only one call to bzero to clear them, rather than n smaller
242 struct reg_info_data
{
243 struct reg_info_data
*next
; /* next set of reg_info structures */
244 size_t min_index
; /* minimum index # */
245 size_t max_index
; /* maximum index # */
246 char used_p
; /* nonzero if this has been used previously */
247 reg_info data
[1]; /* beginning of the reg_info data */
250 static struct reg_info_data
*reg_info_head
;
252 /* No more global register variables may be declared; true once
253 regclass has been initialized. */
255 static int no_global_reg_vars
= 0;
258 /* Function called only once to initialize the above data on reg usage.
259 Once this is done, various switches may override. */
266 /* First copy the register information from the initial int form into
269 for (i
= 0; i
< N_REG_CLASSES
; i
++)
271 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
273 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
274 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
275 if (int_reg_class_contents
[i
][j
/ 32]
276 & ((unsigned) 1 << (j
% 32)))
277 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
280 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
281 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
282 memset (global_regs
, 0, sizeof global_regs
);
284 /* Do any additional initialization regsets may need. */
285 INIT_ONCE_REG_SET ();
287 #ifdef REG_ALLOC_ORDER
288 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
289 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
293 /* After switches have been processed, which perhaps alter
294 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
297 init_reg_sets_1 (void)
300 unsigned int /* enum machine_mode */ m
;
301 char allocatable_regs_of_mode
[MAX_MACHINE_MODE
];
303 /* This macro allows the fixed or call-used registers
304 and the register classes to depend on target flags. */
306 #ifdef CONDITIONAL_REGISTER_USAGE
307 CONDITIONAL_REGISTER_USAGE
;
310 /* Compute number of hard regs in each class. */
312 memset (reg_class_size
, 0, sizeof reg_class_size
);
313 for (i
= 0; i
< N_REG_CLASSES
; i
++)
314 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
315 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
318 /* Initialize the table of subunions.
319 reg_class_subunion[I][J] gets the largest-numbered reg-class
320 that is contained in the union of classes I and J. */
322 for (i
= 0; i
< N_REG_CLASSES
; i
++)
324 for (j
= 0; j
< N_REG_CLASSES
; j
++)
329 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
330 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
331 for (k
= 0; k
< N_REG_CLASSES
; k
++)
333 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
338 /* Keep the largest subclass. */ /* SPEE 900308 */
339 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
340 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
342 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
349 /* Initialize the table of superunions.
350 reg_class_superunion[I][J] gets the smallest-numbered reg-class
351 containing the union of classes I and J. */
353 for (i
= 0; i
< N_REG_CLASSES
; i
++)
355 for (j
= 0; j
< N_REG_CLASSES
; j
++)
360 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
361 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
362 for (k
= 0; k
< N_REG_CLASSES
; k
++)
363 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
366 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
370 /* Initialize the tables of subclasses and superclasses of each reg class.
371 First clear the whole table, then add the elements as they are found. */
373 for (i
= 0; i
< N_REG_CLASSES
; i
++)
375 for (j
= 0; j
< N_REG_CLASSES
; j
++)
377 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
378 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
382 for (i
= 0; i
< N_REG_CLASSES
; i
++)
384 if (i
== (int) NO_REGS
)
387 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
391 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
395 /* Reg class I is a subclass of J.
396 Add J to the table of superclasses of I. */
397 p
= ®_class_superclasses
[i
][0];
398 while (*p
!= LIM_REG_CLASSES
) p
++;
399 *p
= (enum reg_class
) j
;
400 /* Add I to the table of superclasses of J. */
401 p
= ®_class_subclasses
[j
][0];
402 while (*p
!= LIM_REG_CLASSES
) p
++;
403 *p
= (enum reg_class
) i
;
407 /* Initialize "constant" tables. */
409 CLEAR_HARD_REG_SET (fixed_reg_set
);
410 CLEAR_HARD_REG_SET (call_used_reg_set
);
411 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
412 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
414 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
416 n_non_fixed_regs
= 0;
418 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
421 SET_HARD_REG_BIT (fixed_reg_set
, i
);
425 if (call_used_regs
[i
])
426 SET_HARD_REG_BIT (call_used_reg_set
, i
);
427 if (call_fixed_regs
[i
])
428 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
429 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
430 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
432 /* There are a couple of fixed registers that we know are safe to
433 exclude from being clobbered by calls:
435 The frame pointer is always preserved across calls. The arg pointer
436 is if it is fixed. The stack pointer usually is, unless
437 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
438 If we are generating PIC code, the PIC offset table register is
439 preserved across calls, though the target can override that. */
441 if (i
== STACK_POINTER_REGNUM
)
443 else if (global_regs
[i
])
444 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
445 else if (i
== FRAME_POINTER_REGNUM
)
447 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
448 else if (i
== HARD_FRAME_POINTER_REGNUM
)
451 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
452 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
455 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
456 else if (i
== (unsigned) PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
459 else if (CALL_REALLY_USED_REGNO_P (i
))
460 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
463 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
464 memset (allocatable_regs_of_mode
, 0, sizeof (allocatable_regs_of_mode
));
465 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
466 for (i
= 0; i
< N_REG_CLASSES
; i
++)
467 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
468 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
469 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
470 && HARD_REGNO_MODE_OK (j
, m
))
472 contains_reg_of_mode
[i
][m
] = 1;
473 allocatable_regs_of_mode
[m
] = 1;
477 /* Initialize the move cost table. Find every subset of each class
478 and take the maximum cost of moving any subset to any other. */
480 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
481 if (allocatable_regs_of_mode
[m
])
483 for (i
= 0; i
< N_REG_CLASSES
; i
++)
484 if (contains_reg_of_mode
[i
][m
])
485 for (j
= 0; j
< N_REG_CLASSES
; j
++)
488 enum reg_class
*p1
, *p2
;
490 if (!contains_reg_of_mode
[j
][m
])
492 move_cost
[m
][i
][j
] = 65536;
493 may_move_in_cost
[m
][i
][j
] = 65536;
494 may_move_out_cost
[m
][i
][j
] = 65536;
498 cost
= REGISTER_MOVE_COST (m
, i
, j
);
500 for (p2
= ®_class_subclasses
[j
][0];
501 *p2
!= LIM_REG_CLASSES
;
503 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
504 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
506 for (p1
= ®_class_subclasses
[i
][0];
507 *p1
!= LIM_REG_CLASSES
;
509 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
510 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
512 move_cost
[m
][i
][j
] = cost
;
514 if (reg_class_subset_p (i
, j
))
515 may_move_in_cost
[m
][i
][j
] = 0;
517 may_move_in_cost
[m
][i
][j
] = cost
;
519 if (reg_class_subset_p (j
, i
))
520 may_move_out_cost
[m
][i
][j
] = 0;
522 may_move_out_cost
[m
][i
][j
] = cost
;
526 for (j
= 0; j
< N_REG_CLASSES
; j
++)
528 move_cost
[m
][i
][j
] = 65536;
529 may_move_in_cost
[m
][i
][j
] = 65536;
530 may_move_out_cost
[m
][i
][j
] = 65536;
535 /* Compute the table of register modes.
536 These values are used to record death information for individual registers
537 (as opposed to a multi-register mode). */
540 init_reg_modes_once (void)
544 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
546 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1, false);
548 /* If we couldn't find a valid mode, just use the previous mode.
549 ??? One situation in which we need to do this is on the mips where
550 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
551 to use DF mode for the even registers and VOIDmode for the odd
552 (for the cpu models where the odd ones are inaccessible). */
553 if (reg_raw_mode
[i
] == VOIDmode
)
554 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
558 /* Finish initializing the register sets and
559 initialize the register modes. */
564 /* This finishes what was started by init_reg_sets, but couldn't be done
565 until after register usage was specified. */
571 /* Initialize some fake stack-frame MEM references for use in
572 memory_move_secondary_cost. */
575 init_fake_stack_mems (void)
577 #ifdef HAVE_SECONDARY_RELOADS
581 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
582 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
587 #ifdef HAVE_SECONDARY_RELOADS
589 /* Compute extra cost of moving registers to/from memory due to reloads.
590 Only needed if secondary reloads are required for memory moves. */
593 memory_move_secondary_cost (enum machine_mode mode
, enum reg_class
class, int in
)
595 enum reg_class altclass
;
596 int partial_cost
= 0;
597 /* We need a memory reference to feed to SECONDARY... macros. */
598 /* mem may be unused even if the SECONDARY_ macros are defined. */
599 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
604 #ifdef SECONDARY_INPUT_RELOAD_CLASS
605 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
612 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
613 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
619 if (altclass
== NO_REGS
)
623 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
625 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
627 if (class == altclass
)
628 /* This isn't simply a copy-to-temporary situation. Can't guess
629 what it is, so MEMORY_MOVE_COST really ought not to be calling
632 I'm tempted to put in an abort here, but returning this will
633 probably only give poor estimates, which is what we would've
634 had before this code anyways. */
637 /* Check if the secondary reload register will also need a
639 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
643 /* Return a machine mode that is legitimate for hard reg REGNO and large
644 enough to save nregs. If we can't find one, return VOIDmode.
645 If CALL_SAVED is true, only consider modes that are call saved. */
648 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED
,
649 unsigned int nregs
, bool call_saved
)
651 unsigned int /* enum machine_mode */ m
;
652 enum machine_mode found_mode
= VOIDmode
, mode
;
654 /* We first look for the largest integer mode that can be validly
655 held in REGNO. If none, we look for the largest floating-point mode.
656 If we still didn't find a valid mode, try CCmode. */
658 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
660 mode
= GET_MODE_WIDER_MODE (mode
))
661 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
662 && HARD_REGNO_MODE_OK (regno
, mode
)
663 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
666 if (found_mode
!= VOIDmode
)
669 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
671 mode
= GET_MODE_WIDER_MODE (mode
))
672 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
673 && HARD_REGNO_MODE_OK (regno
, mode
)
674 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
677 if (found_mode
!= VOIDmode
)
680 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
682 mode
= GET_MODE_WIDER_MODE (mode
))
683 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
684 && HARD_REGNO_MODE_OK (regno
, mode
)
685 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
688 if (found_mode
!= VOIDmode
)
691 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
693 mode
= GET_MODE_WIDER_MODE (mode
))
694 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
695 && HARD_REGNO_MODE_OK (regno
, mode
)
696 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
699 if (found_mode
!= VOIDmode
)
702 /* Iterate over all of the CCmodes. */
703 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
705 mode
= (enum machine_mode
) m
;
706 if ((unsigned) HARD_REGNO_NREGS (regno
, mode
) == nregs
707 && HARD_REGNO_MODE_OK (regno
, mode
)
708 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
712 /* We can't find a mode valid for this register. */
716 /* Specify the usage characteristics of the register named NAME.
717 It should be a fixed register if FIXED and a
718 call-used register if CALL_USED. */
721 fix_register (const char *name
, int fixed
, int call_used
)
725 /* Decode the name and update the primary form of
726 the register info. */
728 if ((i
= decode_reg_name (name
)) >= 0)
730 if ((i
== STACK_POINTER_REGNUM
731 #ifdef HARD_FRAME_POINTER_REGNUM
732 || i
== HARD_FRAME_POINTER_REGNUM
734 || i
== FRAME_POINTER_REGNUM
737 && (fixed
== 0 || call_used
== 0))
739 static const char * const what_option
[2][2] = {
740 { "call-saved", "call-used" },
741 { "no-such-option", "fixed" }};
743 error ("can't use '%s' as a %s register", name
,
744 what_option
[fixed
][call_used
]);
748 fixed_regs
[i
] = fixed
;
749 call_used_regs
[i
] = call_used
;
750 #ifdef CALL_REALLY_USED_REGISTERS
752 call_really_used_regs
[i
] = call_used
;
758 warning ("unknown register name: %s", name
);
762 /* Mark register number I as global. */
765 globalize_reg (int i
)
767 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
768 error ("global register variable follows a function definition");
772 warning ("register used for two global register variables");
776 if (call_used_regs
[i
] && ! fixed_regs
[i
])
777 warning ("call-clobbered register used for global register variable");
781 /* If we're globalizing the frame pointer, we need to set the
782 appropriate regs_invalidated_by_call bit, even if it's already
783 set in fixed_regs. */
784 if (i
!= STACK_POINTER_REGNUM
)
785 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
787 /* If already fixed, nothing else to do. */
791 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
794 SET_HARD_REG_BIT (fixed_reg_set
, i
);
795 SET_HARD_REG_BIT (call_used_reg_set
, i
);
796 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
799 /* Now the data and code for the `regclass' pass, which happens
800 just before local-alloc. */
802 /* The `costs' struct records the cost of using a hard register of each class
803 and of using memory for each pseudo. We use this data to set up
804 register class preferences. */
808 int cost
[N_REG_CLASSES
];
812 /* Structure used to record preferences of given pseudo. */
815 /* (enum reg_class) prefclass is the preferred class. */
818 /* altclass is a register class that we should use for allocating
819 pseudo if no register in the preferred class is available.
820 If no register in this class is available, memory is preferred.
822 It might appear to be more general to have a bitmask of classes here,
823 but since it is recommended that there be a class corresponding to the
824 union of most major pair of classes, that generality is not required. */
828 /* Record the cost of each class for each pseudo. */
830 static struct costs
*costs
;
832 /* Initialized once, and used to initialize cost values for each insn. */
834 static struct costs init_cost
;
836 /* Record preferences of each pseudo.
837 This is available after `regclass' is run. */
839 static struct reg_pref
*reg_pref
;
841 /* Allocated buffers for reg_pref. */
843 static struct reg_pref
*reg_pref_buffer
;
845 /* Frequency of executions of current insn. */
847 static int frequency
;
849 static rtx
scan_one_insn (rtx
, int);
850 static void record_operand_costs (rtx
, struct costs
*, struct reg_pref
*);
851 static void dump_regclass (FILE *);
852 static void record_reg_classes (int, int, rtx
*, enum machine_mode
*,
853 const char **, rtx
, struct costs
*,
855 static int copy_cost (rtx
, enum machine_mode
, enum reg_class
, int);
856 static void record_address_regs (rtx
, enum reg_class
, int);
857 #ifdef FORBIDDEN_INC_DEC_CLASSES
858 static int auto_inc_dec_reg_p (rtx
, enum machine_mode
);
860 static void reg_scan_mark_refs (rtx
, rtx
, int, unsigned int);
862 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
863 This function is sometimes called before the info has been computed.
864 When that happens, just return GENERAL_REGS, which is innocuous. */
867 reg_preferred_class (int regno
)
871 return (enum reg_class
) reg_pref
[regno
].prefclass
;
875 reg_alternate_class (int regno
)
880 return (enum reg_class
) reg_pref
[regno
].altclass
;
883 /* Initialize some global data for this pass. */
890 init_cost
.mem_cost
= 10000;
891 for (i
= 0; i
< N_REG_CLASSES
; i
++)
892 init_cost
.cost
[i
] = 10000;
894 /* This prevents dump_flow_info from losing if called
895 before regclass is run. */
898 /* No more global register variables may be declared. */
899 no_global_reg_vars
= 1;
902 /* Dump register costs. */
904 dump_regclass (FILE *dump
)
906 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
908 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
910 int /* enum reg_class */ class;
913 fprintf (dump
, " Register %i costs:", i
);
914 for (class = 0; class < (int) N_REG_CLASSES
; class++)
915 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
916 #ifdef FORBIDDEN_INC_DEC_CLASSES
918 || !forbidden_inc_dec_class
[(enum reg_class
) class])
920 #ifdef CANNOT_CHANGE_MODE_CLASS
921 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
922 PSEUDO_REGNO_MODE (i
))
925 fprintf (dump
, " %s:%i", reg_class_names
[class],
926 costs
[i
].cost
[(enum reg_class
) class]);
927 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
933 /* Calculate the costs of insn operands. */
936 record_operand_costs (rtx insn
, struct costs
*op_costs
,
937 struct reg_pref
*reg_pref
)
939 const char *constraints
[MAX_RECOG_OPERANDS
];
940 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
943 for (i
= 0; i
< recog_data
.n_operands
; i
++)
945 constraints
[i
] = recog_data
.constraints
[i
];
946 modes
[i
] = recog_data
.operand_mode
[i
];
949 /* If we get here, we are set up to record the costs of all the
950 operands for this insn. Start by initializing the costs.
951 Then handle any address registers. Finally record the desired
952 classes for any pseudos, doing it twice if some pair of
953 operands are commutative. */
955 for (i
= 0; i
< recog_data
.n_operands
; i
++)
957 op_costs
[i
] = init_cost
;
959 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
960 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
962 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
963 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
964 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
965 else if (constraints
[i
][0] == 'p'
966 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0], constraints
[i
]))
967 record_address_regs (recog_data
.operand
[i
],
968 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
971 /* Check for commutative in a separate loop so everything will
972 have been initialized. We must do this even if one operand
973 is a constant--see addsi3 in m68k.md. */
975 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
976 if (constraints
[i
][0] == '%')
978 const char *xconstraints
[MAX_RECOG_OPERANDS
];
981 /* Handle commutative operands by swapping the constraints.
982 We assume the modes are the same. */
984 for (j
= 0; j
< recog_data
.n_operands
; j
++)
985 xconstraints
[j
] = constraints
[j
];
987 xconstraints
[i
] = constraints
[i
+1];
988 xconstraints
[i
+1] = constraints
[i
];
989 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
990 recog_data
.operand
, modes
,
991 xconstraints
, insn
, op_costs
, reg_pref
);
994 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
995 recog_data
.operand
, modes
,
996 constraints
, insn
, op_costs
, reg_pref
);
999 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1000 time it would save code to put a certain register in a certain class.
1001 PASS, when nonzero, inhibits some optimizations which need only be done
1003 Return the last insn processed, so that the scan can be continued from
1007 scan_one_insn (rtx insn
, int pass
)
1009 enum rtx_code code
= GET_CODE (insn
);
1010 enum rtx_code pat_code
;
1013 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1015 if (GET_RTX_CLASS (code
) != 'i')
1018 pat_code
= GET_CODE (PATTERN (insn
));
1020 || pat_code
== CLOBBER
1021 || pat_code
== ASM_INPUT
1022 || pat_code
== ADDR_VEC
1023 || pat_code
== ADDR_DIFF_VEC
)
1026 set
= single_set (insn
);
1027 extract_insn (insn
);
1029 /* If this insn loads a parameter from its stack slot, then
1030 it represents a savings, rather than a cost, if the
1031 parameter is stored in memory. Record this fact. */
1033 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
1034 && GET_CODE (SET_SRC (set
)) == MEM
1035 && (note
= find_reg_note (insn
, REG_EQUIV
,
1037 && GET_CODE (XEXP (note
, 0)) == MEM
)
1039 costs
[REGNO (SET_DEST (set
))].mem_cost
1040 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1043 record_address_regs (XEXP (SET_SRC (set
), 0),
1044 MODE_BASE_REG_CLASS (VOIDmode
), frequency
* 2);
1048 /* Improve handling of two-address insns such as
1049 (set X (ashift CONST Y)) where CONST must be made to
1050 match X. Change it into two insns: (set X CONST)
1051 (set X (ashift X Y)). If we left this for reloading, it
1052 would probably get three insns because X and Y might go
1053 in the same place. This prevents X and Y from receiving
1056 We can only do this if the modes of operands 0 and 1
1057 (which might not be the same) are tieable and we only need
1058 do this during our first pass. */
1060 if (pass
== 0 && optimize
1061 && recog_data
.n_operands
>= 3
1062 && recog_data
.constraints
[1][0] == '0'
1063 && recog_data
.constraints
[1][1] == 0
1064 && CONSTANT_P (recog_data
.operand
[1])
1065 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1066 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1067 && GET_CODE (recog_data
.operand
[0]) == REG
1068 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1069 recog_data
.operand_mode
[1]))
1071 rtx previnsn
= prev_real_insn (insn
);
1073 = gen_lowpart (recog_data
.operand_mode
[1],
1074 recog_data
.operand
[0]);
1076 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1078 /* If this insn was the start of a basic block,
1079 include the new insn in that block.
1080 We need not check for code_label here;
1081 while a basic block can start with a code_label,
1082 INSN could not be at the beginning of that block. */
1083 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
1087 if (insn
== BB_HEAD (b
))
1088 BB_HEAD (b
) = newinsn
;
1091 /* This makes one more setting of new insns's dest. */
1092 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1093 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1094 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1096 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1097 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1098 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1099 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1100 if (recog_data
.dup_num
[i
] == 1)
1102 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1103 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1104 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1107 return PREV_INSN (newinsn
);
1110 record_operand_costs (insn
, op_costs
, reg_pref
);
1112 /* Now add the cost for each operand to the total costs for
1115 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1116 if (GET_CODE (recog_data
.operand
[i
]) == REG
1117 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1119 int regno
= REGNO (recog_data
.operand
[i
]);
1120 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1122 p
->mem_cost
+= q
->mem_cost
* frequency
;
1123 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1124 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1130 /* Initialize information about which register classes can be used for
1131 pseudos that are auto-incremented or auto-decremented. */
1134 init_reg_autoinc (void)
1136 #ifdef FORBIDDEN_INC_DEC_CLASSES
1139 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1141 rtx r
= gen_rtx_raw_REG (VOIDmode
, 0);
1142 enum machine_mode m
;
1145 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1146 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1150 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1151 m
= (enum machine_mode
) ((int) m
+ 1))
1152 if (HARD_REGNO_MODE_OK (j
, m
))
1156 /* If a register is not directly suitable for an
1157 auto-increment or decrement addressing mode and
1158 requires secondary reloads, disallow its class from
1159 being used in such addresses. */
1162 #ifdef SECONDARY_RELOAD_CLASS
1163 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1166 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1167 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1170 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1171 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1176 && ! auto_inc_dec_reg_p (r
, m
))
1177 forbidden_inc_dec_class
[i
] = 1;
1181 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1184 /* This is a pass of the compiler that scans all instructions
1185 and calculates the preferred class for each pseudo-register.
1186 This information can be accessed later by calling `reg_preferred_class'.
1187 This pass comes just before local register allocation. */
1190 regclass (rtx f
, int nregs
, FILE *dump
)
1198 costs
= xmalloc (nregs
* sizeof (struct costs
));
1200 #ifdef FORBIDDEN_INC_DEC_CLASSES
1202 in_inc_dec
= xmalloc (nregs
);
1204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1206 /* Normally we scan the insns once and determine the best class to use for
1207 each register. However, if -fexpensive_optimizations are on, we do so
1208 twice, the second time using the tentative best classes to guide the
1211 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1216 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1217 /* Zero out our accumulation of the cost of each class for each reg. */
1219 memset (costs
, 0, nregs
* sizeof (struct costs
));
1221 #ifdef FORBIDDEN_INC_DEC_CLASSES
1222 memset (in_inc_dec
, 0, nregs
);
1225 /* Scan the instructions and record each time it would
1226 save code to put a certain register in a certain class. */
1230 frequency
= REG_FREQ_MAX
;
1231 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1232 insn
= scan_one_insn (insn
, pass
);
1237 /* Show that an insn inside a loop is likely to be executed three
1238 times more than insns outside a loop. This is much more
1239 aggressive than the assumptions made elsewhere and is being
1240 tried as an experiment. */
1241 frequency
= REG_FREQ_FROM_BB (bb
);
1242 for (insn
= BB_HEAD (bb
); ; insn
= NEXT_INSN (insn
))
1244 insn
= scan_one_insn (insn
, pass
);
1245 if (insn
== BB_END (bb
))
1250 /* Now for each register look at how desirable each class is
1251 and find which class is preferred. Store that in
1252 `prefclass'. Record in `altclass' the largest register
1253 class any of whose registers is better than memory. */
1256 reg_pref
= reg_pref_buffer
;
1260 dump_regclass (dump
);
1261 fprintf (dump
,"\n");
1263 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1265 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1266 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1267 /* This is an enum reg_class, but we call it an int
1268 to save lots of casts. */
1270 struct costs
*p
= &costs
[i
];
1272 /* In non-optimizing compilation REG_N_REFS is not initialized
1274 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1277 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1279 /* Ignore classes that are too small for this operand or
1280 invalid for an operand that was auto-incremented. */
1281 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1282 #ifdef FORBIDDEN_INC_DEC_CLASSES
1283 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1285 #ifdef CANNOT_CHANGE_MODE_CLASS
1286 || invalid_mode_change_p (i
, (enum reg_class
) class,
1287 PSEUDO_REGNO_MODE (i
))
1291 else if (p
->cost
[class] < best_cost
)
1293 best_cost
= p
->cost
[class];
1294 best
= (enum reg_class
) class;
1296 else if (p
->cost
[class] == best_cost
)
1297 best
= reg_class_subunion
[(int) best
][class];
1300 /* Record the alternate register class; i.e., a class for which
1301 every register in it is better than using memory. If adding a
1302 class would make a smaller class (i.e., no union of just those
1303 classes exists), skip that class. The major unions of classes
1304 should be provided as a register class. Don't do this if we
1305 will be doing it again later. */
1307 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1308 for (class = 0; class < N_REG_CLASSES
; class++)
1309 if (p
->cost
[class] < p
->mem_cost
1310 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1311 > reg_class_size
[(int) alt
])
1312 #ifdef FORBIDDEN_INC_DEC_CLASSES
1313 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1315 #ifdef CANNOT_CHANGE_MODE_CLASS
1316 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1317 PSEUDO_REGNO_MODE (i
))
1320 alt
= reg_class_subunion
[(int) alt
][class];
1322 /* If we don't add any classes, nothing to try. */
1327 && (reg_pref
[i
].prefclass
!= (int) best
1328 || reg_pref
[i
].altclass
!= (int) alt
))
1330 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1331 fprintf (dump
, " Register %i", i
);
1332 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1333 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1334 else if (alt
== NO_REGS
)
1335 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1337 fprintf (dump
, " pref %s, else %s\n",
1338 reg_class_names
[(int) best
],
1339 reg_class_names
[(int) alt
]);
1342 /* We cast to (int) because (char) hits bugs in some compilers. */
1343 reg_pref
[i
].prefclass
= (int) best
;
1344 reg_pref
[i
].altclass
= (int) alt
;
1348 #ifdef FORBIDDEN_INC_DEC_CLASSES
1354 /* Record the cost of using memory or registers of various classes for
1355 the operands in INSN.
1357 N_ALTS is the number of alternatives.
1359 N_OPS is the number of operands.
1361 OPS is an array of the operands.
1363 MODES are the modes of the operands, in case any are VOIDmode.
1365 CONSTRAINTS are the constraints to use for the operands. This array
1366 is modified by this procedure.
1368 This procedure works alternative by alternative. For each alternative
1369 we assume that we will be able to allocate all pseudos to their ideal
1370 register class and calculate the cost of using that alternative. Then
1371 we compute for each operand that is a pseudo-register, the cost of
1372 having the pseudo allocated to each register class and using it in that
1373 alternative. To this cost is added the cost of the alternative.
1375 The cost of each class for this insn is its lowest cost among all the
1379 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
1380 enum machine_mode
*modes
, const char **constraints
,
1381 rtx insn
, struct costs
*op_costs
,
1382 struct reg_pref
*reg_pref
)
1388 /* Process each alternative, each time minimizing an operand's cost with
1389 the cost for each operand in that alternative. */
1391 for (alt
= 0; alt
< n_alts
; alt
++)
1393 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1396 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1397 int allows_mem
[MAX_RECOG_OPERANDS
];
1400 for (i
= 0; i
< n_ops
; i
++)
1402 const char *p
= constraints
[i
];
1404 enum machine_mode mode
= modes
[i
];
1405 int allows_addr
= 0;
1409 /* Initially show we know nothing about the register class. */
1410 classes
[i
] = NO_REGS
;
1413 /* If this operand has no constraints at all, we can conclude
1414 nothing about it since anything is valid. */
1418 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1419 memset (&this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1424 /* If this alternative is only relevant when this operand
1425 matches a previous operand, we do different things depending
1426 on whether this operand is a pseudo-reg or not. We must process
1427 any modifiers for the operand before we can make this test. */
1429 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1432 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1434 /* Copy class and whether memory is allowed from the matching
1435 alternative. Then perform any needed cost computations
1436 and/or adjustments. */
1438 classes
[i
] = classes
[j
];
1439 allows_mem
[i
] = allows_mem
[j
];
1441 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1443 /* If this matches the other operand, we have no added
1445 if (rtx_equal_p (ops
[j
], op
))
1448 /* If we can put the other operand into a register, add to
1449 the cost of this alternative the cost to copy this
1450 operand to the register used for the other operand. */
1452 else if (classes
[j
] != NO_REGS
)
1453 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1455 else if (GET_CODE (ops
[j
]) != REG
1456 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1458 /* This op is a pseudo but the one it matches is not. */
1460 /* If we can't put the other operand into a register, this
1461 alternative can't be used. */
1463 if (classes
[j
] == NO_REGS
)
1466 /* Otherwise, add to the cost of this alternative the cost
1467 to copy the other operand to the register used for this
1471 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1475 /* The costs of this operand are not the same as the other
1476 operand since move costs are not symmetric. Moreover,
1477 if we cannot tie them, this alternative needs to do a
1478 copy, which is one instruction. */
1480 struct costs
*pp
= &this_op_costs
[i
];
1482 for (class = 0; class < N_REG_CLASSES
; class++)
1484 = ((recog_data
.operand_type
[i
] != OP_OUT
1485 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1487 + (recog_data
.operand_type
[i
] != OP_IN
1488 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1491 /* If the alternative actually allows memory, make things
1492 a bit cheaper since we won't need an extra insn to
1496 = ((recog_data
.operand_type
[i
] != OP_IN
1497 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1499 + (recog_data
.operand_type
[i
] != OP_OUT
1500 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1501 : 0) - allows_mem
[i
]);
1503 /* If we have assigned a class to this register in our
1504 first pass, add a cost to this alternative corresponding
1505 to what we would add if this register were not in the
1506 appropriate class. */
1510 += (may_move_in_cost
[mode
]
1511 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1512 [(int) classes
[i
]]);
1514 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1515 && ! find_reg_note (insn
, REG_DEAD
, op
))
1518 /* This is in place of ordinary cost computation
1519 for this operand, so skip to the end of the
1520 alternative (should be just one character). */
1521 while (*p
&& *p
++ != ',')
1529 /* Scan all the constraint letters. See if the operand matches
1530 any of the constraints. Collect the valid register classes
1531 and see if this operand accepts memory. */
1540 /* Ignore the next letter for this pass. */
1546 case '!': case '#': case '&':
1547 case '0': case '1': case '2': case '3': case '4':
1548 case '5': case '6': case '7': case '8': case '9':
1553 win
= address_operand (op
, GET_MODE (op
));
1554 /* We know this operand is an address, so we want it to be
1555 allocated to a register that can be the base of an
1556 address, ie BASE_REG_CLASS. */
1558 = reg_class_subunion
[(int) classes
[i
]]
1559 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1562 case 'm': case 'o': case 'V':
1563 /* It doesn't seem worth distinguishing between offsettable
1564 and non-offsettable addresses here. */
1566 if (GET_CODE (op
) == MEM
)
1571 if (GET_CODE (op
) == MEM
1572 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1573 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1578 if (GET_CODE (op
) == MEM
1579 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1580 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1586 if (GET_CODE (op
) == CONST_DOUBLE
1587 || (GET_CODE (op
) == CONST_VECTOR
1588 && (GET_MODE_CLASS (GET_MODE (op
))
1589 == MODE_VECTOR_FLOAT
)))
1595 if (GET_CODE (op
) == CONST_DOUBLE
1596 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1601 if (GET_CODE (op
) == CONST_INT
1602 || (GET_CODE (op
) == CONST_DOUBLE
1603 && GET_MODE (op
) == VOIDmode
))
1607 #ifdef LEGITIMATE_PIC_OPERAND_P
1608 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1615 if (GET_CODE (op
) == CONST_INT
1616 || (GET_CODE (op
) == CONST_DOUBLE
1617 && GET_MODE (op
) == VOIDmode
))
1629 if (GET_CODE (op
) == CONST_INT
1630 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1639 if (GET_CODE (op
) == MEM
1641 #ifdef LEGITIMATE_PIC_OPERAND_P
1642 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1649 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1653 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
1655 = reg_class_subunion
[(int) classes
[i
]]
1656 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1657 #ifdef EXTRA_CONSTRAINT_STR
1658 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1661 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1663 /* Every MEM can be reloaded to fit. */
1665 if (GET_CODE (op
) == MEM
)
1668 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1670 /* Every address can be reloaded to fit. */
1672 if (address_operand (op
, GET_MODE (op
)))
1674 /* We know this operand is an address, so we want it to
1675 be allocated to a register that can be the base of an
1676 address, ie BASE_REG_CLASS. */
1678 = reg_class_subunion
[(int) classes
[i
]]
1679 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1684 p
+= CONSTRAINT_LEN (c
, p
);
1691 /* How we account for this operand now depends on whether it is a
1692 pseudo register or not. If it is, we first check if any
1693 register classes are valid. If not, we ignore this alternative,
1694 since we want to assume that all pseudos get allocated for
1695 register preferencing. If some register class is valid, compute
1696 the costs of moving the pseudo into that class. */
1698 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1700 if (classes
[i
] == NO_REGS
)
1702 /* We must always fail if the operand is a REG, but
1703 we did not find a suitable class.
1705 Otherwise we may perform an uninitialized read
1706 from this_op_costs after the `continue' statement
1712 struct costs
*pp
= &this_op_costs
[i
];
1714 for (class = 0; class < N_REG_CLASSES
; class++)
1716 = ((recog_data
.operand_type
[i
] != OP_OUT
1717 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1719 + (recog_data
.operand_type
[i
] != OP_IN
1720 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1723 /* If the alternative actually allows memory, make things
1724 a bit cheaper since we won't need an extra insn to
1728 = ((recog_data
.operand_type
[i
] != OP_IN
1729 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1731 + (recog_data
.operand_type
[i
] != OP_OUT
1732 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1733 : 0) - allows_mem
[i
]);
1735 /* If we have assigned a class to this register in our
1736 first pass, add a cost to this alternative corresponding
1737 to what we would add if this register were not in the
1738 appropriate class. */
1742 += (may_move_in_cost
[mode
]
1743 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1744 [(int) classes
[i
]]);
1748 /* Otherwise, if this alternative wins, either because we
1749 have already determined that or if we have a hard register of
1750 the proper class, there is no cost for this alternative. */
1753 || (GET_CODE (op
) == REG
1754 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1757 /* If registers are valid, the cost of this alternative includes
1758 copying the object to and/or from a register. */
1760 else if (classes
[i
] != NO_REGS
)
1762 if (recog_data
.operand_type
[i
] != OP_OUT
)
1763 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1765 if (recog_data
.operand_type
[i
] != OP_IN
)
1766 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1769 /* The only other way this alternative can be used is if this is a
1770 constant that could be placed into memory. */
1772 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1773 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1781 /* Finally, update the costs with the information we've calculated
1782 about this alternative. */
1784 for (i
= 0; i
< n_ops
; i
++)
1785 if (GET_CODE (ops
[i
]) == REG
1786 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1788 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1789 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1791 pp
->mem_cost
= MIN (pp
->mem_cost
,
1792 (qq
->mem_cost
+ alt_cost
) * scale
);
1794 for (class = 0; class < N_REG_CLASSES
; class++)
1795 pp
->cost
[class] = MIN (pp
->cost
[class],
1796 (qq
->cost
[class] + alt_cost
) * scale
);
1800 /* If this insn is a single set copying operand 1 to operand 0
1801 and one operand is a pseudo with the other a hard reg or a pseudo
1802 that prefers a register that is in its own register class then
1803 we may want to adjust the cost of that register class to -1.
1805 Avoid the adjustment if the source does not die to avoid stressing of
1806 register allocator by preferrencing two colliding registers into single
1809 Also avoid the adjustment if a copy between registers of the class
1810 is expensive (ten times the cost of a default copy is considered
1811 arbitrarily expensive). This avoids losing when the preferred class
1812 is very expensive as the source of a copy instruction. */
1814 if ((set
= single_set (insn
)) != 0
1815 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1816 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1817 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1818 for (i
= 0; i
<= 1; i
++)
1819 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1821 unsigned int regno
= REGNO (ops
[!i
]);
1822 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1826 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1828 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1830 if ((reg_class_size
[(unsigned char) pref
]
1831 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1832 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1833 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1835 else if (regno
< FIRST_PSEUDO_REGISTER
)
1836 for (class = 0; class < N_REG_CLASSES
; class++)
1837 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1838 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1840 if (reg_class_size
[class] == 1)
1841 op_costs
[i
].cost
[class] = -1;
1844 for (nr
= 0; nr
< (unsigned) HARD_REGNO_NREGS (regno
, mode
); nr
++)
1846 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1851 if (nr
== (unsigned) HARD_REGNO_NREGS (regno
,mode
))
1852 op_costs
[i
].cost
[class] = -1;
1858 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1859 TO_P is zero) a register of class CLASS in mode MODE.
1861 X must not be a pseudo. */
1864 copy_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1865 enum reg_class
class, int to_p ATTRIBUTE_UNUSED
)
1867 #ifdef HAVE_SECONDARY_RELOADS
1868 enum reg_class secondary_class
= NO_REGS
;
1871 /* If X is a SCRATCH, there is actually nothing to move since we are
1872 assuming optimal allocation. */
1874 if (GET_CODE (x
) == SCRATCH
)
1877 /* Get the class we will actually use for a reload. */
1878 class = PREFERRED_RELOAD_CLASS (x
, class);
1880 #ifdef HAVE_SECONDARY_RELOADS
1881 /* If we need a secondary reload (we assume here that we are using
1882 the secondary reload as an intermediate, not a scratch register), the
1883 cost is that to load the input into the intermediate register, then
1884 to copy them. We use a special value of TO_P to avoid recursion. */
1886 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1888 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1891 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1893 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1896 if (secondary_class
!= NO_REGS
)
1897 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1898 + copy_cost (x
, mode
, secondary_class
, 2));
1899 #endif /* HAVE_SECONDARY_RELOADS */
1901 /* For memory, use the memory move cost, for (hard) registers, use the
1902 cost to move between the register classes, and use 2 for everything
1903 else (constants). */
1905 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1906 return MEMORY_MOVE_COST (mode
, class, to_p
);
1908 else if (GET_CODE (x
) == REG
)
1909 return move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1912 /* If this is a constant, we may eventually want to call rtx_cost here. */
1913 return COSTS_N_INSNS (1);
1916 /* Record the pseudo registers we must reload into hard registers
1917 in a subexpression of a memory address, X.
1919 CLASS is the class that the register needs to be in and is either
1920 BASE_REG_CLASS or INDEX_REG_CLASS.
1922 SCALE is twice the amount to multiply the cost by (it is twice so we
1923 can represent half-cost adjustments). */
1926 record_address_regs (rtx x
, enum reg_class
class, int scale
)
1928 enum rtx_code code
= GET_CODE (x
);
1941 /* When we have an address that is a sum,
1942 we must determine whether registers are "base" or "index" regs.
1943 If there is a sum of two registers, we must choose one to be
1944 the "base". Luckily, we can use the REG_POINTER to make a good
1945 choice most of the time. We only need to do this on machines
1946 that can have two registers in an address and where the base
1947 and index register classes are different.
1949 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1950 that seems bogus since it should only be set when we are sure
1951 the register is being used as a pointer. */
1954 rtx arg0
= XEXP (x
, 0);
1955 rtx arg1
= XEXP (x
, 1);
1956 enum rtx_code code0
= GET_CODE (arg0
);
1957 enum rtx_code code1
= GET_CODE (arg1
);
1959 /* Look inside subregs. */
1960 if (code0
== SUBREG
)
1961 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1962 if (code1
== SUBREG
)
1963 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1965 /* If this machine only allows one register per address, it must
1966 be in the first operand. */
1968 if (MAX_REGS_PER_ADDRESS
== 1)
1969 record_address_regs (arg0
, class, scale
);
1971 /* If index and base registers are the same on this machine, just
1972 record registers in any non-constant operands. We assume here,
1973 as well as in the tests below, that all addresses are in
1976 else if (INDEX_REG_CLASS
== MODE_BASE_REG_CLASS (VOIDmode
))
1978 record_address_regs (arg0
, class, scale
);
1979 if (! CONSTANT_P (arg1
))
1980 record_address_regs (arg1
, class, scale
);
1983 /* If the second operand is a constant integer, it doesn't change
1984 what class the first operand must be. */
1986 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1987 record_address_regs (arg0
, class, scale
);
1989 /* If the second operand is a symbolic constant, the first operand
1990 must be an index register. */
1992 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1993 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1995 /* If both operands are registers but one is already a hard register
1996 of index or base class, give the other the class that the hard
1999 #ifdef REG_OK_FOR_BASE_P
2000 else if (code0
== REG
&& code1
== REG
2001 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2002 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
2003 record_address_regs (arg1
,
2004 REG_OK_FOR_BASE_P (arg0
)
2005 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2007 else if (code0
== REG
&& code1
== REG
2008 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2009 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
2010 record_address_regs (arg0
,
2011 REG_OK_FOR_BASE_P (arg1
)
2012 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2016 /* If one operand is known to be a pointer, it must be the base
2017 with the other operand the index. Likewise if the other operand
2020 else if ((code0
== REG
&& REG_POINTER (arg0
))
2023 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2024 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
2026 else if ((code1
== REG
&& REG_POINTER (arg1
))
2029 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
2030 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2033 /* Otherwise, count equal chances that each might be a base
2034 or index register. This case should be rare. */
2038 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
),
2040 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
2041 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
),
2043 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
2048 /* Double the importance of a pseudo register that is incremented
2049 or decremented, since it would take two extra insns
2050 if it ends up in the wrong place. */
2053 record_address_regs (XEXP (x
, 0), MODE_BASE_REG_CLASS (VOIDmode
),
2055 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2056 record_address_regs (XEXP (XEXP (x
, 1), 1),
2057 INDEX_REG_CLASS
, 2 * scale
);
2064 /* Double the importance of a pseudo register that is incremented
2065 or decremented, since it would take two extra insns
2066 if it ends up in the wrong place. If the operand is a pseudo,
2067 show it is being used in an INC_DEC context. */
2069 #ifdef FORBIDDEN_INC_DEC_CLASSES
2070 if (GET_CODE (XEXP (x
, 0)) == REG
2071 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2072 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2075 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
2080 struct costs
*pp
= &costs
[REGNO (x
)];
2083 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2085 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2086 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2092 const char *fmt
= GET_RTX_FORMAT (code
);
2094 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2096 record_address_regs (XEXP (x
, i
), class, scale
);
2101 #ifdef FORBIDDEN_INC_DEC_CLASSES
2103 /* Return 1 if REG is valid as an auto-increment memory reference
2104 to an object of MODE. */
2107 auto_inc_dec_reg_p (rtx reg
, enum machine_mode mode
)
2109 if (HAVE_POST_INCREMENT
2110 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2113 if (HAVE_POST_DECREMENT
2114 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2117 if (HAVE_PRE_INCREMENT
2118 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2121 if (HAVE_PRE_DECREMENT
2122 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2129 static short *renumber
;
2130 static size_t regno_allocated
;
2131 static unsigned int reg_n_max
;
2133 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2134 reg_scan and flow_analysis that are indexed by the register number. If
2135 NEW_P is nonzero, initialize all of the registers, otherwise only
2136 initialize the new registers allocated. The same table is kept from
2137 function to function, only reallocating it when we need more room. If
2138 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2141 allocate_reg_info (size_t num_regs
, int new_p
, int renumber_p
)
2144 size_t size_renumber
;
2145 size_t min
= (new_p
) ? 0 : reg_n_max
;
2146 struct reg_info_data
*reg_data
;
2148 if (num_regs
> regno_allocated
)
2150 size_t old_allocated
= regno_allocated
;
2152 regno_allocated
= num_regs
+ (num_regs
/ 20); /* Add some slop space. */
2153 size_renumber
= regno_allocated
* sizeof (short);
2157 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2158 renumber
= xmalloc (size_renumber
);
2159 reg_pref_buffer
= xmalloc (regno_allocated
2160 * sizeof (struct reg_pref
));
2165 VARRAY_GROW (reg_n_info
, regno_allocated
);
2167 if (new_p
) /* If we're zapping everything, no need to realloc. */
2169 free ((char *) renumber
);
2170 free ((char *) reg_pref
);
2171 renumber
= xmalloc (size_renumber
);
2172 reg_pref_buffer
= xmalloc (regno_allocated
2173 * sizeof (struct reg_pref
));
2178 renumber
= xrealloc (renumber
, size_renumber
);
2179 reg_pref_buffer
= xrealloc (reg_pref_buffer
,
2181 * sizeof (struct reg_pref
));
2185 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2186 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2187 reg_data
= xcalloc (size_info
, 1);
2188 reg_data
->min_index
= old_allocated
;
2189 reg_data
->max_index
= regno_allocated
- 1;
2190 reg_data
->next
= reg_info_head
;
2191 reg_info_head
= reg_data
;
2194 reg_n_max
= num_regs
;
2197 /* Loop through each of the segments allocated for the actual
2198 reg_info pages, and set up the pointers, zero the pages, etc. */
2199 for (reg_data
= reg_info_head
;
2200 reg_data
&& reg_data
->max_index
>= min
;
2201 reg_data
= reg_data
->next
)
2203 size_t min_index
= reg_data
->min_index
;
2204 size_t max_index
= reg_data
->max_index
;
2205 size_t max
= MIN (max_index
, num_regs
);
2206 size_t local_min
= min
- min_index
;
2209 if (reg_data
->min_index
> num_regs
)
2212 if (min
< min_index
)
2214 if (!reg_data
->used_p
) /* page just allocated with calloc */
2215 reg_data
->used_p
= 1; /* no need to zero */
2217 memset (®_data
->data
[local_min
], 0,
2218 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2220 for (i
= min_index
+local_min
; i
<= max
; i
++)
2222 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2223 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2225 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2226 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2231 /* If {pref,alt}class have already been allocated, update the pointers to
2232 the newly realloced ones. */
2234 reg_pref
= reg_pref_buffer
;
2237 reg_renumber
= renumber
;
2239 /* Tell the regset code about the new number of registers. */
2240 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2243 /* Free up the space allocated by allocate_reg_info. */
2245 free_reg_info (void)
2249 struct reg_info_data
*reg_data
;
2250 struct reg_info_data
*reg_next
;
2252 VARRAY_FREE (reg_n_info
);
2253 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2255 reg_next
= reg_data
->next
;
2256 free ((char *) reg_data
);
2259 free (reg_pref_buffer
);
2260 reg_pref_buffer
= (struct reg_pref
*) 0;
2261 reg_info_head
= (struct reg_info_data
*) 0;
2262 renumber
= (short *) 0;
2264 regno_allocated
= 0;
2268 /* This is the `regscan' pass of the compiler, run just before cse
2269 and again just before loop.
2271 It finds the first and last use of each pseudo-register
2272 and records them in the vectors regno_first_uid, regno_last_uid
2273 and counts the number of sets in the vector reg_n_sets.
2275 REPEAT is nonzero the second time this is called. */
2277 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2278 Always at least 3, since the combiner could put that many together
2279 and we want this to remain correct for all the remaining passes.
2280 This corresponds to the maximum number of times note_stores will call
2281 a function for any insn. */
2285 /* Used as a temporary to record the largest number of registers in
2286 PARALLEL in a SET_DEST. This is added to max_parallel. */
2288 static int max_set_parallel
;
2291 reg_scan (rtx f
, unsigned int nregs
, int repeat ATTRIBUTE_UNUSED
)
2295 timevar_push (TV_REG_SCAN
);
2297 allocate_reg_info (nregs
, TRUE
, FALSE
);
2299 max_set_parallel
= 0;
2301 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2304 rtx pat
= PATTERN (insn
);
2305 if (GET_CODE (pat
) == PARALLEL
2306 && XVECLEN (pat
, 0) > max_parallel
)
2307 max_parallel
= XVECLEN (pat
, 0);
2308 reg_scan_mark_refs (pat
, insn
, 0, 0);
2310 if (REG_NOTES (insn
))
2311 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2314 max_parallel
+= max_set_parallel
;
2316 timevar_pop (TV_REG_SCAN
);
2319 /* Update 'regscan' information by looking at the insns
2320 from FIRST to LAST. Some new REGs have been created,
2321 and any REG with number greater than OLD_MAX_REGNO is
2322 such a REG. We only update information for those. */
2325 reg_scan_update (rtx first
, rtx last
, unsigned int old_max_regno
)
2329 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2331 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2334 rtx pat
= PATTERN (insn
);
2335 if (GET_CODE (pat
) == PARALLEL
2336 && XVECLEN (pat
, 0) > max_parallel
)
2337 max_parallel
= XVECLEN (pat
, 0);
2338 reg_scan_mark_refs (pat
, insn
, 0, old_max_regno
);
2340 if (REG_NOTES (insn
))
2341 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2345 /* X is the expression to scan. INSN is the insn it appears in.
2346 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2347 We should only record information for REGs with numbers
2348 greater than or equal to MIN_REGNO. */
2351 reg_scan_mark_refs (rtx x
, rtx insn
, int note_flag
, unsigned int min_regno
)
2359 code
= GET_CODE (x
);
2376 unsigned int regno
= REGNO (x
);
2378 if (regno
>= min_regno
)
2380 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2382 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2383 if (REGNO_FIRST_UID (regno
) == 0)
2384 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2385 /* If we are called by reg_scan_update() (indicated by min_regno
2386 being set), we also need to update the reference count. */
2388 REG_N_REFS (regno
)++;
2395 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2397 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2402 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2407 rtx reg
= XEXP (x
, 0);
2409 && REGNO (reg
) >= min_regno
)
2411 REG_N_SETS (REGNO (reg
))++;
2412 REG_N_REFS (REGNO (reg
))++;
2414 else if (GET_CODE (reg
) == MEM
)
2415 reg_scan_mark_refs (XEXP (reg
, 0), insn
, note_flag
, min_regno
);
2420 /* Count a set of the destination if it is a register. */
2421 for (dest
= SET_DEST (x
);
2422 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2423 || GET_CODE (dest
) == ZERO_EXTEND
;
2424 dest
= XEXP (dest
, 0))
2427 /* For a PARALLEL, record the number of things (less the usual one for a
2428 SET) that are set. */
2429 if (GET_CODE (dest
) == PARALLEL
)
2430 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2432 if (GET_CODE (dest
) == REG
2433 && REGNO (dest
) >= min_regno
)
2435 REG_N_SETS (REGNO (dest
))++;
2436 REG_N_REFS (REGNO (dest
))++;
2439 /* If this is setting a pseudo from another pseudo or the sum of a
2440 pseudo and a constant integer and the other pseudo is known to be
2441 a pointer, set the destination to be a pointer as well.
2443 Likewise if it is setting the destination from an address or from a
2444 value equivalent to an address or to the sum of an address and
2447 But don't do any of this if the pseudo corresponds to a user
2448 variable since it should have already been set as a pointer based
2451 if (GET_CODE (SET_DEST (x
)) == REG
2452 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2453 && REGNO (SET_DEST (x
)) >= min_regno
2454 /* If the destination pseudo is set more than once, then other
2455 sets might not be to a pointer value (consider access to a
2456 union in two threads of control in the presence of global
2457 optimizations). So only set REG_POINTER on the destination
2458 pseudo if this is the only set of that pseudo. */
2459 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2460 && ! REG_USERVAR_P (SET_DEST (x
))
2461 && ! REG_POINTER (SET_DEST (x
))
2462 && ((GET_CODE (SET_SRC (x
)) == REG
2463 && REG_POINTER (SET_SRC (x
)))
2464 || ((GET_CODE (SET_SRC (x
)) == PLUS
2465 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2466 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2467 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2468 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2469 || GET_CODE (SET_SRC (x
)) == CONST
2470 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2471 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2472 || (GET_CODE (SET_SRC (x
)) == HIGH
2473 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2474 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2475 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2476 || ((GET_CODE (SET_SRC (x
)) == PLUS
2477 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2478 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2479 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2480 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2481 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2482 && (GET_CODE (XEXP (note
, 0)) == CONST
2483 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2484 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2485 REG_POINTER (SET_DEST (x
)) = 1;
2487 /* If this is setting a register from a register or from a simple
2488 conversion of a register, propagate REG_EXPR. */
2489 if (GET_CODE (dest
) == REG
)
2491 rtx src
= SET_SRC (x
);
2493 while (GET_CODE (src
) == SIGN_EXTEND
2494 || GET_CODE (src
) == ZERO_EXTEND
2495 || GET_CODE (src
) == TRUNCATE
2496 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2497 src
= XEXP (src
, 0);
2499 if (!REG_ATTRS (dest
) && REG_P (src
))
2500 REG_ATTRS (dest
) = REG_ATTRS (src
);
2501 if (!REG_ATTRS (dest
) && GET_CODE (src
) == MEM
)
2502 set_reg_attrs_from_mem (dest
, src
);
2505 /* ... fall through ... */
2509 const char *fmt
= GET_RTX_FORMAT (code
);
2511 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2514 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2515 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2518 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2519 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2526 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2530 reg_class_subset_p (enum reg_class c1
, enum reg_class c2
)
2532 if (c1
== c2
) return 1;
2537 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) c1
],
2538 reg_class_contents
[(int) c2
],
2543 /* Return nonzero if there is a register that is in both C1 and C2. */
2546 reg_classes_intersect_p (enum reg_class c1
, enum reg_class c2
)
2550 if (c1
== c2
) return 1;
2552 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2555 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2556 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2558 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2565 /* Release any memory allocated by register sets. */
2568 regset_release_memory (void)
2570 bitmap_release_memory ();
2573 #ifdef CANNOT_CHANGE_MODE_CLASS
2575 struct subregs_of_mode_node
2578 unsigned char modes
[MAX_MACHINE_MODE
];
2581 static htab_t subregs_of_mode
;
2584 som_hash (const void *x
)
2586 const struct subregs_of_mode_node
*a
= x
;
2591 som_eq (const void *x
, const void *y
)
2593 const struct subregs_of_mode_node
*a
= x
;
2594 const struct subregs_of_mode_node
*b
= y
;
2595 return a
->block
== b
->block
;
2599 init_subregs_of_mode (void)
2601 if (subregs_of_mode
)
2602 htab_empty (subregs_of_mode
);
2604 subregs_of_mode
= htab_create (100, som_hash
, som_eq
, free
);
2608 record_subregs_of_mode (rtx subreg
)
2610 struct subregs_of_mode_node dummy
, *node
;
2611 enum machine_mode mode
;
2615 if (!REG_P (SUBREG_REG (subreg
)))
2618 regno
= REGNO (SUBREG_REG (subreg
));
2619 mode
= GET_MODE (subreg
);
2621 if (regno
< FIRST_PSEUDO_REGISTER
)
2624 dummy
.block
= regno
& -8;
2625 slot
= htab_find_slot_with_hash (subregs_of_mode
, &dummy
,
2626 dummy
.block
, INSERT
);
2630 node
= xcalloc (1, sizeof (*node
));
2631 node
->block
= regno
& -8;
2635 node
->modes
[mode
] |= 1 << (regno
& 7);
2638 /* Set bits in *USED which correspond to registers which can't change
2639 their mode from FROM to any mode in which REGNO was encountered. */
2642 cannot_change_mode_set_regs (HARD_REG_SET
*used
, enum machine_mode from
,
2645 struct subregs_of_mode_node dummy
, *node
;
2646 enum machine_mode to
;
2650 dummy
.block
= regno
& -8;
2651 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2655 mask
= 1 << (regno
& 7);
2656 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2657 if (node
->modes
[to
] & mask
)
2658 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2659 if (!TEST_HARD_REG_BIT (*used
, i
)
2660 && REG_CANNOT_CHANGE_MODE_P (i
, from
, to
))
2661 SET_HARD_REG_BIT (*used
, i
);
2664 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2668 invalid_mode_change_p (unsigned int regno
, enum reg_class
class,
2669 enum machine_mode from
)
2671 struct subregs_of_mode_node dummy
, *node
;
2672 enum machine_mode to
;
2675 dummy
.block
= regno
& -8;
2676 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2680 mask
= 1 << (regno
& 7);
2681 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2682 if (node
->modes
[to
] & mask
)
2683 if (CANNOT_CHANGE_MODE_CLASS (from
, to
, class))
2688 #endif /* CANNOT_CHANGE_MODE_CLASS */
2690 #include "gt-regclass.h"