sys/dev/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <drm/i915_component.h>
  26 #include "intel_drv.h"
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_edid.h>
  30 #include "i915_drv.h"
  31
  32 /**
  33  * DOC: High Definition Audio over HDMI and Display Port
  34  *
  35  * The graphics and audio drivers together support High Definition Audio over
  36  * HDMI and Display Port. The audio programming sequences are divided into audio
  37  * codec and controller enable and disable sequences. The graphics driver
  38  * handles the audio codec sequences, while the audio driver handles the audio
  39  * controller sequences.
  40  *
  41  * The disable sequences must be performed before disabling the transcoder or
  42  * port. The enable sequences may only be performed after enabling the
  43  * transcoder and port, and after completed link training. Therefore the audio
  44  * enable/disable sequences are part of the modeset sequence.
  45  *
  46  * The codec and controller sequences could be done either parallel or serial,
  47  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  48  * driver that the controller sequence should start. Indeed, most of the
  49  * co-operation between the graphics and audio drivers is handled via audio
  50  * related registers. (The notable exception is the power management, not
  51  * covered here.)
  52  *
  53  * The struct i915_audio_component is used to interact between the graphics
  54  * and audio drivers. The struct i915_audio_component_ops *ops in it is
  55  * defined in graphics driver and called in audio driver. The
  56  * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
  57  */
  58
  59 static const struct {
  60         int clock;
  61         u32 config;
  62 } hdmi_audio_clock[] = {
  63         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  64         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  65         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  66         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  67         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  68         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  69         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  70         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  71         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  72         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  73 };
  74
  75 /* HDMI N/CTS table */
  76 #define TMDS_297M 297000
  77 #define TMDS_296M 296703
  78 static const struct {
  79         int sample_rate;
  80         int clock;
  81         int n;
  82         int cts;
  83 } aud_ncts[] = {
  84         { 44100, TMDS_296M, 4459, 234375 },
  85         { 44100, TMDS_297M, 4704, 247500 },
  86         { 48000, TMDS_296M, 5824, 281250 },
  87         { 48000, TMDS_297M, 5120, 247500 },
  88         { 32000, TMDS_296M, 5824, 421875 },
  89         { 32000, TMDS_297M, 3072, 222750 },
  90         { 88200, TMDS_296M, 8918, 234375 },
  91         { 88200, TMDS_297M, 9408, 247500 },
  92         { 96000, TMDS_296M, 11648, 281250 },
  93         { 96000, TMDS_297M, 10240, 247500 },
  94         { 176400, TMDS_296M, 17836, 234375 },
  95         { 176400, TMDS_297M, 18816, 247500 },
  96         { 192000, TMDS_296M, 23296, 281250 },
  97         { 192000, TMDS_297M, 20480, 247500 },
  98 };
  99
 100 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 101 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
 102 {
 103         int i;
 104
 105         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 106                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 107                         break;
 108         }
 109
 110         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 111                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 112                               adjusted_mode->crtc_clock);
 113                 i = 1;
 114         }
 115
 116         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 117                       hdmi_audio_clock[i].clock,
 118                       hdmi_audio_clock[i].config);
 119
 120         return hdmi_audio_clock[i].config;
 121 }
 122
 123 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
 124 {
 125         int i;
 126
 127         for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
 128                 if ((rate == aud_ncts[i].sample_rate) &&
 129                         (mode->clock == aud_ncts[i].clock)) {
 130                         return aud_ncts[i].n;
 131                 }
 132         }
 133         return 0;
 134 }
 135
 136 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
 137 {
 138         int n_low, n_up;
 139         uint32_t tmp = val;
 140
 141         n_low = n & 0xfff;
 142         n_up = (n >> 12) & 0xff;
 143         tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
 144         tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
 145                         (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
 146                         AUD_CONFIG_N_PROG_ENABLE);
 147         return tmp;
 148 }
 149
 150 /* check whether N/CTS/M need be set manually */
 151 static bool audio_rate_need_prog(struct intel_crtc *crtc,
 152                                  const struct drm_display_mode *mode)
 153 {
 154         if (((mode->clock == TMDS_297M) ||
 155                  (mode->clock == TMDS_296M)) &&
 156                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 157                 return true;
 158         else
 159                 return false;
 160 }
 161
 162 static bool intel_eld_uptodate(struct drm_connector *connector,
 163                                i915_reg_t reg_eldv, uint32_t bits_eldv,
 164                                i915_reg_t reg_elda, uint32_t bits_elda,
 165                                i915_reg_t reg_edid)
 166 {
 167         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 168         uint8_t *eld = connector->eld;
 169         uint32_t tmp;
 170         int i;
 171
 172         tmp = I915_READ(reg_eldv);
 173         tmp &= bits_eldv;
 174
 175         if (!tmp)
 176                 return false;
 177
 178         tmp = I915_READ(reg_elda);
 179         tmp &= ~bits_elda;
 180         I915_WRITE(reg_elda, tmp);
 181
 182         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 183                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
 184                         return false;
 185
 186         return true;
 187 }
 188
 189 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
 190 {
 191         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 192         uint32_t eldv, tmp;
 193
 194         DRM_DEBUG_KMS("Disable audio codec\n");
 195
 196         tmp = I915_READ(G4X_AUD_VID_DID);
 197         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 198                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 199         else
 200                 eldv = G4X_ELDV_DEVCTG;
 201
 202         /* Invalidate ELD */
 203         tmp = I915_READ(G4X_AUD_CNTL_ST);
 204         tmp &= ~eldv;
 205         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 206 }
 207
 208 static void g4x_audio_codec_enable(struct drm_connector *connector,
 209                                    struct intel_encoder *encoder,
 210                                    const struct drm_display_mode *adjusted_mode)
 211 {
 212         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 213         uint8_t *eld = connector->eld;
 214         uint32_t eldv;
 215         uint32_t tmp;
 216         int len, i;
 217
 218         DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
 219
 220         tmp = I915_READ(G4X_AUD_VID_DID);
 221         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 222                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 223         else
 224                 eldv = G4X_ELDV_DEVCTG;
 225
 226         if (intel_eld_uptodate(connector,
 227                                G4X_AUD_CNTL_ST, eldv,
 228                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 229                                G4X_HDMIW_HDMIEDID))
 230                 return;
 231
 232         tmp = I915_READ(G4X_AUD_CNTL_ST);
 233         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 234         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 235         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 236
 237         len = min(drm_eld_size(eld) / 4, len);
 238         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 239         for (i = 0; i < len; i++)
 240                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 241
 242         tmp = I915_READ(G4X_AUD_CNTL_ST);
 243         tmp |= eldv;
 244         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 245 }
 246
 247 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
 248 {
 249         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 250         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 251         enum i915_pipe pipe = intel_crtc->pipe;
 252         uint32_t tmp;
 253
 254         DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
 255
 256         mutex_lock(&dev_priv->av_mutex);
 257
 258         /* Disable timestamps */
 259         tmp = I915_READ(HSW_AUD_CFG(pipe));
 260         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 261         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 262         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 263         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 264         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 265                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 266         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 267
 268         /* Invalidate ELD */
 269         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 270         tmp &= ~AUDIO_ELD_VALID(pipe);
 271         tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
 272         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 273
 274         mutex_unlock(&dev_priv->av_mutex);
 275 }
 276
 277 static void hsw_audio_codec_enable(struct drm_connector *connector,
 278                                    struct intel_encoder *encoder,
 279                                    const struct drm_display_mode *adjusted_mode)
 280 {
 281         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 282         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 283         enum i915_pipe pipe = intel_crtc->pipe;
 284         struct i915_audio_component *acomp = dev_priv->audio_component;
 285         const uint8_t *eld = connector->eld;
 286         struct intel_digital_port *intel_dig_port =
 287                 enc_to_dig_port(&encoder->base);
 288         enum port port = intel_dig_port->port;
 289         uint32_t tmp;
 290         int len, i;
 291         int n, rate;
 292
 293         DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
 294                       pipe_name(pipe), drm_eld_size(eld));
 295
 296         mutex_lock(&dev_priv->av_mutex);
 297
 298         /* Enable audio presence detect, invalidate ELD */
 299         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 300         tmp |= AUDIO_OUTPUT_ENABLE(pipe);
 301         tmp &= ~AUDIO_ELD_VALID(pipe);
 302         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 303
 304         /*
 305          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 306          * disabled during the mode set. The proper fix would be to push the
 307          * rest of the setup into a vblank work item, queued here, but the
 308          * infrastructure is not there yet.
 309          */
 310
 311         /* Reset ELD write address */
 312         tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
 313         tmp &= ~IBX_ELD_ADDRESS_MASK;
 314         I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
 315
 316         /* Up to 84 bytes of hw ELD buffer */
 317         len = min(drm_eld_size(eld), 84);
 318         for (i = 0; i < len / 4; i++)
 319                 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i));
 320
 321         /* ELD valid */
 322         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 323         tmp |= AUDIO_ELD_VALID(pipe);
 324         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 325
 326         /* Enable timestamps */
 327         tmp = I915_READ(HSW_AUD_CFG(pipe));
 328         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 329         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 330         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 331                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 332         else
 333                 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
 334
 335         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 336         if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
 337                 if (!acomp)
 338                         rate = 0;
 339                 else if (port >= PORT_A && port <= PORT_E)
 340                         rate = acomp->aud_sample_rate[port];
 341                 else {
 342                         DRM_ERROR("invalid port: %d\n", port);
 343                         rate = 0;
 344                 }
 345                 n = audio_config_get_n(adjusted_mode, rate);
 346                 if (n != 0)
 347                         tmp = audio_config_setup_n_reg(n, tmp);
 348                 else
 349                         DRM_DEBUG_KMS("no suitable N value is found\n");
 350         }
 351
 352         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 353
 354         mutex_unlock(&dev_priv->av_mutex);
 355 }
 356
 357 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 358 {
 359         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 360         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 361         struct intel_digital_port *intel_dig_port =
 362                 enc_to_dig_port(&encoder->base);
 363         enum port port = intel_dig_port->port;
 364         enum i915_pipe pipe = intel_crtc->pipe;
 365         uint32_t tmp, eldv;
 366         i915_reg_t aud_config, aud_cntrl_st2;
 367
 368         DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
 369                       port_name(port), pipe_name(pipe));
 370
 371         if (WARN_ON(port == PORT_A))
 372                 return;
 373
 374         if (HAS_PCH_IBX(dev_priv)) {
 375                 aud_config = IBX_AUD_CFG(pipe);
 376                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 377         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 378                 aud_config = VLV_AUD_CFG(pipe);
 379                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 380         } else {
 381                 aud_config = CPT_AUD_CFG(pipe);
 382                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 383         }
 384
 385         /* Disable timestamps */
 386         tmp = I915_READ(aud_config);
 387         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 388         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 389         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 390         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 391         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 392                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 393         I915_WRITE(aud_config, tmp);
 394
 395         eldv = IBX_ELD_VALID(port);
 396
 397         /* Invalidate ELD */
 398         tmp = I915_READ(aud_cntrl_st2);
 399         tmp &= ~eldv;
 400         I915_WRITE(aud_cntrl_st2, tmp);
 401 }
 402
 403 static void ilk_audio_codec_enable(struct drm_connector *connector,
 404                                    struct intel_encoder *encoder,
 405                                    const struct drm_display_mode *adjusted_mode)
 406 {
 407         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 408         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 409         struct intel_digital_port *intel_dig_port =
 410                 enc_to_dig_port(&encoder->base);
 411         enum port port = intel_dig_port->port;
 412         enum i915_pipe pipe = intel_crtc->pipe;
 413         uint8_t *eld = connector->eld;
 414         uint32_t eldv;
 415         uint32_t tmp;
 416         int len, i;
 417         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 418
 419         DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
 420                       port_name(port), pipe_name(pipe), drm_eld_size(eld));
 421
 422         if (WARN_ON(port == PORT_A))
 423                 return;
 424
 425         /*
 426          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 427          * disabled during the mode set. The proper fix would be to push the
 428          * rest of the setup into a vblank work item, queued here, but the
 429          * infrastructure is not there yet.
 430          */
 431
 432         if (HAS_PCH_IBX(connector->dev)) {
 433                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 434                 aud_config = IBX_AUD_CFG(pipe);
 435                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 436                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 437         } else if (IS_VALLEYVIEW(connector->dev) ||
 438                    IS_CHERRYVIEW(connector->dev)) {
 439                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 440                 aud_config = VLV_AUD_CFG(pipe);
 441                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 442                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 443         } else {
 444                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 445                 aud_config = CPT_AUD_CFG(pipe);
 446                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 447                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 448         }
 449
 450         eldv = IBX_ELD_VALID(port);
 451
 452         /* Invalidate ELD */
 453         tmp = I915_READ(aud_cntrl_st2);
 454         tmp &= ~eldv;
 455         I915_WRITE(aud_cntrl_st2, tmp);
 456
 457         /* Reset ELD write address */
 458         tmp = I915_READ(aud_cntl_st);
 459         tmp &= ~IBX_ELD_ADDRESS_MASK;
 460         I915_WRITE(aud_cntl_st, tmp);
 461
 462         /* Up to 84 bytes of hw ELD buffer */
 463         len = min(drm_eld_size(eld), 84);
 464         for (i = 0; i < len / 4; i++)
 465                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 466
 467         /* ELD valid */
 468         tmp = I915_READ(aud_cntrl_st2);
 469         tmp |= eldv;
 470         I915_WRITE(aud_cntrl_st2, tmp);
 471
 472         /* Enable timestamps */
 473         tmp = I915_READ(aud_config);
 474         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 475         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 476         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 477         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 478                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 479         else
 480                 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
 481         I915_WRITE(aud_config, tmp);
 482 }
 483
 484 /**
 485  * intel_audio_codec_enable - Enable the audio codec for HD audio
 486  * @intel_encoder: encoder on which to enable audio
 487  *
 488  * The enable sequences may only be performed after enabling the transcoder and
 489  * port, and after completed link training.
 490  */
 491 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 492 {
 493         struct drm_encoder *encoder = &intel_encoder->base;
 494         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 495         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 496         struct drm_connector *connector;
 497         struct drm_device *dev = encoder->dev;
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         struct i915_audio_component *acomp = dev_priv->audio_component;
 500         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 501         enum port port = intel_dig_port->port;
 502
 503         connector = drm_select_eld(encoder);
 504         if (!connector)
 505                 return;
 506
 507         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 508                          connector->base.id,
 509                          connector->name,
 510                          connector->encoder->base.id,
 511                          connector->encoder->name);
 512
 513         /* ELD Conn_Type */
 514         connector->eld[5] &= ~(3 << 2);
 515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 516                 connector->eld[5] |= (1 << 2);
 517
 518         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 519
 520         if (dev_priv->display.audio_codec_enable)
 521                 dev_priv->display.audio_codec_enable(connector, intel_encoder,
 522                                                      adjusted_mode);
 523
 524         mutex_lock(&dev_priv->av_mutex);
 525         intel_dig_port->audio_connector = connector;
 526         /* referred in audio callbacks */
 527         dev_priv->dig_port_map[port] = intel_encoder;
 528         mutex_unlock(&dev_priv->av_mutex);
 529
 530         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 531                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 532 }
 533
 534 /**
 535  * intel_audio_codec_disable - Disable the audio codec for HD audio
 536  * @intel_encoder: encoder on which to disable audio
 537  *
 538  * The disable sequences must be performed before disabling the transcoder or
 539  * port.
 540  */
 541 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 542 {
 543         struct drm_encoder *encoder = &intel_encoder->base;
 544         struct drm_device *dev = encoder->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         struct i915_audio_component *acomp = dev_priv->audio_component;
 547         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 548         enum port port = intel_dig_port->port;
 549
 550         if (dev_priv->display.audio_codec_disable)
 551                 dev_priv->display.audio_codec_disable(intel_encoder);
 552
 553         mutex_lock(&dev_priv->av_mutex);
 554         intel_dig_port->audio_connector = NULL;
 555         dev_priv->dig_port_map[port] = NULL;
 556         mutex_unlock(&dev_priv->av_mutex);
 557
 558         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 559                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 560 }
 561
 562 /**
 563  * intel_init_audio_hooks - Set up chip specific audio hooks
 564  * @dev_priv: device private
 565  */
 566 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 567 {
 568         if (IS_G4X(dev_priv)) {
 569                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 570                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 571         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 572                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 573                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 574         } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
 575                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 576                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 577         } else if (HAS_PCH_SPLIT(dev_priv)) {
 578                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 579                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 580         }
 581 }
 582
 583 static void i915_audio_component_get_power(struct device *dev)
 584 {
 585         intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 586 }
 587
 588 static void i915_audio_component_put_power(struct device *dev)
 589 {
 590         intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 591 }
 592
 593 static void i915_audio_component_codec_wake_override(struct device *dev,
 594                                                      bool enable)
 595 {
 596         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 597         u32 tmp;
 598
 599         if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
 600                 return;
 601
 602         i915_audio_component_get_power(dev);
 603
 604         /*
 605          * Enable/disable generating the codec wake signal, overriding the
 606          * internal logic to generate the codec wake to controller.
 607          */
 608         tmp = I915_READ(HSW_AUD_CHICKENBIT);
 609         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
 610         I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 611         usleep_range(1000, 1500);
 612
 613         if (enable) {
 614                 tmp = I915_READ(HSW_AUD_CHICKENBIT);
 615                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
 616                 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 617                 usleep_range(1000, 1500);
 618         }
 619
 620         i915_audio_component_put_power(dev);
 621 }
 622
 623 /* Get CDCLK in kHz  */
 624 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 627         int ret;
 628
 629         if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
 630                 return -ENODEV;
 631
 632         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
 633         ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
 634
 635         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
 636
 637         return ret;
 638 }
 639
 640 static int i915_audio_component_sync_audio_rate(struct device *dev,
 641                                                 int port, int rate)
 642 {
 643         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 644         struct intel_encoder *intel_encoder;
 645         struct intel_crtc *crtc;
 646         struct drm_display_mode *mode;
 647         struct i915_audio_component *acomp = dev_priv->audio_component;
 648         enum i915_pipe pipe = INVALID_PIPE;
 649         u32 tmp;
 650         int n;
 651         int err = 0;
 652
 653         /* HSW, BDW, SKL, KBL need this fix */
 654         if (!IS_SKYLAKE(dev_priv) &&
 655             !IS_KABYLAKE(dev_priv) &&
 656             !IS_BROADWELL(dev_priv) &&
 657             !IS_HASWELL(dev_priv))
 658                 return 0;
 659
 660         i915_audio_component_get_power(dev);
 661         mutex_lock(&dev_priv->av_mutex);
 662         /* 1. get the pipe */
 663         intel_encoder = dev_priv->dig_port_map[port];
 664         /* intel_encoder might be NULL for DP MST */
 665         if (!intel_encoder || !intel_encoder->base.crtc ||
 666             intel_encoder->type != INTEL_OUTPUT_HDMI) {
 667                 DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
 668                 err = -ENODEV;
 669                 goto unlock;
 670         }
 671         crtc = to_intel_crtc(intel_encoder->base.crtc);
 672         pipe = crtc->pipe;
 673         if (pipe == INVALID_PIPE) {
 674                 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
 675                 err = -ENODEV;
 676                 goto unlock;
 677         }
 678
 679         DRM_DEBUG_KMS("pipe %c connects port %c\n",
 680                                   pipe_name(pipe), port_name(port));
 681         mode = &crtc->config->base.adjusted_mode;
 682
 683         /* port must be valid now, otherwise the pipe will be invalid */
 684         acomp->aud_sample_rate[port] = rate;
 685
 686         /* 2. check whether to set the N/CTS/M manually or not */
 687         if (!audio_rate_need_prog(crtc, mode)) {
 688                 tmp = I915_READ(HSW_AUD_CFG(pipe));
 689                 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 690                 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 691                 goto unlock;
 692         }
 693
 694         n = audio_config_get_n(mode, rate);
 695         if (n == 0) {
 696                 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
 697                                           port_name(port));
 698                 tmp = I915_READ(HSW_AUD_CFG(pipe));
 699                 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 700                 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 701                 goto unlock;
 702         }
 703
 704         /* 3. set the N/CTS/M */
 705         tmp = I915_READ(HSW_AUD_CFG(pipe));
 706         tmp = audio_config_setup_n_reg(n, tmp);
 707         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 708
 709  unlock:
 710         mutex_unlock(&dev_priv->av_mutex);
 711         i915_audio_component_put_power(dev);
 712         return err;
 713 }
 714
 715 static int i915_audio_component_get_eld(struct device *dev, int port,
 716                                         bool *enabled,
 717                                         unsigned char *buf, int max_bytes)
 718 {
 719         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 720         struct intel_encoder *intel_encoder;
 721         struct intel_digital_port *intel_dig_port;
 722         const u8 *eld;
 723         int ret = -EINVAL;
 724
 725         mutex_lock(&dev_priv->av_mutex);
 726         intel_encoder = dev_priv->dig_port_map[port];
 727         /* intel_encoder might be NULL for DP MST */
 728         if (intel_encoder) {
 729                 ret = 0;
 730                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
 731                 *enabled = intel_dig_port->audio_connector != NULL;
 732                 if (*enabled) {
 733                         eld = intel_dig_port->audio_connector->eld;
 734                         ret = drm_eld_size(eld);
 735                         memcpy(buf, eld, min(max_bytes, ret));
 736                 }
 737         }
 738
 739         mutex_unlock(&dev_priv->av_mutex);
 740         return ret;
 741 }
 742
 743 static const struct i915_audio_component_ops i915_audio_component_ops = {
 744         .owner          = THIS_MODULE,
 745         .get_power      = i915_audio_component_get_power,
 746         .put_power      = i915_audio_component_put_power,
 747         .codec_wake_override = i915_audio_component_codec_wake_override,
 748         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
 749         .sync_audio_rate = i915_audio_component_sync_audio_rate,
 750         .get_eld        = i915_audio_component_get_eld,
 751 };
 752
 753 #if 0
 754 static int i915_audio_component_bind(struct device *i915_dev,
 755                                      struct device *hda_dev, void *data)
 756 {
 757         struct i915_audio_component *acomp = data;
 758         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 759         int i;
 760
 761         if (WARN_ON(acomp->ops || acomp->dev))
 762                 return -EEXIST;
 763
 764         drm_modeset_lock_all(dev_priv->dev);
 765         acomp->ops = &i915_audio_component_ops;
 766         acomp->dev = i915_dev;
 767         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
 768         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
 769                 acomp->aud_sample_rate[i] = 0;
 770         dev_priv->audio_component = acomp;
 771         drm_modeset_unlock_all(dev_priv->dev);
 772
 773         return 0;
 774 }
 775
 776 static void i915_audio_component_unbind(struct device *i915_dev,
 777                                         struct device *hda_dev, void *data)
 778 {
 779         struct i915_audio_component *acomp = data;
 780         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 781
 782         drm_modeset_lock_all(dev_priv->dev);
 783         acomp->ops = NULL;
 784         acomp->dev = NULL;
 785         dev_priv->audio_component = NULL;
 786         drm_modeset_unlock_all(dev_priv->dev);
 787 }
 788
 789 static const struct component_ops i915_audio_component_bind_ops = {
 790         .bind   = i915_audio_component_bind,
 791         .unbind = i915_audio_component_unbind,
 792 };
 793 #endif
 794
 795 /**
 796  * i915_audio_component_init - initialize and register the audio component
 797  * @dev_priv: i915 device instance
 798  *
 799  * This will register with the component framework a child component which
 800  * will bind dynamically to the snd_hda_intel driver's corresponding master
 801  * component when the latter is registered. During binding the child
 802  * initializes an instance of struct i915_audio_component which it receives
 803  * from the master. The master can then start to use the interface defined by
 804  * this struct. Each side can break the binding at any point by deregistering
 805  * its own component after which each side's component unbind callback is
 806  * called.
 807  *
 808  * We ignore any error during registration and continue with reduced
 809  * functionality (i.e. without HDMI audio).
 810  */
 811 void i915_audio_component_init(struct drm_i915_private *dev_priv)
 812 {
 813 #if 0
 814         int ret;
 815
 816         ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 817         if (ret < 0) {
 818                 DRM_ERROR("failed to add audio component (%d)\n", ret);
 819                 /* continue with reduced functionality */
 820                 return;
 821         }
 822 #endif
 823
 824         dev_priv->audio_component_registered = true;
 825 }
 826
 827 /**
 828  * i915_audio_component_cleanup - deregister the audio component
 829  * @dev_priv: i915 device instance
 830  *
 831  * Deregisters the audio component, breaking any existing binding to the
 832  * corresponding snd_hda_intel driver's master component.
 833  */
 834 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
 835 {
 836         if (!dev_priv->audio_component_registered)
 837                 return;
 838
 839 #if 0
 840         component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 841 #endif
 842         dev_priv->audio_component_registered = false;
 843 }