2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * $FreeBSD: src/sys/dev/advansys/adwlib.c,v 1.6.2.1 2000/04/14 13:32:50 nyan Exp $
36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
38 * Copyright (c) 1995-1998 Advanced System Products, Inc.
39 * All Rights Reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that redistributions of source
43 * code retain the above copyright notice and this comment without
47 #include <sys/param.h>
48 #include <sys/systm.h>
50 #include <sys/thread2.h>
52 #include <machine/clock.h>
54 #include <bus/cam/cam.h>
55 #include <bus/cam/cam_ccb.h>
56 #include <bus/cam/cam_sim.h>
57 #include <bus/cam/cam_xpt_sim.h>
58 #include <bus/cam/scsi/scsi_all.h>
62 const struct adw_eeprom adw_asc3550_default_eeprom
=
64 ADW_EEPROM_BIOS_ENABLE
, /* cfg_lsw */
66 0xFFFF, /* disc_enable */
67 0xFFFF, /* wdtr_able */
68 { 0xFFFF }, /* sdtr_able */
69 0xFFFF, /* start_motor */
70 0xFFFF, /* tagqng_able */
71 0xFFFF, /* bios_scan */
72 0, /* scam_tolerant */
73 7, /* adapter_scsi_id */
74 0, /* bios_boot_delay */
75 3, /* scsi_reset_delay */
79 0xFFE7, /* bios_ctrl */
80 { 0xFFFF }, /* ultra_able */
81 { 0 }, /* reserved2 */
82 ADW_DEF_MAX_HOST_QNG
, /* max_host_qng */
83 ADW_DEF_MAX_DVC_QNG
, /* max_dvc_qng */
86 { 0, 0, 0 }, /* serial_number */
89 0, 0, 0, 0, 0, 0, 0, 0,
90 0, 0, 0, 0, 0, 0, 0, 0
95 0, /* saved_dvc_err_code */
96 0, /* saved_adv_err_code */
97 0 /* saved_adv_err_addr */
100 const struct adw_eeprom adw_asc38C0800_default_eeprom
=
102 ADW_EEPROM_BIOS_ENABLE
, /* 00 cfg_lsw */
103 0x0000, /* 01 cfg_msw */
104 0xFFFF, /* 02 disc_enable */
105 0xFFFF, /* 03 wdtr_able */
106 { 0x4444 }, /* 04 sdtr_speed1 */
107 0xFFFF, /* 05 start_motor */
108 0xFFFF, /* 06 tagqng_able */
109 0xFFFF, /* 07 bios_scan */
110 0, /* 08 scam_tolerant */
111 7, /* 09 adapter_scsi_id */
112 0, /* bios_boot_delay */
113 3, /* 10 scsi_reset_delay */
115 0, /* 11 termination_se */
116 0, /* termination_lvd */
117 0xFFE7, /* 12 bios_ctrl */
118 { 0x4444 }, /* 13 sdtr_speed2 */
119 { 0x4444 }, /* 14 sdtr_speed3 */
120 ADW_DEF_MAX_HOST_QNG
, /* 15 max_host_qng */
121 ADW_DEF_MAX_DVC_QNG
, /* max_dvc_qng */
123 { 0x4444 } , /* 17 sdtr_speed4 */
124 { 0, 0, 0 }, /* 18-20 serial_number */
125 0, /* 21 check_sum */
126 { /* 22-29 oem_name[16] */
127 0, 0, 0, 0, 0, 0, 0, 0,
128 0, 0, 0, 0, 0, 0, 0, 0
130 0, /* 30 dvc_err_code */
131 0, /* 31 adv_err_code */
132 0, /* 32 adv_err_addr */
133 0, /* 33 saved_dvc_err_code */
134 0, /* 34 saved_adv_err_code */
135 0, /* 35 saved_adv_err_addr */
136 { /* 36 - 55 reserved */
137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
140 0, /* 56 cisptr_lsw */
141 0, /* 57 cisprt_msw */
143 (PCI_ID_ADVANSYS_38C0800_REV1
& PCI_ID_DEV_VENDOR_MASK
) >> 32,
146 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
147 #define ADW_MC_SDTR_OFFSET_ULTRA2 1
148 #define ADW_MC_SDTR_OFFSET_ULTRA 2
149 const struct adw_syncrate adw_syncrates
[] =
151 /* mc_sdtr period rate */
152 { ADW_MC_SDTR_80
, 9, "80.0" },
153 { ADW_MC_SDTR_40
, 10, "40.0" },
154 { ADW_MC_SDTR_20
, 12, "20.0" },
155 { ADW_MC_SDTR_10
, 25, "10.0" },
156 { ADW_MC_SDTR_5
, 50, "5.0" },
157 { ADW_MC_SDTR_ASYNC
, 0, "async" }
160 const int adw_num_syncrates
= NELEM(adw_syncrates
);
162 static u_int16_t
adw_eeprom_read_16(struct adw_softc
*adw
, int addr
);
163 static void adw_eeprom_write_16(struct adw_softc
*adw
, int addr
,
165 static void adw_eeprom_wait(struct adw_softc
*adw
);
168 adw_find_signature(struct adw_softc
*adw
)
170 if (adw_inb(adw
, ADW_SIGNATURE_BYTE
) == ADW_CHIP_ID_BYTE
171 && adw_inw(adw
, ADW_SIGNATURE_WORD
) == ADW_CHIP_ID_WORD
)
180 adw_reset_chip(struct adw_softc
*adw
)
182 adw_outw(adw
, ADW_CTRL_REG
, ADW_CTRL_REG_CMD_RESET
);
184 adw_outw(adw
, ADW_CTRL_REG
, ADW_CTRL_REG_CMD_WR_IO_REG
);
187 * Initialize Chip registers.
189 adw_outw(adw
, ADW_SCSI_CFG1
,
190 adw_inw(adw
, ADW_SCSI_CFG1
) & ~ADW_SCSI_CFG1_BIG_ENDIAN
);
194 * Reset the SCSI bus.
197 adw_reset_bus(struct adw_softc
*adw
)
199 adw_idle_cmd_status_t status
;
202 adw_idle_cmd_send(adw
, ADW_IDLE_CMD_SCSI_RESET_START
, /*param*/0);
203 if (status
!= ADW_IDLE_CMD_SUCCESS
) {
204 xpt_print_path(adw
->path
);
205 kprintf("Bus Reset start attempt failed\n");
208 DELAY(ADW_BUS_RESET_HOLD_DELAY_US
);
210 adw_idle_cmd_send(adw
, ADW_IDLE_CMD_SCSI_RESET_END
, /*param*/0);
211 if (status
!= ADW_IDLE_CMD_SUCCESS
) {
212 xpt_print_path(adw
->path
);
213 kprintf("Bus Reset end attempt failed\n");
220 * Read the specified EEPROM location
223 adw_eeprom_read_16(struct adw_softc
*adw
, int addr
)
225 adw_outw(adw
, ADW_EEP_CMD
, ADW_EEP_CMD_READ
| addr
);
226 adw_eeprom_wait(adw
);
227 return (adw_inw(adw
, ADW_EEP_DATA
));
231 adw_eeprom_write_16(struct adw_softc
*adw
, int addr
, u_int data
)
233 adw_outw(adw
, ADW_EEP_DATA
, data
);
234 adw_outw(adw
, ADW_EEP_CMD
, ADW_EEP_CMD_WRITE
| addr
);
235 adw_eeprom_wait(adw
);
239 * Wait for and EEPROM command to complete
242 adw_eeprom_wait(struct adw_softc
*adw
)
246 for (i
= 0; i
< ADW_EEP_DELAY_MS
; i
++) {
247 if ((adw_inw(adw
, ADW_EEP_CMD
) & ADW_EEP_CMD_DONE
) != 0)
251 if (i
== ADW_EEP_DELAY_MS
)
252 panic("%s: Timedout Reading EEPROM", adw_name(adw
));
256 * Read EEPROM configuration into the specified buffer.
258 * Return a checksum based on the EEPROM configuration read.
261 adw_eeprom_read(struct adw_softc
*adw
, struct adw_eeprom
*eep_buf
)
268 wbuf
= (u_int16_t
*)eep_buf
;
271 for (eep_addr
= ADW_EEP_DVC_CFG_BEGIN
;
272 eep_addr
< ADW_EEP_DVC_CFG_END
;
273 eep_addr
++, wbuf
++) {
274 wval
= adw_eeprom_read_16(adw
, eep_addr
);
279 /* checksum field is not counted in the checksum */
280 *wbuf
= adw_eeprom_read_16(adw
, eep_addr
);
283 /* Driver seeprom variables are not included in the checksum */
284 for (eep_addr
= ADW_EEP_DVC_CTL_BEGIN
;
285 eep_addr
< ADW_EEP_MAX_WORD_ADDR
;
287 *wbuf
= adw_eeprom_read_16(adw
, eep_addr
);
293 adw_eeprom_write(struct adw_softc
*adw
, struct adw_eeprom
*eep_buf
)
299 wbuf
= (u_int16_t
*)eep_buf
;
302 adw_outw(adw
, ADW_EEP_CMD
, ADW_EEP_CMD_WRITE_ABLE
);
303 adw_eeprom_wait(adw
);
306 * Write EEPROM until checksum.
308 for (addr
= ADW_EEP_DVC_CFG_BEGIN
;
309 addr
< ADW_EEP_DVC_CFG_END
; addr
++, wbuf
++) {
311 adw_eeprom_write_16(adw
, addr
, *wbuf
);
315 * Write calculated EEPROM checksum
317 adw_eeprom_write_16(adw
, addr
, chksum
);
319 /* skip over buffer's checksum */
325 for (addr
= ADW_EEP_DVC_CTL_BEGIN
;
326 addr
< ADW_EEP_MAX_WORD_ADDR
; addr
++, wbuf
++)
327 adw_eeprom_write_16(adw
, addr
, *wbuf
);
329 adw_outw(adw
, ADW_EEP_CMD
, ADW_EEP_CMD_WRITE_DISABLE
);
330 adw_eeprom_wait(adw
);
334 adw_init_chip(struct adw_softc
*adw
, u_int term_scsicfg1
)
336 u_int8_t biosmem
[ADW_MC_BIOSLEN
];
337 const u_int16_t
*word_table
;
338 const u_int8_t
*byte_codes
;
339 const u_int8_t
*byte_codes_end
;
341 u_int bytes_downloaded
;
349 * Save the RISC memory BIOS region before writing the microcode.
350 * The BIOS may already be loaded and using its RISC LRAM region
351 * so its region must be saved and restored.
353 for (addr
= 0; addr
< ADW_MC_BIOSLEN
; addr
++)
354 biosmem
[addr
] = adw_lram_read_8(adw
, ADW_MC_BIOSMEM
+ addr
);
357 * Save current per TID negotiated values if the BIOS has been
358 * loaded (BIOS signature is present). These will be used if
359 * we cannot get information from the EEPROM.
361 addr
= ADW_MC_BIOS_SIGNATURE
- ADW_MC_BIOSMEM
;
362 bios_sig
= biosmem
[addr
]
363 | (biosmem
[addr
+ 1] << 8);
364 if (bios_sig
== 0x55AA
365 && (adw
->flags
& ADW_EEPROM_FAILED
) != 0) {
370 addr
= ADW_MC_BIOS_VERSION
- ADW_MC_BIOSMEM
;
371 minor_ver
= biosmem
[addr
+ 1] & 0xF;
372 major_ver
= (biosmem
[addr
+ 1] >> 4) & 0xF;
373 if ((adw
->chip
== ADW_CHIP_ASC3550
)
375 || (major_ver
== 3 && minor_ver
== 1))) {
377 * BIOS 3.1 and earlier location of
378 * 'wdtr_able' variable.
381 adw_lram_read_16(adw
, ADW_MC_WDTR_ABLE_BIOS_31
);
384 adw_lram_read_16(adw
, ADW_MC_WDTR_ABLE
);
386 sdtr_able
= adw_lram_read_16(adw
, ADW_MC_SDTR_ABLE
);
387 for (tid
= 0; tid
< ADW_MAX_TID
; tid
++) {
391 tid_mask
= 0x1 << tid
;
392 if ((sdtr_able
& tid_mask
) == 0)
393 mc_sdtr
= ADW_MC_SDTR_ASYNC
;
394 else if ((adw
->features
& ADW_DT
) != 0)
395 mc_sdtr
= ADW_MC_SDTR_80
;
396 else if ((adw
->features
& ADW_ULTRA2
) != 0)
397 mc_sdtr
= ADW_MC_SDTR_40
;
399 mc_sdtr
= ADW_MC_SDTR_20
;
400 adw_set_user_sdtr(adw
, tid
, mc_sdtr
);
402 adw
->user_tagenb
= adw_lram_read_16(adw
, ADW_MC_TAGQNG_ABLE
);
406 * Load the Microcode.
408 * Assume the following compressed format of the microcode buffer:
410 * 253 word (506 byte) table indexed by byte code followed
411 * by the following byte codes:
414 * 00: Emit word 0 in table.
415 * 01: Emit word 1 in table.
417 * FD: Emit word 253 in table.
422 * FE WW WW: (3 byte code)
423 * Word to emit is the next word WW WW.
424 * FF BB WW WW: (4 byte code)
425 * Emit BB count times next word WW WW.
428 bytes_downloaded
= 0;
429 word_table
= (const u_int16_t
*)adw
->mcode_data
->mcode_buf
;
430 byte_codes
= (const u_int8_t
*)&word_table
[253];
431 byte_codes_end
= adw
->mcode_data
->mcode_buf
432 + adw
->mcode_data
->mcode_size
;
433 adw_outw(adw
, ADW_RAM_ADDR
, 0);
434 while (byte_codes
< byte_codes_end
) {
435 if (*byte_codes
== 0xFF) {
438 value
= byte_codes
[2]
439 | byte_codes
[3] << 8;
440 adw_set_multi_2(adw
, ADW_RAM_DATA
,
441 value
, byte_codes
[1]);
442 bytes_downloaded
+= byte_codes
[1];
444 } else if (*byte_codes
== 0xFE) {
447 value
= byte_codes
[1]
448 | byte_codes
[2] << 8;
449 adw_outw(adw
, ADW_RAM_DATA
, value
);
453 adw_outw(adw
, ADW_RAM_DATA
, word_table
[*byte_codes
]);
458 /* Convert from words to bytes */
459 bytes_downloaded
*= 2;
462 * Clear the rest of LRAM.
464 for (addr
= bytes_downloaded
; addr
< adw
->memsize
; addr
+= 2)
465 adw_outw(adw
, ADW_RAM_DATA
, 0);
468 * Verify the microcode checksum.
471 adw_outw(adw
, ADW_RAM_ADDR
, 0);
472 for (addr
= 0; addr
< bytes_downloaded
; addr
+= 2)
473 checksum
+= adw_inw(adw
, ADW_RAM_DATA
);
475 if (checksum
!= adw
->mcode_data
->mcode_chksum
) {
476 kprintf("%s: Firmware load failed!\n", adw_name(adw
));
481 * Restore the RISC memory BIOS region.
483 for (addr
= 0; addr
< ADW_MC_BIOSLEN
; addr
++)
484 adw_lram_write_8(adw
, addr
+ ADW_MC_BIOSLEN
, biosmem
[addr
]);
487 * Calculate and write the microcode code checksum to
488 * the microcode code checksum location.
490 addr
= adw_lram_read_16(adw
, ADW_MC_CODE_BEGIN_ADDR
);
491 end_addr
= adw_lram_read_16(adw
, ADW_MC_CODE_END_ADDR
);
493 adw_outw(adw
, ADW_RAM_ADDR
, addr
);
494 for (; addr
< end_addr
; addr
+= 2)
495 checksum
+= adw_inw(adw
, ADW_RAM_DATA
);
496 adw_lram_write_16(adw
, ADW_MC_CODE_CHK_SUM
, checksum
);
499 * Tell the microcode what kind of chip it's running on.
501 adw_lram_write_16(adw
, ADW_MC_CHIP_TYPE
, adw
->chip
);
504 * Leave WDTR and SDTR negotiation disabled until the XPT has
505 * informed us of device capabilities, but do set the desired
506 * user rates in case we receive an SDTR request from the target
507 * before we negotiate. We turn on tagged queuing at the microcode
508 * level for all devices, and modulate this on a per command basis.
510 adw_lram_write_16(adw
, ADW_MC_SDTR_SPEED1
, adw
->user_sdtr
[0]);
511 adw_lram_write_16(adw
, ADW_MC_SDTR_SPEED2
, adw
->user_sdtr
[1]);
512 adw_lram_write_16(adw
, ADW_MC_SDTR_SPEED3
, adw
->user_sdtr
[2]);
513 adw_lram_write_16(adw
, ADW_MC_SDTR_SPEED4
, adw
->user_sdtr
[3]);
514 adw_lram_write_16(adw
, ADW_MC_DISC_ENABLE
, adw
->user_discenb
);
515 for (tid
= 0; tid
< ADW_MAX_TID
; tid
++) {
516 /* Cam limits the maximum number of commands for us */
517 adw_lram_write_8(adw
, ADW_MC_NUMBER_OF_MAX_CMD
+ tid
,
520 adw_lram_write_16(adw
, ADW_MC_TAGQNG_ABLE
, ~0);
523 * Set SCSI_CFG0 Microcode Default Value.
525 * The microcode will set the SCSI_CFG0 register using this value
526 * after it is started.
528 adw_lram_write_16(adw
, ADW_MC_DEFAULT_SCSI_CFG0
,
529 ADW_SCSI_CFG0_PARITY_EN
|ADW_SCSI_CFG0_SEL_TMO_LONG
|
530 ADW_SCSI_CFG0_OUR_ID_EN
|adw
->initiator_id
);
533 * Tell the MC about the memory size that
534 * was setup by the probe code.
536 adw_lram_write_16(adw
, ADW_MC_DEFAULT_MEM_CFG
,
537 adw_inb(adw
, ADW_MEM_CFG
) & ADW_MEM_CFG_RAM_SZ_MASK
);
540 * Determine SCSI_CFG1 Microcode Default Value.
542 * The microcode will set the SCSI_CFG1 register using this value
543 * after it is started below.
545 scsicfg1
= adw_inw(adw
, ADW_SCSI_CFG1
);
548 * If the internal narrow cable is reversed all of the SCSI_CTRL
549 * register signals will be set. Check for and return an error if
550 * this condition is found.
552 if ((adw_inw(adw
, ADW_SCSI_CTRL
) & 0x3F07) == 0x3F07) {
553 kprintf("%s: Illegal Cable Config!\n", adw_name(adw
));
554 kprintf("%s: Internal cable is reversed!\n", adw_name(adw
));
559 * If this is a differential board and a single-ended device
560 * is attached to one of the connectors, return an error.
562 if ((adw
->features
& ADW_ULTRA
) != 0) {
563 if ((scsicfg1
& ADW_SCSI_CFG1_DIFF_MODE
) != 0
564 && (scsicfg1
& ADW_SCSI_CFG1_DIFF_SENSE
) == 0) {
565 kprintf("%s: A Single Ended Device is attached to our "
566 "differential bus!\n", adw_name(adw
));
570 if ((scsicfg1
& ADW2_SCSI_CFG1_DEV_DETECT_HVD
) != 0) {
571 kprintf("%s: A High Voltage Differential Device "
572 "is attached to this controller.\n",
574 kprintf("%s: HVD devices are not supported.\n",
581 * Perform automatic termination control if desired.
583 if ((adw
->features
& ADW_ULTRA2
) != 0) {
587 * Ultra2 Chips require termination disabled to
588 * detect cable presence.
590 adw_outw(adw
, ADW_SCSI_CFG1
,
591 scsicfg1
| ADW2_SCSI_CFG1_DIS_TERM_DRV
);
592 cable_det
= adw_inw(adw
, ADW_SCSI_CFG1
);
593 adw_outw(adw
, ADW_SCSI_CFG1
, scsicfg1
);
595 /* SE Termination first if auto-term has been specified */
596 if ((term_scsicfg1
& ADW_SCSI_CFG1_TERM_CTL_MASK
) == 0) {
599 * For all SE cable configurations, high byte
600 * termination is enabled.
602 term_scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_H
;
603 if ((cable_det
& ADW_SCSI_CFG1_INT8_MASK
) != 0
604 || (cable_det
& ADW_SCSI_CFG1_INT16_MASK
) != 0) {
606 * If either cable is not present, the
607 * low byte must be terminated as well.
609 term_scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_L
;
614 if ((term_scsicfg1
& ADW2_SCSI_CFG1_TERM_CTL_LVD
) == 0
615 && (term_scsicfg1
& ADW2_SCSI_CFG1_DIS_TERM_DRV
) == 0) {
617 * If both cables are installed, termination
618 * is disabled. Otherwise it is enabled.
620 if ((cable_det
& ADW2_SCSI_CFG1_EXTLVD_MASK
) != 0
621 || (cable_det
& ADW2_SCSI_CFG1_INTLVD_MASK
) != 0) {
623 term_scsicfg1
|= ADW2_SCSI_CFG1_TERM_CTL_LVD
;
626 term_scsicfg1
&= ~ADW2_SCSI_CFG1_DIS_TERM_DRV
;
628 /* Ultra Controller Termination */
629 if ((term_scsicfg1
& ADW_SCSI_CFG1_TERM_CTL_MASK
) == 0) {
631 int wide_cable_count
;
634 wide_cable_count
= 0;
635 if ((scsicfg1
& ADW_SCSI_CFG1_INT16_MASK
) == 0) {
639 if ((scsicfg1
& ADW_SCSI_CFG1_INT8_MASK
) == 0)
642 /* There is only one external port */
643 if ((scsicfg1
& ADW_SCSI_CFG1_EXT16_MASK
) == 0) {
646 } else if ((scsicfg1
& ADW_SCSI_CFG1_EXT8_MASK
) == 0)
649 if (cable_count
== 3) {
650 kprintf("%s: Illegal Cable Config!\n",
652 kprintf("%s: Only Two Ports may be used at "
653 "a time!\n", adw_name(adw
));
654 } else if (cable_count
<= 1) {
656 * At least two out of three cables missing.
657 * Terminate both bytes.
659 term_scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_H
660 | ADW_SCSI_CFG1_TERM_CTL_L
;
661 } else if (wide_cable_count
<= 1) {
662 /* No two 16bit cables present. High on. */
663 term_scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_H
;
668 /* Tell the user about our decission */
669 switch (term_scsicfg1
& ADW_SCSI_CFG1_TERM_CTL_MASK
) {
670 case ADW_SCSI_CFG1_TERM_CTL_MASK
:
671 kprintf("High & Low SE Term Enabled, ");
673 case ADW_SCSI_CFG1_TERM_CTL_H
:
674 kprintf("High SE Termination Enabled, ");
676 case ADW_SCSI_CFG1_TERM_CTL_L
:
677 kprintf("Low SE Term Enabled, ");
683 if ((adw
->features
& ADW_ULTRA2
) != 0
684 && (term_scsicfg1
& ADW2_SCSI_CFG1_TERM_CTL_LVD
) != 0)
685 kprintf("LVD Term Enabled, ");
688 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
689 * set 'scsicfg1'. The TERM_POL bit does not need to be
690 * referenced, because the hardware internally inverts
691 * the Termination High and Low bits if TERM_POL is set.
693 if ((adw
->features
& ADW_ULTRA2
) != 0) {
694 term_scsicfg1
= ~term_scsicfg1
;
695 term_scsicfg1
&= ADW_SCSI_CFG1_TERM_CTL_MASK
696 | ADW2_SCSI_CFG1_TERM_CTL_LVD
;
697 scsicfg1
&= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
698 |ADW2_SCSI_CFG1_TERM_CTL_LVD
699 |ADW_SCSI_CFG1_BIG_ENDIAN
700 |ADW_SCSI_CFG1_TERM_POL
701 |ADW2_SCSI_CFG1_DEV_DETECT
);
702 scsicfg1
|= term_scsicfg1
;
704 term_scsicfg1
= ~term_scsicfg1
& ADW_SCSI_CFG1_TERM_CTL_MASK
;
705 scsicfg1
&= ~ADW_SCSI_CFG1_TERM_CTL_MASK
;
706 scsicfg1
|= term_scsicfg1
| ADW_SCSI_CFG1_TERM_CTL_MANUAL
;
707 scsicfg1
|= ADW_SCSI_CFG1_FLTR_DISABLE
;
711 * Set SCSI_CFG1 Microcode Default Value
713 * The microcode will set the SCSI_CFG1 register using this value
714 * after it is started below.
716 adw_lram_write_16(adw
, ADW_MC_DEFAULT_SCSI_CFG1
, scsicfg1
);
719 * Only accept selections on our initiator target id.
720 * This may change in target mode scenarios...
722 adw_lram_write_16(adw
, ADW_MC_DEFAULT_SEL_MASK
,
723 (0x01 << adw
->initiator_id
));
726 * Tell the microcode where it can find our
727 * Initiator Command Queue (ICQ). It is
728 * currently empty hence the "stopper" address.
730 adw
->commandq
= adw
->free_carriers
;
731 adw
->free_carriers
= carrierbotov(adw
, adw
->commandq
->next_ba
);
732 adw
->commandq
->next_ba
= ADW_CQ_STOPPER
;
733 adw_lram_write_32(adw
, ADW_MC_ICQ
, adw
->commandq
->carr_ba
);
736 * Tell the microcode where it can find our
737 * Initiator Response Queue (IRQ). It too
738 * is currently empty.
740 adw
->responseq
= adw
->free_carriers
;
741 adw
->free_carriers
= carrierbotov(adw
, adw
->responseq
->next_ba
);
742 adw
->responseq
->next_ba
= ADW_CQ_STOPPER
;
743 adw_lram_write_32(adw
, ADW_MC_IRQ
, adw
->responseq
->carr_ba
);
745 adw_outb(adw
, ADW_INTR_ENABLES
,
746 ADW_INTR_ENABLE_HOST_INTR
|ADW_INTR_ENABLE_GLOBAL_INTR
);
748 adw_outw(adw
, ADW_PC
, adw_lram_read_16(adw
, ADW_MC_CODE_BEGIN_ADDR
));
754 adw_set_user_sdtr(struct adw_softc
*adw
, u_int tid
, u_int mc_sdtr
)
756 adw
->user_sdtr
[ADW_TARGET_GROUP(tid
)] &= ~ADW_TARGET_GROUP_MASK(tid
);
757 adw
->user_sdtr
[ADW_TARGET_GROUP(tid
)] |=
758 mc_sdtr
<< ADW_TARGET_GROUP_SHIFT(tid
);
762 adw_get_user_sdtr(struct adw_softc
*adw
, u_int tid
)
766 mc_sdtr
= adw
->user_sdtr
[ADW_TARGET_GROUP(tid
)];
767 mc_sdtr
&= ADW_TARGET_GROUP_MASK(tid
);
768 mc_sdtr
>>= ADW_TARGET_GROUP_SHIFT(tid
);
773 adw_set_chip_sdtr(struct adw_softc
*adw
, u_int tid
, u_int sdtr
)
775 u_int mc_sdtr_offset
;
778 mc_sdtr_offset
= ADW_MC_SDTR_SPEED1
;
779 mc_sdtr_offset
+= ADW_TARGET_GROUP(tid
) * 2;
780 mc_sdtr
= adw_lram_read_16(adw
, mc_sdtr_offset
);
781 mc_sdtr
&= ~ADW_TARGET_GROUP_MASK(tid
);
782 mc_sdtr
|= sdtr
<< ADW_TARGET_GROUP_SHIFT(tid
);
783 adw_lram_write_16(adw
, mc_sdtr_offset
, mc_sdtr
);
787 adw_get_chip_sdtr(struct adw_softc
*adw
, u_int tid
)
789 u_int mc_sdtr_offset
;
792 mc_sdtr_offset
= ADW_MC_SDTR_SPEED1
;
793 mc_sdtr_offset
+= ADW_TARGET_GROUP(tid
) * 2;
794 mc_sdtr
= adw_lram_read_16(adw
, mc_sdtr_offset
);
795 mc_sdtr
&= ADW_TARGET_GROUP_MASK(tid
);
796 mc_sdtr
>>= ADW_TARGET_GROUP_SHIFT(tid
);
801 adw_find_sdtr(struct adw_softc
*adw
, u_int period
)
806 if ((adw
->features
& ADW_DT
) == 0)
807 i
= ADW_MC_SDTR_OFFSET_ULTRA2
;
808 if ((adw
->features
& ADW_ULTRA2
) == 0)
809 i
= ADW_MC_SDTR_OFFSET_ULTRA
;
811 return ADW_MC_SDTR_ASYNC
;
813 for (; i
< adw_num_syncrates
; i
++) {
814 if (period
<= adw_syncrates
[i
].period
)
815 return (adw_syncrates
[i
].mc_sdtr
);
817 return ADW_MC_SDTR_ASYNC
;
821 adw_find_period(struct adw_softc
*adw
, u_int mc_sdtr
)
825 for (i
= 0; i
< adw_num_syncrates
; i
++) {
826 if (mc_sdtr
== adw_syncrates
[i
].mc_sdtr
)
829 return (adw_syncrates
[i
].period
);
833 adw_hshk_cfg_period_factor(u_int tinfo
)
835 tinfo
&= ADW_HSHK_CFG_RATE_MASK
;
836 tinfo
>>= ADW_HSHK_CFG_RATE_SHIFT
;
840 else if (tinfo
== 0x10)
844 return (((tinfo
* 25) + 50) / 4);
848 * Send an idle command to the chip and wait for completion.
850 adw_idle_cmd_status_t
851 adw_idle_cmd_send(struct adw_softc
*adw
, adw_idle_cmd_t cmd
, u_int parameter
)
854 adw_idle_cmd_status_t status
;
859 * Clear the idle command status which is set by the microcode
860 * to a non-zero value to indicate when the command is completed.
862 adw_lram_write_16(adw
, ADW_MC_IDLE_CMD_STATUS
, 0);
865 * Write the idle command value after the idle command parameter
866 * has been written to avoid a race condition. If the order is not
867 * followed, the microcode may process the idle command before the
868 * parameters have been written to LRAM.
870 adw_lram_write_32(adw
, ADW_MC_IDLE_CMD_PARAMETER
, parameter
);
871 adw_lram_write_16(adw
, ADW_MC_IDLE_CMD
, cmd
);
874 * Tickle the RISC to tell it to process the idle command.
876 adw_tickle_risc(adw
, ADW_TICKLE_B
);
878 /* Wait for up to 10 seconds for the command to complete */
881 status
= adw_lram_read_16(adw
, ADW_MC_IDLE_CMD_STATUS
);
888 panic("%s: Idle Command Timed Out!", adw_name(adw
));