sys/dev/disk/advansys/adv_pci.c

   1 /*
   2  * Device probe and attach routines for the following
   3  * Advanced Systems Inc. SCSI controllers:
   4  *
   5  *   Connectivity Products:
   6  *      ABP902/3902     - Bus-Master PCI (16 CDB)
   7  *      ABP3905         - Bus-Master PCI (16 CDB)
   8  *      ABP915          - Bus-Master PCI (16 CDB)
   9  *      ABP920          - Bus-Master PCI (16 CDB)
  10  *      ABP3922         - Bus-Master PCI (16 CDB)
  11  *      ABP3925         - Bus-Master PCI (16 CDB)
  12  *      ABP930          - Bus-Master PCI (16 CDB) *
  13  *      ABP930U         - Bus-Master PCI Ultra (16 CDB)
  14  *      ABP930UA        - Bus-Master PCI Ultra (16 CDB)
  15  *      ABP960          - Bus-Master PCI MAC/PC (16 CDB) **
  16  *      ABP960U         - Bus-Master PCI MAC/PC (16 CDB) **
  17  *
  18  *   Single Channel Products:
  19  *      ABP940          - Bus-Master PCI (240 CDB)
  20  *      ABP940U         - Bus-Master PCI Ultra (240 CDB)
  21  *      ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
  22  *      ABP3960UA       - Bus-Master PCI MAC/PC (240 CDB)
  23  *      ABP970          - Bus-Master PCI MAC/PC (240 CDB)
  24  *      ABP970U         - Bus-Master PCI MAC/PC Ultra (240 CDB)
  25  *
  26  *   Dual Channel Products:
  27  *      ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
  28  *      ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
  29  *      ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
  30  *      ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
  31  *
  32  *   Footnotes:
  33  *       * This board has been sold by SIIG as the Fast SCSI Pro PCI.
  34  *      ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
  35  *
  36  * Copyright (c) 1997 Justin Gibbs.
  37  * All rights reserved.
  38  *
  39  * Redistribution and use in source and binary forms, with or without
  40  * modification, are permitted provided that the following conditions
  41  * are met:
  42  * 1. Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions, and the following disclaimer,
  44  *    without modification.
  45  * 2. The name of the author may not be used to endorse or promote products
  46  *    derived from this software without specific prior written permission.
  47  *
  48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  49  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  50  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  51  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  52  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  53  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  54  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  55  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  56  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  57  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  58  * SUCH DAMAGE.
  59  *
  60  * $FreeBSD: src/sys/dev/advansys/adv_pci.c,v 1.11.2.3 2001/06/02 04:38:10 nyan Exp $
  61  */
  62
  63 #include <sys/param.h>
  64 #include <sys/systm.h>
  65 #include <sys/kernel.h>
  66 #include <sys/bus.h>
  67 #include <sys/rman.h>
  68
  69 #include <bus/pci/pcireg.h>
  70 #include <bus/pci/pcivar.h>
  71
  72 #include "advansys.h"
  73
  74 #define PCI_BASEADR0    PCIR_MAPS               /* I/O Address */
  75 #define PCI_BASEADR1    PCIR_MAPS + 4           /* Mem I/O Address */
  76
  77 #define PCI_DEVICE_ID_ADVANSYS_1200A    0x110010CD
  78 #define PCI_DEVICE_ID_ADVANSYS_1200B    0x120010CD
  79 #define PCI_DEVICE_ID_ADVANSYS_3000     0x130010CD
  80 #define PCI_DEVICE_REV_ADVANSYS_3150    0x02
  81 #define PCI_DEVICE_REV_ADVANSYS_3050    0x03
  82
  83 #define ADV_PCI_MAX_DMA_ADDR    (0xFFFFFFFFL)
  84 #define ADV_PCI_MAX_DMA_COUNT   (0xFFFFFFFFL)
  85
  86 static int adv_pci_probe(device_t);
  87 static int adv_pci_attach(device_t);
  88
  89 /*
  90  * The overrun buffer shared amongst all PCI adapters.
  91  */
  92 static  u_int8_t*       overrun_buf;
  93 static  bus_dma_tag_t   overrun_dmat;
  94 static  bus_dmamap_t    overrun_dmamap;
  95 static  bus_addr_t      overrun_physbase;
  96
  97 static int
  98 adv_pci_probe(device_t dev)
  99 {
 100         int     rev = pci_get_revid(dev);
 101
 102         switch (pci_get_devid(dev)) {
 103         case PCI_DEVICE_ID_ADVANSYS_1200A:
 104                 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
 105                 return 0;
 106         case PCI_DEVICE_ID_ADVANSYS_1200B:
 107                 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
 108                 return 0;
 109         case PCI_DEVICE_ID_ADVANSYS_3000:
 110                 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
 111                         device_set_desc(dev,
 112                                         "AdvanSys ASC3150 SCSI controller");
 113                         return 0;
 114                 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
 115                         device_set_desc(dev,
 116                                         "AdvanSys ASC3030/50 SCSI controller");
 117                         return 0;
 118                 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
 119                         device_set_desc(dev, "Unknown AdvanSys controller");
 120                         return 0;
 121                 }
 122                 break;
 123         default:
 124                 break;
 125         }
 126         return ENXIO;
 127 }
 128
 129 static int
 130 adv_pci_attach(device_t dev)
 131 {
 132         struct          adv_softc *adv;
 133         u_int32_t       id;
 134         u_int32_t       command;
 135         int             error, rid, irqrid;
 136         void            *ih;
 137         struct resource *iores, *irqres;
 138
 139         /*
 140          * Determine the chip version.
 141          */
 142         id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
 143         command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
 144
 145         /*
 146          * These cards do not allow memory mapped accesses, so we must
 147          * ensure that I/O accesses are available or we won't be able
 148          * to talk to them.
 149          */
 150         if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
 151          != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
 152                 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
 153                 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
 154         }
 155
 156         /*
 157          * Early chips can't handle non-zero latency timer settings.
 158          */
 159         if (id == PCI_DEVICE_ID_ADVANSYS_1200A
 160          || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
 161                 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
 162         }
 163
 164         rid = PCI_BASEADR0;
 165         iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
 166                                    RF_ACTIVE);
 167         if (iores == NULL)
 168                 return ENXIO;
 169
 170         if (adv_find_signature(rman_get_bustag(iores),
 171                                rman_get_bushandle(iores)) == 0) {
 172                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 173                 return ENXIO;
 174         }
 175
 176         adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
 177         if (adv == NULL) {
 178                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 179                 return ENXIO;
 180         }
 181
 182         /* Allocate a dmatag for our transfer DMA maps */
 183         /* XXX Should be a child of the PCI bus dma tag */
 184         error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
 185                                    /*boundary*/0,
 186                                    /*lowaddr*/ADV_PCI_MAX_DMA_ADDR,
 187                                    /*highaddr*/BUS_SPACE_MAXADDR,
 188                                    /*filter*/NULL, /*filterarg*/NULL,
 189                                    /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
 190                                    /*nsegments*/BUS_SPACE_UNRESTRICTED,
 191                                    /*maxsegsz*/ADV_PCI_MAX_DMA_COUNT,
 192                                    /*flags*/0,
 193                                    &adv->parent_dmat);
 194
 195         if (error != 0) {
 196                 kprintf("%s: Could not allocate DMA tag - error %d\n",
 197                        adv_name(adv), error);
 198                 adv_free(adv);
 199                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 200                 return ENXIO;
 201         }
 202
 203         adv->init_level++;
 204
 205         if (overrun_buf == NULL) {
 206                 /* Need to allocate our overrun buffer */
 207                 if (bus_dma_tag_create(adv->parent_dmat,
 208                                        /*alignment*/8, /*boundary*/0,
 209                                        ADV_PCI_MAX_DMA_ADDR, BUS_SPACE_MAXADDR,
 210                                        /*filter*/NULL, /*filterarg*/NULL,
 211                                        ADV_OVERRUN_BSIZE, /*nsegments*/1,
 212                                        BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
 213                                        &overrun_dmat) != 0) {
 214                         bus_dma_tag_destroy(adv->parent_dmat);
 215                         adv_free(adv);
 216                         bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 217                         return ENXIO;
 218                 }
 219                 if (bus_dmamem_alloc(overrun_dmat,
 220                                      (void *)&overrun_buf,
 221                                      BUS_DMA_NOWAIT,
 222                                      &overrun_dmamap) != 0) {
 223                         bus_dma_tag_destroy(overrun_dmat);
 224                         bus_dma_tag_destroy(adv->parent_dmat);
 225                         adv_free(adv);
 226                         bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 227                         return ENXIO;
 228                 }
 229                 /* And permanently map it in */
 230                 bus_dmamap_load(overrun_dmat, overrun_dmamap,
 231                                 overrun_buf, ADV_OVERRUN_BSIZE,
 232                                 adv_map, &overrun_physbase,
 233                                 /*flags*/0);
 234         }
 235
 236         adv->overrun_physbase = overrun_physbase;
 237
 238         /*
 239          * Stop the chip.
 240          */
 241         ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
 242         ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
 243
 244         adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
 245         adv->type = ADV_PCI;
 246
 247         /*
 248          * Setup active negation and signal filtering.
 249          */
 250         {
 251                 u_int8_t extra_cfg;
 252
 253                 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
 254                         adv->type |= ADV_ULTRA;
 255                 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
 256                         extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
 257                 else
 258                         extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
 259                 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
 260         }
 261
 262         if (adv_init(adv) != 0) {
 263                 adv_free(adv);
 264                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 265                 return ENXIO;
 266         }
 267
 268         adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
 269         adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
 270
 271 #if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT
 272         {
 273                 u_int16_t config_msw;
 274
 275                 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
 276                 config_msw &= 0xFFC0;
 277                 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
 278         }
 279 #endif
 280
 281         if (id == PCI_DEVICE_ID_ADVANSYS_1200A
 282          || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
 283                 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
 284                 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
 285                 adv->fix_asyn_xfer = ~0;
 286         }
 287
 288         irqrid = 0;
 289         irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1,
 290                                     RF_SHAREABLE | RF_ACTIVE);
 291         if (irqres == NULL ||
 292             bus_setup_intr(dev, irqres, 0, adv_intr, adv, &ih, NULL)) {
 293                 adv_free(adv);
 294                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
 295                 return ENXIO;
 296         }
 297
 298         adv_attach(adv);
 299         return 0;
 300 }
 301
 302 static device_method_t adv_pci_methods[] = {
 303         /* Device interface */
 304         DEVMETHOD(device_probe,         adv_pci_probe),
 305         DEVMETHOD(device_attach,        adv_pci_attach),
 306         DEVMETHOD_END
 307 };
 308
 309 static driver_t adv_pci_driver = {
 310         "adv", adv_pci_methods, sizeof(struct adv_softc)
 311 };
 312
 313 static devclass_t adv_pci_devclass;
 314 DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, NULL, NULL);