sys/cpu/i386/include/bus_dma.h

   1 /*-
   2  * Copyright (c) KATO Takenori, 1999.
   3  *
   4  * All rights reserved.  Unpublished rights reserved under the copyright
   5  * laws of Japan.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer as
  13  *    the first lines of this file unmodified.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * $FreeBSD: src/sys/i386/include/bus.h,v 1.7.2.2 2002/03/03 05:42:50 nyan Exp $
  32  * $DragonFly: src/sys/cpu/i386/include/bus_dma.h,v 1.8 2006/11/07 06:43:22 dillon Exp $
  33  */
  34
  35 #ifndef _CPU_BUS_DMA_H_
  36 #define _CPU_BUS_DMA_H_
  37
  38 #ifndef _CPU_BUS_AT386_H_
  39 #include <cpu/bus_at386.h>
  40 #endif
  41
  42 /*
  43  * Stream accesses are the same as normal accesses on i386; there are no
  44  * supported bus systems with an endianess different from the host one.
  45  */
  46 #define bus_space_read_stream_1(t, h, o)        bus_space_read_1((t), (h), (o))
  47 #define bus_space_read_stream_2(t, h, o)        bus_space_read_2((t), (h), (o))
  48 #define bus_space_read_stream_4(t, h, o)        bus_space_read_4((t), (h), (o))
  49
  50 #define bus_space_read_multi_stream_1(t, h, o, a, c) \
  51         bus_space_read_multi_1((t), (h), (o), (a), (c))
  52 #define bus_space_read_multi_stream_2(t, h, o, a, c) \
  53         bus_space_read_multi_2((t), (h), (o), (a), (c))
  54 #define bus_space_read_multi_stream_4(t, h, o, a, c) \
  55         bus_space_read_multi_4((t), (h), (o), (a), (c))
  56
  57 #define bus_space_write_stream_1(t, h, o, v) \
  58         bus_space_write_1((t), (h), (o), (v))
  59 #define bus_space_write_stream_2(t, h, o, v) \
  60         bus_space_write_2((t), (h), (o), (v))
  61 #define bus_space_write_stream_4(t, h, o, v) \
  62         bus_space_write_4((t), (h), (o), (v))
  63
  64 #define bus_space_write_multi_stream_1(t, h, o, a, c) \
  65         bus_space_write_multi_1((t), (h), (o), (a), (c))
  66 #define bus_space_write_multi_stream_2(t, h, o, a, c) \
  67         bus_space_write_multi_2((t), (h), (o), (a), (c))
  68 #define bus_space_write_multi_stream_4(t, h, o, a, c) \
  69         bus_space_write_multi_4((t), (h), (o), (a), (c))
  70
  71 #define bus_space_set_multi_stream_1(t, h, o, v, c) \
  72         bus_space_set_multi_1((t), (h), (o), (v), (c))
  73 #define bus_space_set_multi_stream_2(t, h, o, v, c) \
  74         bus_space_set_multi_2((t), (h), (o), (v), (c))
  75 #define bus_space_set_multi_stream_4(t, h, o, v, c) \
  76         bus_space_set_multi_4((t), (h), (o), (v), (c))
  77
  78 #define bus_space_read_region_stream_1(t, h, o, a, c) \
  79         bus_space_read_region_1((t), (h), (o), (a), (c))
  80 #define bus_space_read_region_stream_2(t, h, o, a, c) \
  81         bus_space_read_region_2((t), (h), (o), (a), (c))
  82 #define bus_space_read_region_stream_4(t, h, o, a, c) \
  83         bus_space_read_region_4((t), (h), (o), (a), (c))
  84
  85 #define bus_space_write_region_stream_1(t, h, o, a, c) \
  86         bus_space_write_region_1((t), (h), (o), (a), (c))
  87 #define bus_space_write_region_stream_2(t, h, o, a, c) \
  88         bus_space_write_region_2((t), (h), (o), (a), (c))
  89 #define bus_space_write_region_stream_4(t, h, o, a, c) \
  90         bus_space_write_region_4((t), (h), (o), (a), (c))
  91
  92 #define bus_space_set_region_stream_1(t, h, o, v, c) \
  93         bus_space_set_region_1((t), (h), (o), (v), (c))
  94 #define bus_space_set_region_stream_2(t, h, o, v, c) \
  95         bus_space_set_region_2((t), (h), (o), (v), (c))
  96 #define bus_space_set_region_stream_4(t, h, o, v, c) \
  97         bus_space_set_region_4((t), (h), (o), (v), (c))
  98
  99 #define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \
 100         bus_space_copy_region_1((t), (h1), (o1), (h2), (o2), (c))
 101 #define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \
 102         bus_space_copy_region_2((t), (h1), (o1), (h2), (o2), (c))
 103 #define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \
 104         bus_space_copy_region_4((t), (h1), (o1), (h2), (o2), (c))
 105
 106 #endif /* _CPU_BUS_DMA_H_ */