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drm/i915/gem: Switch to the Linux scatterlist API
[dragonfly.git] / sys / dev / drm / i915 / intel_ringbuffer.c
blob1d03ff9e3f72179e75aaffea0b7c782c9c5938fc
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117 }
118
119 static int
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
122 u32 flush_domains)
123 {
124 struct drm_device *dev = ring->dev;
125 u32 cmd;
126 int ret;
127
128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
161
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
165
166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
169
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
173
174 return 0;
175 }
176
177 /**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214 static int
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
216 {
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247 }
248
249 static int
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
252 {
253 u32 flags = 0;
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
255 int ret;
256
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
273 flags |= PIPE_CONTROL_CS_STALL;
274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
286 }
287
288 ret = intel_ring_begin(ring, 4);
289 if (ret)
290 return ret;
291
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
297
298 return 0;
299 }
300
301 static int
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
303 {
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318 }
319
320 static int
321 gen7_render_ring_flush(struct intel_engine_cs *ring,
322 u32 invalidate_domains, u32 flush_domains)
323 {
324 u32 flags = 0;
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
326 int ret;
327
328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
345 flags |= PIPE_CONTROL_FLUSH_ENABLE;
346 }
347 if (invalidate_domains) {
348 flags |= PIPE_CONTROL_TLB_INVALIDATE;
349 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
355 /*
356 * TLB invalidate requires a post-sync write.
357 */
358 flags |= PIPE_CONTROL_QW_WRITE;
359 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
360
361 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
362
363 /* Workaround: we must issue a pipe_control with CS-stall bit
364 * set before a pipe_control command that has the state cache
365 * invalidate bit set. */
366 gen7_render_ring_cs_stall_wa(ring);
367 }
368
369 ret = intel_ring_begin(ring, 4);
370 if (ret)
371 return ret;
372
373 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
374 intel_ring_emit(ring, flags);
375 intel_ring_emit(ring, scratch_addr);
376 intel_ring_emit(ring, 0);
377 intel_ring_advance(ring);
378
379 return 0;
380 }
381
382 static int
383 gen8_emit_pipe_control(struct intel_engine_cs *ring,
384 u32 flags, u32 scratch_addr)
385 {
386 int ret;
387
388 ret = intel_ring_begin(ring, 6);
389 if (ret)
390 return ret;
391
392 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
393 intel_ring_emit(ring, flags);
394 intel_ring_emit(ring, scratch_addr);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_emit(ring, 0);
398 intel_ring_advance(ring);
399
400 return 0;
401 }
402
403 static int
404 gen8_render_ring_flush(struct intel_engine_cs *ring,
405 u32 invalidate_domains, u32 flush_domains)
406 {
407 u32 flags = 0;
408 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
409 int ret;
410
411 flags |= PIPE_CONTROL_CS_STALL;
412
413 if (flush_domains) {
414 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
415 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
416 flags |= PIPE_CONTROL_FLUSH_ENABLE;
417 }
418 if (invalidate_domains) {
419 flags |= PIPE_CONTROL_TLB_INVALIDATE;
420 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
424 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_QW_WRITE;
426 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
427
428 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
429 ret = gen8_emit_pipe_control(ring,
430 PIPE_CONTROL_CS_STALL |
431 PIPE_CONTROL_STALL_AT_SCOREBOARD,
432 0);
433 if (ret)
434 return ret;
435 }
436
437 return gen8_emit_pipe_control(ring, flags, scratch_addr);
438 }
439
440 static void ring_write_tail(struct intel_engine_cs *ring,
441 u32 value)
442 {
443 struct drm_i915_private *dev_priv = ring->dev->dev_private;
444 I915_WRITE_TAIL(ring, value);
445 }
446
447 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
448 {
449 struct drm_i915_private *dev_priv = ring->dev->dev_private;
450 u64 acthd;
451
452 if (INTEL_INFO(ring->dev)->gen >= 8)
453 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
454 RING_ACTHD_UDW(ring->mmio_base));
455 else if (INTEL_INFO(ring->dev)->gen >= 4)
456 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
457 else
458 acthd = I915_READ(ACTHD);
459
460 return acthd;
461 }
462
463 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
464 {
465 struct drm_i915_private *dev_priv = ring->dev->dev_private;
466 u32 addr;
467
468 addr = dev_priv->status_page_dmah->busaddr;
469 if (INTEL_INFO(ring->dev)->gen >= 4)
470 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
471 I915_WRITE(HWS_PGA, addr);
472 }
473
474 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
475 {
476 struct drm_device *dev = ring->dev;
477 struct drm_i915_private *dev_priv = ring->dev->dev_private;
478 u32 mmio = 0;
479
480 /* The ring status page addresses are no longer next to the rest of
481 * the ring registers as of gen7.
482 */
483 if (IS_GEN7(dev)) {
484 switch (ring->id) {
485 case RCS:
486 mmio = RENDER_HWS_PGA_GEN7;
487 break;
488 case BCS:
489 mmio = BLT_HWS_PGA_GEN7;
490 break;
491 /*
492 * VCS2 actually doesn't exist on Gen7. Only shut up
493 * gcc switch check warning
494 */
495 case VCS2:
496 case VCS:
497 mmio = BSD_HWS_PGA_GEN7;
498 break;
499 case VECS:
500 mmio = VEBOX_HWS_PGA_GEN7;
501 break;
502 }
503 } else if (IS_GEN6(ring->dev)) {
504 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
505 } else {
506 /* XXX: gen8 returns to sanity */
507 mmio = RING_HWS_PGA(ring->mmio_base);
508 }
509
510 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
511 POSTING_READ(mmio);
512
513 /*
514 * Flush the TLB for this page
515 *
516 * FIXME: These two bits have disappeared on gen8, so a question
517 * arises: do we still need this and if so how should we go about
518 * invalidating the TLB?
519 */
520 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
521 u32 reg = RING_INSTPM(ring->mmio_base);
522
523 /* ring should be idle before issuing a sync flush*/
524 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
525
526 I915_WRITE(reg,
527 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
528 INSTPM_SYNC_FLUSH));
529 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
530 1000))
531 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
532 ring->name);
533 }
534 }
535
536 static bool stop_ring(struct intel_engine_cs *ring)
537 {
538 struct drm_i915_private *dev_priv = to_i915(ring->dev);
539
540 if (!IS_GEN2(ring->dev)) {
541 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
542 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
543 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
544 /* Sometimes we observe that the idle flag is not
545 * set even though the ring is empty. So double
546 * check before giving up.
547 */
548 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
549 return false;
550 }
551 }
552
553 I915_WRITE_CTL(ring, 0);
554 I915_WRITE_HEAD(ring, 0);
555 ring->write_tail(ring, 0);
556
557 if (!IS_GEN2(ring->dev)) {
558 (void)I915_READ_CTL(ring);
559 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
560 }
561
562 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
563 }
564
565 static int init_ring_common(struct intel_engine_cs *ring)
566 {
567 struct drm_device *dev = ring->dev;
568 struct drm_i915_private *dev_priv = dev->dev_private;
569 struct intel_ringbuffer *ringbuf = ring->buffer;
570 struct drm_i915_gem_object *obj = ringbuf->obj;
571 int ret = 0;
572
573 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
574
575 if (!stop_ring(ring)) {
576 /* G45 ring initialization often fails to reset head to zero */
577 DRM_DEBUG_KMS("%s head not reset to zero "
578 "ctl %08x head %08x tail %08x start %08x\n",
579 ring->name,
580 I915_READ_CTL(ring),
581 I915_READ_HEAD(ring),
582 I915_READ_TAIL(ring),
583 I915_READ_START(ring));
584
585 if (!stop_ring(ring)) {
586 DRM_ERROR("failed to set %s head to zero "
587 "ctl %08x head %08x tail %08x start %08x\n",
588 ring->name,
589 I915_READ_CTL(ring),
590 I915_READ_HEAD(ring),
591 I915_READ_TAIL(ring),
592 I915_READ_START(ring));
593 ret = -EIO;
594 goto out;
595 }
596 }
597
598 if (I915_NEED_GFX_HWS(dev))
599 intel_ring_setup_status_page(ring);
600 else
601 ring_setup_phys_status_page(ring);
602
603 /* Enforce ordering by reading HEAD register back */
604 I915_READ_HEAD(ring);
605
606 /* Initialize the ring. This must happen _after_ we've cleared the ring
607 * registers with the above sequence (the readback of the HEAD registers
608 * also enforces ordering), otherwise the hw might lose the new ring
609 * register values. */
610 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
611
612 /* WaClearRingBufHeadRegAtInit:ctg,elk */
613 if (I915_READ_HEAD(ring))
614 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
615 ring->name, I915_READ_HEAD(ring));
616 I915_WRITE_HEAD(ring, 0);
617 (void)I915_READ_HEAD(ring);
618
619 I915_WRITE_CTL(ring,
620 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
621 | RING_VALID);
622
623 /* If the head is still not zero, the ring is dead */
624 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
625 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
626 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
627 DRM_ERROR("%s initialization failed "
628 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
629 ring->name,
630 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
631 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
632 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
633 ret = -EIO;
634 goto out;
635 }
636
637 ringbuf->last_retired_head = -1;
638 ringbuf->head = I915_READ_HEAD(ring);
639 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
640 intel_ring_update_space(ringbuf);
641
642 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
643
644 out:
645 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
646
647 return ret;
648 }
649
650 void
651 intel_fini_pipe_control(struct intel_engine_cs *ring)
652 {
653 struct drm_device *dev = ring->dev;
654
655 if (ring->scratch.obj == NULL)
656 return;
657
658 if (INTEL_INFO(dev)->gen >= 5) {
659 kunmap(sg_page(ring->scratch.obj->pages->sgl));
660 i915_gem_object_ggtt_unpin(ring->scratch.obj);
661 }
662
663 drm_gem_object_unreference(&ring->scratch.obj->base);
664 ring->scratch.obj = NULL;
665 }
666
667 int
668 intel_init_pipe_control(struct intel_engine_cs *ring)
669 {
670 int ret;
671
672 WARN_ON(ring->scratch.obj);
673
674 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
675 if (ring->scratch.obj == NULL) {
676 DRM_ERROR("Failed to allocate seqno page\n");
677 ret = -ENOMEM;
678 goto err;
679 }
680
681 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
682 if (ret)
683 goto err_unref;
684
685 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
686 if (ret)
687 goto err_unref;
688
689 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
690 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
691 if (ring->scratch.cpu_page == NULL) {
692 ret = -ENOMEM;
693 goto err_unpin;
694 }
695
696 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
697 ring->name, ring->scratch.gtt_offset);
698 return 0;
699
700 err_unpin:
701 i915_gem_object_ggtt_unpin(ring->scratch.obj);
702 err_unref:
703 drm_gem_object_unreference(&ring->scratch.obj->base);
704 err:
705 return ret;
706 }
707
708 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
709 struct intel_context *ctx)
710 {
711 int ret, i;
712 struct drm_device *dev = ring->dev;
713 struct drm_i915_private *dev_priv = dev->dev_private;
714 struct i915_workarounds *w = &dev_priv->workarounds;
715
716 if (WARN_ON_ONCE(w->count == 0))
717 return 0;
718
719 ring->gpu_caches_dirty = true;
720 ret = intel_ring_flush_all_caches(ring);
721 if (ret)
722 return ret;
723
724 ret = intel_ring_begin(ring, (w->count * 2 + 2));
725 if (ret)
726 return ret;
727
728 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
729 for (i = 0; i < w->count; i++) {
730 intel_ring_emit(ring, w->reg[i].addr);
731 intel_ring_emit(ring, w->reg[i].value);
732 }
733 intel_ring_emit(ring, MI_NOOP);
734
735 intel_ring_advance(ring);
736
737 ring->gpu_caches_dirty = true;
738 ret = intel_ring_flush_all_caches(ring);
739 if (ret)
740 return ret;
741
742 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
743
744 return 0;
745 }
746
747 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
748 struct intel_context *ctx)
749 {
750 int ret;
751
752 ret = intel_ring_workarounds_emit(ring, ctx);
753 if (ret != 0)
754 return ret;
755
756 ret = i915_gem_render_state_init(ring);
757 if (ret)
758 DRM_ERROR("init render state: %d\n", ret);
759
760 return ret;
761 }
762
763 static int wa_add(struct drm_i915_private *dev_priv,
764 const u32 addr, const u32 mask, const u32 val)
765 {
766 const u32 idx = dev_priv->workarounds.count;
767
768 if (WARN_ON(idx >= I915_MAX_WA_REGS))
769 return -ENOSPC;
770
771 dev_priv->workarounds.reg[idx].addr = addr;
772 dev_priv->workarounds.reg[idx].value = val;
773 dev_priv->workarounds.reg[idx].mask = mask;
774
775 dev_priv->workarounds.count++;
776
777 return 0;
778 }
779
780 #define WA_REG(addr, mask, val) { \
781 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
782 if (r) \
783 return r; \
784 }
785
786 #define WA_SET_BIT_MASKED(addr, mask) \
787 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
788
789 #define WA_CLR_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
791
792 #define WA_SET_FIELD_MASKED(addr, mask, value) \
793 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
794
795 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
796 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
797
798 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
799
800 static int bdw_init_workarounds(struct intel_engine_cs *ring)
801 {
802 struct drm_device *dev = ring->dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804
805 /* WaDisablePartialInstShootdown:bdw */
806 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
807 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
808 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
809 STALL_DOP_GATING_DISABLE);
810
811 /* WaDisableDopClockGating:bdw */
812 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
813 DOP_CLOCK_GATING_DISABLE);
814
815 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
816 GEN8_SAMPLER_POWER_BYPASS_DIS);
817
818 /* Use Force Non-Coherent whenever executing a 3D context. This is a
819 * workaround for for a possible hang in the unlikely event a TLB
820 * invalidation occurs during a PSD flush.
821 */
822 WA_SET_BIT_MASKED(HDC_CHICKEN0,
823 /* WaForceEnableNonCoherent:bdw */
824 HDC_FORCE_NON_COHERENT |
825 /* WaForceContextSaveRestoreNonCoherent:bdw */
826 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
827 /* WaHdcDisableFetchWhenMasked:bdw */
828 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
829 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
830 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
831
832 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
833 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
834 * polygons in the same 8x4 pixel/sample area to be processed without
835 * stalling waiting for the earlier ones to write to Hierarchical Z
836 * buffer."
837 *
838 * This optimization is off by default for Broadwell; turn it on.
839 */
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
841
842 /* Wa4x4STCOptimizationDisable:bdw */
843 WA_SET_BIT_MASKED(CACHE_MODE_1,
844 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
845
846 /*
847 * BSpec recommends 8x4 when MSAA is used,
848 * however in practice 16x4 seems fastest.
849 *
850 * Note that PS/WM thread counts depend on the WIZ hashing
851 * disable bit, which we don't touch here, but it's good
852 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
853 */
854 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
855 GEN6_WIZ_HASHING_MASK,
856 GEN6_WIZ_HASHING_16x4);
857
858 return 0;
859 }
860
861 static int chv_init_workarounds(struct intel_engine_cs *ring)
862 {
863 struct drm_device *dev = ring->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 /* WaDisablePartialInstShootdown:chv */
867 /* WaDisableThreadStallDopClockGating:chv */
868 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
869 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
870 STALL_DOP_GATING_DISABLE);
871
872 /* Use Force Non-Coherent whenever executing a 3D context. This is a
873 * workaround for a possible hang in the unlikely event a TLB
874 * invalidation occurs during a PSD flush.
875 */
876 /* WaForceEnableNonCoherent:chv */
877 /* WaHdcDisableFetchWhenMasked:chv */
878 WA_SET_BIT_MASKED(HDC_CHICKEN0,
879 HDC_FORCE_NON_COHERENT |
880 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
881
882 /* According to the CACHE_MODE_0 default value documentation, some
883 * CHV platforms disable this optimization by default. Turn it on.
884 */
885 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
886
887 /* Wa4x4STCOptimizationDisable:chv */
888 WA_SET_BIT_MASKED(CACHE_MODE_1,
889 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
890
891 /* Improve HiZ throughput on CHV. */
892 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
893
894 /*
895 * BSpec recommends 8x4 when MSAA is used,
896 * however in practice 16x4 seems fastest.
897 *
898 * Note that PS/WM thread counts depend on the WIZ hashing
899 * disable bit, which we don't touch here, but it's good
900 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
901 */
902 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
903 GEN6_WIZ_HASHING_MASK,
904 GEN6_WIZ_HASHING_16x4);
905
906 return 0;
907 }
908
909 static int gen9_init_workarounds(struct intel_engine_cs *ring)
910 {
911 struct drm_device *dev = ring->dev;
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 uint32_t tmp;
914
915 /* WaDisablePartialInstShootdown:skl,bxt */
916 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
917 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
918
919 /* Syncing dependencies between camera and graphics:skl,bxt */
920 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
921 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
922
923 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
924 INTEL_REVID(dev) == SKL_REVID_B0)) ||
925 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
926 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
927 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
928 GEN9_DG_MIRROR_FIX_ENABLE);
929 }
930
931 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
932 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
933 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
934 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
935 GEN9_RHWO_OPTIMIZATION_DISABLE);
936 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
937 DISABLE_PIXEL_MASK_CAMMING);
938 }
939
940 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
941 IS_BROXTON(dev)) {
942 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
943 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
944 GEN9_ENABLE_YV12_BUGFIX);
945 }
946
947 /* Wa4x4STCOptimizationDisable:skl,bxt */
948 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
949
950 /* WaDisablePartialResolveInVc:skl,bxt */
951 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
952
953 /* WaCcsTlbPrefetchDisable:skl,bxt */
954 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
955 GEN9_CCS_TLB_PREFETCH_ENABLE);
956
957 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
958 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
959 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
960 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
961 PIXEL_MASK_CAMMING_DISABLE);
962
963 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
964 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
965 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
966 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
967 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
968 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
969
970 return 0;
971 }
972
973 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
974 {
975 struct drm_device *dev = ring->dev;
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 u8 vals[3] = { 0, 0, 0 };
978 unsigned int i;
979
980 for (i = 0; i < 3; i++) {
981 u8 ss;
982
983 /*
984 * Only consider slices where one, and only one, subslice has 7
985 * EUs
986 */
987 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
988 continue;
989
990 /*
991 * subslice_7eu[i] != 0 (because of the check above) and
992 * ss_max == 4 (maximum number of subslices possible per slice)
993 *
994 * -> 0 <= ss <= 3;
995 */
996 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
997 vals[i] = 3 - ss;
998 }
999
1000 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1001 return 0;
1002
1003 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1004 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1005 GEN9_IZ_HASHING_MASK(2) |
1006 GEN9_IZ_HASHING_MASK(1) |
1007 GEN9_IZ_HASHING_MASK(0),
1008 GEN9_IZ_HASHING(2, vals[2]) |
1009 GEN9_IZ_HASHING(1, vals[1]) |
1010 GEN9_IZ_HASHING(0, vals[0]));
1011
1012 return 0;
1013 }
1014
1015
1016 static int skl_init_workarounds(struct intel_engine_cs *ring)
1017 {
1018 struct drm_device *dev = ring->dev;
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020
1021 gen9_init_workarounds(ring);
1022
1023 /* WaDisablePowerCompilerClockGating:skl */
1024 if (INTEL_REVID(dev) == SKL_REVID_B0)
1025 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1026 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1027
1028 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1029 INTEL_REVID(dev) == SKL_REVID_D0)
1030 /* WaBarrierPerformanceFixDisable:skl */
1031 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1032 HDC_FENCE_DEST_SLM_DISABLE |
1033 HDC_BARRIER_PERFORMANCE_DISABLE);
1034
1035 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1036 /*
1037 *Use Force Non-Coherent whenever executing a 3D context. This
1038 * is a workaround for a possible hang in the unlikely event
1039 * a TLB invalidation occurs during a PSD flush.
1040 */
1041 /* WaForceEnableNonCoherent:skl */
1042 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1043 HDC_FORCE_NON_COHERENT);
1044 }
1045
1046 return skl_tune_iz_hashing(ring);
1047 }
1048
1049 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1050 {
1051 struct drm_device *dev = ring->dev;
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053
1054 gen9_init_workarounds(ring);
1055
1056 /* WaDisableThreadStallDopClockGating:bxt */
1057 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1058 STALL_DOP_GATING_DISABLE);
1059
1060 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1061 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1062 WA_SET_BIT_MASKED(
1063 GEN7_HALF_SLICE_CHICKEN1,
1064 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1065 }
1066
1067 return 0;
1068 }
1069
1070 int init_workarounds_ring(struct intel_engine_cs *ring)
1071 {
1072 struct drm_device *dev = ring->dev;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074
1075 WARN_ON(ring->id != RCS);
1076
1077 dev_priv->workarounds.count = 0;
1078
1079 if (IS_BROADWELL(dev))
1080 return bdw_init_workarounds(ring);
1081
1082 if (IS_CHERRYVIEW(dev))
1083 return chv_init_workarounds(ring);
1084
1085 if (IS_SKYLAKE(dev))
1086 return skl_init_workarounds(ring);
1087
1088 if (IS_BROXTON(dev))
1089 return bxt_init_workarounds(ring);
1090
1091 return 0;
1092 }
1093
1094 static int init_render_ring(struct intel_engine_cs *ring)
1095 {
1096 struct drm_device *dev = ring->dev;
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 int ret = init_ring_common(ring);
1099 if (ret)
1100 return ret;
1101
1102 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1103 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1104 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1105
1106 /* We need to disable the AsyncFlip performance optimisations in order
1107 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1108 * programmed to '1' on all products.
1109 *
1110 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1111 */
1112 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1113 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1114
1115 /* Required for the hardware to program scanline values for waiting */
1116 /* WaEnableFlushTlbInvalidationMode:snb */
1117 if (INTEL_INFO(dev)->gen == 6)
1118 I915_WRITE(GFX_MODE,
1119 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1120
1121 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1122 if (IS_GEN7(dev))
1123 I915_WRITE(GFX_MODE_GEN7,
1124 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1125 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1126
1127 if (IS_GEN6(dev)) {
1128 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1129 * "If this bit is set, STCunit will have LRA as replacement
1130 * policy. [...] This bit must be reset. LRA replacement
1131 * policy is not supported."
1132 */
1133 I915_WRITE(CACHE_MODE_0,
1134 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1135 }
1136
1137 if (INTEL_INFO(dev)->gen >= 6)
1138 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1139
1140 if (HAS_L3_DPF(dev))
1141 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1142
1143 return init_workarounds_ring(ring);
1144 }
1145
1146 static void render_ring_cleanup(struct intel_engine_cs *ring)
1147 {
1148 struct drm_device *dev = ring->dev;
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150
1151 if (dev_priv->semaphore_obj) {
1152 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1153 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1154 dev_priv->semaphore_obj = NULL;
1155 }
1156
1157 intel_fini_pipe_control(ring);
1158 }
1159
1160 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1161 unsigned int num_dwords)
1162 {
1163 #define MBOX_UPDATE_DWORDS 8
1164 struct drm_device *dev = signaller->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 struct intel_engine_cs *waiter;
1167 int i, ret, num_rings;
1168
1169 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1170 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1171 #undef MBOX_UPDATE_DWORDS
1172
1173 ret = intel_ring_begin(signaller, num_dwords);
1174 if (ret)
1175 return ret;
1176
1177 for_each_ring(waiter, dev_priv, i) {
1178 u32 seqno;
1179 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1180 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1181 continue;
1182
1183 seqno = i915_gem_request_get_seqno(
1184 signaller->outstanding_lazy_request);
1185 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1186 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1187 PIPE_CONTROL_QW_WRITE |
1188 PIPE_CONTROL_FLUSH_ENABLE);
1189 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1190 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1191 intel_ring_emit(signaller, seqno);
1192 intel_ring_emit(signaller, 0);
1193 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1194 MI_SEMAPHORE_TARGET(waiter->id));
1195 intel_ring_emit(signaller, 0);
1196 }
1197
1198 return 0;
1199 }
1200
1201 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1202 unsigned int num_dwords)
1203 {
1204 #define MBOX_UPDATE_DWORDS 6
1205 struct drm_device *dev = signaller->dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 struct intel_engine_cs *waiter;
1208 int i, ret, num_rings;
1209
1210 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1211 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1212 #undef MBOX_UPDATE_DWORDS
1213
1214 ret = intel_ring_begin(signaller, num_dwords);
1215 if (ret)
1216 return ret;
1217
1218 for_each_ring(waiter, dev_priv, i) {
1219 u32 seqno;
1220 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1221 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1222 continue;
1223
1224 seqno = i915_gem_request_get_seqno(
1225 signaller->outstanding_lazy_request);
1226 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1227 MI_FLUSH_DW_OP_STOREDW);
1228 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1229 MI_FLUSH_DW_USE_GTT);
1230 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1231 intel_ring_emit(signaller, seqno);
1232 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1233 MI_SEMAPHORE_TARGET(waiter->id));
1234 intel_ring_emit(signaller, 0);
1235 }
1236
1237 return 0;
1238 }
1239
1240 static int gen6_signal(struct intel_engine_cs *signaller,
1241 unsigned int num_dwords)
1242 {
1243 struct drm_device *dev = signaller->dev;
1244 struct drm_i915_private *dev_priv = dev->dev_private;
1245 struct intel_engine_cs *useless;
1246 int i, ret, num_rings;
1247
1248 #define MBOX_UPDATE_DWORDS 3
1249 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1250 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1251 #undef MBOX_UPDATE_DWORDS
1252
1253 ret = intel_ring_begin(signaller, num_dwords);
1254 if (ret)
1255 return ret;
1256
1257 for_each_ring(useless, dev_priv, i) {
1258 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1259 if (mbox_reg != GEN6_NOSYNC) {
1260 u32 seqno = i915_gem_request_get_seqno(
1261 signaller->outstanding_lazy_request);
1262 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1263 intel_ring_emit(signaller, mbox_reg);
1264 intel_ring_emit(signaller, seqno);
1265 }
1266 }
1267
1268 /* If num_dwords was rounded, make sure the tail pointer is correct */
1269 if (num_rings % 2 == 0)
1270 intel_ring_emit(signaller, MI_NOOP);
1271
1272 return 0;
1273 }
1274
1275 /**
1276 * gen6_add_request - Update the semaphore mailbox registers
1277 *
1278 * @ring - ring that is adding a request
1279 * @seqno - return seqno stuck into the ring
1280 *
1281 * Update the mailbox registers in the *other* rings with the current seqno.
1282 * This acts like a signal in the canonical semaphore.
1283 */
1284 static int
1285 gen6_add_request(struct intel_engine_cs *ring)
1286 {
1287 int ret;
1288
1289 if (ring->semaphore.signal)
1290 ret = ring->semaphore.signal(ring, 4);
1291 else
1292 ret = intel_ring_begin(ring, 4);
1293
1294 if (ret)
1295 return ret;
1296
1297 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1298 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1299 intel_ring_emit(ring,
1300 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1301 intel_ring_emit(ring, MI_USER_INTERRUPT);
1302 __intel_ring_advance(ring);
1303
1304 return 0;
1305 }
1306
1307 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1308 u32 seqno)
1309 {
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 return dev_priv->last_seqno < seqno;
1312 }
1313
1314 /**
1315 * intel_ring_sync - sync the waiter to the signaller on seqno
1316 *
1317 * @waiter - ring that is waiting
1318 * @signaller - ring which has, or will signal
1319 * @seqno - seqno which the waiter will block on
1320 */
1321
1322 static int
1323 gen8_ring_sync(struct intel_engine_cs *waiter,
1324 struct intel_engine_cs *signaller,
1325 u32 seqno)
1326 {
1327 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1328 int ret;
1329
1330 ret = intel_ring_begin(waiter, 4);
1331 if (ret)
1332 return ret;
1333
1334 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1335 MI_SEMAPHORE_GLOBAL_GTT |
1336 MI_SEMAPHORE_POLL |
1337 MI_SEMAPHORE_SAD_GTE_SDD);
1338 intel_ring_emit(waiter, seqno);
1339 intel_ring_emit(waiter,
1340 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1341 intel_ring_emit(waiter,
1342 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1343 intel_ring_advance(waiter);
1344 return 0;
1345 }
1346
1347 static int
1348 gen6_ring_sync(struct intel_engine_cs *waiter,
1349 struct intel_engine_cs *signaller,
1350 u32 seqno)
1351 {
1352 u32 dw1 = MI_SEMAPHORE_MBOX |
1353 MI_SEMAPHORE_COMPARE |
1354 MI_SEMAPHORE_REGISTER;
1355 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1356 int ret;
1357
1358 /* Throughout all of the GEM code, seqno passed implies our current
1359 * seqno is >= the last seqno executed. However for hardware the
1360 * comparison is strictly greater than.
1361 */
1362 seqno -= 1;
1363
1364 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1365
1366 ret = intel_ring_begin(waiter, 4);
1367 if (ret)
1368 return ret;
1369
1370 /* If seqno wrap happened, omit the wait with no-ops */
1371 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1372 intel_ring_emit(waiter, dw1 | wait_mbox);
1373 intel_ring_emit(waiter, seqno);
1374 intel_ring_emit(waiter, 0);
1375 intel_ring_emit(waiter, MI_NOOP);
1376 } else {
1377 intel_ring_emit(waiter, MI_NOOP);
1378 intel_ring_emit(waiter, MI_NOOP);
1379 intel_ring_emit(waiter, MI_NOOP);
1380 intel_ring_emit(waiter, MI_NOOP);
1381 }
1382 intel_ring_advance(waiter);
1383
1384 return 0;
1385 }
1386
1387 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1388 do { \
1389 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1390 PIPE_CONTROL_DEPTH_STALL); \
1391 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1392 intel_ring_emit(ring__, 0); \
1393 intel_ring_emit(ring__, 0); \
1394 } while (0)
1395
1396 static int
1397 pc_render_add_request(struct intel_engine_cs *ring)
1398 {
1399 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1400 int ret;
1401
1402 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1403 * incoherent with writes to memory, i.e. completely fubar,
1404 * so we need to use PIPE_NOTIFY instead.
1405 *
1406 * However, we also need to workaround the qword write
1407 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1408 * memory before requesting an interrupt.
1409 */
1410 ret = intel_ring_begin(ring, 32);
1411 if (ret)
1412 return ret;
1413
1414 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1415 PIPE_CONTROL_WRITE_FLUSH |
1416 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1417 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1418 intel_ring_emit(ring,
1419 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1420 intel_ring_emit(ring, 0);
1421 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1422 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1423 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1424 scratch_addr += 2 * CACHELINE_BYTES;
1425 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1426 scratch_addr += 2 * CACHELINE_BYTES;
1427 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1428 scratch_addr += 2 * CACHELINE_BYTES;
1429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1430 scratch_addr += 2 * CACHELINE_BYTES;
1431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1432
1433 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1434 PIPE_CONTROL_WRITE_FLUSH |
1435 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1436 PIPE_CONTROL_NOTIFY);
1437 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1438 intel_ring_emit(ring,
1439 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1440 intel_ring_emit(ring, 0);
1441 __intel_ring_advance(ring);
1442
1443 return 0;
1444 }
1445
1446 static u32
1447 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1448 {
1449 /* Workaround to force correct ordering between irq and seqno writes on
1450 * ivb (and maybe also on snb) by reading from a CS register (like
1451 * ACTHD) before reading the status page. */
1452 if (!lazy_coherency) {
1453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1454 POSTING_READ(RING_ACTHD(ring->mmio_base));
1455 }
1456
1457 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1458 }
1459
1460 static u32
1461 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1462 {
1463 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1464 }
1465
1466 static void
1467 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1468 {
1469 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1470 }
1471
1472 static u32
1473 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1474 {
1475 return ring->scratch.cpu_page[0];
1476 }
1477
1478 static void
1479 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1480 {
1481 ring->scratch.cpu_page[0] = seqno;
1482 }
1483
1484 static bool
1485 gen5_ring_get_irq(struct intel_engine_cs *ring)
1486 {
1487 struct drm_device *dev = ring->dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489
1490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1491 return false;
1492
1493 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1494 if (ring->irq_refcount++ == 0)
1495 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1496 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1497
1498 return true;
1499 }
1500
1501 static void
1502 gen5_ring_put_irq(struct intel_engine_cs *ring)
1503 {
1504 struct drm_device *dev = ring->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506
1507 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1508 if (--ring->irq_refcount == 0)
1509 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1510 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1511 }
1512
1513 static bool
1514 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1515 {
1516 struct drm_device *dev = ring->dev;
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518
1519 if (!intel_irqs_enabled(dev_priv))
1520 return false;
1521
1522 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1523 if (ring->irq_refcount++ == 0) {
1524 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1525 I915_WRITE(IMR, dev_priv->irq_mask);
1526 POSTING_READ(IMR);
1527 }
1528 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1529
1530 return true;
1531 }
1532
1533 static void
1534 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1535 {
1536 struct drm_device *dev = ring->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538
1539 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1540 if (--ring->irq_refcount == 0) {
1541 dev_priv->irq_mask |= ring->irq_enable_mask;
1542 I915_WRITE(IMR, dev_priv->irq_mask);
1543 POSTING_READ(IMR);
1544 }
1545 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1546 }
1547
1548 static bool
1549 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1550 {
1551 struct drm_device *dev = ring->dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553
1554 if (!intel_irqs_enabled(dev_priv))
1555 return false;
1556
1557 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1558 if (ring->irq_refcount++ == 0) {
1559 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1560 I915_WRITE16(IMR, dev_priv->irq_mask);
1561 POSTING_READ16(IMR);
1562 }
1563 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1564
1565 return true;
1566 }
1567
1568 static void
1569 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1570 {
1571 struct drm_device *dev = ring->dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573
1574 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1575 if (--ring->irq_refcount == 0) {
1576 dev_priv->irq_mask |= ring->irq_enable_mask;
1577 I915_WRITE16(IMR, dev_priv->irq_mask);
1578 POSTING_READ16(IMR);
1579 }
1580 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1581 }
1582
1583 static int
1584 bsd_ring_flush(struct intel_engine_cs *ring,
1585 u32 invalidate_domains,
1586 u32 flush_domains)
1587 {
1588 int ret;
1589
1590 ret = intel_ring_begin(ring, 2);
1591 if (ret)
1592 return ret;
1593
1594 intel_ring_emit(ring, MI_FLUSH);
1595 intel_ring_emit(ring, MI_NOOP);
1596 intel_ring_advance(ring);
1597 return 0;
1598 }
1599
1600 static int
1601 i9xx_add_request(struct intel_engine_cs *ring)
1602 {
1603 int ret;
1604
1605 ret = intel_ring_begin(ring, 4);
1606 if (ret)
1607 return ret;
1608
1609 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1610 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1611 intel_ring_emit(ring,
1612 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1613 intel_ring_emit(ring, MI_USER_INTERRUPT);
1614 __intel_ring_advance(ring);
1615
1616 return 0;
1617 }
1618
1619 static bool
1620 gen6_ring_get_irq(struct intel_engine_cs *ring)
1621 {
1622 struct drm_device *dev = ring->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1626 return false;
1627
1628 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1629 if (ring->irq_refcount++ == 0) {
1630 if (HAS_L3_DPF(dev) && ring->id == RCS)
1631 I915_WRITE_IMR(ring,
1632 ~(ring->irq_enable_mask |
1633 GT_PARITY_ERROR(dev)));
1634 else
1635 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1636 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1637 }
1638 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1639
1640 return true;
1641 }
1642
1643 static void
1644 gen6_ring_put_irq(struct intel_engine_cs *ring)
1645 {
1646 struct drm_device *dev = ring->dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648
1649 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1650 if (--ring->irq_refcount == 0) {
1651 if (HAS_L3_DPF(dev) && ring->id == RCS)
1652 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1653 else
1654 I915_WRITE_IMR(ring, ~0);
1655 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1656 }
1657 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1658 }
1659
1660 static bool
1661 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1662 {
1663 struct drm_device *dev = ring->dev;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665
1666 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1667 return false;
1668
1669 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1670 if (ring->irq_refcount++ == 0) {
1671 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1672 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1673 }
1674 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1675
1676 return true;
1677 }
1678
1679 static void
1680 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1681 {
1682 struct drm_device *dev = ring->dev;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1686 if (--ring->irq_refcount == 0) {
1687 I915_WRITE_IMR(ring, ~0);
1688 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1689 }
1690 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1691 }
1692
1693 static bool
1694 gen8_ring_get_irq(struct intel_engine_cs *ring)
1695 {
1696 struct drm_device *dev = ring->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1700 return false;
1701
1702 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1703 if (ring->irq_refcount++ == 0) {
1704 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1705 I915_WRITE_IMR(ring,
1706 ~(ring->irq_enable_mask |
1707 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1708 } else {
1709 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1710 }
1711 POSTING_READ(RING_IMR(ring->mmio_base));
1712 }
1713 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1714
1715 return true;
1716 }
1717
1718 static void
1719 gen8_ring_put_irq(struct intel_engine_cs *ring)
1720 {
1721 struct drm_device *dev = ring->dev;
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1725 if (--ring->irq_refcount == 0) {
1726 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1727 I915_WRITE_IMR(ring,
1728 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1729 } else {
1730 I915_WRITE_IMR(ring, ~0);
1731 }
1732 POSTING_READ(RING_IMR(ring->mmio_base));
1733 }
1734 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1735 }
1736
1737 static int
1738 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1739 u64 offset, u32 length,
1740 unsigned dispatch_flags)
1741 {
1742 int ret;
1743
1744 ret = intel_ring_begin(ring, 2);
1745 if (ret)
1746 return ret;
1747
1748 intel_ring_emit(ring,
1749 MI_BATCH_BUFFER_START |
1750 MI_BATCH_GTT |
1751 (dispatch_flags & I915_DISPATCH_SECURE ?
1752 0 : MI_BATCH_NON_SECURE_I965));
1753 intel_ring_emit(ring, offset);
1754 intel_ring_advance(ring);
1755
1756 return 0;
1757 }
1758
1759 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1760 #define I830_BATCH_LIMIT (256*1024)
1761 #define I830_TLB_ENTRIES (2)
1762 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1763 static int
1764 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1765 u64 offset, u32 len,
1766 unsigned dispatch_flags)
1767 {
1768 u32 cs_offset = ring->scratch.gtt_offset;
1769 int ret;
1770
1771 ret = intel_ring_begin(ring, 6);
1772 if (ret)
1773 return ret;
1774
1775 /* Evict the invalid PTE TLBs */
1776 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1777 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1778 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1779 intel_ring_emit(ring, cs_offset);
1780 intel_ring_emit(ring, 0xdeadbeef);
1781 intel_ring_emit(ring, MI_NOOP);
1782 intel_ring_advance(ring);
1783
1784 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1785 if (len > I830_BATCH_LIMIT)
1786 return -ENOSPC;
1787
1788 ret = intel_ring_begin(ring, 6 + 2);
1789 if (ret)
1790 return ret;
1791
1792 /* Blit the batch (which has now all relocs applied) to the
1793 * stable batch scratch bo area (so that the CS never
1794 * stumbles over its tlb invalidation bug) ...
1795 */
1796 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1797 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1798 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1799 intel_ring_emit(ring, cs_offset);
1800 intel_ring_emit(ring, 4096);
1801 intel_ring_emit(ring, offset);
1802
1803 intel_ring_emit(ring, MI_FLUSH);
1804 intel_ring_emit(ring, MI_NOOP);
1805 intel_ring_advance(ring);
1806
1807 /* ... and execute it. */
1808 offset = cs_offset;
1809 }
1810
1811 ret = intel_ring_begin(ring, 4);
1812 if (ret)
1813 return ret;
1814
1815 intel_ring_emit(ring, MI_BATCH_BUFFER);
1816 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1817 0 : MI_BATCH_NON_SECURE));
1818 intel_ring_emit(ring, offset + len - 8);
1819 intel_ring_emit(ring, MI_NOOP);
1820 intel_ring_advance(ring);
1821
1822 return 0;
1823 }
1824
1825 static int
1826 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1827 u64 offset, u32 len,
1828 unsigned dispatch_flags)
1829 {
1830 int ret;
1831
1832 ret = intel_ring_begin(ring, 2);
1833 if (ret)
1834 return ret;
1835
1836 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1837 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1838 0 : MI_BATCH_NON_SECURE));
1839 intel_ring_advance(ring);
1840
1841 return 0;
1842 }
1843
1844 static void cleanup_status_page(struct intel_engine_cs *ring)
1845 {
1846 struct drm_i915_gem_object *obj;
1847
1848 obj = ring->status_page.obj;
1849 if (obj == NULL)
1850 return;
1851
1852 kunmap(sg_page(obj->pages->sgl));
1853 i915_gem_object_ggtt_unpin(obj);
1854 drm_gem_object_unreference(&obj->base);
1855 ring->status_page.obj = NULL;
1856 }
1857
1858 static int init_status_page(struct intel_engine_cs *ring)
1859 {
1860 struct drm_i915_gem_object *obj;
1861
1862 if ((obj = ring->status_page.obj) == NULL) {
1863 unsigned flags;
1864 int ret;
1865
1866 obj = i915_gem_alloc_object(ring->dev, 4096);
1867 if (obj == NULL) {
1868 DRM_ERROR("Failed to allocate status page\n");
1869 return -ENOMEM;
1870 }
1871
1872 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1873 if (ret)
1874 goto err_unref;
1875
1876 flags = 0;
1877 if (!HAS_LLC(ring->dev))
1878 /* On g33, we cannot place HWS above 256MiB, so
1879 * restrict its pinning to the low mappable arena.
1880 * Though this restriction is not documented for
1881 * gen4, gen5, or byt, they also behave similarly
1882 * and hang if the HWS is placed at the top of the
1883 * GTT. To generalise, it appears that all !llc
1884 * platforms have issues with us placing the HWS
1885 * above the mappable region (even though we never
1886 * actualy map it).
1887 */
1888 flags |= PIN_MAPPABLE;
1889 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1890 if (ret) {
1891 err_unref:
1892 drm_gem_object_unreference(&obj->base);
1893 return ret;
1894 }
1895
1896 ring->status_page.obj = obj;
1897 }
1898
1899 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1900 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1901 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1902
1903 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1904 ring->name, ring->status_page.gfx_addr);
1905
1906 return 0;
1907 }
1908
1909 static int init_phys_status_page(struct intel_engine_cs *ring)
1910 {
1911 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1912
1913 if (!dev_priv->status_page_dmah) {
1914 dev_priv->status_page_dmah =
1915 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1916 if (!dev_priv->status_page_dmah)
1917 return -ENOMEM;
1918 }
1919
1920 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1921 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1922
1923 return 0;
1924 }
1925
1926 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1927 {
1928 iounmap(ringbuf->virtual_start);
1929 ringbuf->virtual_start = NULL;
1930 i915_gem_object_ggtt_unpin(ringbuf->obj);
1931 }
1932
1933 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1934 struct intel_ringbuffer *ringbuf)
1935 {
1936 struct drm_i915_private *dev_priv = to_i915(dev);
1937 struct drm_i915_gem_object *obj = ringbuf->obj;
1938 int ret;
1939
1940 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1941 if (ret)
1942 return ret;
1943
1944 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1945 if (ret) {
1946 i915_gem_object_ggtt_unpin(obj);
1947 return ret;
1948 }
1949
1950 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1951 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1952 if (ringbuf->virtual_start == NULL) {
1953 i915_gem_object_ggtt_unpin(obj);
1954 return -EINVAL;
1955 }
1956
1957 return 0;
1958 }
1959
1960 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1961 {
1962 drm_gem_object_unreference(&ringbuf->obj->base);
1963 ringbuf->obj = NULL;
1964 }
1965
1966 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1967 struct intel_ringbuffer *ringbuf)
1968 {
1969 struct drm_i915_gem_object *obj;
1970
1971 obj = NULL;
1972 if (!HAS_LLC(dev))
1973 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1974 if (obj == NULL)
1975 obj = i915_gem_alloc_object(dev, ringbuf->size);
1976 if (obj == NULL)
1977 return -ENOMEM;
1978
1979 /* mark ring buffers as read-only from GPU side by default */
1980 obj->gt_ro = 1;
1981
1982 ringbuf->obj = obj;
1983
1984 return 0;
1985 }
1986
1987 static int intel_init_ring_buffer(struct drm_device *dev,
1988 struct intel_engine_cs *ring)
1989 {
1990 struct intel_ringbuffer *ringbuf;
1991 int ret;
1992
1993 WARN_ON(ring->buffer);
1994
1995 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1996 if (!ringbuf)
1997 return -ENOMEM;
1998 ring->buffer = ringbuf;
1999
2000 ring->dev = dev;
2001 INIT_LIST_HEAD(&ring->active_list);
2002 INIT_LIST_HEAD(&ring->request_list);
2003 INIT_LIST_HEAD(&ring->execlist_queue);
2004 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2005 ringbuf->size = 32 * PAGE_SIZE;
2006 ringbuf->ring = ring;
2007 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2008
2009 init_waitqueue_head(&ring->irq_queue);
2010
2011 if (I915_NEED_GFX_HWS(dev)) {
2012 ret = init_status_page(ring);
2013 if (ret)
2014 goto error;
2015 } else {
2016 BUG_ON(ring->id != RCS);
2017 ret = init_phys_status_page(ring);
2018 if (ret)
2019 goto error;
2020 }
2021
2022 WARN_ON(ringbuf->obj);
2023
2024 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2025 if (ret) {
2026 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2027 ring->name, ret);
2028 goto error;
2029 }
2030
2031 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2032 if (ret) {
2033 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2034 ring->name, ret);
2035 intel_destroy_ringbuffer_obj(ringbuf);
2036 goto error;
2037 }
2038
2039 /* Workaround an erratum on the i830 which causes a hang if
2040 * the TAIL pointer points to within the last 2 cachelines
2041 * of the buffer.
2042 */
2043 ringbuf->effective_size = ringbuf->size;
2044 if (IS_I830(dev) || IS_845G(dev))
2045 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2046
2047 ret = i915_cmd_parser_init_ring(ring);
2048 if (ret)
2049 goto error;
2050
2051 return 0;
2052
2053 error:
2054 kfree(ringbuf);
2055 ring->buffer = NULL;
2056 return ret;
2057 }
2058
2059 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2060 {
2061 struct drm_i915_private *dev_priv;
2062 struct intel_ringbuffer *ringbuf;
2063
2064 if (!intel_ring_initialized(ring))
2065 return;
2066
2067 dev_priv = to_i915(ring->dev);
2068 ringbuf = ring->buffer;
2069
2070 intel_stop_ring_buffer(ring);
2071 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2072
2073 intel_unpin_ringbuffer_obj(ringbuf);
2074 intel_destroy_ringbuffer_obj(ringbuf);
2075 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2076
2077 if (ring->cleanup)
2078 ring->cleanup(ring);
2079
2080 cleanup_status_page(ring);
2081
2082 i915_cmd_parser_fini_ring(ring);
2083 i915_gem_batch_pool_fini(&ring->batch_pool);
2084
2085 kfree(ringbuf);
2086 ring->buffer = NULL;
2087 }
2088
2089 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2090 {
2091 struct intel_ringbuffer *ringbuf = ring->buffer;
2092 struct drm_i915_gem_request *request;
2093 unsigned space;
2094 int ret;
2095
2096 if (intel_ring_space(ringbuf) >= n)
2097 return 0;
2098
2099 list_for_each_entry(request, &ring->request_list, list) {
2100 space = __intel_ring_space(request->postfix, ringbuf->tail,
2101 ringbuf->size);
2102 if (space >= n)
2103 break;
2104 }
2105
2106 if (WARN_ON(&request->list == &ring->request_list))
2107 return -ENOSPC;
2108
2109 ret = i915_wait_request(request);
2110 if (ret)
2111 return ret;
2112
2113 ringbuf->space = space;
2114 return 0;
2115 }
2116
2117 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2118 {
2119 uint32_t __iomem *virt;
2120 struct intel_ringbuffer *ringbuf = ring->buffer;
2121 int rem = ringbuf->size - ringbuf->tail;
2122
2123 if (ringbuf->space < rem) {
2124 int ret = ring_wait_for_space(ring, rem);
2125 if (ret)
2126 return ret;
2127 }
2128
2129 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail);
2130 rem /= 4;
2131 while (rem--)
2132 iowrite32(MI_NOOP, virt++);
2133
2134 ringbuf->tail = 0;
2135 intel_ring_update_space(ringbuf);
2136
2137 return 0;
2138 }
2139
2140 int intel_ring_idle(struct intel_engine_cs *ring)
2141 {
2142 struct drm_i915_gem_request *req;
2143 int ret;
2144
2145 /* We need to add any requests required to flush the objects and ring */
2146 if (ring->outstanding_lazy_request) {
2147 ret = i915_add_request(ring);
2148 if (ret)
2149 return ret;
2150 }
2151
2152 /* Wait upon the last request to be completed */
2153 if (list_empty(&ring->request_list))
2154 return 0;
2155
2156 req = list_entry(ring->request_list.prev,
2157 struct drm_i915_gem_request,
2158 list);
2159
2160 /* Make sure we do not trigger any retires */
2161 return __i915_wait_request(req,
2162 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2163 to_i915(ring->dev)->mm.interruptible,
2164 NULL, NULL);
2165 }
2166
2167 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2168 {
2169 request->ringbuf = request->ring->buffer;
2170 return 0;
2171 }
2172
2173 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2174 int bytes)
2175 {
2176 struct intel_ringbuffer *ringbuf = ring->buffer;
2177 int ret;
2178
2179 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2180 ret = intel_wrap_ring_buffer(ring);
2181 if (unlikely(ret))
2182 return ret;
2183 }
2184
2185 if (unlikely(ringbuf->space < bytes)) {
2186 ret = ring_wait_for_space(ring, bytes);
2187 if (unlikely(ret))
2188 return ret;
2189 }
2190
2191 return 0;
2192 }
2193
2194 int intel_ring_begin(struct intel_engine_cs *ring,
2195 int num_dwords)
2196 {
2197 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2198 int ret;
2199
2200 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2201 dev_priv->mm.interruptible);
2202 if (ret)
2203 return ret;
2204
2205 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2206 if (ret)
2207 return ret;
2208
2209 /* Preallocate the olr before touching the ring */
2210 ret = i915_gem_request_alloc(ring, ring->default_context);
2211 if (ret)
2212 return ret;
2213
2214 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2215 return 0;
2216 }
2217
2218 /* Align the ring tail to a cacheline boundary */
2219 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2220 {
2221 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2222 int ret;
2223
2224 if (num_dwords == 0)
2225 return 0;
2226
2227 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2228 ret = intel_ring_begin(ring, num_dwords);
2229 if (ret)
2230 return ret;
2231
2232 while (num_dwords--)
2233 intel_ring_emit(ring, MI_NOOP);
2234
2235 intel_ring_advance(ring);
2236
2237 return 0;
2238 }
2239
2240 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2241 {
2242 struct drm_device *dev = ring->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244
2245 BUG_ON(ring->outstanding_lazy_request);
2246
2247 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2248 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2249 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2250 if (HAS_VEBOX(dev))
2251 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2252 }
2253
2254 ring->set_seqno(ring, seqno);
2255 ring->hangcheck.seqno = seqno;
2256 }
2257
2258 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2259 u32 value)
2260 {
2261 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2262
2263 /* Every tail move must follow the sequence below */
2264
2265 /* Disable notification that the ring is IDLE. The GT
2266 * will then assume that it is busy and bring it out of rc6.
2267 */
2268 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2269 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2270
2271 /* Clear the context id. Here be magic! */
2272 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2273
2274 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2275 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2276 GEN6_BSD_SLEEP_INDICATOR) == 0,
2277 50))
2278 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2279
2280 /* Now that the ring is fully powered up, update the tail */
2281 I915_WRITE_TAIL(ring, value);
2282 POSTING_READ(RING_TAIL(ring->mmio_base));
2283
2284 /* Let the ring send IDLE messages to the GT again,
2285 * and so let it sleep to conserve power when idle.
2286 */
2287 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2288 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2289 }
2290
2291 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2292 u32 invalidate, u32 flush)
2293 {
2294 uint32_t cmd;
2295 int ret;
2296
2297 ret = intel_ring_begin(ring, 4);
2298 if (ret)
2299 return ret;
2300
2301 cmd = MI_FLUSH_DW;
2302 if (INTEL_INFO(ring->dev)->gen >= 8)
2303 cmd += 1;
2304
2305 /* We always require a command barrier so that subsequent
2306 * commands, such as breadcrumb interrupts, are strictly ordered
2307 * wrt the contents of the write cache being flushed to memory
2308 * (and thus being coherent from the CPU).
2309 */
2310 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2311
2312 /*
2313 * Bspec vol 1c.5 - video engine command streamer:
2314 * "If ENABLED, all TLBs will be invalidated once the flush
2315 * operation is complete. This bit is only valid when the
2316 * Post-Sync Operation field is a value of 1h or 3h."
2317 */
2318 if (invalidate & I915_GEM_GPU_DOMAINS)
2319 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2320
2321 intel_ring_emit(ring, cmd);
2322 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2323 if (INTEL_INFO(ring->dev)->gen >= 8) {
2324 intel_ring_emit(ring, 0); /* upper addr */
2325 intel_ring_emit(ring, 0); /* value */
2326 } else {
2327 intel_ring_emit(ring, 0);
2328 intel_ring_emit(ring, MI_NOOP);
2329 }
2330 intel_ring_advance(ring);
2331 return 0;
2332 }
2333
2334 static int
2335 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2336 u64 offset, u32 len,
2337 unsigned dispatch_flags)
2338 {
2339 bool ppgtt = USES_PPGTT(ring->dev) &&
2340 !(dispatch_flags & I915_DISPATCH_SECURE);
2341 int ret;
2342
2343 ret = intel_ring_begin(ring, 4);
2344 if (ret)
2345 return ret;
2346
2347 /* FIXME(BDW): Address space and security selectors. */
2348 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2349 intel_ring_emit(ring, lower_32_bits(offset));
2350 intel_ring_emit(ring, upper_32_bits(offset));
2351 intel_ring_emit(ring, MI_NOOP);
2352 intel_ring_advance(ring);
2353
2354 return 0;
2355 }
2356
2357 static int
2358 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2359 u64 offset, u32 len,
2360 unsigned dispatch_flags)
2361 {
2362 int ret;
2363
2364 ret = intel_ring_begin(ring, 2);
2365 if (ret)
2366 return ret;
2367
2368 intel_ring_emit(ring,
2369 MI_BATCH_BUFFER_START |
2370 (dispatch_flags & I915_DISPATCH_SECURE ?
2371 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2372 /* bit0-7 is the length on GEN6+ */
2373 intel_ring_emit(ring, offset);
2374 intel_ring_advance(ring);
2375
2376 return 0;
2377 }
2378
2379 static int
2380 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2381 u64 offset, u32 len,
2382 unsigned dispatch_flags)
2383 {
2384 int ret;
2385
2386 ret = intel_ring_begin(ring, 2);
2387 if (ret)
2388 return ret;
2389
2390 intel_ring_emit(ring,
2391 MI_BATCH_BUFFER_START |
2392 (dispatch_flags & I915_DISPATCH_SECURE ?
2393 0 : MI_BATCH_NON_SECURE_I965));
2394 /* bit0-7 is the length on GEN6+ */
2395 intel_ring_emit(ring, offset);
2396 intel_ring_advance(ring);
2397
2398 return 0;
2399 }
2400
2401 /* Blitter support (SandyBridge+) */
2402
2403 static int gen6_ring_flush(struct intel_engine_cs *ring,
2404 u32 invalidate, u32 flush)
2405 {
2406 struct drm_device *dev = ring->dev;
2407 uint32_t cmd;
2408 int ret;
2409
2410 ret = intel_ring_begin(ring, 4);
2411 if (ret)
2412 return ret;
2413
2414 cmd = MI_FLUSH_DW;
2415 if (INTEL_INFO(dev)->gen >= 8)
2416 cmd += 1;
2417
2418 /* We always require a command barrier so that subsequent
2419 * commands, such as breadcrumb interrupts, are strictly ordered
2420 * wrt the contents of the write cache being flushed to memory
2421 * (and thus being coherent from the CPU).
2422 */
2423 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2424
2425 /*
2426 * Bspec vol 1c.3 - blitter engine command streamer:
2427 * "If ENABLED, all TLBs will be invalidated once the flush
2428 * operation is complete. This bit is only valid when the
2429 * Post-Sync Operation field is a value of 1h or 3h."
2430 */
2431 if (invalidate & I915_GEM_DOMAIN_RENDER)
2432 cmd |= MI_INVALIDATE_TLB;
2433 intel_ring_emit(ring, cmd);
2434 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2435 if (INTEL_INFO(dev)->gen >= 8) {
2436 intel_ring_emit(ring, 0); /* upper addr */
2437 intel_ring_emit(ring, 0); /* value */
2438 } else {
2439 intel_ring_emit(ring, 0);
2440 intel_ring_emit(ring, MI_NOOP);
2441 }
2442 intel_ring_advance(ring);
2443
2444 return 0;
2445 }
2446
2447 int intel_init_render_ring_buffer(struct drm_device *dev)
2448 {
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2451 struct drm_i915_gem_object *obj;
2452 int ret;
2453
2454 ring->name = "render ring";
2455 ring->id = RCS;
2456 ring->mmio_base = RENDER_RING_BASE;
2457
2458 if (INTEL_INFO(dev)->gen >= 8) {
2459 if (i915_semaphore_is_enabled(dev)) {
2460 obj = i915_gem_alloc_object(dev, 4096);
2461 if (obj == NULL) {
2462 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2463 i915.semaphores = 0;
2464 } else {
2465 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2466 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2467 if (ret != 0) {
2468 drm_gem_object_unreference(&obj->base);
2469 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2470 i915.semaphores = 0;
2471 } else
2472 dev_priv->semaphore_obj = obj;
2473 }
2474 }
2475
2476 ring->init_context = intel_rcs_ctx_init;
2477 ring->add_request = gen6_add_request;
2478 ring->flush = gen8_render_ring_flush;
2479 ring->irq_get = gen8_ring_get_irq;
2480 ring->irq_put = gen8_ring_put_irq;
2481 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2482 ring->get_seqno = gen6_ring_get_seqno;
2483 ring->set_seqno = ring_set_seqno;
2484 if (i915_semaphore_is_enabled(dev)) {
2485 WARN_ON(!dev_priv->semaphore_obj);
2486 ring->semaphore.sync_to = gen8_ring_sync;
2487 ring->semaphore.signal = gen8_rcs_signal;
2488 GEN8_RING_SEMAPHORE_INIT;
2489 }
2490 } else if (INTEL_INFO(dev)->gen >= 6) {
2491 ring->add_request = gen6_add_request;
2492 ring->flush = gen7_render_ring_flush;
2493 if (INTEL_INFO(dev)->gen == 6)
2494 ring->flush = gen6_render_ring_flush;
2495 ring->irq_get = gen6_ring_get_irq;
2496 ring->irq_put = gen6_ring_put_irq;
2497 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2498 ring->get_seqno = gen6_ring_get_seqno;
2499 ring->set_seqno = ring_set_seqno;
2500 if (i915_semaphore_is_enabled(dev)) {
2501 ring->semaphore.sync_to = gen6_ring_sync;
2502 ring->semaphore.signal = gen6_signal;
2503 /*
2504 * The current semaphore is only applied on pre-gen8
2505 * platform. And there is no VCS2 ring on the pre-gen8
2506 * platform. So the semaphore between RCS and VCS2 is
2507 * initialized as INVALID. Gen8 will initialize the
2508 * sema between VCS2 and RCS later.
2509 */
2510 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2511 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2512 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2513 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2514 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2515 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2516 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2517 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2518 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2519 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2520 }
2521 } else if (IS_GEN5(dev)) {
2522 ring->add_request = pc_render_add_request;
2523 ring->flush = gen4_render_ring_flush;
2524 ring->get_seqno = pc_render_get_seqno;
2525 ring->set_seqno = pc_render_set_seqno;
2526 ring->irq_get = gen5_ring_get_irq;
2527 ring->irq_put = gen5_ring_put_irq;
2528 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2529 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2530 } else {
2531 ring->add_request = i9xx_add_request;
2532 if (INTEL_INFO(dev)->gen < 4)
2533 ring->flush = gen2_render_ring_flush;
2534 else
2535 ring->flush = gen4_render_ring_flush;
2536 ring->get_seqno = ring_get_seqno;
2537 ring->set_seqno = ring_set_seqno;
2538 if (IS_GEN2(dev)) {
2539 ring->irq_get = i8xx_ring_get_irq;
2540 ring->irq_put = i8xx_ring_put_irq;
2541 } else {
2542 ring->irq_get = i9xx_ring_get_irq;
2543 ring->irq_put = i9xx_ring_put_irq;
2544 }
2545 ring->irq_enable_mask = I915_USER_INTERRUPT;
2546 }
2547 ring->write_tail = ring_write_tail;
2548
2549 if (IS_HASWELL(dev))
2550 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2551 else if (IS_GEN8(dev))
2552 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2553 else if (INTEL_INFO(dev)->gen >= 6)
2554 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2555 else if (INTEL_INFO(dev)->gen >= 4)
2556 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2557 else if (IS_I830(dev) || IS_845G(dev))
2558 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2559 else
2560 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2561 ring->init_hw = init_render_ring;
2562 ring->cleanup = render_ring_cleanup;
2563
2564 /* Workaround batchbuffer to combat CS tlb bug. */
2565 if (HAS_BROKEN_CS_TLB(dev)) {
2566 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2567 if (obj == NULL) {
2568 DRM_ERROR("Failed to allocate batch bo\n");
2569 return -ENOMEM;
2570 }
2571
2572 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2573 if (ret != 0) {
2574 drm_gem_object_unreference(&obj->base);
2575 DRM_ERROR("Failed to ping batch bo\n");
2576 return ret;
2577 }
2578
2579 ring->scratch.obj = obj;
2580 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2581 }
2582
2583 ret = intel_init_ring_buffer(dev, ring);
2584 if (ret)
2585 return ret;
2586
2587 if (INTEL_INFO(dev)->gen >= 5) {
2588 ret = intel_init_pipe_control(ring);
2589 if (ret)
2590 return ret;
2591 }
2592
2593 return 0;
2594 }
2595
2596 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2597 {
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2600
2601 ring->name = "bsd ring";
2602 ring->id = VCS;
2603
2604 ring->write_tail = ring_write_tail;
2605 if (INTEL_INFO(dev)->gen >= 6) {
2606 ring->mmio_base = GEN6_BSD_RING_BASE;
2607 /* gen6 bsd needs a special wa for tail updates */
2608 if (IS_GEN6(dev))
2609 ring->write_tail = gen6_bsd_ring_write_tail;
2610 ring->flush = gen6_bsd_ring_flush;
2611 ring->add_request = gen6_add_request;
2612 ring->get_seqno = gen6_ring_get_seqno;
2613 ring->set_seqno = ring_set_seqno;
2614 if (INTEL_INFO(dev)->gen >= 8) {
2615 ring->irq_enable_mask =
2616 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2617 ring->irq_get = gen8_ring_get_irq;
2618 ring->irq_put = gen8_ring_put_irq;
2619 ring->dispatch_execbuffer =
2620 gen8_ring_dispatch_execbuffer;
2621 if (i915_semaphore_is_enabled(dev)) {
2622 ring->semaphore.sync_to = gen8_ring_sync;
2623 ring->semaphore.signal = gen8_xcs_signal;
2624 GEN8_RING_SEMAPHORE_INIT;
2625 }
2626 } else {
2627 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2628 ring->irq_get = gen6_ring_get_irq;
2629 ring->irq_put = gen6_ring_put_irq;
2630 ring->dispatch_execbuffer =
2631 gen6_ring_dispatch_execbuffer;
2632 if (i915_semaphore_is_enabled(dev)) {
2633 ring->semaphore.sync_to = gen6_ring_sync;
2634 ring->semaphore.signal = gen6_signal;
2635 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2636 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2637 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2638 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2639 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2640 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2641 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2642 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2643 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2644 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2645 }
2646 }
2647 } else {
2648 ring->mmio_base = BSD_RING_BASE;
2649 ring->flush = bsd_ring_flush;
2650 ring->add_request = i9xx_add_request;
2651 ring->get_seqno = ring_get_seqno;
2652 ring->set_seqno = ring_set_seqno;
2653 if (IS_GEN5(dev)) {
2654 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2655 ring->irq_get = gen5_ring_get_irq;
2656 ring->irq_put = gen5_ring_put_irq;
2657 } else {
2658 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2659 ring->irq_get = i9xx_ring_get_irq;
2660 ring->irq_put = i9xx_ring_put_irq;
2661 }
2662 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2663 }
2664 ring->init_hw = init_ring_common;
2665
2666 return intel_init_ring_buffer(dev, ring);
2667 }
2668
2669 /**
2670 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2671 */
2672 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2673 {
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2676
2677 ring->name = "bsd2 ring";
2678 ring->id = VCS2;
2679
2680 ring->write_tail = ring_write_tail;
2681 ring->mmio_base = GEN8_BSD2_RING_BASE;
2682 ring->flush = gen6_bsd_ring_flush;
2683 ring->add_request = gen6_add_request;
2684 ring->get_seqno = gen6_ring_get_seqno;
2685 ring->set_seqno = ring_set_seqno;
2686 ring->irq_enable_mask =
2687 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2688 ring->irq_get = gen8_ring_get_irq;
2689 ring->irq_put = gen8_ring_put_irq;
2690 ring->dispatch_execbuffer =
2691 gen8_ring_dispatch_execbuffer;
2692 if (i915_semaphore_is_enabled(dev)) {
2693 ring->semaphore.sync_to = gen8_ring_sync;
2694 ring->semaphore.signal = gen8_xcs_signal;
2695 GEN8_RING_SEMAPHORE_INIT;
2696 }
2697 ring->init_hw = init_ring_common;
2698
2699 return intel_init_ring_buffer(dev, ring);
2700 }
2701
2702 int intel_init_blt_ring_buffer(struct drm_device *dev)
2703 {
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2706
2707 ring->name = "blitter ring";
2708 ring->id = BCS;
2709
2710 ring->mmio_base = BLT_RING_BASE;
2711 ring->write_tail = ring_write_tail;
2712 ring->flush = gen6_ring_flush;
2713 ring->add_request = gen6_add_request;
2714 ring->get_seqno = gen6_ring_get_seqno;
2715 ring->set_seqno = ring_set_seqno;
2716 if (INTEL_INFO(dev)->gen >= 8) {
2717 ring->irq_enable_mask =
2718 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2719 ring->irq_get = gen8_ring_get_irq;
2720 ring->irq_put = gen8_ring_put_irq;
2721 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2722 if (i915_semaphore_is_enabled(dev)) {
2723 ring->semaphore.sync_to = gen8_ring_sync;
2724 ring->semaphore.signal = gen8_xcs_signal;
2725 GEN8_RING_SEMAPHORE_INIT;
2726 }
2727 } else {
2728 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2729 ring->irq_get = gen6_ring_get_irq;
2730 ring->irq_put = gen6_ring_put_irq;
2731 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2732 if (i915_semaphore_is_enabled(dev)) {
2733 ring->semaphore.signal = gen6_signal;
2734 ring->semaphore.sync_to = gen6_ring_sync;
2735 /*
2736 * The current semaphore is only applied on pre-gen8
2737 * platform. And there is no VCS2 ring on the pre-gen8
2738 * platform. So the semaphore between BCS and VCS2 is
2739 * initialized as INVALID. Gen8 will initialize the
2740 * sema between BCS and VCS2 later.
2741 */
2742 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2743 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2744 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2745 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2746 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2747 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2748 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2749 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2750 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2751 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2752 }
2753 }
2754 ring->init_hw = init_ring_common;
2755
2756 return intel_init_ring_buffer(dev, ring);
2757 }
2758
2759 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2760 {
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2763
2764 ring->name = "video enhancement ring";
2765 ring->id = VECS;
2766
2767 ring->mmio_base = VEBOX_RING_BASE;
2768 ring->write_tail = ring_write_tail;
2769 ring->flush = gen6_ring_flush;
2770 ring->add_request = gen6_add_request;
2771 ring->get_seqno = gen6_ring_get_seqno;
2772 ring->set_seqno = ring_set_seqno;
2773
2774 if (INTEL_INFO(dev)->gen >= 8) {
2775 ring->irq_enable_mask =
2776 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2777 ring->irq_get = gen8_ring_get_irq;
2778 ring->irq_put = gen8_ring_put_irq;
2779 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2780 if (i915_semaphore_is_enabled(dev)) {
2781 ring->semaphore.sync_to = gen8_ring_sync;
2782 ring->semaphore.signal = gen8_xcs_signal;
2783 GEN8_RING_SEMAPHORE_INIT;
2784 }
2785 } else {
2786 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2787 ring->irq_get = hsw_vebox_get_irq;
2788 ring->irq_put = hsw_vebox_put_irq;
2789 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2790 if (i915_semaphore_is_enabled(dev)) {
2791 ring->semaphore.sync_to = gen6_ring_sync;
2792 ring->semaphore.signal = gen6_signal;
2793 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2794 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2795 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2796 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2797 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2798 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2799 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2800 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2801 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2802 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2803 }
2804 }
2805 ring->init_hw = init_ring_common;
2806
2807 return intel_init_ring_buffer(dev, ring);
2808 }
2809
2810 int
2811 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2812 {
2813 int ret;
2814
2815 if (!ring->gpu_caches_dirty)
2816 return 0;
2817
2818 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2819 if (ret)
2820 return ret;
2821
2822 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2823
2824 ring->gpu_caches_dirty = false;
2825 return 0;
2826 }
2827
2828 int
2829 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2830 {
2831 uint32_t flush_domains;
2832 int ret;
2833
2834 flush_domains = 0;
2835 if (ring->gpu_caches_dirty)
2836 flush_domains = I915_GEM_GPU_DOMAINS;
2837
2838 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2839 if (ret)
2840 return ret;
2841
2842 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2843
2844 ring->gpu_caches_dirty = false;
2845 return 0;
2846 }
2847
2848 void
2849 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2850 {
2851 int ret;
2852
2853 if (!intel_ring_initialized(ring))
2854 return;
2855
2856 ret = intel_ring_idle(ring);
2857 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2858 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2859 ring->name, ret);
2860
2861 stop_ring(ring);
2862 }
DragonFly BSD