2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
34 #include <linux/bitmap.h>
35 #include <linux/highmem.h>
38 * DOC: Global GTT views
40 * Background and previous state
42 * Historically objects could exists (be bound) in global GTT space only as
43 * singular instances with a view representing all of the object's backing pages
44 * in a linear fashion. This view will be called a normal view.
46 * To support multiple views of the same object, where the number of mapped
47 * pages is not equal to the backing store, or where the layout of the pages
48 * is not linear, concept of a GGTT view was added.
50 * One example of an alternative view is a stereo display driven by a single
51 * image. In this case we would have a framebuffer looking like this
57 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
58 * rendering. In contrast, fed to the display engine would be an alternative
59 * view which could look something like this:
64 * In this example both the size and layout of pages in the alternative view is
65 * different from the normal view.
67 * Implementation and usage
69 * GGTT views are implemented using VMAs and are distinguished via enum
70 * i915_ggtt_view_type and struct i915_ggtt_view.
72 * A new flavour of core GEM functions which work with GGTT bound objects were
73 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
74 * renaming in large amounts of code. They take the struct i915_ggtt_view
75 * parameter encapsulating all metadata required to implement a view.
77 * As a helper for callers which are only interested in the normal view,
78 * globally const i915_ggtt_view_normal singleton instance exists. All old core
79 * GEM API functions, the ones not taking the view parameter, are operating on,
80 * or with the normal GGTT view.
82 * Code wanting to add or use a new GGTT view needs to:
84 * 1. Add a new enum with a suitable name.
85 * 2. Extend the metadata in the i915_ggtt_view structure if required.
86 * 3. Add support to i915_get_vma_pages().
88 * New views are required to build a scatter-gather table from within the
89 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
90 * exists for the lifetime of an VMA.
92 * Core API is designed to have copy semantics which means that passed in
93 * struct i915_ggtt_view does not need to be persistent (left around after
94 * calling the core API functions).
99 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
101 const struct i915_ggtt_view i915_ggtt_view_normal
;
102 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
103 .type
= I915_GGTT_VIEW_ROTATED
106 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
108 bool has_aliasing_ppgtt
;
111 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
112 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
114 if (intel_vgpu_active(dev
))
115 has_full_ppgtt
= false; /* emulation is too hard */
118 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
119 * execlists, the sole mechanism available to submit work.
121 if (INTEL_INFO(dev
)->gen
< 9 &&
122 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
125 if (enable_ppgtt
== 1)
128 if (enable_ppgtt
== 2 && has_full_ppgtt
)
131 #ifdef CONFIG_INTEL_IOMMU
132 /* Disable ppgtt on SNB if VT-d is on. */
133 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
134 DRM_INFO("Disabling PPGTT because VT-d is on\n");
139 /* Early VLV doesn't have this */
140 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
141 dev
->pdev
->revision
< 0xb) {
142 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
146 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
149 return has_aliasing_ppgtt
? 1 : 0;
152 static int ppgtt_bind_vma(struct i915_vma
*vma
,
153 enum i915_cache_level cache_level
,
158 /* Currently applicable only to VLV */
160 pte_flags
|= PTE_READ_ONLY
;
162 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
163 cache_level
, pte_flags
);
168 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
170 vma
->vm
->clear_range(vma
->vm
,
176 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
177 enum i915_cache_level level
,
180 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
184 case I915_CACHE_NONE
:
185 pte
|= PPAT_UNCACHED_INDEX
;
188 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
191 pte
|= PPAT_CACHED_INDEX
;
198 static gen8_pde_t
gen8_pde_encode(struct drm_device
*dev
,
200 enum i915_cache_level level
)
202 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
204 if (level
!= I915_CACHE_NONE
)
205 pde
|= PPAT_CACHED_PDE_INDEX
;
207 pde
|= PPAT_UNCACHED_INDEX
;
211 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
212 enum i915_cache_level level
,
213 bool valid
, u32 unused
)
215 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
216 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
219 case I915_CACHE_L3_LLC
:
221 pte
|= GEN6_PTE_CACHE_LLC
;
223 case I915_CACHE_NONE
:
224 pte
|= GEN6_PTE_UNCACHED
;
233 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
234 enum i915_cache_level level
,
235 bool valid
, u32 unused
)
237 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
238 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
241 case I915_CACHE_L3_LLC
:
242 pte
|= GEN7_PTE_CACHE_L3_LLC
;
245 pte
|= GEN6_PTE_CACHE_LLC
;
247 case I915_CACHE_NONE
:
248 pte
|= GEN6_PTE_UNCACHED
;
257 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
258 enum i915_cache_level level
,
259 bool valid
, u32 flags
)
261 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
262 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
264 if (!(flags
& PTE_READ_ONLY
))
265 pte
|= BYT_PTE_WRITEABLE
;
267 if (level
!= I915_CACHE_NONE
)
268 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
273 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
274 enum i915_cache_level level
,
275 bool valid
, u32 unused
)
277 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
278 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
280 if (level
!= I915_CACHE_NONE
)
281 pte
|= HSW_WB_LLC_AGE3
;
286 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
287 enum i915_cache_level level
,
288 bool valid
, u32 unused
)
290 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
291 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
294 case I915_CACHE_NONE
:
297 pte
|= HSW_WT_ELLC_LLC_AGE3
;
300 pte
|= HSW_WB_ELLC_LLC_AGE3
;
307 #define i915_dma_unmap_single(px, dev) \
308 __i915_dma_unmap_single((px)->daddr, dev)
310 static void __i915_dma_unmap_single(dma_addr_t daddr
,
311 struct drm_device
*dev
)
314 struct device
*device
= &dev
->pdev
->dev
;
316 dma_unmap_page(device
, daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
321 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
322 * @px: Page table/dir/etc to get a DMA map for
325 * Page table allocations are unified across all gens. They always require a
326 * single 4k allocation, as well as a DMA mapping. If we keep the structs
327 * symmetric here, the simple macro covers us for every page table type.
329 * Return: 0 if success.
331 #define i915_dma_map_single(px, dev) \
332 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
334 static int i915_dma_map_page_single(struct vm_page
*page
,
335 struct drm_device
*dev
,
338 struct device
*device
= dev
->pdev
->dev
;
340 *daddr
= dma_map_page(device
, page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
341 if (dma_mapping_error(device
, *daddr
))
347 static void unmap_and_free_pt(struct i915_page_table
*pt
,
348 struct drm_device
*dev
)
350 if (WARN_ON(!pt
->page
))
353 i915_dma_unmap_single(pt
, dev
);
354 __free_page(pt
->page
);
355 kfree(pt
->used_ptes
);
359 static void gen8_initialize_pt(struct i915_address_space
*vm
,
360 struct i915_page_table
*pt
)
362 gen8_pte_t
*pt_vaddr
, scratch_pte
;
365 pt_vaddr
= kmap_atomic(pt
->page
);
366 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
367 I915_CACHE_LLC
, true);
369 for (i
= 0; i
< GEN8_PTES
; i
++)
370 pt_vaddr
[i
] = scratch_pte
;
372 if (!HAS_LLC(vm
->dev
))
373 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
374 kunmap_atomic(pt_vaddr
);
377 static struct i915_page_table
*alloc_pt_single(struct drm_device
*dev
)
379 struct i915_page_table
*pt
;
380 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
381 GEN8_PTES
: GEN6_PTES
;
384 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
386 return ERR_PTR(-ENOMEM
);
388 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
394 pt
->page
= alloc_page(GFP_KERNEL
);
398 ret
= i915_dma_map_single(pt
, dev
);
405 __free_page(pt
->page
);
407 kfree(pt
->used_ptes
);
415 * alloc_pt_range() - Allocate a multiple page tables
416 * @pd: The page directory which will have at least @count entries
417 * available to point to the allocated page tables.
418 * @pde: First page directory entry for which we are allocating.
419 * @count: Number of pages to allocate.
422 * Allocates multiple page table pages and sets the appropriate entries in the
423 * page table structure within the page directory. Function cleans up after
424 * itself on any failures.
426 * Return: 0 if allocation succeeded.
428 static int alloc_pt_range(struct i915_page_directory
*pd
, uint16_t pde
, size_t count
,
429 struct drm_device
*dev
)
433 /* 512 is the max page tables per page_directory on any platform. */
434 if (WARN_ON(pde
+ count
> I915_PDES
))
437 for (i
= pde
; i
< pde
+ count
; i
++) {
438 struct i915_page_table
*pt
= alloc_pt_single(dev
);
444 WARN(pd
->page_table
[i
],
445 "Leaking page directory entry %d (%p)\n",
446 i
, pd
->page_table
[i
]);
447 pd
->page_table
[i
] = pt
;
454 unmap_and_free_pt(pd
->page_table
[i
], dev
);
458 static void unmap_and_free_pd(struct i915_page_directory
*pd
,
459 struct drm_device
*dev
)
462 i915_dma_unmap_single(pd
, dev
);
463 __free_page(pd
->page
);
464 kfree(pd
->used_pdes
);
469 static struct i915_page_directory
*alloc_pd_single(struct drm_device
*dev
)
471 struct i915_page_directory
*pd
;
474 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
476 return ERR_PTR(-ENOMEM
);
478 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
479 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
483 pd
->page
= alloc_page(GFP_KERNEL
);
487 ret
= i915_dma_map_single(pd
, dev
);
494 __free_page(pd
->page
);
496 kfree(pd
->used_pdes
);
503 /* Broadwell Page Directory Pointer Descriptors */
504 static int gen8_write_pdp(struct intel_engine_cs
*ring
,
512 ret
= intel_ring_begin(ring
, 6);
516 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
517 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
518 intel_ring_emit(ring
, upper_32_bits(addr
));
519 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
520 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
521 intel_ring_emit(ring
, lower_32_bits(addr
));
522 intel_ring_advance(ring
);
527 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
528 struct intel_engine_cs
*ring
)
532 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
533 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[i
];
534 dma_addr_t pd_daddr
= pd
? pd
->daddr
: ppgtt
->scratch_pd
->daddr
;
535 /* The page directory might be NULL, but we need to clear out
536 * whatever the previous context might have used. */
537 ret
= gen8_write_pdp(ring
, i
, pd_daddr
);
545 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
550 struct i915_hw_ppgtt
*ppgtt
=
551 container_of(vm
, struct i915_hw_ppgtt
, base
);
552 gen8_pte_t
*pt_vaddr
, scratch_pte
;
553 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
554 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
555 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
556 unsigned num_entries
= length
>> PAGE_SHIFT
;
557 unsigned last_pte
, i
;
559 scratch_pte
= gen8_pte_encode(ppgtt
->base
.scratch
.addr
,
560 I915_CACHE_LLC
, use_scratch
);
562 while (num_entries
) {
563 struct i915_page_directory
*pd
;
564 struct i915_page_table
*pt
;
565 struct vm_page
*page_table
;
567 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
570 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
572 if (WARN_ON(!pd
->page_table
[pde
]))
575 pt
= pd
->page_table
[pde
];
577 if (WARN_ON(!pt
->page
))
580 page_table
= pt
->page
;
582 last_pte
= pte
+ num_entries
;
583 if (last_pte
> GEN8_PTES
)
584 last_pte
= GEN8_PTES
;
586 pt_vaddr
= kmap_atomic(page_table
);
588 for (i
= pte
; i
< last_pte
; i
++) {
589 pt_vaddr
[i
] = scratch_pte
;
593 if (!HAS_LLC(ppgtt
->base
.dev
))
594 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
595 kunmap_atomic(pt_vaddr
);
598 if (++pde
== I915_PDES
) {
605 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
606 struct sg_table
*pages
,
608 enum i915_cache_level cache_level
, u32 unused
)
610 struct i915_hw_ppgtt
*ppgtt
=
611 container_of(vm
, struct i915_hw_ppgtt
, base
);
612 gen8_pte_t
*pt_vaddr
;
613 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
614 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
615 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
616 struct sg_page_iter sg_iter
;
620 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
621 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
624 if (pt_vaddr
== NULL
) {
625 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
626 struct i915_page_table
*pt
= pd
->page_table
[pde
];
627 struct vm_page
*page_table
= pt
->page
;
629 pt_vaddr
= kmap_atomic(page_table
);
633 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
635 if (++pte
== GEN8_PTES
) {
636 if (!HAS_LLC(ppgtt
->base
.dev
))
637 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
638 kunmap_atomic(pt_vaddr
);
640 if (++pde
== I915_PDES
) {
648 if (!HAS_LLC(ppgtt
->base
.dev
))
649 drm_clflush_virt_range(pt_vaddr
, PAGE_SIZE
);
650 kunmap_atomic(pt_vaddr
);
654 static void __gen8_do_map_pt(gen8_pde_t
* const pde
,
655 struct i915_page_table
*pt
,
656 struct drm_device
*dev
)
659 gen8_pde_encode(dev
, pt
->daddr
, I915_CACHE_LLC
);
663 static void gen8_initialize_pd(struct i915_address_space
*vm
,
664 struct i915_page_directory
*pd
)
666 struct i915_hw_ppgtt
*ppgtt
=
667 container_of(vm
, struct i915_hw_ppgtt
, base
);
668 gen8_pde_t
*page_directory
;
669 struct i915_page_table
*pt
;
672 page_directory
= kmap_atomic(pd
->page
);
673 pt
= ppgtt
->scratch_pt
;
674 for (i
= 0; i
< I915_PDES
; i
++)
675 /* Map the PDE to the page table */
676 __gen8_do_map_pt(page_directory
+ i
, pt
, vm
->dev
);
678 if (!HAS_LLC(vm
->dev
))
679 drm_clflush_virt_range(page_directory
, PAGE_SIZE
);
680 kunmap_atomic(page_directory
);
683 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
690 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
691 if (WARN_ON(!pd
->page_table
[i
]))
694 unmap_and_free_pt(pd
->page_table
[i
], dev
);
695 pd
->page_table
[i
] = NULL
;
699 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
701 struct i915_hw_ppgtt
*ppgtt
=
702 container_of(vm
, struct i915_hw_ppgtt
, base
);
705 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
706 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
709 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
710 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
713 unmap_and_free_pd(ppgtt
->scratch_pd
, ppgtt
->base
.dev
);
714 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
718 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
719 * @ppgtt: Master ppgtt structure.
720 * @pd: Page directory for this address range.
721 * @start: Starting virtual address to begin allocations.
722 * @length Size of the allocations.
723 * @new_pts: Bitmap set by function with new allocations. Likely used by the
724 * caller to free on error.
726 * Allocate the required number of page tables. Extremely similar to
727 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
728 * the page directory boundary (instead of the page directory pointer). That
729 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
730 * possible, and likely that the caller will need to use multiple calls of this
731 * function to achieve the appropriate allocation.
733 * Return: 0 if success; negative error code otherwise.
735 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
736 struct i915_page_directory
*pd
,
739 unsigned long *new_pts
)
741 struct drm_device
*dev
= ppgtt
->base
.dev
;
742 struct i915_page_table
*pt
;
746 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
747 /* Don't reallocate page tables */
749 /* Scratch is never allocated this way */
750 WARN_ON(pt
== ppgtt
->scratch_pt
);
754 pt
= alloc_pt_single(dev
);
758 gen8_initialize_pt(&ppgtt
->base
, pt
);
759 pd
->page_table
[pde
] = pt
;
760 set_bit(pde
, new_pts
);
766 for_each_set_bit(pde
, new_pts
, I915_PDES
)
767 unmap_and_free_pt(pd
->page_table
[pde
], dev
);
773 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
774 * @ppgtt: Master ppgtt structure.
775 * @pdp: Page directory pointer for this address range.
776 * @start: Starting virtual address to begin allocations.
777 * @length Size of the allocations.
778 * @new_pds Bitmap set by function with new allocations. Likely used by the
779 * caller to free on error.
781 * Allocate the required number of page directories starting at the pde index of
782 * @start, and ending at the pde index @start + @length. This function will skip
783 * over already allocated page directories within the range, and only allocate
784 * new ones, setting the appropriate pointer within the pdp as well as the
785 * correct position in the bitmap @new_pds.
787 * The function will only allocate the pages within the range for a give page
788 * directory pointer. In other words, if @start + @length straddles a virtually
789 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
790 * required by the caller, This is not currently possible, and the BUG in the
791 * code will prevent it.
793 * Return: 0 if success; negative error code otherwise.
795 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
796 struct i915_page_directory_pointer
*pdp
,
799 unsigned long *new_pds
)
801 struct drm_device
*dev
= ppgtt
->base
.dev
;
802 struct i915_page_directory
*pd
;
806 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
808 /* FIXME: upper bound must not overflow 32 bits */
809 WARN_ON((start
+ length
) > (1ULL << 32));
811 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
815 pd
= alloc_pd_single(dev
);
819 gen8_initialize_pd(&ppgtt
->base
, pd
);
820 pdp
->page_directory
[pdpe
] = pd
;
821 set_bit(pdpe
, new_pds
);
827 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
828 unmap_and_free_pd(pdp
->page_directory
[pdpe
], dev
);
834 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
838 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
844 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
845 * of these are based on the number of PDPEs in the system.
848 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
849 unsigned long ***new_pts
)
855 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
859 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
865 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
866 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
867 sizeof(unsigned long), GFP_KERNEL
);
878 free_gen8_temp_bitmaps(pds
, pts
);
882 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
886 struct i915_hw_ppgtt
*ppgtt
=
887 container_of(vm
, struct i915_hw_ppgtt
, base
);
888 unsigned long *new_page_dirs
, **new_page_tables
;
889 struct i915_page_directory
*pd
;
890 const uint64_t orig_start
= start
;
891 const uint64_t orig_length
= length
;
896 /* Wrap is never okay since we can only represent 48b, and we don't
897 * actually use the other side of the canonical address space.
899 if (WARN_ON(start
+ length
< start
))
902 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
906 /* Do the allocations first so we can easily bail out */
907 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
910 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
914 /* For every page directory referenced, allocate page tables */
915 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
916 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
917 new_page_tables
[pdpe
]);
923 length
= orig_length
;
925 /* Allocations have completed successfully, so set the bitmaps, and do
927 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
928 gen8_pde_t
*const page_directory
= kmap_atomic(pd
->page
);
929 struct i915_page_table
*pt
;
930 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
931 uint64_t pd_start
= start
;
934 /* Every pd should be allocated, we just did that above. */
937 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
938 /* Same reasoning as pd */
941 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
943 /* Set our used ptes within the page table */
944 bitmap_set(pt
->used_ptes
,
945 gen8_pte_index(pd_start
),
946 gen8_pte_count(pd_start
, pd_len
));
948 /* Our pde is now pointing to the pagetable, pt */
949 set_bit(pde
, pd
->used_pdes
);
951 /* Map the PDE to the page table */
952 __gen8_do_map_pt(page_directory
+ pde
, pt
, vm
->dev
);
954 /* NB: We haven't yet mapped ptes to pages. At this
955 * point we're still relying on insert_entries() */
958 if (!HAS_LLC(vm
->dev
))
959 drm_clflush_virt_range(page_directory
, PAGE_SIZE
);
961 kunmap_atomic(page_directory
);
963 set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
966 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
971 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
972 unmap_and_free_pt(ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
], vm
->dev
);
975 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
976 unmap_and_free_pd(ppgtt
->pdp
.page_directory
[pdpe
], vm
->dev
);
978 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
983 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
984 * with a net effect resembling a 2-level page table in normal x86 terms. Each
985 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
989 static int gen8_ppgtt_init_common(struct i915_hw_ppgtt
*ppgtt
, uint64_t size
)
991 ppgtt
->scratch_pt
= alloc_pt_single(ppgtt
->base
.dev
);
992 if (IS_ERR(ppgtt
->scratch_pt
))
993 return PTR_ERR(ppgtt
->scratch_pt
);
995 ppgtt
->scratch_pd
= alloc_pd_single(ppgtt
->base
.dev
);
996 if (IS_ERR(ppgtt
->scratch_pd
))
997 return PTR_ERR(ppgtt
->scratch_pd
);
999 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1000 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->scratch_pd
);
1002 ppgtt
->base
.start
= 0;
1003 ppgtt
->base
.total
= size
;
1004 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1005 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1006 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1007 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1008 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1010 ppgtt
->switch_mm
= gen8_mm_switch
;
1015 static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1017 struct drm_device
*dev
= ppgtt
->base
.dev
;
1018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1019 uint64_t start
= 0, size
= dev_priv
->gtt
.base
.total
;
1022 ret
= gen8_ppgtt_init_common(ppgtt
, dev_priv
->gtt
.base
.total
);
1026 /* Aliasing PPGTT has to always work and be mapped because of the way we
1027 * use RESTORE_INHIBIT in the context switch. This will be fixed
1029 ret
= gen8_alloc_va_range(&ppgtt
->base
, start
, size
);
1031 unmap_and_free_pd(ppgtt
->scratch_pd
, ppgtt
->base
.dev
);
1032 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1036 ppgtt
->base
.allocate_va_range
= NULL
;
1037 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1043 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1044 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1045 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1049 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1051 ppgtt
->scratch_pt
= alloc_pt_single(ppgtt
->base
.dev
);
1052 if (IS_ERR(ppgtt
->scratch_pt
))
1053 return PTR_ERR(ppgtt
->scratch_pt
);
1055 ppgtt
->scratch_pd
= alloc_pd_single(ppgtt
->base
.dev
);
1056 if (IS_ERR(ppgtt
->scratch_pd
))
1057 return PTR_ERR(ppgtt
->scratch_pd
);
1059 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1060 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->scratch_pd
);
1062 ppgtt
->base
.start
= 0;
1063 ppgtt
->base
.total
= 1ULL << 32;
1064 #define CONFIG_X86_32 0
1065 if (IS_ENABLED(CONFIG_X86_32
))
1066 /* While we have a proliferation of size_t variables
1067 * we cannot represent the full ppgtt size on 32bit,
1068 * so limit it to the same size as the GGTT (currently
1071 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
1072 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1073 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1074 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1075 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1076 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1077 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1079 ppgtt
->switch_mm
= gen8_mm_switch
;
1084 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1086 struct i915_address_space
*vm
= &ppgtt
->base
;
1087 struct i915_page_table
*unused
;
1088 gen6_pte_t scratch_pte
;
1090 uint32_t pte
, pde
, temp
;
1091 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1093 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
1095 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1097 gen6_pte_t
*pt_vaddr
;
1098 dma_addr_t pt_addr
= ppgtt
->pd
.page_table
[pde
]->daddr
;
1099 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1100 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1102 if (pd_entry
!= expected
)
1103 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1107 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1109 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[pde
]->page
);
1110 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1112 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1116 for (i
= 0; i
< 4; i
++)
1117 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1122 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1123 for (i
= 0; i
< 4; i
++) {
1124 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1125 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1127 seq_puts(m
, " SCRATCH ");
1131 kunmap_atomic(pt_vaddr
);
1135 /* Write pde (index) from the page directory @pd to the page table @pt */
1136 static void gen6_write_pde(struct i915_page_directory
*pd
,
1137 const int pde
, struct i915_page_table
*pt
)
1139 /* Caller needs to make sure the write completes if necessary */
1140 struct i915_hw_ppgtt
*ppgtt
=
1141 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1144 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt
->daddr
);
1145 pd_entry
|= GEN6_PDE_VALID
;
1147 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1150 /* Write all the page tables found in the ppgtt structure to incrementing page
1152 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1153 struct i915_page_directory
*pd
,
1154 uint32_t start
, uint32_t length
)
1156 struct i915_page_table
*pt
;
1159 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1160 gen6_write_pde(pd
, pde
, pt
);
1162 /* Make sure write is complete before other code can use this page
1163 * table. Also require for WC mapped PTEs */
1164 readl(dev_priv
->gtt
.gsm
);
1167 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1169 BUG_ON(ppgtt
->pd
.pd_offset
& 0x3f);
1171 return (ppgtt
->pd
.pd_offset
/ 64) << 16;
1174 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1175 struct intel_engine_cs
*ring
)
1179 /* NB: TLBs must be flushed and invalidated before a switch */
1180 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1184 ret
= intel_ring_begin(ring
, 6);
1188 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1189 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1190 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1191 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1192 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1193 intel_ring_emit(ring
, MI_NOOP
);
1194 intel_ring_advance(ring
);
1199 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1200 struct intel_engine_cs
*ring
)
1202 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1204 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1205 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1209 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1210 struct intel_engine_cs
*ring
)
1214 /* NB: TLBs must be flushed and invalidated before a switch */
1215 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1219 ret
= intel_ring_begin(ring
, 6);
1223 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1224 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1225 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1226 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1227 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1228 intel_ring_emit(ring
, MI_NOOP
);
1229 intel_ring_advance(ring
);
1231 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1232 if (ring
->id
!= RCS
) {
1233 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1241 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1242 struct intel_engine_cs
*ring
)
1244 struct drm_device
*dev
= ppgtt
->base
.dev
;
1245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1248 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1249 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1251 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1256 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 struct intel_engine_cs
*ring
;
1262 for_each_ring(ring
, dev_priv
, j
) {
1263 I915_WRITE(RING_MODE_GEN7(ring
),
1264 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1268 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1271 struct intel_engine_cs
*ring
;
1272 uint32_t ecochk
, ecobits
;
1275 ecobits
= I915_READ(GAC_ECO_BITS
);
1276 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1278 ecochk
= I915_READ(GAM_ECOCHK
);
1279 if (IS_HASWELL(dev
)) {
1280 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1282 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1283 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1285 I915_WRITE(GAM_ECOCHK
, ecochk
);
1287 for_each_ring(ring
, dev_priv
, i
) {
1288 /* GFX_MODE is per-ring on gen7+ */
1289 I915_WRITE(RING_MODE_GEN7(ring
),
1290 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1294 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1297 uint32_t ecochk
, gab_ctl
, ecobits
;
1299 ecobits
= I915_READ(GAC_ECO_BITS
);
1300 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1301 ECOBITS_PPGTT_CACHE64B
);
1303 gab_ctl
= I915_READ(GAB_CTL
);
1304 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1306 ecochk
= I915_READ(GAM_ECOCHK
);
1307 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1309 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1312 /* PPGTT support for Sandybdrige/Gen6 and later */
1313 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1318 struct i915_hw_ppgtt
*ppgtt
=
1319 container_of(vm
, struct i915_hw_ppgtt
, base
);
1320 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1321 unsigned first_entry
= start
>> PAGE_SHIFT
;
1322 unsigned num_entries
= length
>> PAGE_SHIFT
;
1323 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1324 unsigned first_pte
= first_entry
% GEN6_PTES
;
1325 unsigned last_pte
, i
;
1327 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, true, 0);
1329 while (num_entries
) {
1330 last_pte
= first_pte
+ num_entries
;
1331 if (last_pte
> GEN6_PTES
)
1332 last_pte
= GEN6_PTES
;
1334 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->page
);
1336 for (i
= first_pte
; i
< last_pte
; i
++)
1337 pt_vaddr
[i
] = scratch_pte
;
1339 kunmap_atomic(pt_vaddr
);
1341 num_entries
-= last_pte
- first_pte
;
1347 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1348 struct sg_table
*pages
,
1350 enum i915_cache_level cache_level
, u32 flags
)
1352 struct i915_hw_ppgtt
*ppgtt
=
1353 container_of(vm
, struct i915_hw_ppgtt
, base
);
1354 gen6_pte_t
*pt_vaddr
;
1355 unsigned first_entry
= start
>> PAGE_SHIFT
;
1356 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1357 unsigned act_pte
= first_entry
% GEN6_PTES
;
1358 struct sg_page_iter sg_iter
;
1361 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1362 if (pt_vaddr
== NULL
)
1363 pt_vaddr
= kmap_atomic(ppgtt
->pd
.page_table
[act_pt
]->page
);
1366 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1367 cache_level
, true, flags
);
1369 if (++act_pte
== GEN6_PTES
) {
1370 kunmap_atomic(pt_vaddr
);
1377 kunmap_atomic(pt_vaddr
);
1380 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1381 * are switching between contexts with the same LRCA, we also must do a force
1384 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1386 /* If current vm != vm, */
1387 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1390 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1391 struct i915_page_table
*pt
)
1393 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1396 WARN_ON(vm
->scratch
.addr
== 0);
1398 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
,
1399 I915_CACHE_LLC
, true, 0);
1401 pt_vaddr
= kmap_atomic(pt
->page
);
1403 for (i
= 0; i
< GEN6_PTES
; i
++)
1404 pt_vaddr
[i
] = scratch_pte
;
1406 kunmap_atomic(pt_vaddr
);
1409 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1410 uint64_t start
, uint64_t length
)
1412 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1413 struct drm_device
*dev
= vm
->dev
;
1414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1415 struct i915_hw_ppgtt
*ppgtt
=
1416 container_of(vm
, struct i915_hw_ppgtt
, base
);
1417 struct i915_page_table
*pt
;
1418 const uint32_t start_save
= start
, length_save
= length
;
1422 WARN_ON(upper_32_bits(start
));
1424 bitmap_zero(new_page_tables
, I915_PDES
);
1426 /* The allocation is done in two stages so that we can bail out with
1427 * minimal amount of pain. The first stage finds new page tables that
1428 * need allocation. The second stage marks use ptes within the page
1431 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1432 if (pt
!= ppgtt
->scratch_pt
) {
1433 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1437 /* We've already allocated a page table */
1438 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1440 pt
= alloc_pt_single(dev
);
1446 gen6_initialize_pt(vm
, pt
);
1448 ppgtt
->pd
.page_table
[pde
] = pt
;
1449 set_bit(pde
, new_page_tables
);
1450 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1454 length
= length_save
;
1456 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1457 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1459 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1460 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1461 gen6_pte_count(start
, length
));
1463 if (test_and_clear_bit(pde
, new_page_tables
))
1464 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1466 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1467 gen6_pte_index(start
),
1468 gen6_pte_count(start
, length
),
1470 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1474 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1476 /* Make sure write is complete before other code can use this page
1477 * table. Also require for WC mapped PTEs */
1478 readl(dev_priv
->gtt
.gsm
);
1480 mark_tlbs_dirty(ppgtt
);
1484 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1485 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1487 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1488 unmap_and_free_pt(pt
, vm
->dev
);
1491 mark_tlbs_dirty(ppgtt
);
1495 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1497 struct i915_hw_ppgtt
*ppgtt
=
1498 container_of(vm
, struct i915_hw_ppgtt
, base
);
1499 struct i915_page_table
*pt
;
1503 drm_mm_remove_node(&ppgtt
->node
);
1505 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1506 if (pt
!= ppgtt
->scratch_pt
)
1507 unmap_and_free_pt(pt
, ppgtt
->base
.dev
);
1510 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1511 unmap_and_free_pd(&ppgtt
->pd
, ppgtt
->base
.dev
);
1514 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1516 struct drm_device
*dev
= ppgtt
->base
.dev
;
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1518 bool retried
= false;
1521 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1522 * allocator works in address space sizes, so it's multiplied by page
1523 * size. We allocate at the top of the GTT to avoid fragmentation.
1525 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1526 ppgtt
->scratch_pt
= alloc_pt_single(ppgtt
->base
.dev
);
1527 if (IS_ERR(ppgtt
->scratch_pt
))
1528 return PTR_ERR(ppgtt
->scratch_pt
);
1530 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1533 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1534 &ppgtt
->node
, GEN6_PD_SIZE
,
1536 0, dev_priv
->gtt
.base
.total
,
1538 if (ret
== -ENOSPC
&& !retried
) {
1539 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1540 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1542 0, dev_priv
->gtt
.base
.total
,
1555 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1556 DRM_DEBUG("Forced to use aperture for PDEs\n");
1561 unmap_and_free_pt(ppgtt
->scratch_pt
, ppgtt
->base
.dev
);
1565 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1567 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1570 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1571 uint64_t start
, uint64_t length
)
1573 struct i915_page_table
*unused
;
1576 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1577 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1580 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
, bool aliasing
)
1582 struct drm_device
*dev
= ppgtt
->base
.dev
;
1583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1588 ppgtt
->switch_mm
= gen6_mm_switch
;
1589 } else if (IS_HASWELL(dev
)) {
1590 ppgtt
->switch_mm
= hsw_mm_switch
;
1591 } else if (IS_GEN7(dev
)) {
1592 ppgtt
->switch_mm
= gen7_mm_switch
;
1596 if (intel_vgpu_active(dev
))
1597 ppgtt
->switch_mm
= vgpu_mm_switch
;
1599 ret
= gen6_ppgtt_alloc(ppgtt
);
1604 /* preallocate all pts */
1605 ret
= alloc_pt_range(&ppgtt
->pd
, 0, I915_PDES
,
1609 gen6_ppgtt_cleanup(&ppgtt
->base
);
1614 ppgtt
->base
.allocate_va_range
= aliasing
? NULL
: gen6_alloc_va_range
;
1615 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1616 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1617 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1618 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1619 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1620 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1621 ppgtt
->base
.start
= 0;
1622 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1623 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1625 ppgtt
->pd
.pd_offset
=
1626 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1628 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1629 ppgtt
->pd
.pd_offset
/ sizeof(gen6_pte_t
);
1632 ppgtt
->base
.clear_range(&ppgtt
->base
, 0, ppgtt
->base
.total
, true);
1634 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1636 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1638 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1639 ppgtt
->node
.size
>> 20,
1640 ppgtt
->node
.start
/ PAGE_SIZE
);
1642 DRM_DEBUG("Adding PPGTT at offset %x\n",
1643 ppgtt
->pd
.pd_offset
<< 10);
1648 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
,
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 ppgtt
->base
.dev
= dev
;
1654 ppgtt
->base
.scratch
= dev_priv
->gtt
.base
.scratch
;
1656 if (INTEL_INFO(dev
)->gen
< 8)
1657 return gen6_ppgtt_init(ppgtt
, aliasing
);
1659 return gen8_aliasing_ppgtt_init(ppgtt
);
1661 return gen8_ppgtt_init(ppgtt
);
1663 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1668 ret
= __hw_ppgtt_init(dev
, ppgtt
, false);
1670 kref_init(&ppgtt
->ref
);
1671 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1673 i915_init_vm(dev_priv
, &ppgtt
->base
);
1679 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1682 struct intel_engine_cs
*ring
;
1683 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1686 /* In the case of execlists, PPGTT is enabled by the context descriptor
1687 * and the PDPs are contained within the context itself. We don't
1688 * need to do anything here. */
1689 if (i915
.enable_execlists
)
1692 if (!USES_PPGTT(dev
))
1696 gen6_ppgtt_enable(dev
);
1697 else if (IS_GEN7(dev
))
1698 gen7_ppgtt_enable(dev
);
1699 else if (INTEL_INFO(dev
)->gen
>= 8)
1700 gen8_ppgtt_enable(dev
);
1702 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1705 for_each_ring(ring
, dev_priv
, i
) {
1706 ret
= ppgtt
->switch_mm(ppgtt
, ring
);
1714 struct i915_hw_ppgtt
*
1715 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1717 struct i915_hw_ppgtt
*ppgtt
;
1720 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1722 return ERR_PTR(-ENOMEM
);
1724 ret
= i915_ppgtt_init(dev
, ppgtt
);
1727 return ERR_PTR(ret
);
1730 ppgtt
->file_priv
= fpriv
;
1732 trace_i915_ppgtt_create(&ppgtt
->base
);
1737 void i915_ppgtt_release(struct kref
*kref
)
1739 struct i915_hw_ppgtt
*ppgtt
=
1740 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1742 trace_i915_ppgtt_release(&ppgtt
->base
);
1744 /* vmas should already be unbound */
1745 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1746 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1748 list_del(&ppgtt
->base
.global_link
);
1749 drm_mm_takedown(&ppgtt
->base
.mm
);
1751 ppgtt
->base
.cleanup(&ppgtt
->base
);
1755 extern int intel_iommu_gfx_mapped
;
1756 /* Certain Gen5 chipsets require require idling the GPU before
1757 * unmapping anything from the GTT when VT-d is enabled.
1759 static bool needs_idle_maps(struct drm_device
*dev
)
1761 #ifdef CONFIG_INTEL_IOMMU
1762 /* Query intel_iommu to see if we need the workaround. Presumably that
1765 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1771 static bool do_idling(struct drm_i915_private
*dev_priv
)
1773 bool ret
= dev_priv
->mm
.interruptible
;
1775 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1776 dev_priv
->mm
.interruptible
= false;
1777 if (i915_gpu_idle(dev_priv
->dev
)) {
1778 DRM_ERROR("Couldn't idle GPU\n");
1779 /* Wait a bit, in hopes it avoids the hang */
1787 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1789 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1790 dev_priv
->mm
.interruptible
= interruptible
;
1793 void i915_check_and_clear_faults(struct drm_device
*dev
)
1795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1796 struct intel_engine_cs
*ring
;
1799 if (INTEL_INFO(dev
)->gen
< 6)
1802 for_each_ring(ring
, dev_priv
, i
) {
1804 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1805 if (fault_reg
& RING_FAULT_VALID
) {
1807 DRM_DEBUG_DRIVER("Unexpected fault\n"
1809 "\tAddress space: %s\n"
1812 fault_reg
& PAGE_MASK
,
1813 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1814 RING_FAULT_SRCID(fault_reg
),
1815 RING_FAULT_FAULT_TYPE(fault_reg
));
1817 I915_WRITE(RING_FAULT_REG(ring
),
1818 fault_reg
& ~RING_FAULT_VALID
);
1821 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1824 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1826 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1827 intel_gtt_chipset_flush();
1829 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1830 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1834 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1838 /* Don't bother messing with faults pre GEN6 as we have little
1839 * documentation supporting that it's a good idea.
1841 if (INTEL_INFO(dev
)->gen
< 6)
1844 i915_check_and_clear_faults(dev
);
1846 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1847 dev_priv
->gtt
.base
.start
,
1848 dev_priv
->gtt
.base
.total
,
1851 i915_ggtt_flush(dev_priv
);
1854 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1856 if (!dma_map_sg(obj
->base
.dev
->pdev
->dev
,
1857 obj
->pages
->sgl
, obj
->pages
->nents
,
1858 PCI_DMA_BIDIRECTIONAL
))
1864 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1869 iowrite32((u32
)pte
, addr
);
1870 iowrite32(pte
>> 32, addr
+ 4);
1874 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1875 struct sg_table
*st
,
1877 enum i915_cache_level level
, u32 unused
)
1879 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1880 unsigned first_entry
= start
>> PAGE_SHIFT
;
1881 gen8_pte_t __iomem
*gtt_entries
=
1882 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1884 struct sg_page_iter sg_iter
;
1885 dma_addr_t addr
= 0; /* shut up gcc */
1887 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1888 addr
= sg_dma_address(sg_iter
.sg
) +
1889 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1890 gen8_set_pte(>t_entries
[i
],
1891 gen8_pte_encode(addr
, level
, true));
1896 * XXX: This serves as a posting read to make sure that the PTE has
1897 * actually been updated. There is some concern that even though
1898 * registers and PTEs are within the same BAR that they are potentially
1899 * of NUMA access patterns. Therefore, even with the way we assume
1900 * hardware should work, we must keep this posting read for paranoia.
1903 WARN_ON(readq(>t_entries
[i
-1])
1904 != gen8_pte_encode(addr
, level
, true));
1906 /* This next bit makes the above posting read even more important. We
1907 * want to flush the TLBs only after we're certain all the PTE updates
1910 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1911 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1915 * Binds an object into the global gtt with the specified cache level. The object
1916 * will be accessible to the GPU via commands whose operands reference offsets
1917 * within the global GTT as well as accessible by the GPU through the GMADR
1918 * mapped BAR (dev_priv->mm.gtt->gtt).
1920 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1921 struct sg_table
*st
,
1923 enum i915_cache_level level
, u32 flags
)
1925 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1926 unsigned first_entry
= start
>> PAGE_SHIFT
;
1927 gen6_pte_t __iomem
*gtt_entries
=
1928 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1930 struct sg_page_iter sg_iter
;
1931 dma_addr_t addr
= 0;
1933 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1934 addr
= sg_page_iter_dma_address(&sg_iter
);
1935 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1939 /* XXX: This serves as a posting read to make sure that the PTE has
1940 * actually been updated. There is some concern that even though
1941 * registers and PTEs are within the same BAR that they are potentially
1942 * of NUMA access patterns. Therefore, even with the way we assume
1943 * hardware should work, we must keep this posting read for paranoia.
1946 unsigned long gtt
= readl(>t_entries
[i
-1]);
1947 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1950 /* This next bit makes the above posting read even more important. We
1951 * want to flush the TLBs only after we're certain all the PTE updates
1954 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1955 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1958 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1963 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1964 unsigned first_entry
= start
>> PAGE_SHIFT
;
1965 unsigned num_entries
= length
>> PAGE_SHIFT
;
1966 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1967 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1968 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1971 if (WARN(num_entries
> max_entries
,
1972 "First entry = %d; Num entries = %d (max=%d)\n",
1973 first_entry
, num_entries
, max_entries
))
1974 num_entries
= max_entries
;
1976 scratch_pte
= gen8_pte_encode(vm
->scratch
.addr
,
1979 for (i
= 0; i
< num_entries
; i
++)
1980 gen8_set_pte(>t_base
[i
], scratch_pte
);
1984 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1989 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1990 unsigned first_entry
= start
>> PAGE_SHIFT
;
1991 unsigned num_entries
= length
>> PAGE_SHIFT
;
1992 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1993 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1994 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1997 if (WARN(num_entries
> max_entries
,
1998 "First entry = %d; Num entries = %d (max=%d)\n",
1999 first_entry
, num_entries
, max_entries
))
2000 num_entries
= max_entries
;
2002 scratch_pte
= vm
->pte_encode(vm
->scratch
.addr
, I915_CACHE_LLC
, use_scratch
, 0);
2004 for (i
= 0; i
< num_entries
; i
++)
2005 iowrite32(scratch_pte
, >t_base
[i
]);
2009 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2010 struct sg_table
*pages
,
2012 enum i915_cache_level cache_level
, u32 unused
)
2014 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2015 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2017 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2020 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2025 unsigned first_entry
= start
>> PAGE_SHIFT
;
2026 unsigned num_entries
= length
>> PAGE_SHIFT
;
2027 intel_gtt_clear_range(first_entry
, num_entries
);
2030 static int ggtt_bind_vma(struct i915_vma
*vma
,
2031 enum i915_cache_level cache_level
,
2034 struct drm_device
*dev
= vma
->vm
->dev
;
2035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2036 struct drm_i915_gem_object
*obj
= vma
->obj
;
2037 struct sg_table
*pages
= obj
->pages
;
2041 ret
= i915_get_ggtt_vma_pages(vma
);
2044 pages
= vma
->ggtt_view
.pages
;
2046 /* Currently applicable only to VLV */
2048 pte_flags
|= PTE_READ_ONLY
;
2051 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
2052 vma
->vm
->insert_entries(vma
->vm
, pages
,
2054 cache_level
, pte_flags
);
2056 /* Note the inconsistency here is due to absence of the
2057 * aliasing ppgtt on gen4 and earlier. Though we always
2058 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2059 * without the appgtt, we cannot honour that request and so
2060 * must substitute it with a global binding. Since we do this
2061 * behind the upper layers back, we need to explicitly set
2062 * the bound flag ourselves.
2064 vma
->bound
|= GLOBAL_BIND
;
2068 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
2069 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2070 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
2072 cache_level
, pte_flags
);
2078 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2080 struct drm_device
*dev
= vma
->vm
->dev
;
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 struct drm_i915_gem_object
*obj
= vma
->obj
;
2083 const uint64_t size
= min_t(uint64_t,
2087 if (vma
->bound
& GLOBAL_BIND
) {
2088 vma
->vm
->clear_range(vma
->vm
,
2094 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
2095 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2097 appgtt
->base
.clear_range(&appgtt
->base
,
2104 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2106 struct drm_device
*dev
= obj
->base
.dev
;
2107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 interruptible
= do_idling(dev_priv
);
2112 dma_unmap_sg(dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2113 PCI_DMA_BIDIRECTIONAL
);
2115 undo_idling(dev_priv
, interruptible
);
2118 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2119 unsigned long color
,
2123 if (node
->color
!= color
)
2126 if (!list_empty(&node
->node_list
)) {
2127 node
= list_entry(node
->node_list
.next
,
2130 if (node
->allocated
&& node
->color
!= color
)
2135 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
2136 unsigned long start
,
2137 unsigned long mappable_end
,
2140 /* Let GEM Manage all of the aperture.
2142 * However, leave one page at the end still bound to the scratch page.
2143 * There are a number of places where the hardware apparently prefetches
2144 * past the end of the object, and we've seen multiple hangs with the
2145 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2146 * aperture. One page should be enough to keep any prefetching inside
2149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2150 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2151 unsigned long mappable
;
2153 struct drm_mm_node
*entry
;
2154 struct drm_i915_gem_object
*obj
;
2155 unsigned long hole_start
, hole_end
;
2158 mappable
= min(end
, mappable_end
) - start
;
2159 BUG_ON(mappable_end
> end
);
2161 /* Subtract the guard page ... */
2162 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2164 dev_priv
->gtt
.base
.start
= start
;
2165 dev_priv
->gtt
.base
.total
= end
- start
;
2167 if (intel_vgpu_active(dev
)) {
2168 ret
= intel_vgt_balloon(dev
);
2174 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2176 /* Mark any preallocated objects as occupied */
2177 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2178 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2180 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2181 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2183 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2184 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2186 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2189 vma
->bound
|= GLOBAL_BIND
;
2192 /* Clear any non-preallocated blocks */
2193 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2194 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2195 hole_start
, hole_end
);
2196 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2197 hole_end
- hole_start
, true);
2200 #ifdef __DragonFly__
2201 device_printf(dev
->dev
,
2202 "taking over the fictitious range 0x%lx-0x%lx\n",
2203 dev_priv
->gtt
.mappable_base
+ start
, dev_priv
->gtt
.mappable_base
+ start
+ mappable
);
2204 error
= -vm_phys_fictitious_reg_range(dev_priv
->gtt
.mappable_base
+ start
,
2205 dev_priv
->gtt
.mappable_base
+ start
+ mappable
, VM_MEMATTR_WRITE_COMBINING
);
2208 /* And finally clear the reserved guard page */
2209 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2211 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2212 struct i915_hw_ppgtt
*ppgtt
;
2214 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2218 ret
= __hw_ppgtt_init(dev
, ppgtt
, true);
2220 ppgtt
->base
.cleanup(&ppgtt
->base
);
2225 if (ppgtt
->base
.allocate_va_range
)
2226 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2229 ppgtt
->base
.cleanup(&ppgtt
->base
);
2234 ppgtt
->base
.clear_range(&ppgtt
->base
,
2239 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2245 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 unsigned long gtt_size
, mappable_size
;
2250 gtt_size
= dev_priv
->gtt
.base
.total
;
2251 mappable_size
= dev_priv
->gtt
.mappable_end
;
2253 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2256 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2261 if (dev_priv
->mm
.aliasing_ppgtt
) {
2262 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2264 ppgtt
->base
.cleanup(&ppgtt
->base
);
2267 if (drm_mm_initialized(&vm
->mm
)) {
2268 if (intel_vgpu_active(dev
))
2269 intel_vgt_deballoon();
2271 drm_mm_takedown(&vm
->mm
);
2272 list_del(&vm
->global_link
);
2278 static int setup_scratch_page(struct drm_device
*dev
)
2280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2281 struct vm_page
*page
;
2282 dma_addr_t dma_addr
;
2284 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
2287 set_pages_uc(page
, 1);
2289 #ifdef CONFIG_INTEL_IOMMU
2290 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
2291 PCI_DMA_BIDIRECTIONAL
);
2292 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
2295 dma_addr
= page_to_phys(page
);
2297 dev_priv
->gtt
.base
.scratch
.page
= page
;
2298 dev_priv
->gtt
.base
.scratch
.addr
= dma_addr
;
2303 static void teardown_scratch_page(struct drm_device
*dev
)
2305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 struct vm_page
*page
= dev_priv
->gtt
.base
.scratch
.page
;
2308 set_pages_wb(page
, 1);
2309 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.base
.scratch
.addr
,
2310 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
2314 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2316 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2317 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2318 return snb_gmch_ctl
<< 20;
2321 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2323 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2324 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2326 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2328 #ifdef CONFIG_X86_32
2329 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2330 if (bdw_gmch_ctl
> 4)
2334 return bdw_gmch_ctl
<< 20;
2337 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2339 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2340 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2343 return 1 << (20 + gmch_ctrl
);
2348 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2350 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2351 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2352 return snb_gmch_ctl
<< 25; /* 32 MB units */
2355 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2357 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2358 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2359 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2362 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2364 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2365 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2368 * 0x0 to 0x10: 32MB increments starting at 0MB
2369 * 0x11 to 0x16: 4MB increments starting at 8MB
2370 * 0x17 to 0x1d: 4MB increments start at 36MB
2372 if (gmch_ctrl
< 0x11)
2373 return gmch_ctrl
<< 25;
2374 else if (gmch_ctrl
< 0x17)
2375 return (gmch_ctrl
- 0x11 + 2) << 22;
2377 return (gmch_ctrl
- 0x17 + 9) << 22;
2380 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2382 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2383 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2385 if (gen9_gmch_ctl
< 0xf0)
2386 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2388 /* 4MB increments starting at 0xf0 for 4MB */
2389 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2392 static int ggtt_probe_common(struct drm_device
*dev
,
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 phys_addr_t gtt_phys_addr
;
2399 /* For Modern GENs the PTEs and register space are split in the BAR */
2400 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2401 (pci_resource_len(dev
->pdev
, 0) / 2);
2404 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2405 * dropped. For WC mappings in general we have 64 byte burst writes
2406 * when the WC buffer is flushed, so we can't use it, but have to
2407 * resort to an uncached mapping. The WC issue is easily caught by the
2408 * readback check when writing GTT PTE entries.
2410 if (IS_BROXTON(dev
))
2411 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2413 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2414 if (!dev_priv
->gtt
.gsm
) {
2415 DRM_ERROR("Failed to map the gtt page table\n");
2419 ret
= setup_scratch_page(dev
);
2421 DRM_ERROR("Scratch setup failed\n");
2422 /* iounmap will also get called at remove, but meh */
2423 iounmap(dev_priv
->gtt
.gsm
);
2429 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2430 * bits. When using advanced contexts each context stores its own PAT, but
2431 * writing this data shouldn't be harmful even in those cases. */
2432 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2436 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2437 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2438 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2439 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2440 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2441 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2442 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2443 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2445 if (!USES_PPGTT(dev_priv
->dev
))
2446 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2447 * so RTL will always use the value corresponding to
2449 * So let's disable cache for GGTT to avoid screen corruptions.
2450 * MOCS still can be used though.
2451 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2452 * before this patch, i.e. the same uncached + snooping access
2453 * like on gen6/7 seems to be in effect.
2454 * - So this just fixes blitter/render access. Again it looks
2455 * like it's not just uncached access, but uncached + snooping.
2456 * So we can still hold onto all our assumptions wrt cpu
2457 * clflushing on LLC machines.
2459 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2461 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2462 * write would work. */
2463 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2464 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2467 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2472 * Map WB on BDW to snooped on CHV.
2474 * Only the snoop bit has meaning for CHV, the rest is
2477 * The hardware will never snoop for certain types of accesses:
2478 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2479 * - PPGTT page tables
2480 * - some other special cycles
2482 * As with BDW, we also need to consider the following for GT accesses:
2483 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2484 * so RTL will always use the value corresponding to
2486 * Which means we must set the snoop bit in PAT entry 0
2487 * in order to keep the global status page working.
2489 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2493 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2494 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2495 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2496 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2498 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2499 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2502 static int gen8_gmch_probe(struct drm_device
*dev
,
2505 phys_addr_t
*mappable_base
,
2506 unsigned long *mappable_end
)
2508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2509 unsigned int gtt_size
;
2513 /* TODO: We're not aware of mappable constraints on gen8 yet */
2514 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2515 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2518 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2519 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2522 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2524 if (INTEL_INFO(dev
)->gen
>= 9) {
2525 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2526 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2527 } else if (IS_CHERRYVIEW(dev
)) {
2528 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2529 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2531 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2532 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2535 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2537 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2538 chv_setup_private_ppat(dev_priv
);
2540 bdw_setup_private_ppat(dev_priv
);
2542 ret
= ggtt_probe_common(dev
, gtt_size
);
2544 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2545 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2546 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2547 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2552 static int gen6_gmch_probe(struct drm_device
*dev
,
2555 phys_addr_t
*mappable_base
,
2556 unsigned long *mappable_end
)
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 unsigned int gtt_size
;
2563 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2564 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2566 /* 64/512MB is the current min/max we actually know of, but this is just
2567 * a coarse sanity check.
2569 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2570 DRM_ERROR("Unknown GMADR size (%lx)\n",
2571 dev_priv
->gtt
.mappable_end
);
2576 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2577 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2579 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2581 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2583 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2584 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2586 ret
= ggtt_probe_common(dev
, gtt_size
);
2588 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2589 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2590 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2591 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2596 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2598 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2601 teardown_scratch_page(vm
->dev
);
2604 static int i915_gmch_probe(struct drm_device
*dev
,
2607 phys_addr_t
*mappable_base
,
2608 unsigned long *mappable_end
)
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2614 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2616 DRM_ERROR("failed to set up gmch\n");
2621 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2623 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2624 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2625 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2626 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2627 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2629 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2630 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2635 static void i915_gmch_remove(struct i915_address_space
*vm
)
2637 intel_gmch_remove();
2640 int i915_gem_gtt_init(struct drm_device
*dev
)
2642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2643 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2646 if (INTEL_INFO(dev
)->gen
<= 5) {
2647 gtt
->gtt_probe
= i915_gmch_probe
;
2648 gtt
->base
.cleanup
= i915_gmch_remove
;
2649 } else if (INTEL_INFO(dev
)->gen
< 8) {
2650 gtt
->gtt_probe
= gen6_gmch_probe
;
2651 gtt
->base
.cleanup
= gen6_gmch_remove
;
2652 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2653 gtt
->base
.pte_encode
= iris_pte_encode
;
2654 else if (IS_HASWELL(dev
))
2655 gtt
->base
.pte_encode
= hsw_pte_encode
;
2656 else if (IS_VALLEYVIEW(dev
))
2657 gtt
->base
.pte_encode
= byt_pte_encode
;
2658 else if (INTEL_INFO(dev
)->gen
>= 7)
2659 gtt
->base
.pte_encode
= ivb_pte_encode
;
2661 gtt
->base
.pte_encode
= snb_pte_encode
;
2663 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2664 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2667 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2668 >t
->mappable_base
, >t
->mappable_end
);
2672 gtt
->base
.dev
= dev
;
2674 /* GMADR is the PCI mmio aperture into the global GTT. */
2675 DRM_INFO("Memory usable by graphics device = %zdM\n",
2676 gtt
->base
.total
>> 20);
2677 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt
->mappable_end
>> 20);
2678 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2679 #ifdef CONFIG_INTEL_IOMMU
2680 if (intel_iommu_gfx_mapped
)
2681 DRM_INFO("VT-d active for gfx access\n");
2684 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2685 * user's requested state against the hardware/driver capabilities. We
2686 * do this now so that we can print out any log messages once rather
2687 * than every time we check intel_enable_ppgtt().
2689 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2690 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2695 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2698 struct drm_i915_gem_object
*obj
;
2699 struct i915_address_space
*vm
;
2700 struct i915_vma
*vma
;
2703 i915_check_and_clear_faults(dev
);
2705 /* First fill our portion of the GTT with scratch pages */
2706 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2707 dev_priv
->gtt
.base
.start
,
2708 dev_priv
->gtt
.base
.total
,
2711 /* Cache flush objects bound into GGTT and rebind them. */
2712 vm
= &dev_priv
->gtt
.base
;
2713 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2715 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2719 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
2726 i915_gem_clflush_object(obj
, obj
->pin_display
);
2729 if (INTEL_INFO(dev
)->gen
>= 8) {
2730 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2731 chv_setup_private_ppat(dev_priv
);
2733 bdw_setup_private_ppat(dev_priv
);
2738 if (USES_PPGTT(dev
)) {
2739 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2740 /* TODO: Perhaps it shouldn't be gen6 specific */
2742 struct i915_hw_ppgtt
*ppgtt
=
2743 container_of(vm
, struct i915_hw_ppgtt
,
2746 if (i915_is_ggtt(vm
))
2747 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2749 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2750 0, ppgtt
->base
.total
);
2754 i915_ggtt_flush(dev_priv
);
2757 static struct i915_vma
*
2758 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2759 struct i915_address_space
*vm
,
2760 const struct i915_ggtt_view
*ggtt_view
)
2762 struct i915_vma
*vma
;
2764 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2765 return ERR_PTR(-EINVAL
);
2767 vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
2769 return ERR_PTR(-ENOMEM
);
2771 INIT_LIST_HEAD(&vma
->vma_link
);
2772 INIT_LIST_HEAD(&vma
->mm_list
);
2773 INIT_LIST_HEAD(&vma
->exec_list
);
2777 if (i915_is_ggtt(vm
))
2778 vma
->ggtt_view
= *ggtt_view
;
2780 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2781 if (!i915_is_ggtt(vm
))
2782 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2788 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2789 struct i915_address_space
*vm
)
2791 struct i915_vma
*vma
;
2793 vma
= i915_gem_obj_to_vma(obj
, vm
);
2795 vma
= __i915_gem_vma_create(obj
, vm
,
2796 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2802 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2803 const struct i915_ggtt_view
*view
)
2805 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2806 struct i915_vma
*vma
;
2809 return ERR_PTR(-EINVAL
);
2811 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2817 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2824 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2825 struct sg_table
*st
)
2827 unsigned int column
, row
;
2828 unsigned int src_idx
;
2829 struct scatterlist
*sg
= st
->sgl
;
2833 for (column
= 0; column
< width
; column
++) {
2834 src_idx
= width
* (height
- 1) + column
;
2835 for (row
= 0; row
< height
; row
++) {
2837 /* We don't need the pages, but need to initialize
2838 * the entries so the sg list can be happily traversed.
2839 * The only thing we need are DMA addresses.
2841 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2842 sg_dma_address(sg
) = in
[src_idx
];
2843 sg_dma_len(sg
) = PAGE_SIZE
;
2850 static struct sg_table
*
2851 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2852 struct drm_i915_gem_object
*obj
)
2854 struct drm_device
*dev
= obj
->base
.dev
;
2855 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2856 unsigned long size
, pages
, rot_pages
;
2857 struct sg_page_iter sg_iter
;
2859 dma_addr_t
*page_addr_list
;
2860 struct sg_table
*st
;
2861 unsigned int tile_pitch
, tile_height
;
2862 unsigned int width_pages
, height_pages
;
2865 pages
= obj
->base
.size
/ PAGE_SIZE
;
2867 /* Calculate tiling geometry. */
2868 tile_height
= intel_tile_height(dev
, rot_info
->pixel_format
,
2869 rot_info
->fb_modifier
);
2870 tile_pitch
= PAGE_SIZE
/ tile_height
;
2871 width_pages
= DIV_ROUND_UP(rot_info
->pitch
, tile_pitch
);
2872 height_pages
= DIV_ROUND_UP(rot_info
->height
, tile_height
);
2873 rot_pages
= width_pages
* height_pages
;
2874 size
= rot_pages
* PAGE_SIZE
;
2876 /* Allocate a temporary list of source pages for random access. */
2877 page_addr_list
= drm_malloc_ab(pages
, sizeof(dma_addr_t
));
2878 if (!page_addr_list
)
2879 return ERR_PTR(ret
);
2881 /* Allocate target SG list. */
2882 st
= kmalloc(sizeof(*st
), M_DRM
, M_WAITOK
);
2886 ret
= sg_alloc_table(st
, rot_pages
, GFP_KERNEL
);
2890 /* Populate source page list from the object. */
2892 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2893 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2897 /* Rotate the pages. */
2898 rotate_pages(page_addr_list
, width_pages
, height_pages
, st
);
2901 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2902 size
, rot_info
->pitch
, rot_info
->height
,
2903 rot_info
->pixel_format
, width_pages
, height_pages
,
2906 drm_free_large(page_addr_list
);
2913 drm_free_large(page_addr_list
);
2916 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2917 size
, ret
, rot_info
->pitch
, rot_info
->height
,
2918 rot_info
->pixel_format
, width_pages
, height_pages
,
2920 return ERR_PTR(ret
);
2923 static struct sg_table
*
2924 intel_partial_pages(const struct i915_ggtt_view
*view
,
2925 struct drm_i915_gem_object
*obj
)
2927 struct sg_table
*st
;
2928 struct scatterlist
*sg
;
2929 struct sg_page_iter obj_sg_iter
;
2932 st
= kmalloc(sizeof(*st
), M_DRM
, M_WAITOK
);
2936 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2942 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2943 view
->params
.partial
.offset
)
2945 if (st
->nents
>= view
->params
.partial
.size
)
2948 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2949 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2950 sg_dma_len(sg
) = PAGE_SIZE
;
2961 return ERR_PTR(ret
);
2965 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2969 if (vma
->ggtt_view
.pages
)
2972 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2973 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2974 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2975 vma
->ggtt_view
.pages
=
2976 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2977 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2978 vma
->ggtt_view
.pages
=
2979 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2981 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2982 vma
->ggtt_view
.type
);
2984 if (!vma
->ggtt_view
.pages
) {
2985 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2986 vma
->ggtt_view
.type
);
2988 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2989 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2990 vma
->ggtt_view
.pages
= NULL
;
2991 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2992 vma
->ggtt_view
.type
, ret
);
2999 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3001 * @cache_level: mapping cache level
3002 * @flags: flags like global or local mapping
3004 * DMA addresses are taken from the scatter-gather table of this object (or of
3005 * this VMA in case of non-default GGTT views) and PTE entries set up.
3006 * Note that DMA addresses are also the only part of the SG table we care about.
3008 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3014 if (WARN_ON(flags
== 0))
3018 if (flags
& PIN_GLOBAL
)
3019 bind_flags
|= GLOBAL_BIND
;
3020 if (flags
& PIN_USER
)
3021 bind_flags
|= LOCAL_BIND
;
3023 if (flags
& PIN_UPDATE
)
3024 bind_flags
|= vma
->bound
;
3026 bind_flags
&= ~vma
->bound
;
3028 if (bind_flags
== 0)
3031 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
3032 trace_i915_va_alloc(vma
->vm
,
3035 VM_TO_TRACE_NAME(vma
->vm
));
3037 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3044 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3048 vma
->bound
|= bind_flags
;
3054 * i915_ggtt_view_size - Get the size of a GGTT view.
3055 * @obj: Object the view is of.
3056 * @view: The view in question.
3058 * @return The size of the GGTT view in bytes.
3061 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
3062 const struct i915_ggtt_view
*view
)
3064 if (view
->type
== I915_GGTT_VIEW_NORMAL
||
3065 view
->type
== I915_GGTT_VIEW_ROTATED
) {
3066 return obj
->base
.size
;
3067 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3068 return view
->params
.partial
.size
<< PAGE_SHIFT
;
3070 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
3071 return obj
->base
.size
;