2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
40 #define RQ_BUG_ON(expr)
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
48 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
49 struct drm_i915_gem_object
*obj
);
50 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
51 struct drm_i915_fence_reg
*fence
,
54 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
55 enum i915_cache_level level
)
57 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
60 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
62 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
65 return obj
->pin_display
;
68 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
71 i915_gem_release_mmap(obj
);
73 /* As we do not have an associated fence register, we will force
74 * a tiling change if we ever need to acquire one.
76 obj
->fence_dirty
= false;
77 obj
->fence_reg
= I915_FENCE_REG_NONE
;
80 /* some bookkeeping */
81 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
84 spin_lock(&dev_priv
->mm
.object_stat_lock
);
85 dev_priv
->mm
.object_count
++;
86 dev_priv
->mm
.object_memory
+= size
;
87 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
90 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
93 spin_lock(&dev_priv
->mm
.object_stat_lock
);
94 dev_priv
->mm
.object_count
--;
95 dev_priv
->mm
.object_memory
-= size
;
96 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
100 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
104 #define EXIT_COND (!i915_reset_in_progress(error) || \
105 i915_terminally_wedged(error))
110 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
111 * userspace. If it takes that long something really bad is going on and
112 * we should simply try to bail out and fail as gracefully as possible.
114 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
118 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
120 } else if (ret
< 0) {
128 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
137 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
141 WARN_ON(i915_verify_lists(dev
));
146 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
147 struct drm_file
*file
)
149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
150 struct drm_i915_gem_get_aperture
*args
= data
;
151 struct drm_i915_gem_object
*obj
;
155 mutex_lock(&dev
->struct_mutex
);
156 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
157 if (i915_gem_obj_is_pinned(obj
))
158 pinned
+= i915_gem_obj_ggtt_size(obj
);
159 mutex_unlock(&dev
->struct_mutex
);
161 args
->aper_size
= dev_priv
->gtt
.base
.total
;
162 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
220 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
224 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
226 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
228 /* In the event of a disaster, abandon all caches and
231 WARN_ON(ret
!= -EIO
);
232 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
235 if (obj
->madv
== I915_MADV_DONTNEED
)
239 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
240 char *vaddr
= obj
->phys_handle
->vaddr
;
243 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
247 page
= shmem_read_mapping_page(mapping
, i
);
251 dst
= kmap_atomic(page
);
252 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
253 memcpy(dst
, vaddr
, PAGE_SIZE
);
256 set_page_dirty(page
);
257 if (obj
->madv
== I915_MADV_WILLNEED
)
258 mark_page_accessed(page
);
259 page_cache_release(page
);
265 sg_free_table(obj
->pages
);
270 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
272 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
275 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
276 .get_pages
= i915_gem_object_get_pages_phys
,
277 .put_pages
= i915_gem_object_put_pages_phys
,
278 .release
= i915_gem_object_release_phys
,
283 drop_pages(struct drm_i915_gem_object
*obj
)
285 struct i915_vma
*vma
, *next
;
288 drm_gem_object_reference(&obj
->base
);
289 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
290 if (i915_vma_unbind(vma
))
293 ret
= i915_gem_object_put_pages(obj
);
294 drm_gem_object_unreference(&obj
->base
);
300 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
303 drm_dma_handle_t
*phys
;
306 if (obj
->phys_handle
) {
307 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
313 if (obj
->madv
!= I915_MADV_WILLNEED
)
317 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
332 obj
->ops
= &i915_gem_phys_ops
;
335 return i915_gem_object_get_pages(obj
);
339 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
340 struct drm_i915_gem_pwrite
*args
,
341 struct drm_file
*file_priv
)
343 struct drm_device
*dev
= obj
->base
.dev
;
344 void *vaddr
= (char *)obj
->phys_handle
->vaddr
+ args
->offset
;
345 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
348 /* We manually control the domain here and pretend that it
349 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
351 ret
= i915_gem_object_wait_rendering(obj
, false);
355 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
356 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
357 unsigned long unwritten
;
359 /* The physical object once assigned is fixed for the lifetime
360 * of the obj, so we can safely drop the lock and continue
363 mutex_unlock(&dev
->struct_mutex
);
364 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
365 mutex_lock(&dev
->struct_mutex
);
372 drm_clflush_virt_range(vaddr
, args
->size
);
373 i915_gem_chipset_flush(dev
);
376 intel_fb_obj_flush(obj
, false);
380 void *i915_gem_object_alloc(struct drm_device
*dev
)
382 return kmalloc(sizeof(struct drm_i915_gem_object
),
383 M_DRM
, M_WAITOK
| M_ZERO
);
386 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
392 i915_gem_create(struct drm_file
*file
,
393 struct drm_device
*dev
,
397 struct drm_i915_gem_object
*obj
;
401 size
= roundup(size
, PAGE_SIZE
);
405 /* Allocate the new object */
406 obj
= i915_gem_alloc_object(dev
, size
);
410 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
411 /* drop reference from allocate - handle holds it now */
412 drm_gem_object_unreference_unlocked(&obj
->base
);
421 i915_gem_dumb_create(struct drm_file
*file
,
422 struct drm_device
*dev
,
423 struct drm_mode_create_dumb
*args
)
425 /* have to work out size/pitch and return them */
426 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
427 args
->size
= args
->pitch
* args
->height
;
428 return i915_gem_create(file
, dev
,
429 args
->size
, &args
->handle
);
433 * Creates a new mm object and returns a handle to it.
436 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
437 struct drm_file
*file
)
439 struct drm_i915_gem_create
*args
= data
;
441 return i915_gem_create(file
, dev
,
442 args
->size
, &args
->handle
);
446 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
447 const char *gpu_vaddr
, int gpu_offset
,
450 int ret
, cpu_offset
= 0;
453 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
454 int this_length
= min(cacheline_end
- gpu_offset
, length
);
455 int swizzled_gpu_offset
= gpu_offset
^ 64;
457 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
458 gpu_vaddr
+ swizzled_gpu_offset
,
463 cpu_offset
+= this_length
;
464 gpu_offset
+= this_length
;
465 length
-= this_length
;
472 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
473 const char __user
*cpu_vaddr
,
476 int ret
, cpu_offset
= 0;
479 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
480 int this_length
= min(cacheline_end
- gpu_offset
, length
);
481 int swizzled_gpu_offset
= gpu_offset
^ 64;
483 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
484 cpu_vaddr
+ cpu_offset
,
489 cpu_offset
+= this_length
;
490 gpu_offset
+= this_length
;
491 length
-= this_length
;
498 * Pins the specified object's pages and synchronizes the object with
499 * GPU accesses. Sets needs_clflush to non-zero if the caller should
500 * flush the object from the CPU cache.
502 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
514 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
521 ret
= i915_gem_object_wait_rendering(obj
, true);
526 ret
= i915_gem_object_get_pages(obj
);
530 i915_gem_object_pin_pages(obj
);
535 /* Per-page copy function for the shmem pread fastpath.
536 * Flushes invalid cachelines before reading the target if
537 * needs_clflush is set. */
539 shmem_pread_fast(struct vm_page
*page
, int shmem_page_offset
, int page_length
,
540 char __user
*user_data
,
541 bool page_do_bit17_swizzling
, bool needs_clflush
)
546 if (unlikely(page_do_bit17_swizzling
))
549 vaddr
= kmap_atomic(page
);
551 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
553 ret
= __copy_to_user_inatomic(user_data
,
554 vaddr
+ shmem_page_offset
,
556 kunmap_atomic(vaddr
);
558 return ret
? -EFAULT
: 0;
562 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
565 if (unlikely(swizzled
)) {
566 unsigned long start
= (unsigned long) addr
;
567 unsigned long end
= (unsigned long) addr
+ length
;
569 /* For swizzling simply ensure that we always flush both
570 * channels. Lame, but simple and it works. Swizzled
571 * pwrite/pread is far from a hotpath - current userspace
572 * doesn't use it at all. */
573 start
= round_down(start
, 128);
574 end
= round_up(end
, 128);
576 drm_clflush_virt_range((void *)start
, end
- start
);
578 drm_clflush_virt_range(addr
, length
);
583 /* Only difference to the fast-path function is that this can handle bit17
584 * and uses non-atomic copy and kmap functions. */
586 shmem_pread_slow(struct vm_page
*page
, int shmem_page_offset
, int page_length
,
587 char __user
*user_data
,
588 bool page_do_bit17_swizzling
, bool needs_clflush
)
595 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
597 page_do_bit17_swizzling
);
599 if (page_do_bit17_swizzling
)
600 ret
= __copy_to_user_swizzled(user_data
,
601 vaddr
, shmem_page_offset
,
604 ret
= __copy_to_user(user_data
,
605 vaddr
+ shmem_page_offset
,
609 return ret
? - EFAULT
: 0;
613 i915_gem_shmem_pread(struct drm_device
*dev
,
614 struct drm_i915_gem_object
*obj
,
615 struct drm_i915_gem_pread
*args
,
616 struct drm_file
*file
)
618 char __user
*user_data
;
621 int shmem_page_offset
, page_length
, ret
= 0;
622 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
624 int needs_clflush
= 0;
625 struct sg_page_iter sg_iter
;
627 user_data
= to_user_ptr(args
->data_ptr
);
630 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
632 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
636 offset
= args
->offset
;
638 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
639 offset
>> PAGE_SHIFT
) {
640 struct vm_page
*page
= sg_page_iter_page(&sg_iter
);
645 /* Operation in this page
647 * shmem_page_offset = offset within page in shmem file
648 * page_length = bytes to copy for this page
650 shmem_page_offset
= offset_in_page(offset
);
651 page_length
= remain
;
652 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
653 page_length
= PAGE_SIZE
- shmem_page_offset
;
655 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
656 (page_to_phys(page
) & (1 << 17)) != 0;
658 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
659 user_data
, page_do_bit17_swizzling
,
664 mutex_unlock(&dev
->struct_mutex
);
666 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
667 ret
= fault_in_multipages_writeable(user_data
, remain
);
668 /* Userspace is tricking us, but we've already clobbered
669 * its pages with the prefault and promised to write the
670 * data up to the first fault. Hence ignore any errors
671 * and just continue. */
676 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
677 user_data
, page_do_bit17_swizzling
,
680 mutex_lock(&dev
->struct_mutex
);
686 remain
-= page_length
;
687 user_data
+= page_length
;
688 offset
+= page_length
;
692 i915_gem_object_unpin_pages(obj
);
698 * Reads data from the object referenced by handle.
700 * On error, the contents of *data are undefined.
703 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
704 struct drm_file
*file
)
706 struct drm_i915_gem_pread
*args
= data
;
707 struct drm_i915_gem_object
*obj
;
713 ret
= i915_mutex_lock_interruptible(dev
);
717 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
718 if (&obj
->base
== NULL
) {
723 /* Bounds check source. */
724 if (args
->offset
> obj
->base
.size
||
725 args
->size
> obj
->base
.size
- args
->offset
) {
730 /* prime objects have no backing filp to GEM pread/pwrite
734 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
736 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
739 drm_gem_object_unreference(&obj
->base
);
741 mutex_unlock(&dev
->struct_mutex
);
745 /* This is the fast write path which cannot handle
746 * page faults in the source data
750 fast_user_write(struct io_mapping
*mapping
,
751 loff_t page_base
, int page_offset
,
752 char __user
*user_data
,
755 void __iomem
*vaddr_atomic
;
757 unsigned long unwritten
;
759 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
760 /* We can use the cpu mem copy function because this is X86. */
761 vaddr
= (char __force
*)vaddr_atomic
+ page_offset
;
762 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
764 io_mapping_unmap_atomic(vaddr_atomic
);
769 * This is the fast pwrite path, where we copy the data directly from the
770 * user into the GTT, uncached.
773 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
774 struct drm_i915_gem_object
*obj
,
775 struct drm_i915_gem_pwrite
*args
,
776 struct drm_file
*file
)
778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
780 loff_t offset
, page_base
;
781 char __user
*user_data
;
782 int page_offset
, page_length
, ret
;
784 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
788 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
792 ret
= i915_gem_object_put_fence(obj
);
796 user_data
= to_user_ptr(args
->data_ptr
);
799 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
801 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
804 /* Operation in this page
806 * page_base = page offset within aperture
807 * page_offset = offset within page
808 * page_length = bytes to copy for this page
810 page_base
= offset
& ~PAGE_MASK
;
811 page_offset
= offset_in_page(offset
);
812 page_length
= remain
;
813 if ((page_offset
+ remain
) > PAGE_SIZE
)
814 page_length
= PAGE_SIZE
- page_offset
;
816 /* If we get a fault while copying data, then (presumably) our
817 * source page isn't available. Return the error and we'll
818 * retry in the slow path.
820 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
821 page_offset
, user_data
, page_length
)) {
826 remain
-= page_length
;
827 user_data
+= page_length
;
828 offset
+= page_length
;
832 intel_fb_obj_flush(obj
, false);
834 i915_gem_object_ggtt_unpin(obj
);
839 /* Per-page copy function for the shmem pwrite fastpath.
840 * Flushes invalid cachelines before writing to the target if
841 * needs_clflush_before is set and flushes out any written cachelines after
842 * writing if needs_clflush is set. */
844 shmem_pwrite_fast(struct vm_page
*page
, int shmem_page_offset
, int page_length
,
845 char __user
*user_data
,
846 bool page_do_bit17_swizzling
,
847 bool needs_clflush_before
,
848 bool needs_clflush_after
)
853 if (unlikely(page_do_bit17_swizzling
))
856 vaddr
= kmap_atomic(page
);
857 if (needs_clflush_before
)
858 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
860 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
861 user_data
, page_length
);
862 if (needs_clflush_after
)
863 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
865 kunmap_atomic(vaddr
);
867 return ret
? -EFAULT
: 0;
870 /* Only difference to the fast-path function is that this can handle bit17
871 * and uses non-atomic copy and kmap functions. */
873 shmem_pwrite_slow(struct vm_page
*page
, int shmem_page_offset
, int page_length
,
874 char __user
*user_data
,
875 bool page_do_bit17_swizzling
,
876 bool needs_clflush_before
,
877 bool needs_clflush_after
)
883 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
884 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
886 page_do_bit17_swizzling
);
887 if (page_do_bit17_swizzling
)
888 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
892 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
895 if (needs_clflush_after
)
896 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
898 page_do_bit17_swizzling
);
901 return ret
? -EFAULT
: 0;
905 i915_gem_shmem_pwrite(struct drm_device
*dev
,
906 struct drm_i915_gem_object
*obj
,
907 struct drm_i915_gem_pwrite
*args
,
908 struct drm_file
*file
)
912 char __user
*user_data
;
913 int shmem_page_offset
, page_length
, ret
= 0;
914 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
915 int hit_slowpath
= 0;
916 int needs_clflush_after
= 0;
917 int needs_clflush_before
= 0;
918 struct sg_page_iter sg_iter
;
920 user_data
= to_user_ptr(args
->data_ptr
);
923 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
925 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
926 /* If we're not in the cpu write domain, set ourself into the gtt
927 * write domain and manually flush cachelines (if required). This
928 * optimizes for the case when the gpu will use the data
929 * right away and we therefore have to clflush anyway. */
930 needs_clflush_after
= cpu_write_needs_clflush(obj
);
931 ret
= i915_gem_object_wait_rendering(obj
, false);
935 /* Same trick applies to invalidate partially written cachelines read
937 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
938 needs_clflush_before
=
939 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
941 ret
= i915_gem_object_get_pages(obj
);
945 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
947 i915_gem_object_pin_pages(obj
);
949 offset
= args
->offset
;
952 VM_OBJECT_LOCK(obj
->base
.vm_obj
);
953 vm_object_pip_add(obj
->base
.vm_obj
, 1);
955 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
956 offset
>> PAGE_SHIFT
) {
957 struct vm_page
*page
= sg_page_iter_page(&sg_iter
);
958 int partial_cacheline_write
;
963 /* Operation in this page
965 * shmem_page_offset = offset within page in shmem file
966 * page_length = bytes to copy for this page
968 shmem_page_offset
= offset_in_page(offset
);
970 page_length
= remain
;
971 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
972 page_length
= PAGE_SIZE
- shmem_page_offset
;
974 /* If we don't overwrite a cacheline completely we need to be
975 * careful to have up-to-date data by first clflushing. Don't
976 * overcomplicate things and flush the entire patch. */
977 partial_cacheline_write
= needs_clflush_before
&&
978 ((shmem_page_offset
| page_length
)
979 & (cpu_clflush_line_size
- 1));
981 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
982 (page_to_phys(page
) & (1 << 17)) != 0;
984 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
985 user_data
, page_do_bit17_swizzling
,
986 partial_cacheline_write
,
987 needs_clflush_after
);
992 mutex_unlock(&dev
->struct_mutex
);
993 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
994 user_data
, page_do_bit17_swizzling
,
995 partial_cacheline_write
,
996 needs_clflush_after
);
998 mutex_lock(&dev
->struct_mutex
);
1004 remain
-= page_length
;
1005 user_data
+= page_length
;
1006 offset
+= page_length
;
1008 vm_object_pip_wakeup(obj
->base
.vm_obj
);
1009 VM_OBJECT_UNLOCK(obj
->base
.vm_obj
);
1012 i915_gem_object_unpin_pages(obj
);
1016 * Fixup: Flush cpu caches in case we didn't flush the dirty
1017 * cachelines in-line while writing and the object moved
1018 * out of the cpu write domain while we've dropped the lock.
1020 if (!needs_clflush_after
&&
1021 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1022 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1023 i915_gem_chipset_flush(dev
);
1027 if (needs_clflush_after
)
1028 i915_gem_chipset_flush(dev
);
1030 intel_fb_obj_flush(obj
, false);
1035 * Writes data to the object referenced by handle.
1037 * On error, the contents of the buffer that were to be modified are undefined.
1040 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1041 struct drm_file
*file
)
1043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1044 struct drm_i915_gem_pwrite
*args
= data
;
1045 struct drm_i915_gem_object
*obj
;
1048 if (args
->size
== 0)
1051 if (likely(!i915
.prefault_disable
)) {
1052 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1058 intel_runtime_pm_get(dev_priv
);
1060 ret
= i915_mutex_lock_interruptible(dev
);
1064 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1065 if (&obj
->base
== NULL
) {
1070 /* Bounds check destination. */
1071 if (args
->offset
> obj
->base
.size
||
1072 args
->size
> obj
->base
.size
- args
->offset
) {
1077 /* prime objects have no backing filp to GEM pread/pwrite
1081 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1084 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1085 * it would end up going through the fenced access, and we'll get
1086 * different detiling behavior between reading and writing.
1087 * pread/pwrite currently are reading and writing from the CPU
1088 * perspective, requiring manual detiling by the client.
1090 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1091 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1092 cpu_write_needs_clflush(obj
)) {
1093 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1094 /* Note that the gtt paths might fail with non-page-backed user
1095 * pointers (e.g. gtt mappings when moving data between
1096 * textures). Fallback to the shmem path in that case. */
1099 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1100 if (obj
->phys_handle
)
1101 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1103 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1107 drm_gem_object_unreference(&obj
->base
);
1109 mutex_unlock(&dev
->struct_mutex
);
1111 intel_runtime_pm_put(dev_priv
);
1117 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1120 if (i915_reset_in_progress(error
)) {
1121 /* Non-interruptible callers can't handle -EAGAIN, hence return
1122 * -EIO unconditionally for these. */
1126 /* Recovery complete, but the reset failed ... */
1127 if (i915_terminally_wedged(error
))
1131 * Check if GPU Reset is in progress - we need intel_ring_begin
1132 * to work properly to reinit the hw state while the gpu is
1133 * still marked as reset-in-progress. Handle this with a flag.
1135 if (!error
->reload_in_reset
)
1143 * Compare arbitrary request against outstanding lazy request. Emit on match.
1146 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1150 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1153 if (req
== req
->ring
->outstanding_lazy_request
)
1154 ret
= i915_add_request(req
->ring
);
1159 static void fake_irq(unsigned long data
)
1161 wakeup_one((void *)data
);
1164 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1165 struct intel_engine_cs
*ring
)
1167 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1171 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1173 unsigned long timeout
;
1175 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1178 timeout
= jiffies
+ 1;
1179 while (!need_resched()) {
1180 if (i915_gem_request_completed(req
, true))
1183 if (time_after_eq(jiffies
, timeout
))
1186 cpu_relax_lowlatency();
1188 if (i915_gem_request_completed(req
, false))
1196 * __i915_wait_request - wait until execution of request has finished
1198 * @reset_counter: reset sequence associated with the given request
1199 * @interruptible: do an interruptible wait (normally yes)
1200 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1202 * Note: It is of utmost importance that the passed in seqno and reset_counter
1203 * values have been read by the caller in an smp safe manner. Where read-side
1204 * locks are involved, it is sufficient to read the reset_counter before
1205 * unlocking the lock that protects the seqno. For lockless tricks, the
1206 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1209 * Returns 0 if the request was found within the alloted time. Else returns the
1210 * errno with remaining time filled in timeout argument.
1212 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1213 unsigned reset_counter
,
1216 struct intel_rps_client
*rps
)
1218 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1219 struct drm_device
*dev
= ring
->dev
;
1220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 const bool irq_test_in_progress
=
1222 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1223 unsigned long timeout_expire
;
1225 int ret
, sl_timeout
= 1;
1227 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1229 if (list_empty(&req
->list
))
1232 if (i915_gem_request_completed(req
, true))
1235 timeout_expire
= timeout
?
1236 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1238 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1239 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1241 /* Record current time in case interrupted by signal, or wedged */
1242 trace_i915_gem_request_wait_begin(req
);
1243 before
= ktime_get_raw_ns();
1245 /* Optimistic spin for the next jiffie before touching IRQs */
1247 ret
= __i915_spin_request(req
);
1252 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1257 lockmgr(&ring
->irq_queue
.lock
, LK_EXCLUSIVE
);
1259 struct timer_list timer
;
1261 /* We need to check whether any gpu reset happened in between
1262 * the caller grabbing the seqno and now ... */
1263 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1264 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1265 * is truely gone. */
1266 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1272 if (i915_gem_request_completed(req
, false)) {
1277 if (interruptible
&& signal_pending(curthread
->td_lwp
)) {
1282 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1287 timer
.function
= NULL
;
1288 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1289 unsigned long expire
;
1291 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)&ring
->irq_queue
);
1292 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1293 sl_timeout
= expire
- jiffies
;
1296 mod_timer(&timer
, expire
);
1303 if (timer
.function
) {
1304 del_singleshot_timer_sync(&timer
);
1305 destroy_timer_on_stack(&timer
);
1308 lksleep(&ring
->irq_queue
, &ring
->irq_queue
.lock
,
1309 interruptible
? PCATCH
: 0, "lwe", sl_timeout
);
1311 lockmgr(&ring
->irq_queue
.lock
, LK_RELEASE
);
1312 if (!irq_test_in_progress
)
1313 ring
->irq_put(ring
);
1316 now
= ktime_get_raw_ns();
1317 trace_i915_gem_request_wait_end(req
);
1320 s64 tres
= *timeout
- (now
- before
);
1322 *timeout
= tres
< 0 ? 0 : tres
;
1325 * Apparently ktime isn't accurate enough and occasionally has a
1326 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1327 * things up to make the test happy. We allow up to 1 jiffy.
1329 * This is a regrssion from the timespec->ktime conversion.
1331 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1339 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1341 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1346 spin_lock(&file_priv
->mm
.lock
);
1347 list_del(&request
->client_list
);
1348 request
->file_priv
= NULL
;
1349 spin_unlock(&file_priv
->mm
.lock
);
1352 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1354 trace_i915_gem_request_retire(request
);
1356 /* We know the GPU must have read the request to have
1357 * sent us the seqno + interrupt, so use the position
1358 * of tail of the request to update the last known position
1361 * Note this requires that we are always called in request
1364 request
->ringbuf
->last_retired_head
= request
->postfix
;
1366 list_del_init(&request
->list
);
1367 i915_gem_request_remove_from_client(request
);
1370 put_pid(request
->pid
);
1373 i915_gem_request_unreference(request
);
1377 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1379 struct intel_engine_cs
*engine
= req
->ring
;
1380 struct drm_i915_gem_request
*tmp
;
1382 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1384 if (list_empty(&req
->list
))
1388 tmp
= list_first_entry(&engine
->request_list
,
1389 typeof(*tmp
), list
);
1391 i915_gem_request_retire(tmp
);
1392 } while (tmp
!= req
);
1394 WARN_ON(i915_verify_lists(engine
->dev
));
1398 * Waits for a request to be signaled, and cleans up the
1399 * request and object lists appropriately for that event.
1402 i915_wait_request(struct drm_i915_gem_request
*req
)
1404 struct drm_device
*dev
;
1405 struct drm_i915_private
*dev_priv
;
1409 BUG_ON(req
== NULL
);
1411 dev
= req
->ring
->dev
;
1412 dev_priv
= dev
->dev_private
;
1413 interruptible
= dev_priv
->mm
.interruptible
;
1415 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1417 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1421 ret
= i915_gem_check_olr(req
);
1425 ret
= __i915_wait_request(req
,
1426 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1427 interruptible
, NULL
, NULL
);
1431 __i915_gem_request_retire__upto(req
);
1436 * Ensures that all rendering to the object has completed and the object is
1437 * safe to unbind from the GTT or access from the CPU.
1440 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1449 if (obj
->last_write_req
!= NULL
) {
1450 ret
= i915_wait_request(obj
->last_write_req
);
1454 i
= obj
->last_write_req
->ring
->id
;
1455 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1456 i915_gem_object_retire__read(obj
, i
);
1458 i915_gem_object_retire__write(obj
);
1461 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1462 if (obj
->last_read_req
[i
] == NULL
)
1465 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1469 i915_gem_object_retire__read(obj
, i
);
1471 RQ_BUG_ON(obj
->active
);
1478 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1479 struct drm_i915_gem_request
*req
)
1481 int ring
= req
->ring
->id
;
1483 if (obj
->last_read_req
[ring
] == req
)
1484 i915_gem_object_retire__read(obj
, ring
);
1485 else if (obj
->last_write_req
== req
)
1486 i915_gem_object_retire__write(obj
);
1488 __i915_gem_request_retire__upto(req
);
1491 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1492 * as the object state may change during this call.
1494 static __must_check
int
1495 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1496 struct intel_rps_client
*rps
,
1499 struct drm_device
*dev
= obj
->base
.dev
;
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1502 unsigned reset_counter
;
1505 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1506 BUG_ON(!dev_priv
->mm
.interruptible
);
1511 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1515 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1518 struct drm_i915_gem_request
*req
;
1520 req
= obj
->last_write_req
;
1524 ret
= i915_gem_check_olr(req
);
1528 requests
[n
++] = i915_gem_request_reference(req
);
1530 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1531 struct drm_i915_gem_request
*req
;
1533 req
= obj
->last_read_req
[i
];
1537 ret
= i915_gem_check_olr(req
);
1541 requests
[n
++] = i915_gem_request_reference(req
);
1545 mutex_unlock(&dev
->struct_mutex
);
1546 for (i
= 0; ret
== 0 && i
< n
; i
++)
1547 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1549 mutex_lock(&dev
->struct_mutex
);
1552 for (i
= 0; i
< n
; i
++) {
1554 i915_gem_object_retire_request(obj
, requests
[i
]);
1555 i915_gem_request_unreference(requests
[i
]);
1561 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1563 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1568 * Called when user space prepares to use an object with the CPU, either
1569 * through the mmap ioctl's mapping or a GTT mapping.
1572 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1573 struct drm_file
*file
)
1575 struct drm_i915_gem_set_domain
*args
= data
;
1576 struct drm_i915_gem_object
*obj
;
1577 uint32_t read_domains
= args
->read_domains
;
1578 uint32_t write_domain
= args
->write_domain
;
1581 /* Only handle setting domains to types used by the CPU. */
1582 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1585 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1588 /* Having something in the write domain implies it's in the read
1589 * domain, and only that read domain. Enforce that in the request.
1591 if (write_domain
!= 0 && read_domains
!= write_domain
)
1594 ret
= i915_mutex_lock_interruptible(dev
);
1598 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1599 if (&obj
->base
== NULL
) {
1604 /* Try to flush the object off the GPU without holding the lock.
1605 * We will repeat the flush holding the lock in the normal manner
1606 * to catch cases where we are gazumped.
1608 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1609 to_rps_client(file
),
1614 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1615 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1617 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1620 drm_gem_object_unreference(&obj
->base
);
1622 mutex_unlock(&dev
->struct_mutex
);
1627 * Called when user space has done writes to this buffer
1630 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1631 struct drm_file
*file
)
1633 struct drm_i915_gem_sw_finish
*args
= data
;
1634 struct drm_i915_gem_object
*obj
;
1637 ret
= i915_mutex_lock_interruptible(dev
);
1641 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1642 if (&obj
->base
== NULL
) {
1647 /* Pinned buffers may be scanout, so flush the cache */
1648 if (obj
->pin_display
)
1649 i915_gem_object_flush_cpu_write_domain(obj
);
1651 drm_gem_object_unreference(&obj
->base
);
1653 mutex_unlock(&dev
->struct_mutex
);
1658 * Maps the contents of an object, returning the address it is mapped
1661 * While the mapping holds a reference on the contents of the object, it doesn't
1662 * imply a ref on the object itself.
1666 * DRM driver writers who look a this function as an example for how to do GEM
1667 * mmap support, please don't implement mmap support like here. The modern way
1668 * to implement DRM mmap support is with an mmap offset ioctl (like
1669 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1670 * That way debug tooling like valgrind will understand what's going on, hiding
1671 * the mmap call in a driver private ioctl will break that. The i915 driver only
1672 * does cpu mmaps this way because we didn't know better.
1675 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1676 struct drm_file
*file
)
1678 struct drm_i915_gem_mmap
*args
= data
;
1679 struct drm_gem_object
*obj
;
1682 struct proc
*p
= curproc
;
1683 vm_map_t map
= &p
->p_vmspace
->vm_map
;
1687 if (args
->flags
& ~(I915_MMAP_WC
))
1690 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1694 if (args
->size
== 0)
1697 size
= round_page(args
->size
);
1698 if (map
->size
+ size
> p
->p_rlimit
[RLIMIT_VMEM
].rlim_cur
) {
1703 /* prime objects have no backing filp to GEM mmap
1708 * Call hint to ensure that NULL is not returned as a valid address
1709 * and to reduce vm_map traversals. XXX causes instability, use a
1710 * fixed low address as the start point instead to avoid the NULL
1717 * Use 256KB alignment. It is unclear why this matters for a
1718 * virtual address but it appears to fix a number of application/X
1719 * crashes and kms console switching is much faster.
1721 vm_object_hold(obj
->vm_obj
);
1722 vm_object_reference_locked(obj
->vm_obj
);
1723 vm_object_drop(obj
->vm_obj
);
1725 rv
= vm_map_find(map
, obj
->vm_obj
, NULL
,
1726 args
->offset
, &addr
, args
->size
,
1727 256 * 1024, /* align */
1729 VM_MAPTYPE_NORMAL
, /* maptype */
1730 VM_PROT_READ
| VM_PROT_WRITE
, /* prot */
1731 VM_PROT_READ
| VM_PROT_WRITE
, /* max */
1732 MAP_SHARED
/* cow */);
1733 if (rv
!= KERN_SUCCESS
) {
1734 vm_object_deallocate(obj
->vm_obj
);
1735 error
= -vm_mmap_to_errno(rv
);
1737 args
->addr_ptr
= (uint64_t)addr
;
1740 drm_gem_object_unreference(obj
);
1745 * i915_gem_fault - fault a page into the GTT
1747 * vm_obj is locked on entry and expected to be locked on return.
1749 * The vm_pager has placemarked the object with an anonymous memory page
1750 * which we must replace atomically to avoid races against concurrent faults
1751 * on the same page. XXX we currently are unable to do this atomically.
1753 * If we are to return an error we should not touch the anonymous page,
1754 * the caller will deallocate it.
1756 * XXX Most GEM calls appear to be interruptable, but we can't hard loop
1757 * in that case. Release all resources and wait 1 tick before retrying.
1758 * This is a huge problem which needs to be fixed by getting rid of most
1759 * of the interruptability. The linux code does not retry but does appear
1760 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level
1761 * to be able to retry.
1764 * vma: VMA in question
1767 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1768 * from userspace. The fault handler takes care of binding the object to
1769 * the GTT (if needed), allocating and programming a fence register (again,
1770 * only if needed based on whether the old reg is still valid or the object
1771 * is tiled) and inserting a new PTE into the faulting process.
1773 * Note that the faulting process may involve evicting existing objects
1774 * from the GTT and/or fence registers to make room. So performance may
1775 * suffer if the GTT working set is large or there are few fence registers
1778 * vm_obj is locked on entry and expected to be locked on return. The VM
1779 * pager has placed an anonymous memory page at (obj,offset) which we have
1782 int i915_gem_fault(vm_object_t vm_obj
, vm_ooffset_t offset
, int prot
, vm_page_t
*mres
)
1784 struct drm_i915_gem_object
*obj
= to_intel_bo(vm_obj
->handle
);
1785 struct drm_device
*dev
= obj
->base
.dev
;
1786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1787 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1788 unsigned long page_offset
;
1789 vm_page_t m
, oldm
= NULL
;
1791 bool write
= !!(prot
& VM_PROT_WRITE
);
1793 intel_runtime_pm_get(dev_priv
);
1795 /* We don't use vmf->pgoff since that has the fake offset */
1796 page_offset
= (unsigned long)offset
;
1799 ret
= i915_mutex_lock_interruptible(dev
);
1803 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1805 /* Try to flush the object off the GPU first without holding the lock.
1806 * Upon reacquiring the lock, we will perform our sanity checks and then
1807 * repeat the flush holding the lock in the normal manner to catch cases
1808 * where we are gazumped.
1810 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1814 /* Access to snoopable pages through the GTT is incoherent. */
1815 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1820 /* Use a partial view if the object is bigger than the aperture. */
1821 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1822 obj
->tiling_mode
== I915_TILING_NONE
) {
1824 static const unsigned int chunk_size
= 256; // 1 MiB
1826 memset(&view
, 0, sizeof(view
));
1827 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1828 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1829 view
.params
.partial
.size
=
1832 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1833 view
.params
.partial
.offset
);
1837 /* Now pin it into the GTT if needed */
1838 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1842 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1846 ret
= i915_gem_object_get_fence(obj
);
1851 * START FREEBSD MAGIC
1853 * Add a pip count to avoid destruction and certain other
1854 * complex operations (such as collapses?) while unlocked.
1856 vm_object_pip_add(vm_obj
, 1);
1859 * XXX We must currently remove the placeholder page now to avoid
1860 * a deadlock against a concurrent i915_gem_release_mmap().
1861 * Otherwise concurrent operation will block on the busy page
1862 * while holding locks which we need to obtain.
1864 if (*mres
!= NULL
) {
1866 if ((oldm
->flags
& PG_BUSY
) == 0)
1867 kprintf("i915_gem_fault: Page was not busy\n");
1869 vm_page_remove(oldm
);
1879 * Since the object lock was dropped, another thread might have
1880 * faulted on the same GTT address and instantiated the mapping.
1883 m
= vm_page_lookup(vm_obj
, OFF_TO_IDX(offset
));
1886 * Try to busy the page, retry on failure (non-zero ret).
1888 if (vm_page_busy_try(m
, false)) {
1889 kprintf("i915_gem_fault: PG_BUSY\n");
1899 obj
->fault_mappable
= true;
1901 /* Finally, remap it using the new GTT offset */
1902 m
= vm_phys_fictitious_to_vm_page(dev_priv
->gtt
.mappable_base
+
1903 i915_gem_obj_ggtt_offset_view(obj
, &view
) + offset
);
1908 KASSERT((m
->flags
& PG_FICTITIOUS
) != 0, ("not fictitious %p", m
));
1909 KASSERT(m
->wire_count
== 1, ("wire_count not 1 %p", m
));
1912 * Try to busy the page. Fails on non-zero return.
1914 if (vm_page_busy_try(m
, false)) {
1915 kprintf("i915_gem_fault: PG_BUSY(2)\n");
1919 m
->valid
= VM_PAGE_BITS_ALL
;
1922 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1923 /* Overriding existing pages in partial view does not cause
1924 * us any trouble as TLBs are still valid because the fault
1925 * is due to userspace losing part of the mapping or never
1926 * having accessed it before (at this partials' range).
1928 unsigned long base
= vma
->vm_start
+
1929 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1932 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1933 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1938 obj
->fault_mappable
= true;
1940 if (!obj
->fault_mappable
) {
1941 unsigned long size
= min_t(unsigned long,
1942 vma
->vm_end
- vma
->vm_start
,
1946 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1947 ret
= vm_insert_pfn(vma
,
1948 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1954 obj
->fault_mappable
= true;
1956 ret
= vm_insert_pfn(vma
,
1957 (unsigned long)vmf
->virtual_address
,
1960 vm_page_insert(m
, vm_obj
, OFF_TO_IDX(offset
));
1968 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1969 mutex_unlock(&dev
->struct_mutex
);
1974 * ALTERNATIVE ERROR RETURN.
1976 * OBJECT EXPECTED TO BE LOCKED.
1979 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1981 mutex_unlock(&dev
->struct_mutex
);
1986 * We eat errors when the gpu is terminally wedged to avoid
1987 * userspace unduly crashing (gl has no provisions for mmaps to
1988 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1989 * and so needs to be reported.
1991 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1992 // ret = VM_FAULT_SIGBUS;
1997 * EAGAIN means the gpu is hung and we'll wait for the error
1998 * handler to reset everything when re-faulting in
1999 * i915_mutex_lock_interruptible.
2003 VM_OBJECT_UNLOCK(vm_obj
);
2005 tsleep(&dummy
, 0, "delay", 1); /* XXX */
2006 VM_OBJECT_LOCK(vm_obj
);
2009 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
2010 ret
= VM_PAGER_ERROR
;
2017 vm_object_pip_wakeup(vm_obj
);
2019 intel_runtime_pm_put(dev_priv
);
2024 * i915_gem_release_mmap - remove physical page mappings
2025 * @obj: obj in question
2027 * Preserve the reservation of the mmapping with the DRM core code, but
2028 * relinquish ownership of the pages back to the system.
2030 * It is vital that we remove the page mapping if we have mapped a tiled
2031 * object through the GTT and then lose the fence register due to
2032 * resource pressure. Similarly if the object has been moved out of the
2033 * aperture, than pages mapped into userspace must be revoked. Removing the
2034 * mapping will then trigger a page fault on the next user access, allowing
2035 * fixup by i915_gem_fault().
2038 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
2044 if (!obj
->fault_mappable
)
2047 devobj
= cdev_pager_lookup(obj
);
2048 if (devobj
!= NULL
) {
2049 page_count
= OFF_TO_IDX(obj
->base
.size
);
2051 VM_OBJECT_LOCK(devobj
);
2052 for (i
= 0; i
< page_count
; i
++) {
2053 m
= vm_page_lookup_busy_wait(devobj
, i
, TRUE
, "915unm");
2056 cdev_pager_free_page(devobj
, m
);
2058 VM_OBJECT_UNLOCK(devobj
);
2059 vm_object_deallocate(devobj
);
2062 obj
->fault_mappable
= false;
2066 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
2068 struct drm_i915_gem_object
*obj
;
2070 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
2071 i915_gem_release_mmap(obj
);
2075 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
2079 if (INTEL_INFO(dev
)->gen
>= 4 ||
2080 tiling_mode
== I915_TILING_NONE
)
2083 /* Previous chips need a power-of-two fence region when tiling */
2084 if (INTEL_INFO(dev
)->gen
== 3)
2085 gtt_size
= 1024*1024;
2087 gtt_size
= 512*1024;
2089 while (gtt_size
< size
)
2096 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2097 * @obj: object to check
2099 * Return the required GTT alignment for an object, taking into account
2100 * potential fence register mapping.
2103 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2104 int tiling_mode
, bool fenced
)
2107 * Minimum alignment is 4k (GTT page size), but might be greater
2108 * if a fence register is needed for the object.
2110 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2111 tiling_mode
== I915_TILING_NONE
)
2115 * Previous chips need to be aligned to the size of the smallest
2116 * fence register that can contain the object.
2118 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2121 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2123 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2127 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2131 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2133 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2137 /* Badly fragmented mmap space? The only way we can recover
2138 * space is by destroying unwanted objects. We can't randomly release
2139 * mmap_offsets as userspace expects them to be persistent for the
2140 * lifetime of the objects. The closest we can is to release the
2141 * offsets on purgeable objects by truncating it and marking it purged,
2142 * which prevents userspace from ever using that object again.
2144 i915_gem_shrink(dev_priv
,
2145 obj
->base
.size
>> PAGE_SHIFT
,
2147 I915_SHRINK_UNBOUND
|
2148 I915_SHRINK_PURGEABLE
);
2149 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2153 i915_gem_shrink_all(dev_priv
);
2154 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2156 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2161 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2163 drm_gem_free_mmap_offset(&obj
->base
);
2167 i915_gem_mmap_gtt(struct drm_file
*file
,
2168 struct drm_device
*dev
,
2172 struct drm_i915_gem_object
*obj
;
2175 ret
= i915_mutex_lock_interruptible(dev
);
2179 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2180 if (&obj
->base
== NULL
) {
2185 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2186 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2191 ret
= i915_gem_object_create_mmap_offset(obj
);
2195 *offset
= DRM_GEM_MAPPING_OFF(obj
->base
.map_list
.key
) |
2196 DRM_GEM_MAPPING_KEY
;
2199 drm_gem_object_unreference(&obj
->base
);
2201 mutex_unlock(&dev
->struct_mutex
);
2206 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2208 * @data: GTT mapping ioctl data
2209 * @file: GEM object info
2211 * Simply returns the fake offset to userspace so it can mmap it.
2212 * The mmap call will end up in drm_gem_mmap(), which will set things
2213 * up so we can get faults in the handler above.
2215 * The fault handler will take care of binding the object into the GTT
2216 * (since it may have been evicted to make room for something), allocating
2217 * a fence register, and mapping the appropriate aperture address into
2221 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2222 struct drm_file
*file
)
2224 struct drm_i915_gem_mmap_gtt
*args
= data
;
2226 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2229 /* Immediately discard the backing storage */
2231 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2235 vm_obj
= obj
->base
.vm_obj
;
2236 VM_OBJECT_LOCK(vm_obj
);
2237 vm_object_page_remove(vm_obj
, 0, 0, false);
2238 VM_OBJECT_UNLOCK(vm_obj
);
2240 obj
->madv
= __I915_MADV_PURGED
;
2243 /* Try to discard unwanted pages */
2245 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2248 struct address_space
*mapping
;
2251 switch (obj
->madv
) {
2252 case I915_MADV_DONTNEED
:
2253 i915_gem_object_truncate(obj
);
2254 case __I915_MADV_PURGED
:
2259 if (obj
->base
.filp
== NULL
)
2262 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2263 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2268 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2270 struct sg_page_iter sg_iter
;
2273 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2275 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2277 /* In the event of a disaster, abandon all caches and
2278 * hope for the best.
2280 WARN_ON(ret
!= -EIO
);
2281 i915_gem_clflush_object(obj
, true);
2282 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2285 i915_gem_gtt_finish_object(obj
);
2287 if (i915_gem_object_needs_bit17_swizzle(obj
))
2288 i915_gem_object_save_bit_17_swizzle(obj
);
2290 if (obj
->madv
== I915_MADV_DONTNEED
)
2293 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2294 struct vm_page
*page
= sg_page_iter_page(&sg_iter
);
2297 set_page_dirty(page
);
2299 if (obj
->madv
== I915_MADV_WILLNEED
)
2300 mark_page_accessed(page
);
2302 vm_page_busy_wait(page
, FALSE
, "i915gem");
2303 vm_page_unwire(page
, 1);
2304 vm_page_wakeup(page
);
2308 sg_free_table(obj
->pages
);
2313 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2315 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2317 if (obj
->pages
== NULL
)
2320 if (obj
->pages_pin_count
)
2323 BUG_ON(i915_gem_obj_bound_any(obj
));
2325 /* ->put_pages might need to allocate memory for the bit17 swizzle
2326 * array, hence protect them from being reaped by removing them from gtt
2328 list_del(&obj
->global_list
);
2330 ops
->put_pages(obj
);
2333 i915_gem_object_invalidate(obj
);
2339 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2341 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2344 struct sg_table
*st
;
2345 struct scatterlist
*sg
;
2346 struct sg_page_iter sg_iter
;
2347 struct vm_page
*page
;
2348 unsigned long last_pfn
= 0; /* suppress gcc warning */
2351 /* Assert that the object is not currently in any GPU domain. As it
2352 * wasn't in the GTT, there shouldn't be any way it could have been in
2355 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2356 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2358 st
= kmalloc(sizeof(*st
), M_DRM
, M_WAITOK
);
2362 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2363 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2368 /* Get the list of pages out of our struct file. They'll be pinned
2369 * at this point until we release them.
2371 * Fail silently without starting the shrinker
2373 vm_obj
= obj
->base
.vm_obj
;
2374 VM_OBJECT_LOCK(vm_obj
);
2377 for (i
= 0; i
< page_count
; i
++) {
2378 page
= shmem_read_mapping_page(vm_obj
, i
);
2380 i915_gem_shrink(dev_priv
,
2383 I915_SHRINK_UNBOUND
|
2384 I915_SHRINK_PURGEABLE
);
2385 page
= shmem_read_mapping_page(vm_obj
, i
);
2388 /* We've tried hard to allocate the memory by reaping
2389 * our own buffer, now let the real VM do its job and
2390 * go down in flames if truly OOM.
2392 i915_gem_shrink_all(dev_priv
);
2393 page
= shmem_read_mapping_page(vm_obj
, i
);
2395 ret
= PTR_ERR(page
);
2399 #ifdef CONFIG_SWIOTLB
2400 if (swiotlb_nr_tbl()) {
2402 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2407 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2411 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2413 sg
->length
+= PAGE_SIZE
;
2415 last_pfn
= page_to_pfn(page
);
2417 /* Check that the i965g/gm workaround works. */
2419 #ifdef CONFIG_SWIOTLB
2420 if (!swiotlb_nr_tbl())
2424 VM_OBJECT_UNLOCK(vm_obj
);
2426 ret
= i915_gem_gtt_prepare_object(obj
);
2430 if (i915_gem_object_needs_bit17_swizzle(obj
))
2431 i915_gem_object_do_bit_17_swizzle(obj
);
2433 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2434 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2435 i915_gem_object_pin_pages(obj
);
2441 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
2442 page
= sg_page_iter_page(&sg_iter
);
2443 vm_page_busy_wait(page
, FALSE
, "i915gem");
2444 vm_page_unwire(page
, 0);
2445 vm_page_wakeup(page
);
2447 VM_OBJECT_UNLOCK(vm_obj
);
2451 /* shmemfs first checks if there is enough memory to allocate the page
2452 * and reports ENOSPC should there be insufficient, along with the usual
2453 * ENOMEM for a genuine allocation failure.
2455 * We use ENOSPC in our driver to mean that we have run out of aperture
2456 * space and so want to translate the error from shmemfs back to our
2457 * usual understanding of ENOMEM.
2465 /* Ensure that the associated pages are gathered from the backing storage
2466 * and pinned into our object. i915_gem_object_get_pages() may be called
2467 * multiple times before they are released by a single call to
2468 * i915_gem_object_put_pages() - once the pages are no longer referenced
2469 * either as a result of memory pressure (reaping pages under the shrinker)
2470 * or as the object is itself released.
2473 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2475 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2476 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2482 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2483 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2487 BUG_ON(obj
->pages_pin_count
);
2489 ret
= ops
->get_pages(obj
);
2493 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2495 obj
->get_page
.sg
= obj
->pages
->sgl
;
2496 obj
->get_page
.last
= 0;
2501 void i915_vma_move_to_active(struct i915_vma
*vma
,
2502 struct intel_engine_cs
*ring
)
2504 struct drm_i915_gem_object
*obj
= vma
->obj
;
2506 /* Add a reference if we're newly entering the active list. */
2507 if (obj
->active
== 0)
2508 drm_gem_object_reference(&obj
->base
);
2509 obj
->active
|= intel_ring_flag(ring
);
2511 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2512 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
],
2513 intel_ring_get_request(ring
));
2515 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2519 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2521 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2522 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2524 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2525 intel_fb_obj_flush(obj
, true);
2529 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2531 struct i915_vma
*vma
;
2533 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2534 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2536 list_del_init(&obj
->ring_list
[ring
]);
2537 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2539 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2540 i915_gem_object_retire__write(obj
);
2542 obj
->active
&= ~(1 << ring
);
2546 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2547 if (!list_empty(&vma
->mm_list
))
2548 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2551 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2552 drm_gem_object_unreference(&obj
->base
);
2556 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 struct intel_engine_cs
*ring
;
2562 /* Carefully retire all requests without writing to the rings */
2563 for_each_ring(ring
, dev_priv
, i
) {
2564 ret
= intel_ring_idle(ring
);
2568 i915_gem_retire_requests(dev
);
2570 /* Finally reset hw state */
2571 for_each_ring(ring
, dev_priv
, i
) {
2572 intel_ring_init_seqno(ring
, seqno
);
2574 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2575 ring
->semaphore
.sync_seqno
[j
] = 0;
2581 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2589 /* HWS page needs to be set less than what we
2590 * will inject to ring
2592 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2596 /* Carefully set the last_seqno value so that wrap
2597 * detection still works
2599 dev_priv
->next_seqno
= seqno
;
2600 dev_priv
->last_seqno
= seqno
- 1;
2601 if (dev_priv
->last_seqno
== 0)
2602 dev_priv
->last_seqno
--;
2608 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2612 /* reserve 0 for non-seqno */
2613 if (dev_priv
->next_seqno
== 0) {
2614 int ret
= i915_gem_init_seqno(dev
, 0);
2618 dev_priv
->next_seqno
= 1;
2621 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2625 int __i915_add_request(struct intel_engine_cs
*ring
,
2626 struct drm_file
*file
,
2627 struct drm_i915_gem_object
*obj
)
2629 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2630 struct drm_i915_gem_request
*request
;
2631 struct intel_ringbuffer
*ringbuf
;
2635 request
= ring
->outstanding_lazy_request
;
2636 if (WARN_ON(request
== NULL
))
2639 if (i915
.enable_execlists
) {
2640 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2642 ringbuf
= ring
->buffer
;
2644 request_start
= intel_ring_get_tail(ringbuf
);
2646 * Emit any outstanding flushes - execbuf can fail to emit the flush
2647 * after having emitted the batchbuffer command. Hence we need to fix
2648 * things up similar to emitting the lazy request. The difference here
2649 * is that the flush _must_ happen before the next request, no matter
2652 if (i915
.enable_execlists
) {
2653 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2657 ret
= intel_ring_flush_all_caches(ring
);
2662 /* Record the position of the start of the request so that
2663 * should we detect the updated seqno part-way through the
2664 * GPU processing the request, we never over-estimate the
2665 * position of the head.
2667 request
->postfix
= intel_ring_get_tail(ringbuf
);
2669 if (i915
.enable_execlists
) {
2670 ret
= ring
->emit_request(ringbuf
, request
);
2674 ret
= ring
->add_request(ring
);
2678 request
->tail
= intel_ring_get_tail(ringbuf
);
2681 request
->head
= request_start
;
2683 /* Whilst this request exists, batch_obj will be on the
2684 * active_list, and so will hold the active reference. Only when this
2685 * request is retired will the the batch_obj be moved onto the
2686 * inactive_list and lose its active reference. Hence we do not need
2687 * to explicitly hold another reference here.
2689 request
->batch_obj
= obj
;
2691 if (!i915
.enable_execlists
) {
2692 /* Hold a reference to the current context so that we can inspect
2693 * it later in case a hangcheck error event fires.
2695 request
->ctx
= ring
->last_context
;
2697 i915_gem_context_reference(request
->ctx
);
2700 request
->emitted_jiffies
= jiffies
;
2701 ring
->last_submitted_seqno
= request
->seqno
;
2702 list_add_tail(&request
->list
, &ring
->request_list
);
2703 request
->file_priv
= NULL
;
2706 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2708 spin_lock(&file_priv
->mm
.lock
);
2709 request
->file_priv
= file_priv
;
2710 list_add_tail(&request
->client_list
,
2711 &file_priv
->mm
.request_list
);
2712 spin_unlock(&file_priv
->mm
.lock
);
2714 request
->pid
= curproc
->p_pid
;
2717 trace_i915_gem_request_add(request
);
2718 ring
->outstanding_lazy_request
= NULL
;
2720 i915_queue_hangcheck(ring
->dev
);
2722 queue_delayed_work(dev_priv
->wq
,
2723 &dev_priv
->mm
.retire_work
,
2724 round_jiffies_up_relative(HZ
));
2725 intel_mark_busy(dev_priv
->dev
);
2730 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2731 const struct intel_context
*ctx
)
2733 unsigned long elapsed
;
2735 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2737 if (ctx
->hang_stats
.banned
)
2740 if (ctx
->hang_stats
.ban_period_seconds
&&
2741 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2742 if (!i915_gem_context_is_default(ctx
)) {
2743 DRM_DEBUG("context hanging too fast, banning!\n");
2745 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2746 if (i915_stop_ring_allow_warn(dev_priv
))
2747 DRM_ERROR("gpu hanging too fast, banning!\n");
2755 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2756 struct intel_context
*ctx
,
2759 struct i915_ctx_hang_stats
*hs
;
2764 hs
= &ctx
->hang_stats
;
2767 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2769 hs
->guilty_ts
= get_seconds();
2771 hs
->batch_pending
++;
2775 void i915_gem_request_free(struct kref
*req_ref
)
2777 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2779 struct intel_context
*ctx
= req
->ctx
;
2782 if (i915
.enable_execlists
) {
2783 struct intel_engine_cs
*ring
= req
->ring
;
2785 if (ctx
!= ring
->default_context
)
2786 intel_lr_context_unpin(ring
, ctx
);
2789 i915_gem_context_unreference(ctx
);
2795 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2796 struct intel_context
*ctx
)
2798 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2799 struct drm_i915_gem_request
*req
;
2802 if (ring
->outstanding_lazy_request
)
2805 req
= kzalloc(sizeof(*req
), GFP_KERNEL
);
2809 kref_init(&req
->ref
);
2810 req
->i915
= dev_priv
;
2812 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2818 if (i915
.enable_execlists
)
2819 ret
= intel_logical_ring_alloc_request_extras(req
, ctx
);
2821 ret
= intel_ring_alloc_request_extras(req
);
2825 ring
->outstanding_lazy_request
= req
;
2833 struct drm_i915_gem_request
*
2834 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2836 struct drm_i915_gem_request
*request
;
2838 list_for_each_entry(request
, &ring
->request_list
, list
) {
2839 if (i915_gem_request_completed(request
, false))
2848 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2849 struct intel_engine_cs
*ring
)
2851 struct drm_i915_gem_request
*request
;
2854 request
= i915_gem_find_active_request(ring
);
2856 if (request
== NULL
)
2859 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2861 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2863 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2864 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2867 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2868 struct intel_engine_cs
*ring
)
2870 while (!list_empty(&ring
->active_list
)) {
2871 struct drm_i915_gem_object
*obj
;
2873 obj
= list_first_entry(&ring
->active_list
,
2874 struct drm_i915_gem_object
,
2875 ring_list
[ring
->id
]);
2877 i915_gem_object_retire__read(obj
, ring
->id
);
2881 * Clear the execlists queue up before freeing the requests, as those
2882 * are the ones that keep the context and ringbuffer backing objects
2885 while (!list_empty(&ring
->execlist_queue
)) {
2886 struct drm_i915_gem_request
*submit_req
;
2888 submit_req
= list_first_entry(&ring
->execlist_queue
,
2889 struct drm_i915_gem_request
,
2891 list_del(&submit_req
->execlist_link
);
2893 if (submit_req
->ctx
!= ring
->default_context
)
2894 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2896 i915_gem_request_unreference(submit_req
);
2900 * We must free the requests after all the corresponding objects have
2901 * been moved off active lists. Which is the same order as the normal
2902 * retire_requests function does. This is important if object hold
2903 * implicit references on things like e.g. ppgtt address spaces through
2906 while (!list_empty(&ring
->request_list
)) {
2907 struct drm_i915_gem_request
*request
;
2909 request
= list_first_entry(&ring
->request_list
,
2910 struct drm_i915_gem_request
,
2913 i915_gem_request_retire(request
);
2916 /* This may not have been flushed before the reset, so clean it now */
2917 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2920 void i915_gem_restore_fences(struct drm_device
*dev
)
2922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2925 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2926 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2929 * Commit delayed tiling changes if we have an object still
2930 * attached to the fence, otherwise just clear the fence.
2933 i915_gem_object_update_fence(reg
->obj
, reg
,
2934 reg
->obj
->tiling_mode
);
2936 i915_gem_write_fence(dev
, i
, NULL
);
2941 void i915_gem_reset(struct drm_device
*dev
)
2943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2944 struct intel_engine_cs
*ring
;
2948 * Before we free the objects from the requests, we need to inspect
2949 * them for finding the guilty party. As the requests only borrow
2950 * their reference to the objects, the inspection must be done first.
2952 for_each_ring(ring
, dev_priv
, i
)
2953 i915_gem_reset_ring_status(dev_priv
, ring
);
2955 for_each_ring(ring
, dev_priv
, i
)
2956 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2958 i915_gem_context_reset(dev
);
2960 i915_gem_restore_fences(dev
);
2962 WARN_ON(i915_verify_lists(dev
));
2966 * This function clears the request list as sequence numbers are passed.
2969 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2971 WARN_ON(i915_verify_lists(ring
->dev
));
2973 /* Retire requests first as we use it above for the early return.
2974 * If we retire requests last, we may use a later seqno and so clear
2975 * the requests lists without clearing the active list, leading to
2978 while (!list_empty(&ring
->request_list
)) {
2979 struct drm_i915_gem_request
*request
;
2981 request
= list_first_entry(&ring
->request_list
,
2982 struct drm_i915_gem_request
,
2985 if (!i915_gem_request_completed(request
, true))
2988 i915_gem_request_retire(request
);
2991 /* Move any buffers on the active list that are no longer referenced
2992 * by the ringbuffer to the flushing/inactive lists as appropriate,
2993 * before we free the context associated with the requests.
2995 while (!list_empty(&ring
->active_list
)) {
2996 struct drm_i915_gem_object
*obj
;
2998 obj
= list_first_entry(&ring
->active_list
,
2999 struct drm_i915_gem_object
,
3000 ring_list
[ring
->id
]);
3002 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
3005 i915_gem_object_retire__read(obj
, ring
->id
);
3008 if (unlikely(ring
->trace_irq_req
&&
3009 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
3010 ring
->irq_put(ring
);
3011 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
3014 WARN_ON(i915_verify_lists(ring
->dev
));
3018 i915_gem_retire_requests(struct drm_device
*dev
)
3020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3021 struct intel_engine_cs
*ring
;
3025 for_each_ring(ring
, dev_priv
, i
) {
3026 i915_gem_retire_requests_ring(ring
);
3027 idle
&= list_empty(&ring
->request_list
);
3028 if (i915
.enable_execlists
) {
3030 lockmgr(&ring
->execlist_lock
, LK_EXCLUSIVE
);
3031 idle
&= list_empty(&ring
->execlist_queue
);
3032 lockmgr(&ring
->execlist_lock
, LK_RELEASE
);
3034 intel_execlists_retire_requests(ring
);
3039 mod_delayed_work(dev_priv
->wq
,
3040 &dev_priv
->mm
.idle_work
,
3041 msecs_to_jiffies(100));
3047 i915_gem_retire_work_handler(struct work_struct
*work
)
3049 struct drm_i915_private
*dev_priv
=
3050 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3051 struct drm_device
*dev
= dev_priv
->dev
;
3054 /* Come back later if the device is busy... */
3056 if (mutex_trylock(&dev
->struct_mutex
)) {
3057 idle
= i915_gem_retire_requests(dev
);
3058 mutex_unlock(&dev
->struct_mutex
);
3061 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3062 round_jiffies_up_relative(HZ
));
3066 i915_gem_idle_work_handler(struct work_struct
*work
)
3068 struct drm_i915_private
*dev_priv
=
3069 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3070 struct drm_device
*dev
= dev_priv
->dev
;
3071 struct intel_engine_cs
*ring
;
3074 for_each_ring(ring
, dev_priv
, i
)
3075 if (!list_empty(&ring
->request_list
))
3078 intel_mark_idle(dev
);
3080 if (mutex_trylock(&dev
->struct_mutex
)) {
3081 struct intel_engine_cs
*ring
;
3084 for_each_ring(ring
, dev_priv
, i
)
3085 i915_gem_batch_pool_fini(&ring
->batch_pool
);
3087 mutex_unlock(&dev
->struct_mutex
);
3092 * Ensures that an object will eventually get non-busy by flushing any required
3093 * write domains, emitting any outstanding lazy request and retiring and
3094 * completed requests.
3097 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3104 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3105 struct drm_i915_gem_request
*req
;
3107 req
= obj
->last_read_req
[i
];
3111 if (list_empty(&req
->list
))
3114 ret
= i915_gem_check_olr(req
);
3118 if (i915_gem_request_completed(req
, true)) {
3119 __i915_gem_request_retire__upto(req
);
3121 i915_gem_object_retire__read(obj
, i
);
3129 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3130 * @DRM_IOCTL_ARGS: standard ioctl arguments
3132 * Returns 0 if successful, else an error is returned with the remaining time in
3133 * the timeout parameter.
3134 * -ETIME: object is still busy after timeout
3135 * -ERESTARTSYS: signal interrupted the wait
3136 * -ENONENT: object doesn't exist
3137 * Also possible, but rare:
3138 * -EAGAIN: GPU wedged
3140 * -ENODEV: Internal IRQ fail
3141 * -E?: The add request failed
3143 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3144 * non-zero timeout parameter the wait ioctl will wait for the given number of
3145 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3146 * without holding struct_mutex the object may become re-busied before this
3147 * function completes. A similar but shorter * race condition exists in the busy
3151 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3154 struct drm_i915_gem_wait
*args
= data
;
3155 struct drm_i915_gem_object
*obj
;
3156 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3157 unsigned reset_counter
;
3161 if (args
->flags
!= 0)
3164 ret
= i915_mutex_lock_interruptible(dev
);
3168 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3169 if (&obj
->base
== NULL
) {
3170 mutex_unlock(&dev
->struct_mutex
);
3174 /* Need to make sure the object gets inactive eventually. */
3175 ret
= i915_gem_object_flush_active(obj
);
3182 /* Do this after OLR check to make sure we make forward progress polling
3183 * on this IOCTL with a timeout == 0 (like busy ioctl)
3185 if (args
->timeout_ns
== 0) {
3190 drm_gem_object_unreference(&obj
->base
);
3191 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3193 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3194 if (obj
->last_read_req
[i
] == NULL
)
3197 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3200 mutex_unlock(&dev
->struct_mutex
);
3202 for (i
= 0; i
< n
; i
++) {
3204 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3205 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3207 i915_gem_request_unreference__unlocked(req
[i
]);
3212 drm_gem_object_unreference(&obj
->base
);
3213 mutex_unlock(&dev
->struct_mutex
);
3218 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3219 struct intel_engine_cs
*to
,
3220 struct drm_i915_gem_request
*req
)
3222 struct intel_engine_cs
*from
;
3225 from
= i915_gem_request_get_ring(req
);
3229 if (i915_gem_request_completed(req
, true))
3232 ret
= i915_gem_check_olr(req
);
3236 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3237 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3238 ret
= __i915_wait_request(req
,
3239 atomic_read(&i915
->gpu_error
.reset_counter
),
3240 i915
->mm
.interruptible
,
3242 &i915
->rps
.semaphores
);
3246 i915_gem_object_retire_request(obj
, req
);
3248 int idx
= intel_ring_sync_index(from
, to
);
3249 u32 seqno
= i915_gem_request_get_seqno(req
);
3251 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3254 trace_i915_gem_ring_sync_to(from
, to
, req
);
3255 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3259 /* We use last_read_req because sync_to()
3260 * might have just caused seqno wrap under
3263 from
->semaphore
.sync_seqno
[idx
] =
3264 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3271 * i915_gem_object_sync - sync an object to a ring.
3273 * @obj: object which may be in use on another ring.
3274 * @to: ring we wish to use the object on. May be NULL.
3276 * This code is meant to abstract object synchronization with the GPU.
3277 * Calling with NULL implies synchronizing the object with the CPU
3278 * rather than a particular GPU ring. Conceptually we serialise writes
3279 * between engines inside the GPU. We only allow on engine to write
3280 * into a buffer at any time, but multiple readers. To ensure each has
3281 * a coherent view of memory, we must:
3283 * - If there is an outstanding write request to the object, the new
3284 * request must wait for it to complete (either CPU or in hw, requests
3285 * on the same ring will be naturally ordered).
3287 * - If we are a write request (pending_write_domain is set), the new
3288 * request must wait for outstanding read requests to complete.
3290 * Returns 0 if successful, else propagates up the lower layer error.
3293 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3294 struct intel_engine_cs
*to
)
3296 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3297 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3304 return i915_gem_object_wait_rendering(obj
, readonly
);
3308 if (obj
->last_write_req
)
3309 req
[n
++] = obj
->last_write_req
;
3311 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3312 if (obj
->last_read_req
[i
])
3313 req
[n
++] = obj
->last_read_req
[i
];
3315 for (i
= 0; i
< n
; i
++) {
3316 ret
= __i915_gem_object_sync(obj
, to
, req
[i
]);
3324 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3326 u32 old_write_domain
, old_read_domains
;
3328 /* Force a pagefault for domain tracking on next user access */
3329 i915_gem_release_mmap(obj
);
3331 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3334 /* Wait for any direct GTT access to complete */
3337 old_read_domains
= obj
->base
.read_domains
;
3338 old_write_domain
= obj
->base
.write_domain
;
3340 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3341 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3343 trace_i915_gem_object_change_domain(obj
,
3348 int i915_vma_unbind(struct i915_vma
*vma
)
3350 struct drm_i915_gem_object
*obj
= vma
->obj
;
3351 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3354 if (list_empty(&vma
->vma_link
))
3357 if (!drm_mm_node_allocated(&vma
->node
)) {
3358 i915_gem_vma_destroy(vma
);
3365 BUG_ON(obj
->pages
== NULL
);
3367 ret
= i915_gem_object_wait_rendering(obj
, false);
3370 /* Continue on if we fail due to EIO, the GPU is hung so we
3371 * should be safe and we need to cleanup or else we might
3372 * cause memory corruption through use-after-free.
3375 if (i915_is_ggtt(vma
->vm
) &&
3376 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3377 i915_gem_object_finish_gtt(obj
);
3379 /* release the fence reg _after_ flushing */
3380 ret
= i915_gem_object_put_fence(obj
);
3385 trace_i915_vma_unbind(vma
);
3387 vma
->vm
->unbind_vma(vma
);
3390 list_del_init(&vma
->mm_list
);
3391 if (i915_is_ggtt(vma
->vm
)) {
3392 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3393 obj
->map_and_fenceable
= false;
3394 } else if (vma
->ggtt_view
.pages
) {
3395 sg_free_table(vma
->ggtt_view
.pages
);
3396 kfree(vma
->ggtt_view
.pages
);
3398 vma
->ggtt_view
.pages
= NULL
;
3401 drm_mm_remove_node(&vma
->node
);
3402 i915_gem_vma_destroy(vma
);
3404 /* Since the unbound list is global, only move to that list if
3405 * no more VMAs exist. */
3406 if (list_empty(&obj
->vma_list
))
3407 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3409 /* And finally now the object is completely decoupled from this vma,
3410 * we can drop its hold on the backing storage and allow it to be
3411 * reaped by the shrinker.
3413 i915_gem_object_unpin_pages(obj
);
3418 int i915_gpu_idle(struct drm_device
*dev
)
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3421 struct intel_engine_cs
*ring
;
3424 /* Flush everything onto the inactive list. */
3425 for_each_ring(ring
, dev_priv
, i
) {
3426 if (!i915
.enable_execlists
) {
3427 ret
= i915_switch_context(ring
, ring
->default_context
);
3432 ret
= intel_ring_idle(ring
);
3437 WARN_ON(i915_verify_lists(dev
));
3441 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3442 struct drm_i915_gem_object
*obj
)
3444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3446 int fence_pitch_shift
;
3448 if (INTEL_INFO(dev
)->gen
>= 6) {
3449 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3450 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3452 fence_reg
= FENCE_REG_965_0
;
3453 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3456 fence_reg
+= reg
* 8;
3458 /* To w/a incoherency with non-atomic 64-bit register updates,
3459 * we split the 64-bit update into two 32-bit writes. In order
3460 * for a partial fence not to be evaluated between writes, we
3461 * precede the update with write to turn off the fence register,
3462 * and only enable the fence as the last step.
3464 * For extra levels of paranoia, we make sure each step lands
3465 * before applying the next step.
3467 I915_WRITE(fence_reg
, 0);
3468 POSTING_READ(fence_reg
);
3471 u32 size
= i915_gem_obj_ggtt_size(obj
);
3474 /* Adjust fence size to match tiled area */
3475 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3476 uint32_t row_size
= obj
->stride
*
3477 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3478 size
= (size
/ row_size
) * row_size
;
3481 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3483 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3484 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3485 if (obj
->tiling_mode
== I915_TILING_Y
)
3486 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3487 val
|= I965_FENCE_REG_VALID
;
3489 I915_WRITE(fence_reg
+ 4, val
>> 32);
3490 POSTING_READ(fence_reg
+ 4);
3492 I915_WRITE(fence_reg
+ 0, val
);
3493 POSTING_READ(fence_reg
);
3495 I915_WRITE(fence_reg
+ 4, 0);
3496 POSTING_READ(fence_reg
+ 4);
3500 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3501 struct drm_i915_gem_object
*obj
)
3503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3507 u32 size
= i915_gem_obj_ggtt_size(obj
);
3511 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3512 (size
& -size
) != size
||
3513 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3514 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3515 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3517 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3522 /* Note: pitch better be a power of two tile widths */
3523 pitch_val
= obj
->stride
/ tile_width
;
3524 pitch_val
= ffs(pitch_val
) - 1;
3526 val
= i915_gem_obj_ggtt_offset(obj
);
3527 if (obj
->tiling_mode
== I915_TILING_Y
)
3528 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3529 val
|= I915_FENCE_SIZE_BITS(size
);
3530 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3531 val
|= I830_FENCE_REG_VALID
;
3536 reg
= FENCE_REG_830_0
+ reg
* 4;
3538 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3540 I915_WRITE(reg
, val
);
3544 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3545 struct drm_i915_gem_object
*obj
)
3547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3551 u32 size
= i915_gem_obj_ggtt_size(obj
);
3554 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3555 (size
& -size
) != size
||
3556 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3557 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3558 i915_gem_obj_ggtt_offset(obj
), size
);
3560 pitch_val
= obj
->stride
/ 128;
3561 pitch_val
= ffs(pitch_val
) - 1;
3563 val
= i915_gem_obj_ggtt_offset(obj
);
3564 if (obj
->tiling_mode
== I915_TILING_Y
)
3565 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3566 val
|= I830_FENCE_SIZE_BITS(size
);
3567 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3568 val
|= I830_FENCE_REG_VALID
;
3572 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3573 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3576 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3578 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3581 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3582 struct drm_i915_gem_object
*obj
)
3584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3586 /* Ensure that all CPU reads are completed before installing a fence
3587 * and all writes before removing the fence.
3589 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3592 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3593 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3594 obj
->stride
, obj
->tiling_mode
);
3597 i830_write_fence_reg(dev
, reg
, obj
);
3598 else if (IS_GEN3(dev
))
3599 i915_write_fence_reg(dev
, reg
, obj
);
3600 else if (INTEL_INFO(dev
)->gen
>= 4)
3601 i965_write_fence_reg(dev
, reg
, obj
);
3603 /* And similarly be paranoid that no direct access to this region
3604 * is reordered to before the fence is installed.
3606 if (i915_gem_object_needs_mb(obj
))
3610 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3611 struct drm_i915_fence_reg
*fence
)
3613 return fence
- dev_priv
->fence_regs
;
3616 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3617 struct drm_i915_fence_reg
*fence
,
3620 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3621 int reg
= fence_number(dev_priv
, fence
);
3623 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3626 obj
->fence_reg
= reg
;
3628 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3630 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3632 list_del_init(&fence
->lru_list
);
3634 obj
->fence_dirty
= false;
3638 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3640 if (obj
->last_fenced_req
) {
3641 int ret
= i915_wait_request(obj
->last_fenced_req
);
3645 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3652 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3654 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3655 struct drm_i915_fence_reg
*fence
;
3658 ret
= i915_gem_object_wait_fence(obj
);
3662 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3665 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3667 if (WARN_ON(fence
->pin_count
))
3670 i915_gem_object_fence_lost(obj
);
3671 i915_gem_object_update_fence(obj
, fence
, false);
3676 static struct drm_i915_fence_reg
*
3677 i915_find_fence_reg(struct drm_device
*dev
)
3679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3680 struct drm_i915_fence_reg
*reg
, *avail
;
3683 /* First try to find a free reg */
3685 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3686 reg
= &dev_priv
->fence_regs
[i
];
3690 if (!reg
->pin_count
)
3697 /* None available, try to steal one or wait for a user to finish */
3698 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3706 /* Wait for completion of pending flips which consume fences */
3707 if (intel_has_pending_fb_unpin(dev
))
3708 return ERR_PTR(-EAGAIN
);
3710 return ERR_PTR(-EDEADLK
);
3714 * i915_gem_object_get_fence - set up fencing for an object
3715 * @obj: object to map through a fence reg
3717 * When mapping objects through the GTT, userspace wants to be able to write
3718 * to them without having to worry about swizzling if the object is tiled.
3719 * This function walks the fence regs looking for a free one for @obj,
3720 * stealing one if it can't find any.
3722 * It then sets up the reg based on the object's properties: address, pitch
3723 * and tiling format.
3725 * For an untiled surface, this removes any existing fence.
3728 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3730 struct drm_device
*dev
= obj
->base
.dev
;
3731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3732 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3733 struct drm_i915_fence_reg
*reg
;
3736 /* Have we updated the tiling parameters upon the object and so
3737 * will need to serialise the write to the associated fence register?
3739 if (obj
->fence_dirty
) {
3740 ret
= i915_gem_object_wait_fence(obj
);
3745 /* Just update our place in the LRU if our fence is getting reused. */
3746 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3747 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3748 if (!obj
->fence_dirty
) {
3749 list_move_tail(®
->lru_list
,
3750 &dev_priv
->mm
.fence_list
);
3753 } else if (enable
) {
3754 if (WARN_ON(!obj
->map_and_fenceable
))
3757 reg
= i915_find_fence_reg(dev
);
3759 return PTR_ERR(reg
);
3762 struct drm_i915_gem_object
*old
= reg
->obj
;
3764 ret
= i915_gem_object_wait_fence(old
);
3768 i915_gem_object_fence_lost(old
);
3773 i915_gem_object_update_fence(obj
, reg
, enable
);
3778 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3779 unsigned long cache_level
)
3781 struct drm_mm_node
*gtt_space
= &vma
->node
;
3782 struct drm_mm_node
*other
;
3785 * On some machines we have to be careful when putting differing types
3786 * of snoopable memory together to avoid the prefetcher crossing memory
3787 * domains and dying. During vm initialisation, we decide whether or not
3788 * these constraints apply and set the drm_mm.color_adjust
3791 if (vma
->vm
->mm
.color_adjust
== NULL
)
3794 if (!drm_mm_node_allocated(gtt_space
))
3797 if (list_empty(>t_space
->node_list
))
3800 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3801 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3804 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3805 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3812 * Finds free space in the GTT aperture and binds the object or a view of it
3815 static struct i915_vma
*
3816 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3817 struct i915_address_space
*vm
,
3818 const struct i915_ggtt_view
*ggtt_view
,
3822 struct drm_device
*dev
= obj
->base
.dev
;
3823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3825 unsigned long start
=
3826 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3828 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3829 struct i915_vma
*vma
;
3832 if (i915_is_ggtt(vm
)) {
3835 if (WARN_ON(!ggtt_view
))
3836 return ERR_PTR(-EINVAL
);
3838 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3840 fence_size
= i915_gem_get_gtt_size(dev
,
3843 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3847 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3851 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3853 fence_size
= i915_gem_get_gtt_size(dev
,
3856 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3860 unfenced_alignment
=
3861 i915_gem_get_gtt_alignment(dev
,
3865 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3869 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3871 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3872 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3873 ggtt_view
? ggtt_view
->type
: 0,
3875 return ERR_PTR(-EINVAL
);
3878 /* If binding the object/GGTT view requires more space than the entire
3879 * aperture has, reject it early before evicting everything in a vain
3880 * attempt to find space.
3883 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3884 ggtt_view
? ggtt_view
->type
: 0,
3886 flags
& PIN_MAPPABLE
? "mappable" : "total",
3888 return ERR_PTR(-E2BIG
);
3891 ret
= i915_gem_object_get_pages(obj
);
3893 return ERR_PTR(ret
);
3895 i915_gem_object_pin_pages(obj
);
3897 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3898 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3904 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3908 DRM_MM_SEARCH_DEFAULT
,
3909 DRM_MM_CREATE_DEFAULT
);
3911 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3920 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3922 goto err_remove_node
;
3925 trace_i915_vma_bind(vma
, flags
);
3926 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3928 goto err_remove_node
;
3930 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3931 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3936 drm_mm_remove_node(&vma
->node
);
3938 i915_gem_vma_destroy(vma
);
3941 i915_gem_object_unpin_pages(obj
);
3946 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3949 /* If we don't have a page list set up, then we're not pinned
3950 * to GPU, and we can ignore the cache flush because it'll happen
3951 * again at bind time.
3953 if (obj
->pages
== NULL
)
3957 * Stolen memory is always coherent with the GPU as it is explicitly
3958 * marked as wc by the system, or the system is cache-coherent.
3960 if (obj
->stolen
|| obj
->phys_handle
)
3963 /* If the GPU is snooping the contents of the CPU cache,
3964 * we do not need to manually clear the CPU cache lines. However,
3965 * the caches are only snooped when the render cache is
3966 * flushed/invalidated. As we always have to emit invalidations
3967 * and flushes when moving into and out of the RENDER domain, correct
3968 * snooping behaviour occurs naturally as the result of our domain
3971 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3972 obj
->cache_dirty
= true;
3976 trace_i915_gem_object_clflush(obj
);
3977 drm_clflush_sg(obj
->pages
);
3978 obj
->cache_dirty
= false;
3983 /** Flushes the GTT write domain for the object if it's dirty. */
3985 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3987 uint32_t old_write_domain
;
3989 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3992 /* No actual flushing is required for the GTT write domain. Writes
3993 * to it immediately go to main memory as far as we know, so there's
3994 * no chipset flush. It also doesn't land in render cache.
3996 * However, we do have to enforce the order so that all writes through
3997 * the GTT land before any writes to the device, such as updates to
4002 old_write_domain
= obj
->base
.write_domain
;
4003 obj
->base
.write_domain
= 0;
4005 intel_fb_obj_flush(obj
, false);
4007 trace_i915_gem_object_change_domain(obj
,
4008 obj
->base
.read_domains
,
4012 /** Flushes the CPU write domain for the object if it's dirty. */
4014 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
4016 uint32_t old_write_domain
;
4018 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
4021 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
4022 i915_gem_chipset_flush(obj
->base
.dev
);
4024 old_write_domain
= obj
->base
.write_domain
;
4025 obj
->base
.write_domain
= 0;
4027 intel_fb_obj_flush(obj
, false);
4029 trace_i915_gem_object_change_domain(obj
,
4030 obj
->base
.read_domains
,
4035 * Moves a single object to the GTT read, and possibly write domain.
4037 * This function returns when the move is complete, including waiting on
4041 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
4043 uint32_t old_write_domain
, old_read_domains
;
4044 struct i915_vma
*vma
;
4047 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
4050 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4054 /* Flush and acquire obj->pages so that we are coherent through
4055 * direct access in memory with previous cached writes through
4056 * shmemfs and that our cache domain tracking remains valid.
4057 * For example, if the obj->filp was moved to swap without us
4058 * being notified and releasing the pages, we would mistakenly
4059 * continue to assume that the obj remained out of the CPU cached
4062 ret
= i915_gem_object_get_pages(obj
);
4066 i915_gem_object_flush_cpu_write_domain(obj
);
4068 /* Serialise direct access to this object with the barriers for
4069 * coherent writes from the GPU, by effectively invalidating the
4070 * GTT domain upon first access.
4072 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
4075 old_write_domain
= obj
->base
.write_domain
;
4076 old_read_domains
= obj
->base
.read_domains
;
4078 /* It should now be out of any other write domains, and we can update
4079 * the domain values for our changes.
4081 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4082 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4084 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4085 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4090 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
4092 trace_i915_gem_object_change_domain(obj
,
4096 /* And bump the LRU for this access */
4097 vma
= i915_gem_obj_to_ggtt(obj
);
4098 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4099 list_move_tail(&vma
->mm_list
,
4100 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
4105 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4106 enum i915_cache_level cache_level
)
4108 struct drm_device
*dev
= obj
->base
.dev
;
4109 struct i915_vma
*vma
, *next
;
4112 if (obj
->cache_level
== cache_level
)
4115 if (i915_gem_obj_is_pinned(obj
)) {
4116 DRM_DEBUG("can not change the cache level of pinned objects\n");
4120 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4121 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4122 ret
= i915_vma_unbind(vma
);
4128 if (i915_gem_obj_bound_any(obj
)) {
4129 ret
= i915_gem_object_wait_rendering(obj
, false);
4133 i915_gem_object_finish_gtt(obj
);
4135 /* Before SandyBridge, you could not use tiling or fence
4136 * registers with snooped memory, so relinquish any fences
4137 * currently pointing to our region in the aperture.
4139 if (INTEL_INFO(dev
)->gen
< 6) {
4140 ret
= i915_gem_object_put_fence(obj
);
4145 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4146 if (drm_mm_node_allocated(&vma
->node
)) {
4147 ret
= i915_vma_bind(vma
, cache_level
,
4154 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4155 vma
->node
.color
= cache_level
;
4156 obj
->cache_level
= cache_level
;
4158 if (obj
->cache_dirty
&&
4159 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4160 cpu_write_needs_clflush(obj
)) {
4161 if (i915_gem_clflush_object(obj
, true))
4162 i915_gem_chipset_flush(obj
->base
.dev
);
4168 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4169 struct drm_file
*file
)
4171 struct drm_i915_gem_caching
*args
= data
;
4172 struct drm_i915_gem_object
*obj
;
4174 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4175 if (&obj
->base
== NULL
)
4178 switch (obj
->cache_level
) {
4179 case I915_CACHE_LLC
:
4180 case I915_CACHE_L3_LLC
:
4181 args
->caching
= I915_CACHING_CACHED
;
4185 args
->caching
= I915_CACHING_DISPLAY
;
4189 args
->caching
= I915_CACHING_NONE
;
4193 drm_gem_object_unreference_unlocked(&obj
->base
);
4197 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4198 struct drm_file
*file
)
4200 struct drm_i915_gem_caching
*args
= data
;
4201 struct drm_i915_gem_object
*obj
;
4202 enum i915_cache_level level
;
4205 switch (args
->caching
) {
4206 case I915_CACHING_NONE
:
4207 level
= I915_CACHE_NONE
;
4209 case I915_CACHING_CACHED
:
4210 level
= I915_CACHE_LLC
;
4212 case I915_CACHING_DISPLAY
:
4213 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4219 ret
= i915_mutex_lock_interruptible(dev
);
4223 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4224 if (&obj
->base
== NULL
) {
4229 ret
= i915_gem_object_set_cache_level(obj
, level
);
4231 drm_gem_object_unreference(&obj
->base
);
4233 mutex_unlock(&dev
->struct_mutex
);
4238 * Prepare buffer for display plane (scanout, cursors, etc).
4239 * Can be called from an uninterruptible phase (modesetting) and allows
4240 * any flushes to be pipelined (for pageflips).
4243 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4245 struct intel_engine_cs
*pipelined
,
4246 const struct i915_ggtt_view
*view
)
4248 u32 old_read_domains
, old_write_domain
;
4251 ret
= i915_gem_object_sync(obj
, pipelined
);
4255 /* Mark the pin_display early so that we account for the
4256 * display coherency whilst setting up the cache domains.
4260 /* The display engine is not coherent with the LLC cache on gen6. As
4261 * a result, we make sure that the pinning that is about to occur is
4262 * done with uncached PTEs. This is lowest common denominator for all
4265 * However for gen6+, we could do better by using the GFDT bit instead
4266 * of uncaching, which would allow us to flush all the LLC-cached data
4267 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4269 ret
= i915_gem_object_set_cache_level(obj
,
4270 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4272 goto err_unpin_display
;
4274 /* As the user may map the buffer once pinned in the display plane
4275 * (e.g. libkms for the bootup splash), we have to ensure that we
4276 * always use map_and_fenceable for all scanout buffers.
4278 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4279 view
->type
== I915_GGTT_VIEW_NORMAL
?
4282 goto err_unpin_display
;
4284 i915_gem_object_flush_cpu_write_domain(obj
);
4286 old_write_domain
= obj
->base
.write_domain
;
4287 old_read_domains
= obj
->base
.read_domains
;
4289 /* It should now be out of any other write domains, and we can update
4290 * the domain values for our changes.
4292 obj
->base
.write_domain
= 0;
4293 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4295 trace_i915_gem_object_change_domain(obj
,
4307 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4308 const struct i915_ggtt_view
*view
)
4310 if (WARN_ON(obj
->pin_display
== 0))
4313 i915_gem_object_ggtt_unpin_view(obj
, view
);
4319 * Moves a single object to the CPU read, and possibly write domain.
4321 * This function returns when the move is complete, including waiting on
4325 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4327 uint32_t old_write_domain
, old_read_domains
;
4330 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4333 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4337 i915_gem_object_flush_gtt_write_domain(obj
);
4339 old_write_domain
= obj
->base
.write_domain
;
4340 old_read_domains
= obj
->base
.read_domains
;
4342 /* Flush the CPU cache if it's still invalid. */
4343 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4344 i915_gem_clflush_object(obj
, false);
4346 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4349 /* It should now be out of any other write domains, and we can update
4350 * the domain values for our changes.
4352 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4354 /* If we're writing through the CPU, then the GPU read domains will
4355 * need to be invalidated at next use.
4358 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4359 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4363 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4365 trace_i915_gem_object_change_domain(obj
,
4372 /* Throttle our rendering by waiting until the ring has completed our requests
4373 * emitted over 20 msec ago.
4375 * Note that if we were to use the current jiffies each time around the loop,
4376 * we wouldn't escape the function with any frames outstanding if the time to
4377 * render a frame was over 20ms.
4379 * This should get us reasonable parallelism between CPU and GPU but also
4380 * relatively low latency when blocking on a particular request to finish.
4383 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4386 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4387 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4388 struct drm_i915_gem_request
*request
, *target
= NULL
;
4389 unsigned reset_counter
;
4392 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4396 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4400 spin_lock(&file_priv
->mm
.lock
);
4401 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4402 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4407 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4409 i915_gem_request_reference(target
);
4410 spin_unlock(&file_priv
->mm
.lock
);
4415 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4417 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4419 i915_gem_request_unreference__unlocked(target
);
4425 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4427 struct drm_i915_gem_object
*obj
= vma
->obj
;
4430 vma
->node
.start
& (alignment
- 1))
4433 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4436 if (flags
& PIN_OFFSET_BIAS
&&
4437 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4444 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4445 struct i915_address_space
*vm
,
4446 const struct i915_ggtt_view
*ggtt_view
,
4450 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4451 struct i915_vma
*vma
;
4455 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4458 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4461 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4464 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4467 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4468 i915_gem_obj_to_vma(obj
, vm
);
4471 return PTR_ERR(vma
);
4474 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4477 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4478 unsigned long offset
;
4479 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4480 i915_gem_obj_offset(obj
, vm
);
4481 WARN(vma
->pin_count
,
4482 "bo is already pinned in %s with incorrect alignment:"
4483 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4484 " obj->map_and_fenceable=%d\n",
4485 ggtt_view
? "ggtt" : "ppgtt",
4488 !!(flags
& PIN_MAPPABLE
),
4489 obj
->map_and_fenceable
);
4490 ret
= i915_vma_unbind(vma
);
4498 bound
= vma
? vma
->bound
: 0;
4499 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4500 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4503 return PTR_ERR(vma
);
4505 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4510 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4511 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4512 bool mappable
, fenceable
;
4513 u32 fence_size
, fence_alignment
;
4515 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4518 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4523 fenceable
= (vma
->node
.size
== fence_size
&&
4524 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4526 mappable
= (vma
->node
.start
+ fence_size
<=
4527 dev_priv
->gtt
.mappable_end
);
4529 obj
->map_and_fenceable
= mappable
&& fenceable
;
4531 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4539 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4540 struct i915_address_space
*vm
,
4544 return i915_gem_object_do_pin(obj
, vm
,
4545 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4550 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4551 const struct i915_ggtt_view
*view
,
4555 if (WARN_ONCE(!view
, "no view specified"))
4558 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4559 alignment
, flags
| PIN_GLOBAL
);
4563 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4564 const struct i915_ggtt_view
*view
)
4566 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4569 WARN_ON(vma
->pin_count
== 0);
4570 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4576 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4578 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4579 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4580 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4582 WARN_ON(!ggtt_vma
||
4583 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4584 ggtt_vma
->pin_count
);
4585 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4592 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4594 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4595 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4596 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4597 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4602 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4603 struct drm_file
*file
)
4605 struct drm_i915_gem_busy
*args
= data
;
4606 struct drm_i915_gem_object
*obj
;
4609 ret
= i915_mutex_lock_interruptible(dev
);
4613 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4614 if (&obj
->base
== NULL
) {
4619 /* Count all active objects as busy, even if they are currently not used
4620 * by the gpu. Users of this interface expect objects to eventually
4621 * become non-busy without any further actions, therefore emit any
4622 * necessary flushes here.
4624 ret
= i915_gem_object_flush_active(obj
);
4628 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4629 args
->busy
= obj
->active
<< 16;
4630 if (obj
->last_write_req
)
4631 args
->busy
|= obj
->last_write_req
->ring
->id
;
4634 drm_gem_object_unreference(&obj
->base
);
4636 mutex_unlock(&dev
->struct_mutex
);
4641 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4642 struct drm_file
*file_priv
)
4644 return i915_gem_ring_throttle(dev
, file_priv
);
4648 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4649 struct drm_file
*file_priv
)
4651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4652 struct drm_i915_gem_madvise
*args
= data
;
4653 struct drm_i915_gem_object
*obj
;
4656 switch (args
->madv
) {
4657 case I915_MADV_DONTNEED
:
4658 case I915_MADV_WILLNEED
:
4664 ret
= i915_mutex_lock_interruptible(dev
);
4668 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4669 if (&obj
->base
== NULL
) {
4674 if (i915_gem_obj_is_pinned(obj
)) {
4680 obj
->tiling_mode
!= I915_TILING_NONE
&&
4681 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4682 if (obj
->madv
== I915_MADV_WILLNEED
)
4683 i915_gem_object_unpin_pages(obj
);
4684 if (args
->madv
== I915_MADV_WILLNEED
)
4685 i915_gem_object_pin_pages(obj
);
4688 if (obj
->madv
!= __I915_MADV_PURGED
)
4689 obj
->madv
= args
->madv
;
4691 /* if the object is no longer attached, discard its backing storage */
4692 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4693 i915_gem_object_truncate(obj
);
4695 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4698 drm_gem_object_unreference(&obj
->base
);
4700 mutex_unlock(&dev
->struct_mutex
);
4704 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4705 const struct drm_i915_gem_object_ops
*ops
)
4709 INIT_LIST_HEAD(&obj
->global_list
);
4710 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4711 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4712 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4713 INIT_LIST_HEAD(&obj
->vma_list
);
4714 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4718 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4719 obj
->madv
= I915_MADV_WILLNEED
;
4721 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4724 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4725 .get_pages
= i915_gem_object_get_pages_gtt
,
4726 .put_pages
= i915_gem_object_put_pages_gtt
,
4729 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4732 struct drm_i915_gem_object
*obj
;
4734 struct address_space
*mapping
;
4738 obj
= i915_gem_object_alloc(dev
);
4742 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4743 i915_gem_object_free(obj
);
4748 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4749 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4750 /* 965gm cannot relocate objects above 4GiB. */
4751 mask
&= ~__GFP_HIGHMEM
;
4752 mask
|= __GFP_DMA32
;
4755 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4756 mapping_set_gfp_mask(mapping
, mask
);
4759 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4761 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4762 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4765 /* On some devices, we can have the GPU use the LLC (the CPU
4766 * cache) for about a 10% performance improvement
4767 * compared to uncached. Graphics requests other than
4768 * display scanout are coherent with the CPU in
4769 * accessing this cache. This means in this mode we
4770 * don't need to clflush on the CPU side, and on the
4771 * GPU side we only need to flush internal caches to
4772 * get data visible to the CPU.
4774 * However, we maintain the display planes as UC, and so
4775 * need to rebind when first used as such.
4777 obj
->cache_level
= I915_CACHE_LLC
;
4779 obj
->cache_level
= I915_CACHE_NONE
;
4781 trace_i915_gem_object_create(obj
);
4786 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4788 /* If we are the last user of the backing storage (be it shmemfs
4789 * pages or stolen etc), we know that the pages are going to be
4790 * immediately released. In this case, we can then skip copying
4791 * back the contents from the GPU.
4794 if (obj
->madv
!= I915_MADV_WILLNEED
)
4797 if (obj
->base
.vm_obj
== NULL
)
4800 /* At first glance, this looks racy, but then again so would be
4801 * userspace racing mmap against close. However, the first external
4802 * reference to the filp can only be obtained through the
4803 * i915_gem_mmap_ioctl() which safeguards us against the user
4804 * acquiring such a reference whilst we are in the middle of
4805 * freeing the object.
4808 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4814 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4816 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4817 struct drm_device
*dev
= obj
->base
.dev
;
4818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4819 struct i915_vma
*vma
, *next
;
4821 intel_runtime_pm_get(dev_priv
);
4823 trace_i915_gem_object_destroy(obj
);
4825 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4829 ret
= i915_vma_unbind(vma
);
4830 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4831 bool was_interruptible
;
4833 was_interruptible
= dev_priv
->mm
.interruptible
;
4834 dev_priv
->mm
.interruptible
= false;
4836 WARN_ON(i915_vma_unbind(vma
));
4838 dev_priv
->mm
.interruptible
= was_interruptible
;
4842 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4843 * before progressing. */
4845 i915_gem_object_unpin_pages(obj
);
4847 WARN_ON(obj
->frontbuffer_bits
);
4849 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4850 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4851 obj
->tiling_mode
!= I915_TILING_NONE
)
4852 i915_gem_object_unpin_pages(obj
);
4854 if (WARN_ON(obj
->pages_pin_count
))
4855 obj
->pages_pin_count
= 0;
4856 if (discard_backing_storage(obj
))
4857 obj
->madv
= I915_MADV_DONTNEED
;
4858 i915_gem_object_put_pages(obj
);
4859 i915_gem_object_free_mmap_offset(obj
);
4864 if (obj
->base
.import_attach
)
4865 drm_prime_gem_destroy(&obj
->base
, NULL
);
4868 if (obj
->ops
->release
)
4869 obj
->ops
->release(obj
);
4871 drm_gem_object_release(&obj
->base
);
4872 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4875 i915_gem_object_free(obj
);
4877 intel_runtime_pm_put(dev_priv
);
4880 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4881 struct i915_address_space
*vm
)
4883 struct i915_vma
*vma
;
4884 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4885 if (i915_is_ggtt(vma
->vm
) &&
4886 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4894 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4895 const struct i915_ggtt_view
*view
)
4897 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4898 struct i915_vma
*vma
;
4900 if (WARN_ONCE(!view
, "no view specified"))
4901 return ERR_PTR(-EINVAL
);
4903 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4904 if (vma
->vm
== ggtt
&&
4905 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4910 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4912 struct i915_address_space
*vm
= NULL
;
4913 WARN_ON(vma
->node
.allocated
);
4915 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4916 if (!list_empty(&vma
->exec_list
))
4921 if (!i915_is_ggtt(vm
))
4922 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4924 list_del(&vma
->vma_link
);
4930 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4933 struct intel_engine_cs
*ring
;
4936 for_each_ring(ring
, dev_priv
, i
)
4937 dev_priv
->gt
.stop_ring(ring
);
4941 i915_gem_suspend(struct drm_device
*dev
)
4943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4946 mutex_lock(&dev
->struct_mutex
);
4947 ret
= i915_gpu_idle(dev
);
4951 i915_gem_retire_requests(dev
);
4953 i915_gem_stop_ringbuffers(dev
);
4954 mutex_unlock(&dev
->struct_mutex
);
4956 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4957 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4959 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4962 /* Assert that we sucessfully flushed all the work and
4963 * reset the GPU back to its idle, low power state.
4965 WARN_ON(dev_priv
->mm
.busy
);
4970 mutex_unlock(&dev
->struct_mutex
);
4974 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4976 struct drm_device
*dev
= ring
->dev
;
4977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4978 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4979 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4982 if (!HAS_L3_DPF(dev
) || !remap_info
)
4985 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4990 * Note: We do not worry about the concurrent register cacheline hang
4991 * here because no other code should access these registers other than
4992 * at initialization time.
4994 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4995 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4996 intel_ring_emit(ring
, reg_base
+ i
);
4997 intel_ring_emit(ring
, remap_info
[i
/4]);
5000 intel_ring_advance(ring
);
5005 void i915_gem_init_swizzling(struct drm_device
*dev
)
5007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5009 if (INTEL_INFO(dev
)->gen
< 5 ||
5010 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
5013 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
5014 DISP_TILE_SURFACE_SWIZZLING
);
5019 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
5021 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
5022 else if (IS_GEN7(dev
))
5023 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
5024 else if (IS_GEN8(dev
))
5025 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
5031 intel_enable_blt(struct drm_device
*dev
)
5036 /* The blitter was dysfunctional on early prototypes */
5037 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
5038 DRM_INFO("BLT not supported on this pre-production hardware;"
5039 " graphics performance will be degraded.\n");
5046 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
5048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5050 I915_WRITE(RING_CTL(base
), 0);
5051 I915_WRITE(RING_HEAD(base
), 0);
5052 I915_WRITE(RING_TAIL(base
), 0);
5053 I915_WRITE(RING_START(base
), 0);
5056 static void init_unused_rings(struct drm_device
*dev
)
5059 init_unused_ring(dev
, PRB1_BASE
);
5060 init_unused_ring(dev
, SRB0_BASE
);
5061 init_unused_ring(dev
, SRB1_BASE
);
5062 init_unused_ring(dev
, SRB2_BASE
);
5063 init_unused_ring(dev
, SRB3_BASE
);
5064 } else if (IS_GEN2(dev
)) {
5065 init_unused_ring(dev
, SRB0_BASE
);
5066 init_unused_ring(dev
, SRB1_BASE
);
5067 } else if (IS_GEN3(dev
)) {
5068 init_unused_ring(dev
, PRB1_BASE
);
5069 init_unused_ring(dev
, PRB2_BASE
);
5073 int i915_gem_init_rings(struct drm_device
*dev
)
5075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5078 ret
= intel_init_render_ring_buffer(dev
);
5083 ret
= intel_init_bsd_ring_buffer(dev
);
5085 goto cleanup_render_ring
;
5088 if (intel_enable_blt(dev
)) {
5089 ret
= intel_init_blt_ring_buffer(dev
);
5091 goto cleanup_bsd_ring
;
5094 if (HAS_VEBOX(dev
)) {
5095 ret
= intel_init_vebox_ring_buffer(dev
);
5097 goto cleanup_blt_ring
;
5100 if (HAS_BSD2(dev
)) {
5101 ret
= intel_init_bsd2_ring_buffer(dev
);
5103 goto cleanup_vebox_ring
;
5106 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
5108 goto cleanup_bsd2_ring
;
5113 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
5115 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
5117 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
5119 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
5120 cleanup_render_ring
:
5121 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
5127 i915_gem_init_hw(struct drm_device
*dev
)
5129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5130 struct intel_engine_cs
*ring
;
5134 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
5138 /* Double layer security blanket, see i915_gem_init() */
5139 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5141 if (dev_priv
->ellc_size
)
5142 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5144 if (IS_HASWELL(dev
))
5145 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5146 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5148 if (HAS_PCH_NOP(dev
)) {
5149 if (IS_IVYBRIDGE(dev
)) {
5150 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5151 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5152 I915_WRITE(GEN7_MSG_CTL
, temp
);
5153 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5154 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5155 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5156 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5160 i915_gem_init_swizzling(dev
);
5163 * At least 830 can leave some of the unused rings
5164 * "active" (ie. head != tail) after resume which
5165 * will prevent c3 entry. Makes sure all unused rings
5168 init_unused_rings(dev
);
5170 for_each_ring(ring
, dev_priv
, i
) {
5171 ret
= ring
->init_hw(ring
);
5176 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
5177 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
5179 ret
= i915_ppgtt_init_hw(dev
);
5180 if (ret
&& ret
!= -EIO
) {
5181 DRM_ERROR("PPGTT enable failed %d\n", ret
);
5182 i915_gem_cleanup_ringbuffer(dev
);
5185 ret
= i915_gem_context_enable(dev_priv
);
5186 if (ret
&& ret
!= -EIO
) {
5187 DRM_ERROR("Context enable failed %d\n", ret
);
5188 i915_gem_cleanup_ringbuffer(dev
);
5194 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5198 int i915_gem_init(struct drm_device
*dev
)
5200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5203 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5204 i915
.enable_execlists
);
5206 mutex_lock(&dev
->struct_mutex
);
5208 if (IS_VALLEYVIEW(dev
)) {
5209 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5210 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5211 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5212 VLV_GTLC_ALLOWWAKEACK
), 10))
5213 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5216 if (!i915
.enable_execlists
) {
5217 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5218 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5219 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5220 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5222 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5223 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5224 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5225 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5228 /* This is just a security blanket to placate dragons.
5229 * On some systems, we very sporadically observe that the first TLBs
5230 * used by the CS may be stale, despite us poking the TLB reset. If
5231 * we hold the forcewake during initialisation these problems
5232 * just magically go away.
5234 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5236 ret
= i915_gem_init_userptr(dev
);
5240 i915_gem_init_global_gtt(dev
);
5242 ret
= i915_gem_context_init(dev
);
5246 ret
= dev_priv
->gt
.init_rings(dev
);
5250 ret
= i915_gem_init_hw(dev
);
5252 /* Allow ring initialisation to fail by marking the GPU as
5253 * wedged. But we only want to do this where the GPU is angry,
5254 * for all other failure, such as an allocation failure, bail.
5256 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5257 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5262 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5263 mutex_unlock(&dev
->struct_mutex
);
5269 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5272 struct intel_engine_cs
*ring
;
5275 for_each_ring(ring
, dev_priv
, i
)
5276 dev_priv
->gt
.cleanup_ring(ring
);
5280 init_ring_lists(struct intel_engine_cs
*ring
)
5282 INIT_LIST_HEAD(&ring
->active_list
);
5283 INIT_LIST_HEAD(&ring
->request_list
);
5286 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5287 struct i915_address_space
*vm
)
5289 if (!i915_is_ggtt(vm
))
5290 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5291 vm
->dev
= dev_priv
->dev
;
5292 INIT_LIST_HEAD(&vm
->active_list
);
5293 INIT_LIST_HEAD(&vm
->inactive_list
);
5294 INIT_LIST_HEAD(&vm
->global_link
);
5295 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5299 i915_gem_load(struct drm_device
*dev
)
5301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5304 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5305 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5307 INIT_LIST_HEAD(&dev_priv
->context_list
);
5308 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5309 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5310 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5311 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5312 init_ring_lists(&dev_priv
->ring
[i
]);
5313 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5314 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5315 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5316 i915_gem_retire_work_handler
);
5317 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5318 i915_gem_idle_work_handler
);
5319 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5321 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5323 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5324 dev_priv
->num_fence_regs
= 32;
5325 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5326 dev_priv
->num_fence_regs
= 16;
5328 dev_priv
->num_fence_regs
= 8;
5330 if (intel_vgpu_active(dev
))
5331 dev_priv
->num_fence_regs
=
5332 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5334 /* Initialize fence registers to zero */
5335 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5336 i915_gem_restore_fences(dev
);
5338 i915_gem_detect_bit_6_swizzle(dev
);
5339 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5341 dev_priv
->mm
.interruptible
= true;
5343 i915_gem_shrinker_init(dev_priv
);
5345 lockinit(&dev_priv
->fb_tracking
.lock
, "drmftl", 0, LK_CANRECURSE
);
5348 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5350 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5352 /* Clean up our request list when the client is going away, so that
5353 * later retire_requests won't dereference our soon-to-be-gone
5356 spin_lock(&file_priv
->mm
.lock
);
5357 while (!list_empty(&file_priv
->mm
.request_list
)) {
5358 struct drm_i915_gem_request
*request
;
5360 request
= list_first_entry(&file_priv
->mm
.request_list
,
5361 struct drm_i915_gem_request
,
5363 list_del(&request
->client_list
);
5364 request
->file_priv
= NULL
;
5366 spin_unlock(&file_priv
->mm
.lock
);
5368 if (!list_empty(&file_priv
->rps
.link
)) {
5369 lockmgr(&to_i915(dev
)->rps
.client_lock
, LK_EXCLUSIVE
);
5370 list_del(&file_priv
->rps
.link
);
5371 lockmgr(&to_i915(dev
)->rps
.client_lock
, LK_RELEASE
);
5376 i915_gem_pager_ctor(void *handle
, vm_ooffset_t size
, vm_prot_t prot
,
5377 vm_ooffset_t foff
, struct ucred
*cred
, u_short
*color
)
5379 *color
= 0; /* XXXKIB */
5384 i915_gem_pager_dtor(void *handle
)
5386 struct drm_gem_object
*obj
;
5387 struct drm_device
*dev
;
5392 mutex_lock(&dev
->struct_mutex
);
5393 drm_gem_free_mmap_offset(obj
);
5394 i915_gem_release_mmap(to_intel_bo(obj
));
5395 drm_gem_object_unreference(obj
);
5396 mutex_unlock(&dev
->struct_mutex
);
5399 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5401 struct drm_i915_file_private
*file_priv
;
5404 DRM_DEBUG_DRIVER("\n");
5406 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5410 file
->driver_priv
= file_priv
;
5411 file_priv
->dev_priv
= dev
->dev_private
;
5412 file_priv
->file
= file
;
5413 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5415 spin_init(&file_priv
->mm
.lock
, "i915_priv");
5416 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5418 ret
= i915_gem_context_open(dev
, file
);
5426 * i915_gem_track_fb - update frontbuffer tracking
5427 * old: current GEM buffer for the frontbuffer slots
5428 * new: new GEM buffer for the frontbuffer slots
5429 * frontbuffer_bits: bitmask of frontbuffer slots
5431 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5432 * from @old and setting them in @new. Both @old and @new can be NULL.
5434 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5435 struct drm_i915_gem_object
*new,
5436 unsigned frontbuffer_bits
)
5439 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5440 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5441 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5445 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5446 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5447 new->frontbuffer_bits
|= frontbuffer_bits
;
5451 /* All the new VM stuff */
5453 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5454 struct i915_address_space
*vm
)
5456 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5457 struct i915_vma
*vma
;
5459 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5461 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5462 if (i915_is_ggtt(vma
->vm
) &&
5463 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5466 return vma
->node
.start
;
5469 WARN(1, "%s vma for this object not found.\n",
5470 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5475 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5476 const struct i915_ggtt_view
*view
)
5478 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5479 struct i915_vma
*vma
;
5481 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5482 if (vma
->vm
== ggtt
&&
5483 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5484 return vma
->node
.start
;
5486 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5490 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5491 struct i915_address_space
*vm
)
5493 struct i915_vma
*vma
;
5495 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5496 if (i915_is_ggtt(vma
->vm
) &&
5497 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5499 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5506 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5507 const struct i915_ggtt_view
*view
)
5509 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5510 struct i915_vma
*vma
;
5512 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5513 if (vma
->vm
== ggtt
&&
5514 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5515 drm_mm_node_allocated(&vma
->node
))
5521 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5523 struct i915_vma
*vma
;
5525 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5526 if (drm_mm_node_allocated(&vma
->node
))
5532 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5533 struct i915_address_space
*vm
)
5535 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5536 struct i915_vma
*vma
;
5538 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5540 BUG_ON(list_empty(&o
->vma_list
));
5542 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5543 if (i915_is_ggtt(vma
->vm
) &&
5544 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5547 return vma
->node
.size
;
5552 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5554 struct i915_vma
*vma
;
5555 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5556 if (vma
->pin_count
> 0)