1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi_drm/i915_drm.h>
34 #include <uapi_drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/kref.h>
50 #include <linux/kconfig.h>
51 #include <linux/pm_qos.h>
52 #include <linux/delay.h>
54 #define CONFIG_DRM_I915_FBDEV 1
55 #define CONFIG_DRM_I915_KMS 1
56 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1
60 /* General customization:
63 #define DRIVER_NAME "i915"
64 #define DRIVER_DESC "Intel Graphics"
65 #define DRIVER_DATE "20150522"
68 /* Many gcc seem to no see through this and fall over :( */
70 #define WARN_ON(x) ({ \
71 bool __i915_warn_cond = (x); \
72 if (__builtin_constant_p(__i915_warn_cond)) \
73 BUILD_BUG_ON(__i915_warn_cond); \
74 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
76 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
80 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
82 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
83 (long) (x), __func__);
85 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
86 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
87 * which may not necessarily be a user visible problem. This will either
88 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
89 * enable distros and users to tailor their preferred amount of i915 abrt
92 #define I915_STATE_WARN(condition, format...) ({ \
93 int __ret_warn_on = !!(condition); \
94 if (unlikely(__ret_warn_on)) { \
95 if (i915.verbose_state_checks) \
100 unlikely(__ret_warn_on); \
103 #define I915_STATE_WARN_ON(condition) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) { \
106 if (i915.verbose_state_checks) \
107 WARN(1, "WARN_ON(" #condition ")\n"); \
109 DRM_ERROR("WARN_ON(" #condition ")\n"); \
111 unlikely(__ret_warn_on); \
120 I915_MAX_PIPES
= _PIPE_EDP
122 #define pipe_name(p) ((p) + 'A')
131 #define transcoder_name(t) ((t) + 'A')
134 * This is the maximum (across all platforms) number of planes (primary +
135 * sprites) that can be active at the same time on one pipe.
137 * This value doesn't count the cursor plane.
139 #define I915_MAX_PLANES 4
146 #define plane_name(p) ((p) + 'A')
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
158 #define port_name(p) ((p) + 'A')
160 #define I915_NUM_PHYS_VLV 2
172 enum intel_display_power_domain
{
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
179 POWER_DOMAIN_TRANSCODER_A
,
180 POWER_DOMAIN_TRANSCODER_B
,
181 POWER_DOMAIN_TRANSCODER_C
,
182 POWER_DOMAIN_TRANSCODER_EDP
,
183 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
185 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
186 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
187 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
188 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
189 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
190 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
191 POWER_DOMAIN_PORT_DSI
,
192 POWER_DOMAIN_PORT_CRT
,
193 POWER_DOMAIN_PORT_OTHER
,
206 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
207 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
208 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
209 #define POWER_DOMAIN_TRANSCODER(tran) \
210 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
211 (tran) + POWER_DOMAIN_TRANSCODER_A)
215 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
216 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
226 #define I915_GEM_GPU_DOMAINS \
227 (I915_GEM_DOMAIN_RENDER | \
228 I915_GEM_DOMAIN_SAMPLER | \
229 I915_GEM_DOMAIN_COMMAND | \
230 I915_GEM_DOMAIN_INSTRUCTION | \
231 I915_GEM_DOMAIN_VERTEX)
233 #define for_each_pipe(__dev_priv, __p) \
234 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
235 #define for_each_plane(__dev_priv, __pipe, __p) \
237 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
239 #define for_each_sprite(__dev_priv, __p, __s) \
241 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
244 #define for_each_crtc(dev, crtc) \
245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
247 #define for_each_intel_plane(dev, intel_plane) \
248 list_for_each_entry(intel_plane, \
249 &dev->mode_config.plane_list, \
252 #define for_each_intel_crtc(dev, intel_crtc) \
253 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
255 #define for_each_intel_encoder(dev, intel_encoder) \
256 list_for_each_entry(intel_encoder, \
257 &(dev)->mode_config.encoder_list, \
260 #define for_each_intel_connector(dev, intel_connector) \
261 list_for_each_entry(intel_connector, \
262 &dev->mode_config.connector_list, \
265 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
266 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
267 if ((intel_encoder)->base.crtc == (__crtc))
269 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
270 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
271 if ((intel_connector)->base.encoder == (__encoder))
273 #define for_each_power_domain(domain, mask) \
274 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
275 if ((1 << (domain)) & (mask))
277 struct drm_i915_private
;
278 struct i915_mm_struct
;
279 struct i915_mmu_object
;
281 struct drm_i915_file_private
{
282 struct drm_i915_private
*dev_priv
;
283 struct drm_file
*file
;
286 struct spinlock lock
;
287 struct list_head request_list
;
288 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
289 * chosen to prevent the CPU getting more than a frame ahead of the GPU
290 * (when using lax throttling for the frontbuffer). We also use it to
291 * offer free GPU waitboosts for severely congested workloads.
293 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
295 struct idr context_idr
;
297 struct intel_rps_client
{
298 struct list_head link
;
302 struct intel_engine_cs
*bsd_ring
;
306 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
307 /* real shared dpll ids must be >= 0 */
308 DPLL_ID_PCH_PLL_A
= 0,
309 DPLL_ID_PCH_PLL_B
= 1,
314 DPLL_ID_SKL_DPLL1
= 0,
315 DPLL_ID_SKL_DPLL2
= 1,
316 DPLL_ID_SKL_DPLL3
= 2,
318 #define I915_NUM_PLLS 3
320 struct intel_dpll_hw_state
{
332 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
333 * lower part of ctrl1 and they get shifted into position when writing
334 * the register. This allows us to easily compare the state to share
338 /* HDMI only, 0 when used for DP */
339 uint32_t cfgcr1
, cfgcr2
;
342 uint32_t ebb0
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll10
, pcsdw12
;
345 struct intel_shared_dpll_config
{
346 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
347 struct intel_dpll_hw_state hw_state
;
350 struct intel_shared_dpll
{
351 struct intel_shared_dpll_config config
;
352 struct intel_shared_dpll_config
*new_config
;
354 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
355 bool on
; /* is the PLL actually active? Disabled during modeset */
357 /* should match the index in the dev_priv->shared_dplls array */
358 enum intel_dpll_id id
;
359 /* The mode_set hook is optional and should be used together with the
360 * intel_prepare_shared_dpll function. */
361 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
362 struct intel_shared_dpll
*pll
);
363 void (*enable
)(struct drm_i915_private
*dev_priv
,
364 struct intel_shared_dpll
*pll
);
365 void (*disable
)(struct drm_i915_private
*dev_priv
,
366 struct intel_shared_dpll
*pll
);
367 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
368 struct intel_shared_dpll
*pll
,
369 struct intel_dpll_hw_state
*hw_state
);
377 /* Used by dp and fdi links */
378 struct intel_link_m_n
{
386 void intel_link_compute_m_n(int bpp
, int nlanes
,
387 int pixel_clock
, int link_clock
,
388 struct intel_link_m_n
*m_n
);
390 /* Interface history:
393 * 1.2: Add Power Management
394 * 1.3: Add vblank support
395 * 1.4: Fix cmdbuffer path, add heap destroy
396 * 1.5: Add vblank pipe configuration
397 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
398 * - Support vertical blank on secondary display pipe
400 #define DRIVER_MAJOR 1
401 #define DRIVER_MINOR 6
402 #define DRIVER_PATCHLEVEL 0
404 #define WATCH_LISTS 0
406 struct opregion_header
;
407 struct opregion_acpi
;
408 struct opregion_swsci
;
409 struct opregion_asle
;
411 struct intel_opregion
{
412 struct opregion_header __iomem
*header
;
413 struct opregion_acpi __iomem
*acpi
;
414 struct opregion_swsci __iomem
*swsci
;
415 u32 swsci_gbda_sub_functions
;
416 u32 swsci_sbcb_sub_functions
;
417 struct opregion_asle __iomem
*asle
;
419 u32 __iomem
*lid_state
;
420 struct work_struct asle_work
;
422 #define OPREGION_SIZE (8*1024)
424 struct intel_overlay
;
425 struct intel_overlay_error_state
;
427 #define I915_FENCE_REG_NONE -1
428 #define I915_MAX_NUM_FENCES 32
429 /* 32 fences + sign bit for FENCE_REG_NONE */
430 #define I915_MAX_NUM_FENCE_BITS 6
432 struct drm_i915_fence_reg
{
433 struct list_head lru_list
;
434 struct drm_i915_gem_object
*obj
;
438 struct sdvo_device_mapping
{
447 struct intel_display_error_state
;
449 struct drm_i915_error_state
{
457 /* Generic register state */
465 u32 error
; /* gen6+ */
466 u32 err_int
; /* gen7 */
467 u32 fault_data0
; /* gen8, gen9 */
468 u32 fault_data1
; /* gen8, gen9 */
474 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
475 u64 fence
[I915_MAX_NUM_FENCES
];
476 struct intel_overlay_error_state
*overlay
;
477 struct intel_display_error_state
*display
;
478 struct drm_i915_error_object
*semaphore_obj
;
480 struct drm_i915_error_ring
{
482 /* Software tracked state */
485 enum intel_ring_hangcheck_action hangcheck_action
;
488 /* our own tracking of ring head and tail */
492 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
511 u32 rc_psmi
; /* sleep state */
512 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
514 struct drm_i915_error_object
{
518 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
520 struct drm_i915_error_request
{
535 char comm
[TASK_COMM_LEN
];
536 } ring
[I915_NUM_RINGS
];
538 struct drm_i915_error_buffer
{
541 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
545 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
553 } **active_bo
, **pinned_bo
;
555 u32
*active_bo_count
, *pinned_bo_count
;
559 struct intel_connector
;
560 struct intel_encoder
;
561 struct intel_crtc_state
;
562 struct intel_initial_plane_config
;
567 struct drm_i915_display_funcs
{
568 bool (*fbc_enabled
)(struct drm_device
*dev
);
569 void (*enable_fbc
)(struct drm_crtc
*crtc
);
570 void (*disable_fbc
)(struct drm_device
*dev
);
571 int (*get_display_clock_speed
)(struct drm_device
*dev
);
572 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
574 * find_dpll() - Find the best values for the PLL
575 * @limit: limits for the PLL
576 * @crtc: current CRTC
577 * @target: target frequency in kHz
578 * @refclk: reference clock frequency in kHz
579 * @match_clock: if provided, @best_clock P divider must
580 * match the P divider from @match_clock
581 * used for LVDS downclocking
582 * @best_clock: best PLL values found
584 * Returns true on success, false on failure.
586 bool (*find_dpll
)(const struct intel_limit
*limit
,
587 struct intel_crtc_state
*crtc_state
,
588 int target
, int refclk
,
589 struct dpll
*match_clock
,
590 struct dpll
*best_clock
);
591 void (*update_wm
)(struct drm_crtc
*crtc
);
592 void (*update_sprite_wm
)(struct drm_plane
*plane
,
593 struct drm_crtc
*crtc
,
594 uint32_t sprite_width
, uint32_t sprite_height
,
595 int pixel_size
, bool enable
, bool scaled
);
596 void (*modeset_global_resources
)(struct drm_atomic_state
*state
);
597 /* Returns the active state of the crtc, and if the crtc is active,
598 * fills out the pipe-config with the hw state. */
599 bool (*get_pipe_config
)(struct intel_crtc
*,
600 struct intel_crtc_state
*);
601 void (*get_initial_plane_config
)(struct intel_crtc
*,
602 struct intel_initial_plane_config
*);
603 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
604 struct intel_crtc_state
*crtc_state
);
605 void (*crtc_enable
)(struct drm_crtc
*crtc
);
606 void (*crtc_disable
)(struct drm_crtc
*crtc
);
607 void (*off
)(struct drm_crtc
*crtc
);
608 void (*audio_codec_enable
)(struct drm_connector
*connector
,
609 struct intel_encoder
*encoder
,
610 struct drm_display_mode
*mode
);
611 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
612 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
613 void (*init_clock_gating
)(struct drm_device
*dev
);
614 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
615 struct drm_framebuffer
*fb
,
616 struct drm_i915_gem_object
*obj
,
617 struct intel_engine_cs
*ring
,
619 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
620 struct drm_framebuffer
*fb
,
622 void (*hpd_irq_setup
)(struct drm_device
*dev
);
623 /* clock updates for mode set */
625 /* render clock increase/decrease */
626 /* display clock increase/decrease */
627 /* pll clock increase/decrease */
629 int (*setup_backlight
)(struct intel_connector
*connector
, enum i915_pipe pipe
);
630 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
631 void (*set_backlight
)(struct intel_connector
*connector
,
633 void (*disable_backlight
)(struct intel_connector
*connector
);
634 void (*enable_backlight
)(struct intel_connector
*connector
);
637 enum forcewake_domain_id
{
638 FW_DOMAIN_ID_RENDER
= 0,
639 FW_DOMAIN_ID_BLITTER
,
645 enum forcewake_domains
{
646 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
647 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
648 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
649 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
654 struct intel_uncore_funcs
{
655 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
656 enum forcewake_domains domains
);
657 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
658 enum forcewake_domains domains
);
660 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
661 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
662 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
663 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
665 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
666 uint8_t val
, bool trace
);
667 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
668 uint16_t val
, bool trace
);
669 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
670 uint32_t val
, bool trace
);
671 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
672 uint64_t val
, bool trace
);
675 struct intel_uncore
{
676 struct lock lock
; /** lock is also taken in irq contexts. */
678 struct intel_uncore_funcs funcs
;
681 enum forcewake_domains fw_domains
;
683 struct intel_uncore_forcewake_domain
{
684 struct drm_i915_private
*i915
;
685 enum forcewake_domain_id id
;
687 struct timer_list timer
;
694 } fw_domain
[FW_DOMAIN_ID_COUNT
];
697 /* Iterate over initialised fw domains */
698 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
699 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
700 (i__) < FW_DOMAIN_ID_COUNT; \
701 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
702 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
704 #define for_each_fw_domain(domain__, dev_priv__, i__) \
705 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
708 FW_UNINITIALIZED
= 0,
716 uint32_t dmc_fw_size
;
718 uint32_t mmioaddr
[8];
719 uint32_t mmiodata
[8];
720 enum csr_state state
;
723 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
724 func(is_mobile) sep \
727 func(is_i945gm) sep \
729 func(need_gfx_hws) sep \
731 func(is_pineview) sep \
732 func(is_broadwater) sep \
733 func(is_crestline) sep \
734 func(is_ivybridge) sep \
735 func(is_valleyview) sep \
736 func(is_haswell) sep \
737 func(is_skylake) sep \
738 func(is_preliminary) sep \
740 func(has_pipe_cxsr) sep \
741 func(has_hotplug) sep \
742 func(cursor_needs_physical) sep \
743 func(has_overlay) sep \
744 func(overlay_needs_physical) sep \
745 func(supports_tv) sep \
750 #define DEFINE_FLAG(name) u8 name:1
751 #define SEP_SEMICOLON ;
753 struct intel_device_info
{
754 u32 display_mmio_offset
;
757 u8 num_sprites
[I915_MAX_PIPES
];
759 u8 ring_mask
; /* Rings supported by the HW */
760 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
761 /* Register offsets for the various display pipes and transcoders */
762 int pipe_offsets
[I915_MAX_TRANSCODERS
];
763 int trans_offsets
[I915_MAX_TRANSCODERS
];
764 int palette_offsets
[I915_MAX_PIPES
];
765 int cursor_offsets
[I915_MAX_PIPES
];
767 /* Slice/subslice/EU info */
770 u8 subslice_per_slice
;
773 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
776 u8 has_subslice_pg
:1;
783 enum i915_cache_level
{
785 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
786 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
787 caches, eg sampler/render caches, and the
788 large Last-Level-Cache. LLC is coherent with
789 the CPU, but L3 is only visible to the GPU. */
790 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
793 struct i915_ctx_hang_stats
{
794 /* This context had batch pending when hang was declared */
795 unsigned batch_pending
;
797 /* This context had batch active when hang was declared */
798 unsigned batch_active
;
800 /* Time when this context was last blamed for a GPU reset */
801 unsigned long guilty_ts
;
803 /* If the contexts causes a second GPU hang within this time,
804 * it is permanently banned from submitting any more work.
806 unsigned long ban_period_seconds
;
808 /* This context is banned to submit more work */
812 /* This must match up with the value previously used for execbuf2.rsvd1. */
813 #define DEFAULT_CONTEXT_HANDLE 0
815 * struct intel_context - as the name implies, represents a context.
816 * @ref: reference count.
817 * @user_handle: userspace tracking identity for this context.
818 * @remap_slice: l3 row remapping information.
819 * @file_priv: filp associated with this context (NULL for global default
821 * @hang_stats: information about the role of this context in possible GPU
823 * @ppgtt: virtual memory space used by this context.
824 * @legacy_hw_ctx: render context backing object and whether it is correctly
825 * initialized (legacy ring submission mechanism only).
826 * @link: link in the global list of contexts.
828 * Contexts are memory images used by the hardware to store copies of their
831 struct intel_context
{
835 struct drm_i915_private
*i915
;
836 struct drm_i915_file_private
*file_priv
;
837 struct i915_ctx_hang_stats hang_stats
;
838 struct i915_hw_ppgtt
*ppgtt
;
840 /* Legacy ring buffer submission */
842 struct drm_i915_gem_object
*rcs_state
;
847 bool rcs_initialized
;
849 struct drm_i915_gem_object
*state
;
850 struct intel_ringbuffer
*ringbuf
;
852 } engine
[I915_NUM_RINGS
];
854 struct list_head link
;
865 unsigned long uncompressed_size
;
868 unsigned int possible_framebuffer_bits
;
869 unsigned int busy_bits
;
870 struct intel_crtc
*crtc
;
873 struct drm_mm_node compressed_fb
;
874 struct drm_mm_node
*compressed_llb
;
878 /* Tracks whether the HW is actually enabled, not whether the feature is
882 struct intel_fbc_work
{
883 struct delayed_work work
;
884 struct drm_crtc
*crtc
;
885 struct drm_framebuffer
*fb
;
889 FBC_OK
, /* FBC is enabled */
890 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
891 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
892 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
893 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
894 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
895 FBC_BAD_PLANE
, /* fbc not supported on plane */
896 FBC_NOT_TILED
, /* buffer not tiled */
897 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
899 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
904 * HIGH_RR is the highest eDP panel refresh rate read from EDID
905 * LOW_RR is the lowest eDP panel refresh rate found from EDID
906 * parsing for same resolution.
908 enum drrs_refresh_rate_type
{
911 DRRS_MAX_RR
, /* RR count */
914 enum drrs_support_type
{
915 DRRS_NOT_SUPPORTED
= 0,
916 STATIC_DRRS_SUPPORT
= 1,
917 SEAMLESS_DRRS_SUPPORT
= 2
923 struct delayed_work work
;
925 unsigned busy_frontbuffer_bits
;
926 enum drrs_refresh_rate_type refresh_rate_type
;
927 enum drrs_support_type type
;
934 struct intel_dp
*enabled
;
936 struct delayed_work work
;
937 unsigned busy_frontbuffer_bits
;
943 PCH_NONE
= 0, /* No PCH present */
944 PCH_IBX
, /* Ibexpeak PCH */
945 PCH_CPT
, /* Cougarpoint PCH */
946 PCH_LPT
, /* Lynxpoint PCH */
947 PCH_SPT
, /* Sunrisepoint PCH */
951 enum intel_sbi_destination
{
956 #define QUIRK_PIPEA_FORCE (1<<0)
957 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
958 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
959 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
960 #define QUIRK_PIPEB_FORCE (1<<4)
961 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
964 struct intel_fbc_work
;
967 struct i2c_adapter adapter
;
971 struct drm_i915_private
*dev_priv
;
974 struct intel_iic_softc
{
975 struct drm_device
*drm_dev
;
983 struct i915_suspend_saved_registers
{
986 u32 savePP_ON_DELAYS
;
987 u32 savePP_OFF_DELAYS
;
993 u32 saveCACHE_MODE_0
;
994 u32 saveMI_ARB_STATE
;
998 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
999 u32 savePCH_PORT_HOTPLUG
;
1003 struct vlv_s0ix_state
{
1010 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1011 u32 media_max_req_count
;
1012 u32 gfx_max_req_count
;
1038 u32 rp_down_timeout
;
1044 /* Display 1 CZ domain */
1049 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1051 /* GT SA CZ domain */
1058 /* Display 2 CZ domain */
1062 u32 clock_gate_dis2
;
1065 struct intel_rps_ei
{
1071 struct intel_gen6_power_mgmt
{
1073 * work, interrupts_enabled and pm_iir are protected by
1074 * dev_priv->irq_lock
1076 struct work_struct work
;
1077 bool interrupts_enabled
;
1080 /* Frequencies are stored in potentially platform dependent multiples.
1081 * In other words, *_freq needs to be multiplied by X to be interesting.
1082 * Soft limits are those which are used for the dynamic reclocking done
1083 * by the driver (raise frequencies under heavy loads, and lower for
1084 * lighter loads). Hard limits are those imposed by the hardware.
1086 * A distinction is made for overclocking, which is never enabled by
1087 * default, and is considered to be above the hard limit if it's
1090 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1091 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1092 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1093 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1094 u8 min_freq
; /* AKA RPn. Minimum frequency */
1095 u8 idle_freq
; /* Frequency to request when we are idle */
1096 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1097 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1098 u8 rp0_freq
; /* Non-overclocked max frequency. */
1101 u8 up_threshold
; /* Current %busy required to uplock */
1102 u8 down_threshold
; /* Current %busy required to downclock */
1105 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1107 struct lock client_lock
;
1108 struct list_head clients
;
1112 struct delayed_work delayed_resume_work
;
1115 struct intel_rps_client semaphores
, mmioflips
;
1117 /* manual wa residency calculations */
1118 struct intel_rps_ei up_ei
, down_ei
;
1121 * Protects RPS/RC6 register access and PCU communication.
1122 * Must be taken after struct_mutex if nested. Note that
1123 * this lock may be held for long periods of time when
1124 * talking to hw - so only take it when talking to hw!
1126 struct lock hw_lock
;
1129 /* defined intel_pm.c */
1130 extern struct lock mchdev_lock
;
1132 struct intel_ilk_power_mgmt
{
1140 unsigned long last_time1
;
1141 unsigned long chipset_power
;
1144 unsigned long gfx_power
;
1151 struct drm_i915_private
;
1152 struct i915_power_well
;
1154 struct i915_power_well_ops
{
1156 * Synchronize the well's hw state to match the current sw state, for
1157 * example enable/disable it based on the current refcount. Called
1158 * during driver init and resume time, possibly after first calling
1159 * the enable/disable handlers.
1161 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1162 struct i915_power_well
*power_well
);
1164 * Enable the well and resources that depend on it (for example
1165 * interrupts located on the well). Called after the 0->1 refcount
1168 void (*enable
)(struct drm_i915_private
*dev_priv
,
1169 struct i915_power_well
*power_well
);
1171 * Disable the well and resources that depend on it. Called after
1172 * the 1->0 refcount transition.
1174 void (*disable
)(struct drm_i915_private
*dev_priv
,
1175 struct i915_power_well
*power_well
);
1176 /* Returns the hw enabled state. */
1177 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1178 struct i915_power_well
*power_well
);
1181 /* Power well structure for haswell */
1182 struct i915_power_well
{
1185 /* power well enable/disable usage count */
1187 /* cached hw enabled state */
1189 unsigned long domains
;
1191 const struct i915_power_well_ops
*ops
;
1194 struct i915_power_domains
{
1196 * Power wells needed for initialization at driver init and suspend
1197 * time are on. They are kept on until after the first modeset.
1201 int power_well_count
;
1204 int domain_use_count
[POWER_DOMAIN_NUM
];
1205 struct i915_power_well
*power_wells
;
1208 #define MAX_L3_SLICES 2
1209 struct intel_l3_parity
{
1210 u32
*remap_info
[MAX_L3_SLICES
];
1211 struct work_struct error_work
;
1215 struct i915_gem_mm
{
1216 /** Memory allocator for GTT stolen memory */
1217 struct drm_mm stolen
;
1218 /** List of all objects in gtt_space. Used to restore gtt
1219 * mappings on resume */
1220 struct list_head bound_list
;
1222 * List of objects which are not bound to the GTT (thus
1223 * are idle and not used by the GPU) but still have
1224 * (presumably uncached) pages still attached.
1226 struct list_head unbound_list
;
1228 /** Usable portion of the GTT for GEM */
1229 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1231 /** PPGTT used for aliasing the PPGTT with the GTT */
1232 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1234 struct notifier_block oom_notifier
;
1236 struct shrinker shrinker
;
1238 bool shrinker_no_lock_stealing
;
1240 /** LRU list of objects with fence regs on them. */
1241 struct list_head fence_list
;
1244 * We leave the user IRQ off as much as possible,
1245 * but this means that requests will finish and never
1246 * be retired once the system goes idle. Set a timer to
1247 * fire periodically while the ring is running. When it
1248 * fires, go retire requests.
1250 struct delayed_work retire_work
;
1253 * When we detect an idle GPU, we want to turn on
1254 * powersaving features. So once we see that there
1255 * are no more requests outstanding and no more
1256 * arrive within a small period of time, we fire
1257 * off the idle_work.
1259 struct delayed_work idle_work
;
1262 * Are we in a non-interruptible section of code like
1268 * Is the GPU currently considered idle, or busy executing userspace
1269 * requests? Whilst idle, we attempt to power down the hardware and
1270 * display clocks. In order to reduce the effect on performance, there
1271 * is a slight delay before we do so.
1275 /* the indicator for dispatch video commands on two BSD rings */
1276 int bsd_ring_dispatch_index
;
1278 /** Bit 6 swizzling required for X tiling */
1279 uint32_t bit_6_swizzle_x
;
1280 /** Bit 6 swizzling required for Y tiling */
1281 uint32_t bit_6_swizzle_y
;
1283 /* accounting, useful for userland debugging */
1284 struct spinlock object_stat_lock
;
1285 size_t object_memory
;
1289 struct drm_i915_error_state_buf
{
1290 struct drm_i915_private
*i915
;
1299 struct i915_error_state_file_priv
{
1300 struct drm_device
*dev
;
1301 struct drm_i915_error_state
*error
;
1304 struct i915_gpu_error
{
1305 /* For hangcheck timer */
1306 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1307 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1308 /* Hang gpu twice in this window and your context gets banned */
1309 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1311 struct workqueue_struct
*hangcheck_wq
;
1312 struct delayed_work hangcheck_work
;
1314 /* For reset and error_state handling. */
1316 /* Protected by the above dev->gpu_error.lock. */
1317 struct drm_i915_error_state
*first_error
;
1319 unsigned long missed_irq_rings
;
1322 * State variable controlling the reset flow and count
1324 * This is a counter which gets incremented when reset is triggered,
1325 * and again when reset has been handled. So odd values (lowest bit set)
1326 * means that reset is in progress and even values that
1327 * (reset_counter >> 1):th reset was successfully completed.
1329 * If reset is not completed succesfully, the I915_WEDGE bit is
1330 * set meaning that hardware is terminally sour and there is no
1331 * recovery. All waiters on the reset_queue will be woken when
1334 * This counter is used by the wait_seqno code to notice that reset
1335 * event happened and it needs to restart the entire ioctl (since most
1336 * likely the seqno it waited for won't ever signal anytime soon).
1338 * This is important for lock-free wait paths, where no contended lock
1339 * naturally enforces the correct ordering between the bail-out of the
1340 * waiter and the gpu reset work code.
1342 atomic_t reset_counter
;
1344 #define I915_RESET_IN_PROGRESS_FLAG 1
1345 #define I915_WEDGED (1 << 31)
1348 * Waitqueue to signal when the reset has completed. Used by clients
1349 * that wait for dev_priv->mm.wedged to settle.
1351 wait_queue_head_t reset_queue
;
1353 /* Userspace knobs for gpu hang simulation;
1354 * combines both a ring mask, and extra flags
1357 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1358 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1360 /* For missed irq/seqno simulation. */
1361 unsigned int test_irq_rings
;
1363 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1364 bool reload_in_reset
;
1367 enum modeset_restore
{
1368 MODESET_ON_LID_OPEN
,
1373 struct ddi_vbt_port_info
{
1375 * This is an index in the HDMI/DVI DDI buffer translation table.
1376 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1377 * populate this field.
1379 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1380 uint8_t hdmi_level_shift
;
1382 uint8_t supports_dvi
:1;
1383 uint8_t supports_hdmi
:1;
1384 uint8_t supports_dp
:1;
1387 enum psr_lines_to_wait
{
1388 PSR_0_LINES_TO_WAIT
= 0,
1390 PSR_4_LINES_TO_WAIT
,
1394 struct intel_vbt_data
{
1395 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1396 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1399 unsigned int int_tv_support
:1;
1400 unsigned int lvds_dither
:1;
1401 unsigned int lvds_vbt
:1;
1402 unsigned int int_crt_support
:1;
1403 unsigned int lvds_use_ssc
:1;
1404 unsigned int display_clock_mode
:1;
1405 unsigned int fdi_rx_polarity_inverted
:1;
1406 unsigned int has_mipi
:1;
1408 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1410 enum drrs_support_type drrs_type
;
1415 int edp_preemphasis
;
1417 bool edp_initialized
;
1420 struct edp_power_seq edp_pps
;
1424 bool require_aux_wakeup
;
1426 enum psr_lines_to_wait lines_to_wait
;
1427 int tp1_wakeup_time
;
1428 int tp2_tp3_wakeup_time
;
1434 bool active_low_pwm
;
1435 u8 min_brightness
; /* min_brightness/255 of max */
1442 struct mipi_config
*config
;
1443 struct mipi_pps_data
*pps
;
1447 u8
*sequence
[MIPI_SEQ_MAX
];
1453 union child_device_config
*child_dev
;
1455 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1458 enum intel_ddb_partitioning
{
1460 INTEL_DDB_PART_5_6
, /* IVB+ */
1463 struct intel_wm_level
{
1471 struct ilk_wm_values
{
1472 uint32_t wm_pipe
[3];
1474 uint32_t wm_lp_spr
[3];
1475 uint32_t wm_linetime
[3];
1477 enum intel_ddb_partitioning partitioning
;
1480 struct vlv_wm_values
{
1499 struct skl_ddb_entry
{
1500 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1503 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1505 return entry
->end
- entry
->start
;
1508 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1509 const struct skl_ddb_entry
*e2
)
1511 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1517 struct skl_ddb_allocation
{
1518 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1519 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1520 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* y-plane */
1521 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1524 struct skl_wm_values
{
1525 bool dirty
[I915_MAX_PIPES
];
1526 struct skl_ddb_allocation ddb
;
1527 uint32_t wm_linetime
[I915_MAX_PIPES
];
1528 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1529 uint32_t cursor
[I915_MAX_PIPES
][8];
1530 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1531 uint32_t cursor_trans
[I915_MAX_PIPES
];
1534 struct skl_wm_level
{
1535 bool plane_en
[I915_MAX_PLANES
];
1537 uint16_t plane_res_b
[I915_MAX_PLANES
];
1538 uint8_t plane_res_l
[I915_MAX_PLANES
];
1539 uint16_t cursor_res_b
;
1540 uint8_t cursor_res_l
;
1544 * This struct helps tracking the state needed for runtime PM, which puts the
1545 * device in PCI D3 state. Notice that when this happens, nothing on the
1546 * graphics device works, even register access, so we don't get interrupts nor
1549 * Every piece of our code that needs to actually touch the hardware needs to
1550 * either call intel_runtime_pm_get or call intel_display_power_get with the
1551 * appropriate power domain.
1553 * Our driver uses the autosuspend delay feature, which means we'll only really
1554 * suspend if we stay with zero refcount for a certain amount of time. The
1555 * default value is currently very conservative (see intel_runtime_pm_enable), but
1556 * it can be changed with the standard runtime PM files from sysfs.
1558 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1559 * goes back to false exactly before we reenable the IRQs. We use this variable
1560 * to check if someone is trying to enable/disable IRQs while they're supposed
1561 * to be disabled. This shouldn't happen and we'll print some error messages in
1564 * For more, read the Documentation/power/runtime_pm.txt.
1566 struct i915_runtime_pm
{
1571 enum intel_pipe_crc_source
{
1572 INTEL_PIPE_CRC_SOURCE_NONE
,
1573 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1574 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1575 INTEL_PIPE_CRC_SOURCE_PF
,
1576 INTEL_PIPE_CRC_SOURCE_PIPE
,
1577 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1578 INTEL_PIPE_CRC_SOURCE_TV
,
1579 INTEL_PIPE_CRC_SOURCE_DP_B
,
1580 INTEL_PIPE_CRC_SOURCE_DP_C
,
1581 INTEL_PIPE_CRC_SOURCE_DP_D
,
1582 INTEL_PIPE_CRC_SOURCE_AUTO
,
1583 INTEL_PIPE_CRC_SOURCE_MAX
,
1586 struct intel_pipe_crc_entry
{
1591 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1592 struct intel_pipe_crc
{
1593 struct spinlock lock
;
1594 bool opened
; /* exclusive access to the result file */
1595 struct intel_pipe_crc_entry
*entries
;
1596 enum intel_pipe_crc_source source
;
1598 wait_queue_head_t wq
;
1601 struct i915_frontbuffer_tracking
{
1605 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1612 struct i915_wa_reg
{
1615 /* bitmask representing WA bits */
1619 #define I915_MAX_WA_REGS 16
1621 struct i915_workarounds
{
1622 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1626 struct i915_virtual_gpu
{
1630 struct drm_i915_private
{
1631 struct drm_device
*dev
;
1632 struct kmem_cache
*objects
;
1633 struct kmem_cache
*vmas
;
1634 struct kmem_cache
*requests
;
1636 struct intel_device_info info
;
1638 int relative_constants_mode
;
1640 device_t
*gmbus_bridge
;
1641 device_t
*bbbus_bridge
;
1644 drm_local_map_t
*sarea
;
1645 drm_local_map_t
*mmio_map
;
1648 struct intel_uncore uncore
;
1650 struct i915_virtual_gpu vgpu
;
1652 struct intel_csr csr
;
1654 /* Display CSR-related protection */
1655 struct lock csr_lock
;
1660 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1661 * controller on different i2c buses. */
1662 struct lock gmbus_mutex
;
1664 struct _drm_i915_sarea
*sarea_priv
;
1666 * Base address of the gmbus and gpio block.
1668 uint32_t gpio_mmio_base
;
1670 /* MMIO base address for MIPI regs */
1671 uint32_t mipi_mmio_base
;
1673 wait_queue_head_t gmbus_wait_queue
;
1675 struct pci_dev
*bridge_dev
;
1676 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1677 struct drm_i915_gem_object
*semaphore_obj
;
1678 uint32_t last_seqno
, next_seqno
;
1680 struct drm_dma_handle
*status_page_dmah
;
1681 struct resource
*mch_res
;
1684 /* protects the irq masks */
1685 struct lock irq_lock
;
1687 /* protects the mmio flip data */
1688 struct spinlock mmio_flip_lock
;
1690 bool display_irqs_enabled
;
1692 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1693 struct pm_qos_request pm_qos
;
1695 /* Sideband mailbox protection */
1696 struct lock sb_lock
;
1698 /** Cached value of IMR to avoid reads in updating the bitfield */
1701 u32 de_irq_mask
[I915_MAX_PIPES
];
1706 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1708 struct work_struct hotplug_work
;
1710 unsigned long hpd_last_jiffies
;
1715 HPD_MARK_DISABLED
= 2
1717 } hpd_stats
[HPD_NUM_PINS
];
1719 struct delayed_work hotplug_reenable_work
;
1721 struct i915_fbc fbc
;
1722 struct i915_drrs drrs
;
1723 struct intel_opregion opregion
;
1724 struct intel_vbt_data vbt
;
1726 bool preserve_bios_swizzle
;
1729 struct intel_overlay
*overlay
;
1731 /* backlight registers and fields in struct intel_panel */
1732 struct lock backlight_lock
;
1735 bool no_aux_handshake
;
1737 /* protects panel power sequencer state */
1738 struct lock pps_mutex
;
1740 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1741 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1742 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1744 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1745 unsigned int skl_boot_cdclk
;
1746 unsigned int cdclk_freq
;
1747 unsigned int hpll_freq
;
1750 * wq - Driver workqueue for GEM.
1752 * NOTE: Work items scheduled here are not allowed to grab any modeset
1753 * locks, for otherwise the flushing done in the pageflip code will
1754 * result in deadlocks.
1756 struct workqueue_struct
*wq
;
1758 /* Display functions */
1759 struct drm_i915_display_funcs display
;
1761 /* PCH chipset type */
1762 enum intel_pch pch_type
;
1763 unsigned short pch_id
;
1765 unsigned long quirks
;
1767 enum modeset_restore modeset_restore
;
1768 struct lock modeset_restore_lock
;
1770 struct list_head vm_list
; /* Global list of all address spaces */
1771 struct i915_gtt gtt
; /* VM representing the global address space */
1773 struct i915_gem_mm mm
;
1774 DECLARE_HASHTABLE(mm_structs
, 7);
1775 struct lock mm_lock
;
1777 /* Kernel Modesetting */
1779 struct sdvo_device_mapping sdvo_mappings
[2];
1781 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1782 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1783 wait_queue_head_t pending_flip_queue
;
1785 #ifdef CONFIG_DEBUG_FS
1786 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1789 int num_shared_dpll
;
1790 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1791 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1793 struct i915_workarounds workarounds
;
1795 /* Reclocking support */
1796 bool render_reclock_avail
;
1797 bool lvds_downclock_avail
;
1798 /* indicates the reduced downclock for LVDS*/
1801 struct i915_frontbuffer_tracking fb_tracking
;
1805 bool mchbar_need_disable
;
1807 struct intel_l3_parity l3_parity
;
1809 /* Cannot be determined by PCIID. You must always read a register. */
1812 /* gen6+ rps state */
1813 struct intel_gen6_power_mgmt rps
;
1815 /* ilk-only ips/rps state. Everything in here is protected by the global
1816 * mchdev_lock in intel_pm.c */
1817 struct intel_ilk_power_mgmt ips
;
1819 struct i915_power_domains power_domains
;
1821 struct i915_psr psr
;
1823 struct i915_gpu_error gpu_error
;
1825 struct drm_i915_gem_object
*vlv_pctx
;
1827 #ifdef CONFIG_DRM_I915_FBDEV
1828 /* list of fbdev register on this device */
1829 struct intel_fbdev
*fbdev
;
1830 struct work_struct fbdev_suspend_work
;
1833 struct drm_property
*broadcast_rgb_property
;
1834 struct drm_property
*force_audio_property
;
1836 /* hda/i915 audio component */
1837 bool audio_component_registered
;
1839 uint32_t hw_context_size
;
1840 struct list_head context_list
;
1844 u32 chv_phy_control
;
1847 struct i915_suspend_saved_registers regfile
;
1848 struct vlv_s0ix_state vlv_s0ix_state
;
1852 * Raw watermark latency values:
1853 * in 0.1us units for WM0,
1854 * in 0.5us units for WM1+.
1857 uint16_t pri_latency
[5];
1859 uint16_t spr_latency
[5];
1861 uint16_t cur_latency
[5];
1863 * Raw watermark memory latency values
1864 * for SKL for all 8 levels
1867 uint16_t skl_latency
[8];
1870 * The skl_wm_values structure is a bit too big for stack
1871 * allocation, so we keep the staging struct where we store
1872 * intermediate results here instead.
1874 struct skl_wm_values skl_results
;
1876 /* current hardware state */
1878 struct ilk_wm_values hw
;
1879 struct skl_wm_values skl_hw
;
1880 struct vlv_wm_values vlv
;
1884 struct i915_runtime_pm pm
;
1886 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1887 u32 long_hpd_port_mask
;
1888 u32 short_hpd_port_mask
;
1889 struct work_struct dig_port_work
;
1892 * if we get a HPD irq from DP and a HPD irq from non-DP
1893 * the non-DP HPD could block the workqueue on a mode config
1894 * mutex getting, that userspace may have taken. However
1895 * userspace is waiting on the DP workqueue to run which is
1896 * blocked behind the non-DP one.
1898 struct workqueue_struct
*dp_wq
;
1900 uint32_t bios_vgacntr
;
1902 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1904 int (*execbuf_submit
)(struct drm_device
*dev
, struct drm_file
*file
,
1905 struct intel_engine_cs
*ring
,
1906 struct intel_context
*ctx
,
1907 struct drm_i915_gem_execbuffer2
*args
,
1908 struct list_head
*vmas
,
1909 struct drm_i915_gem_object
*batch_obj
,
1910 u64 exec_start
, u32 flags
);
1911 int (*init_rings
)(struct drm_device
*dev
);
1912 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1913 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1916 bool edp_low_vswing
;
1919 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1920 * will be rejected. Instead look for a better place.
1924 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1926 return dev
->dev_private
;
1929 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1934 /* Iterate over initialised rings */
1935 #define for_each_ring(ring__, dev_priv__, i__) \
1936 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1937 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1939 enum hdmi_force_audio
{
1940 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1941 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1942 HDMI_AUDIO_AUTO
, /* trust EDID */
1943 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1946 #define I915_GTT_OFFSET_NONE ((u32)-1)
1948 struct drm_i915_gem_object_ops
{
1949 /* Interface between the GEM object and its backing storage.
1950 * get_pages() is called once prior to the use of the associated set
1951 * of pages before to binding them into the GTT, and put_pages() is
1952 * called after we no longer need them. As we expect there to be
1953 * associated cost with migrating pages between the backing storage
1954 * and making them available for the GPU (e.g. clflush), we may hold
1955 * onto the pages after they are no longer referenced by the GPU
1956 * in case they may be used again shortly (for example migrating the
1957 * pages to a different memory domain within the GTT). put_pages()
1958 * will therefore most likely be called when the object itself is
1959 * being released or under memory pressure (where we attempt to
1960 * reap pages for the shrinker).
1962 int (*get_pages
)(struct drm_i915_gem_object
*);
1963 void (*put_pages
)(struct drm_i915_gem_object
*);
1964 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1965 void (*release
)(struct drm_i915_gem_object
*);
1969 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1970 * considered to be the frontbuffer for the given plane interface-vise. This
1971 * doesn't mean that the hw necessarily already scans it out, but that any
1972 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1974 * We have one bit per pipe and per scanout plane type.
1976 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1977 #define INTEL_FRONTBUFFER_BITS \
1978 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1979 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1980 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1981 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1982 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1983 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1984 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1985 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1986 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1987 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1988 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1990 struct drm_i915_gem_object
{
1991 struct drm_gem_object base
;
1993 const struct drm_i915_gem_object_ops
*ops
;
1995 /** List of VMAs backed by this object */
1996 struct list_head vma_list
;
1998 /** Stolen memory for this object, instead of being backed by shmem. */
1999 struct drm_mm_node
*stolen
;
2000 struct list_head global_list
;
2002 struct list_head ring_list
[I915_NUM_RINGS
];
2003 /** Used in execbuf to temporarily hold a ref */
2004 struct list_head obj_exec_link
;
2006 struct list_head batch_pool_link
;
2009 * This is set if the object is on the active lists (has pending
2010 * rendering and so a non-zero seqno), and is not set if it i s on
2011 * inactive (ready to be unbound) list.
2013 unsigned int active
:I915_NUM_RINGS
;
2016 * This is set if the object has been written to since last bound
2019 unsigned int dirty
:1;
2022 * Fence register bits (if any) for this object. Will be set
2023 * as needed when mapped into the GTT.
2024 * Protected by dev->struct_mutex.
2026 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2029 * Advice: are the backing pages purgeable?
2031 unsigned int madv
:2;
2034 * Current tiling mode for the object.
2036 unsigned int tiling_mode
:2;
2038 * Whether the tiling parameters for the currently associated fence
2039 * register have changed. Note that for the purposes of tracking
2040 * tiling changes we also treat the unfenced register, the register
2041 * slot that the object occupies whilst it executes a fenced
2042 * command (such as BLT on gen2/3), as a "fence".
2044 unsigned int fence_dirty
:1;
2047 * Is the object at the current location in the gtt mappable and
2048 * fenceable? Used to avoid costly recalculations.
2050 unsigned int map_and_fenceable
:1;
2053 * Whether the current gtt mapping needs to be mappable (and isn't just
2054 * mappable by accident). Track pin and fault separate for a more
2055 * accurate mappable working set.
2057 unsigned int fault_mappable
:1;
2060 * Is the object to be mapped as read-only to the GPU
2061 * Only honoured if hardware has relevant pte bit
2063 unsigned long gt_ro
:1;
2064 unsigned int cache_level
:3;
2065 unsigned int cache_dirty
:1;
2067 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2069 unsigned int pin_display
;
2071 struct sg_table
*pages
;
2072 int pages_pin_count
;
2074 struct scatterlist
*sg
;
2078 /* prime dma-buf support */
2079 void *dma_buf_vmapping
;
2082 /** Breadcrumb of last rendering to the buffer.
2083 * There can only be one writer, but we allow for multiple readers.
2084 * If there is a writer that necessarily implies that all other
2085 * read requests are complete - but we may only be lazily clearing
2086 * the read requests. A read request is naturally the most recent
2087 * request on a ring, so we may have two different write and read
2088 * requests on one ring where the write request is older than the
2089 * read request. This allows for the CPU to read from an active
2090 * buffer by only waiting for the write to complete.
2092 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2093 struct drm_i915_gem_request
*last_write_req
;
2094 /** Breadcrumb of last fenced GPU access to the buffer. */
2095 struct drm_i915_gem_request
*last_fenced_req
;
2097 /** Current tiling stride for the object, if it's tiled. */
2100 /** References from framebuffers, locks out tiling changes. */
2101 unsigned long framebuffer_references
;
2103 /** Record of address bit 17 of each page at last unbind. */
2104 unsigned long *bit_17
;
2107 /** for phy allocated objects */
2108 struct drm_dma_handle
*phys_handle
;
2110 struct i915_gem_userptr
{
2112 unsigned read_only
:1;
2113 unsigned workers
:4;
2114 #define I915_GEM_USERPTR_MAX_WORKERS 15
2116 struct i915_mm_struct
*mm
;
2117 struct i915_mmu_object
*mmu_object
;
2118 struct work_struct
*work
;
2122 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2124 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2125 struct drm_i915_gem_object
*new,
2126 unsigned frontbuffer_bits
);
2129 * Request queue structure.
2131 * The request queue allows us to note sequence numbers that have been emitted
2132 * and may be associated with active buffers to be retired.
2134 * By keeping this list, we can avoid having to do questionable sequence
2135 * number comparisons on buffer last_read|write_seqno. It also allows an
2136 * emission time to be associated with the request for tracking how far ahead
2137 * of the GPU the submission is.
2139 * The requests are reference counted, so upon creation they should have an
2140 * initial reference taken using kref_init
2142 struct drm_i915_gem_request
{
2145 /** On Which ring this request was generated */
2146 struct drm_i915_private
*i915
;
2147 struct intel_engine_cs
*ring
;
2149 /** GEM sequence number associated with this request. */
2152 /** Position in the ringbuffer of the start of the request */
2156 * Position in the ringbuffer of the start of the postfix.
2157 * This is required to calculate the maximum available ringbuffer
2158 * space without overwriting the postfix.
2162 /** Position in the ringbuffer of the end of the whole request */
2166 * Context and ring buffer related to this request
2167 * Contexts are refcounted, so when this request is associated with a
2168 * context, we must increment the context's refcount, to guarantee that
2169 * it persists while any request is linked to it. Requests themselves
2170 * are also refcounted, so the request will only be freed when the last
2171 * reference to it is dismissed, and the code in
2172 * i915_gem_request_free() will then decrement the refcount on the
2175 struct intel_context
*ctx
;
2176 struct intel_ringbuffer
*ringbuf
;
2178 /** Batch buffer related to this request if any */
2179 struct drm_i915_gem_object
*batch_obj
;
2181 /** Time at which this request was emitted, in jiffies. */
2182 unsigned long emitted_jiffies
;
2184 /** global list entry for this request */
2185 struct list_head list
;
2187 struct drm_i915_file_private
*file_priv
;
2188 /** file_priv list entry for this request */
2189 struct list_head client_list
;
2191 /** process identifier submitting this request */
2195 * The ELSP only accepts two elements at a time, so we queue
2196 * context/tail pairs on a given queue (ring->execlist_queue) until the
2197 * hardware is available. The queue serves a double purpose: we also use
2198 * it to keep track of the up to 2 contexts currently in the hardware
2199 * (usually one in execution and the other queued up by the GPU): We
2200 * only remove elements from the head of the queue when the hardware
2201 * informs us that an element has been completed.
2203 * All accesses to the queue are mediated by a spinlock
2204 * (ring->execlist_lock).
2207 /** Execlist link in the submission queue.*/
2208 struct list_head execlist_link
;
2210 /** Execlists no. of times this request has been sent to the ELSP */
2215 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2216 struct intel_context
*ctx
);
2217 void i915_gem_request_free(struct kref
*req_ref
);
2219 static inline uint32_t
2220 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2222 return req
? req
->seqno
: 0;
2225 static inline struct intel_engine_cs
*
2226 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2228 return req
? req
->ring
: NULL
;
2231 static inline struct drm_i915_gem_request
*
2232 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2235 kref_get(&req
->ref
);
2240 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2242 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2243 kref_put(&req
->ref
, i915_gem_request_free
);
2247 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2249 struct drm_device
*dev
;
2254 dev
= req
->ring
->dev
;
2255 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2256 mutex_unlock(&dev
->struct_mutex
);
2259 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2260 struct drm_i915_gem_request
*src
)
2263 i915_gem_request_reference(src
);
2266 i915_gem_request_unreference(*pdst
);
2272 * XXX: i915_gem_request_completed should be here but currently needs the
2273 * definition of i915_seqno_passed() which is below. It will be moved in
2274 * a later patch when the call to i915_seqno_passed() is obsoleted...
2278 * A command that requires special handling by the command parser.
2280 struct drm_i915_cmd_descriptor
{
2282 * Flags describing how the command parser processes the command.
2284 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2285 * a length mask if not set
2286 * CMD_DESC_SKIP: The command is allowed but does not follow the
2287 * standard length encoding for the opcode range in
2289 * CMD_DESC_REJECT: The command is never allowed
2290 * CMD_DESC_REGISTER: The command should be checked against the
2291 * register whitelist for the appropriate ring
2292 * CMD_DESC_MASTER: The command is allowed if the submitting process
2296 #define CMD_DESC_FIXED (1<<0)
2297 #define CMD_DESC_SKIP (1<<1)
2298 #define CMD_DESC_REJECT (1<<2)
2299 #define CMD_DESC_REGISTER (1<<3)
2300 #define CMD_DESC_BITMASK (1<<4)
2301 #define CMD_DESC_MASTER (1<<5)
2304 * The command's unique identification bits and the bitmask to get them.
2305 * This isn't strictly the opcode field as defined in the spec and may
2306 * also include type, subtype, and/or subop fields.
2314 * The command's length. The command is either fixed length (i.e. does
2315 * not include a length field) or has a length field mask. The flag
2316 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2317 * a length mask. All command entries in a command table must include
2318 * length information.
2326 * Describes where to find a register address in the command to check
2327 * against the ring's register whitelist. Only valid if flags has the
2328 * CMD_DESC_REGISTER bit set.
2330 * A non-zero step value implies that the command may access multiple
2331 * registers in sequence (e.g. LRI), in that case step gives the
2332 * distance in dwords between individual offset fields.
2340 #define MAX_CMD_DESC_BITMASKS 3
2342 * Describes command checks where a particular dword is masked and
2343 * compared against an expected value. If the command does not match
2344 * the expected value, the parser rejects it. Only valid if flags has
2345 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2348 * If the check specifies a non-zero condition_mask then the parser
2349 * only performs the check when the bits specified by condition_mask
2356 u32 condition_offset
;
2358 } bits
[MAX_CMD_DESC_BITMASKS
];
2362 * A table of commands requiring special handling by the command parser.
2364 * Each ring has an array of tables. Each table consists of an array of command
2365 * descriptors, which must be sorted with command opcodes in ascending order.
2367 struct drm_i915_cmd_table
{
2368 const struct drm_i915_cmd_descriptor
*table
;
2372 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2373 #define __I915__(p) ({ \
2374 const struct drm_i915_private *__p; \
2375 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2376 __p = (const struct drm_i915_private *)p; \
2377 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2378 __p = to_i915((const struct drm_device *)p); \
2381 #define INTEL_INFO(p) (&__I915__(p)->info)
2382 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2383 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2385 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2386 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2387 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2388 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2389 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2390 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2391 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2392 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2393 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2394 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2395 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2396 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2397 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2398 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2399 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2400 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2401 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2402 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2403 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2404 INTEL_DEVID(dev) == 0x0152 || \
2405 INTEL_DEVID(dev) == 0x015a)
2406 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2407 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2408 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2409 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2410 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2411 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2412 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2413 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2414 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2415 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2416 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2417 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2418 (INTEL_DEVID(dev) & 0xf) == 0xe))
2419 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2420 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2421 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2422 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2423 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2424 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2425 /* ULX machines are also considered ULT. */
2426 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2427 INTEL_DEVID(dev) == 0x0A1E)
2428 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2430 #define SKL_REVID_A0 (0x0)
2431 #define SKL_REVID_B0 (0x1)
2432 #define SKL_REVID_C0 (0x2)
2433 #define SKL_REVID_D0 (0x3)
2434 #define SKL_REVID_E0 (0x4)
2435 #define SKL_REVID_F0 (0x5)
2437 #define BXT_REVID_A0 (0x0)
2438 #define BXT_REVID_B0 (0x3)
2439 #define BXT_REVID_C0 (0x6)
2442 * The genX designation typically refers to the render engine, so render
2443 * capability related checks should use IS_GEN, while display and other checks
2444 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2447 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2448 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2449 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2450 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2451 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2452 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2453 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2454 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2456 #define RENDER_RING (1<<RCS)
2457 #define BSD_RING (1<<VCS)
2458 #define BLT_RING (1<<BCS)
2459 #define VEBOX_RING (1<<VECS)
2460 #define BSD2_RING (1<<VCS2)
2461 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2462 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2463 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2464 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2465 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2466 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2467 __I915__(dev)->ellc_size)
2468 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2470 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2471 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2472 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2473 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2475 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2476 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2478 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2479 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2481 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2482 * even when in MSI mode. This results in spurious interrupt warnings if the
2483 * legacy irq no. is shared with another device. The kernel then disables that
2484 * interrupt source and so prevents the other device from working properly.
2486 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2487 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2489 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2490 * rows, which changed the alignment requirements and fence programming.
2492 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2494 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2495 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2496 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2497 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2498 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2500 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2501 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2502 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2504 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2506 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2507 INTEL_INFO(dev)->gen >= 9)
2509 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2510 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2511 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2512 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2514 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2515 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2517 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2518 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2520 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2522 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2523 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2524 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2525 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2526 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2527 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2528 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2529 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2531 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2532 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2533 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2534 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2535 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2536 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2537 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2539 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2541 /* DPF == dynamic parity feature */
2542 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2543 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2545 #define GT_FREQUENCY_MULTIPLIER 50
2546 #define GEN9_FREQ_SCALER 3
2548 #include "i915_trace.h"
2550 extern const struct drm_ioctl_desc i915_ioctls
[];
2551 extern int i915_max_ioctl
;
2553 extern int i915_suspend_legacy(device_t kdev
);
2554 extern int i915_resume_legacy(struct drm_device
*dev
);
2557 struct i915_params
{
2559 int panel_ignore_lid
;
2561 unsigned int lvds_downclock
;
2562 int lvds_channel_mode
;
2564 int vbt_sdvo_panel_type
;
2568 int enable_execlists
;
2570 unsigned int preliminary_hw_support
;
2571 int disable_power_well
;
2573 int invert_brightness
;
2574 int enable_cmd_parser
;
2575 /* leave bools at the end to not create holes */
2576 bool enable_hangcheck
;
2578 bool prefault_disable
;
2579 bool load_detect_test
;
2581 bool disable_display
;
2582 bool disable_vtd_wa
;
2585 bool verbose_state_checks
;
2586 bool nuclear_pageflip
;
2589 extern struct i915_params i915 __read_mostly
;
2592 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2593 extern int i915_driver_unload(struct drm_device
*);
2594 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2595 extern void i915_driver_lastclose(struct drm_device
* dev
);
2596 extern void i915_driver_preclose(struct drm_device
*dev
,
2597 struct drm_file
*file
);
2598 extern void i915_driver_postclose(struct drm_device
*dev
,
2599 struct drm_file
*file
);
2600 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2601 #ifdef CONFIG_COMPAT
2602 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2605 extern int intel_gpu_reset(struct drm_device
*dev
);
2606 extern int i915_reset(struct drm_device
*dev
);
2607 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2608 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2609 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2610 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2611 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2612 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2613 void i915_firmware_load_error_print(const char *fw_path
, int err
);
2616 void i915_queue_hangcheck(struct drm_device
*dev
);
2618 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2619 const char *fmt
, ...);
2621 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2622 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2623 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2624 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2626 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2627 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2628 bool restore_forcewake
);
2629 extern void intel_uncore_init(struct drm_device
*dev
);
2630 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2631 extern void intel_uncore_fini(struct drm_device
*dev
);
2632 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2633 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2634 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2635 enum forcewake_domains domains
);
2636 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2637 enum forcewake_domains domains
);
2638 /* Like above but the caller must manage the uncore.lock itself.
2639 * Must be used with I915_READ_FW and friends.
2641 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2642 enum forcewake_domains domains
);
2643 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2644 enum forcewake_domains domains
);
2645 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2646 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2648 return to_i915(dev
)->vgpu
.active
;
2652 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2656 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2659 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2660 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2662 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2664 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2665 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2666 uint32_t interrupt_mask
,
2667 uint32_t enabled_irq_mask
);
2668 #define ibx_enable_display_interrupt(dev_priv, bits) \
2669 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2670 #define ibx_disable_display_interrupt(dev_priv, bits) \
2671 ibx_display_interrupt_update((dev_priv), (bits), 0)
2674 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2675 struct drm_file
*file_priv
);
2676 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2677 struct drm_file
*file_priv
);
2678 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2679 struct drm_file
*file_priv
);
2680 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2681 struct drm_file
*file_priv
);
2682 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2683 struct drm_file
*file_priv
);
2684 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2685 struct drm_file
*file_priv
);
2686 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2687 struct drm_file
*file_priv
);
2688 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2689 struct intel_engine_cs
*ring
);
2690 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2691 struct drm_file
*file
,
2692 struct intel_engine_cs
*ring
,
2693 struct drm_i915_gem_object
*obj
);
2694 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2695 struct drm_file
*file
,
2696 struct intel_engine_cs
*ring
,
2697 struct intel_context
*ctx
,
2698 struct drm_i915_gem_execbuffer2
*args
,
2699 struct list_head
*vmas
,
2700 struct drm_i915_gem_object
*batch_obj
,
2701 u64 exec_start
, u32 flags
);
2702 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2703 struct drm_file
*file_priv
);
2704 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2705 struct drm_file
*file_priv
);
2706 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2707 struct drm_file
*file_priv
);
2708 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2709 struct drm_file
*file
);
2710 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2711 struct drm_file
*file
);
2712 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2713 struct drm_file
*file_priv
);
2714 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2715 struct drm_file
*file_priv
);
2716 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2717 struct drm_file
*file_priv
);
2718 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2719 struct drm_file
*file_priv
);
2720 int i915_gem_init_userptr(struct drm_device
*dev
);
2721 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2722 struct drm_file
*file
);
2723 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2724 struct drm_file
*file_priv
);
2725 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2726 struct drm_file
*file_priv
);
2727 void i915_gem_load(struct drm_device
*dev
);
2728 void *i915_gem_object_alloc(struct drm_device
*dev
);
2729 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2730 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2731 const struct drm_i915_gem_object_ops
*ops
);
2732 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2734 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2735 struct i915_address_space
*vm
);
2736 void i915_gem_free_object(struct drm_gem_object
*obj
);
2737 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2739 /* Flags used by pin/bind&friends. */
2740 #define PIN_MAPPABLE (1<<0)
2741 #define PIN_NONBLOCK (1<<1)
2742 #define PIN_GLOBAL (1<<2)
2743 #define PIN_OFFSET_BIAS (1<<3)
2744 #define PIN_USER (1<<4)
2745 #define PIN_UPDATE (1<<5)
2746 #define PIN_OFFSET_MASK (~4095)
2748 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2749 struct i915_address_space
*vm
,
2753 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2754 const struct i915_ggtt_view
*view
,
2758 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2760 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2761 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2762 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2763 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2765 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2766 int *needs_clflush
);
2768 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2770 static inline int __sg_page_count(struct scatterlist
*sg
)
2772 return sg
->length
>> PAGE_SHIFT
;
2775 static inline struct vm_page
*
2776 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2778 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2781 if (n
< obj
->get_page
.last
) {
2782 obj
->get_page
.sg
= obj
->pages
->sgl
;
2783 obj
->get_page
.last
= 0;
2786 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2787 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2789 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2790 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2794 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2797 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2799 BUG_ON(obj
->pages
== NULL
);
2800 obj
->pages_pin_count
++;
2802 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2804 BUG_ON(obj
->pages_pin_count
== 0);
2805 obj
->pages_pin_count
--;
2808 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2809 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2810 struct intel_engine_cs
*to
);
2811 void i915_vma_move_to_active(struct i915_vma
*vma
,
2812 struct intel_engine_cs
*ring
);
2813 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2814 struct drm_device
*dev
,
2815 struct drm_mode_create_dumb
*args
);
2816 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2817 uint32_t handle
, uint64_t *offset
);
2819 * Returns true if seq1 is later than seq2.
2822 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2824 return (int32_t)(seq1
- seq2
) >= 0;
2827 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2828 bool lazy_coherency
)
2832 BUG_ON(req
== NULL
);
2834 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2836 return i915_seqno_passed(seqno
, req
->seqno
);
2839 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2840 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2841 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2842 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2844 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2845 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2847 struct drm_i915_gem_request
*
2848 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2850 bool i915_gem_retire_requests(struct drm_device
*dev
);
2851 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2852 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2853 bool interruptible
);
2854 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2856 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2858 return unlikely(atomic_read(&error
->reset_counter
)
2859 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2862 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2864 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2867 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2869 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2872 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2874 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2875 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2878 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2880 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2881 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2884 void i915_gem_reset(struct drm_device
*dev
);
2885 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2886 int __must_check
i915_gem_init(struct drm_device
*dev
);
2887 int i915_gem_init_rings(struct drm_device
*dev
);
2888 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2889 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2890 void i915_gem_init_swizzling(struct drm_device
*dev
);
2891 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2892 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2893 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2894 int __i915_add_request(struct intel_engine_cs
*ring
,
2895 struct drm_file
*file
,
2896 struct drm_i915_gem_object
*batch_obj
);
2897 #define i915_add_request(ring) \
2898 __i915_add_request(ring, NULL, NULL)
2899 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2900 unsigned reset_counter
,
2903 struct intel_rps_client
*rps
);
2904 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2905 int i915_gem_fault(vm_object_t vm_obj
, vm_ooffset_t offset
, int prot
, vm_page_t
*mres
);
2907 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2910 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2913 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2915 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2917 struct intel_engine_cs
*pipelined
,
2918 const struct i915_ggtt_view
*view
);
2919 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
2920 const struct i915_ggtt_view
*view
);
2921 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2923 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2924 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2927 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2929 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2930 int tiling_mode
, bool fenced
);
2932 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2933 enum i915_cache_level cache_level
);
2936 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2937 struct dma_buf
*dma_buf
);
2939 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2940 struct drm_gem_object
*gem_obj
, int flags
);
2943 void i915_gem_restore_fences(struct drm_device
*dev
);
2946 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
2947 const struct i915_ggtt_view
*view
);
2949 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2950 struct i915_address_space
*vm
);
2951 static inline unsigned long
2952 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
2954 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
2957 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2958 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
2959 const struct i915_ggtt_view
*view
);
2960 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2961 struct i915_address_space
*vm
);
2963 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2964 struct i915_address_space
*vm
);
2966 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2967 struct i915_address_space
*vm
);
2969 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
2970 const struct i915_ggtt_view
*view
);
2973 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2974 struct i915_address_space
*vm
);
2976 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2977 const struct i915_ggtt_view
*view
);
2979 static inline struct i915_vma
*
2980 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
2982 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
2984 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
2986 /* Some GGTT VM helpers */
2987 #define i915_obj_to_ggtt(obj) \
2988 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2989 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2991 struct i915_address_space
*ggtt
=
2992 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2996 static inline struct i915_hw_ppgtt
*
2997 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2999 WARN_ON(i915_is_ggtt(vm
));
3001 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3005 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3007 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3010 static inline unsigned long
3011 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3013 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3016 static inline int __must_check
3017 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3021 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3022 alignment
, flags
| PIN_GLOBAL
);
3026 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3028 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3031 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3032 const struct i915_ggtt_view
*view
);
3034 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3036 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3039 /* i915_gem_context.c */
3040 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3041 void i915_gem_context_fini(struct drm_device
*dev
);
3042 void i915_gem_context_reset(struct drm_device
*dev
);
3043 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3044 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
3045 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3046 int i915_switch_context(struct intel_engine_cs
*ring
,
3047 struct intel_context
*to
);
3048 struct intel_context
*
3049 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3050 void i915_gem_context_free(struct kref
*ctx_ref
);
3051 struct drm_i915_gem_object
*
3052 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3053 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3055 kref_get(&ctx
->ref
);
3058 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3060 kref_put(&ctx
->ref
, i915_gem_context_free
);
3063 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3065 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3068 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3069 struct drm_file
*file
);
3070 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3071 struct drm_file
*file
);
3072 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3073 struct drm_file
*file_priv
);
3074 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3075 struct drm_file
*file_priv
);
3077 /* i915_gem_evict.c */
3078 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3079 struct i915_address_space
*vm
,
3082 unsigned cache_level
,
3083 unsigned long start
,
3086 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3087 int i915_gem_evict_everything(struct drm_device
*dev
);
3089 /* belongs in i915_gem_gtt.h */
3090 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3092 if (INTEL_INFO(dev
)->gen
< 6)
3093 intel_gtt_chipset_flush();
3096 /* i915_gem_stolen.c */
3097 int i915_gem_init_stolen(struct drm_device
*dev
);
3098 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
3099 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
3100 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3101 struct drm_i915_gem_object
*
3102 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3103 struct drm_i915_gem_object
*
3104 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3109 /* i915_gem_shrinker.c */
3110 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3113 #define I915_SHRINK_PURGEABLE 0x1
3114 #define I915_SHRINK_UNBOUND 0x2
3115 #define I915_SHRINK_BOUND 0x4
3116 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3117 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3120 /* i915_gem_tiling.c */
3121 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3123 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3125 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3126 obj
->tiling_mode
!= I915_TILING_NONE
;
3129 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3130 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3131 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3133 /* i915_gem_debug.c */
3135 int i915_verify_lists(struct drm_device
*dev
);
3137 #define i915_verify_lists(dev) 0
3140 /* i915_debugfs.c */
3141 int i915_debugfs_init(struct drm_minor
*minor
);
3142 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3143 #ifdef CONFIG_DEBUG_FS
3144 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3145 void intel_display_crc_init(struct drm_device
*dev
);
3147 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3149 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3152 /* i915_gpu_error.c */
3154 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3155 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3156 const struct i915_error_state_file_priv
*error
);
3157 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3158 struct drm_i915_private
*i915
,
3159 size_t count
, loff_t pos
);
3160 static inline void i915_error_state_buf_release(
3161 struct drm_i915_error_state_buf
*eb
)
3165 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3166 const char *error_msg
);
3167 void i915_error_state_get(struct drm_device
*dev
,
3168 struct i915_error_state_file_priv
*error_priv
);
3169 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3170 void i915_destroy_error_state(struct drm_device
*dev
);
3172 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3173 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3175 /* i915_cmd_parser.c */
3176 int i915_cmd_parser_get_version(void);
3177 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3178 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3179 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3180 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3181 struct drm_i915_gem_object
*batch_obj
,
3182 struct drm_i915_gem_object
*shadow_batch_obj
,
3183 u32 batch_start_offset
,
3187 /* i915_suspend.c */
3188 extern int i915_save_state(struct drm_device
*dev
);
3189 extern int i915_restore_state(struct drm_device
*dev
);
3192 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3193 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3196 extern int intel_setup_gmbus(struct drm_device
*dev
);
3197 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3198 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3201 extern struct i2c_adapter
*
3202 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3203 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3204 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3205 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3207 struct intel_iic_softc
*sc
;
3208 sc
= device_get_softc(device_get_parent(adapter
));
3210 return sc
->force_bit_dev
;
3212 extern void intel_i2c_reset(struct drm_device
*dev
);
3214 /* intel_opregion.c */
3216 extern int intel_opregion_setup(struct drm_device
*dev
);
3217 extern void intel_opregion_init(struct drm_device
*dev
);
3218 extern void intel_opregion_fini(struct drm_device
*dev
);
3219 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3220 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3222 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3225 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3226 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3227 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3228 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3230 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3235 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3243 extern void intel_register_dsm_handler(void);
3244 extern void intel_unregister_dsm_handler(void);
3246 static inline void intel_register_dsm_handler(void) { return; }
3247 static inline void intel_unregister_dsm_handler(void) { return; }
3248 #endif /* CONFIG_ACPI */
3251 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3252 extern void intel_modeset_init(struct drm_device
*dev
);
3253 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3254 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3255 extern void intel_connector_unregister(struct intel_connector
*);
3256 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3257 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3258 bool force_restore
);
3259 extern void i915_redisable_vga(struct drm_device
*dev
);
3260 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3261 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3262 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3263 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3264 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3266 extern void intel_detect_pch(struct drm_device
*dev
);
3267 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3268 extern int intel_enable_rc6(const struct drm_device
*dev
);
3270 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3271 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3272 struct drm_file
*file
);
3273 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3274 struct drm_file
*file
);
3276 struct intel_device_info
*i915_get_device_id(int device
);
3279 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3280 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3281 struct intel_overlay_error_state
*error
);
3283 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3284 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3285 struct drm_device
*dev
,
3286 struct intel_display_error_state
*error
);
3288 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3289 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3291 /* intel_sideband.c */
3292 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3293 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3294 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3295 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3296 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3297 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3298 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3299 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3300 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3301 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3302 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3303 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3304 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3305 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
);
3306 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
, u32 val
);
3307 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3308 enum intel_sbi_destination destination
);
3309 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3310 enum intel_sbi_destination destination
);
3311 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3312 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3314 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3315 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3317 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3318 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3320 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3321 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3322 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3323 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3325 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3326 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3327 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3328 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3330 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3331 * will be implemented using 2 32-bit writes in an arbitrary order with
3332 * an arbitrary delay between them. This can cause the hardware to
3333 * act upon the intermediate value, possibly leading to corruption and
3334 * machine death. You have been warned.
3336 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3337 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3339 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3340 u32 upper, lower, tmp; \
3341 tmp = I915_READ(upper_reg); \
3344 lower = I915_READ(lower_reg); \
3345 tmp = I915_READ(upper_reg); \
3346 } while (upper != tmp); \
3347 (u64)upper << 32 | lower; })
3349 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3350 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3352 /* These are untraced mmio-accessors that are only valid to be used inside
3353 * criticial sections inside IRQ handlers where forcewake is explicitly
3355 * Think twice, and think again, before using these.
3356 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3357 * intel_uncore_forcewake_irqunlock().
3359 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3360 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3361 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3363 /* "Broadcast RGB" property */
3364 #define INTEL_BROADCAST_RGB_AUTO 0
3365 #define INTEL_BROADCAST_RGB_FULL 1
3366 #define INTEL_BROADCAST_RGB_LIMITED 2
3368 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3370 if (IS_VALLEYVIEW(dev
))
3371 return VLV_VGACNTRL
;
3372 else if (INTEL_INFO(dev
)->gen
>= 5)
3373 return CPU_VGACNTRL
;
3378 static inline void __user
*to_user_ptr(u64 address
)
3380 return (void __user
*)(uintptr_t)address
;
3383 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3385 unsigned long j
= msecs_to_jiffies(m
);
3387 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3390 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3392 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3395 static inline unsigned long
3396 timespec_to_jiffies_timeout(const struct timespec
*value
)
3398 unsigned long j
= timespec_to_jiffies(value
);
3400 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3404 * If you need to wait X milliseconds between events A and B, but event B
3405 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3406 * when event A happened, then just before event B you call this function and
3407 * pass the timestamp as the first argument, and X as the second argument.
3410 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3412 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3415 * Don't re-read the value of "jiffies" every time since it may change
3416 * behind our back and break the math.
3418 tmp_jiffies
= jiffies
;
3419 target_jiffies
= timestamp_jiffies
+
3420 msecs_to_jiffies_timeout(to_wait_ms
);
3422 if (time_after(target_jiffies
, tmp_jiffies
)) {
3423 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3425 while (remaining_jiffies
)
3427 schedule_timeout_uninterruptible(remaining_jiffies
);
3429 msleep(jiffies_to_msecs(remaining_jiffies
));
3434 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3435 struct drm_i915_gem_request
*req
)
3437 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3438 i915_gem_request_assign(&ring
->trace_irq_req
, req
);