2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $
28 * $DragonFly: src/sys/dev/acpica5/acpi_cpu.c,v 1.21 2008/09/05 10:28:35 hasso Exp $
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/globaldata.h>
37 #include <sys/power.h>
40 #include <sys/thread2.h>
42 #include <bus/pci/pcivar.h>
43 #include <machine/atomic.h>
44 #include <machine/globaldata.h>
45 #include <machine/md_var.h>
46 #include <machine/smp.h>
54 * Support for ACPI Processor devices, including C[1-3] sleep states.
57 /* Hooks for the ACPI CA debugging infrastructure */
58 #define _COMPONENT ACPI_PROCESSOR
59 ACPI_MODULE_NAME("PROCESSOR")
62 struct resource
*p_lvlx
; /* Register to read to enter state. */
63 int rid
; /* rid of p_lvlx */
64 uint32_t type
; /* C1-3 (C4 and up treated as C3). */
65 uint32_t trans_lat
; /* Transition latency (usec). */
66 uint32_t power
; /* Power consumed (mW). */
67 int res_type
; /* Resource type for p_lvlx. */
69 #define MAX_CX_STATES 8
71 struct acpi_cpu_softc
{
73 struct acpi_cpux_softc
*cpu_parent
;
74 ACPI_HANDLE cpu_handle
;
75 struct mdglobaldata
*md
;
76 uint32_t cpu_acpi_id
; /* ACPI processor id */
77 uint32_t cpu_p_blk
; /* ACPI P_BLK location */
78 uint32_t cpu_p_blk_len
; /* P_BLK length (must be 6). */
79 struct acpi_cx cpu_cx_states
[MAX_CX_STATES
];
80 int cpu_cx_count
; /* Number of valid Cx states. */
81 int cpu_prev_sleep
;/* Last idle sleep duration. */
82 int cpu_features
; /* Child driver supported features. */
84 int cpu_non_c3
; /* Index of lowest non-C3 state. */
85 u_int cpu_cx_stats
[MAX_CX_STATES
];/* Cx usage history. */
86 /* Values for sysctl. */
88 char cpu_cx_supported
[64];
91 struct acpi_cpu_device
{
92 struct resource_list ad_rl
;
95 #define CPU_GET_REG(reg, width) \
96 (bus_space_read_ ## width(rman_get_bustag((reg)), \
97 rman_get_bushandle((reg)), 0))
98 #define CPU_SET_REG(reg, width, val) \
99 (bus_space_write_ ## width(rman_get_bustag((reg)), \
100 rman_get_bushandle((reg)), 0, (val)))
102 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */
104 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
106 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
107 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
109 #define PCI_VENDOR_INTEL 0x8086
110 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
111 #define PCI_REVISION_A_STEP 0
112 #define PCI_REVISION_B_STEP 1
113 #define PCI_REVISION_4E 2
114 #define PCI_REVISION_4M 3
115 #define PIIX4_DEVACTB_REG 0x58
116 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
117 #define PIIX4_BRLD_EN_IRQ (1<<1)
118 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
119 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
120 #define PIIX4_PCNTRL_BST_EN (1<<10)
122 /* Platform hardware resource information. */
123 static uint32_t cpu_smi_cmd
; /* Value to write to SMI_CMD. */
124 static uint8_t cpu_cst_cnt
; /* Indicate we are _CST aware. */
125 static int cpu_quirks
; /* Indicate any hardware bugs. */
128 static int cpu_disable_idle
; /* Disable entry to idle function */
129 static int cpu_cx_count
; /* Number of valid Cx states */
131 /* Values for sysctl. */
132 static int cpu_cx_generic
;
133 static int cpu_cx_lowest
;
135 /* C3 state transition */
136 static int cpu_c3_ncpus
;
138 static device_t
*cpu_devices
;
139 static int cpu_ndevices
;
140 static struct acpi_cpu_softc
**cpu_softc
;
142 static int acpi_cpu_cst_probe(device_t dev
);
143 static int acpi_cpu_cst_attach(device_t dev
);
144 static int acpi_cpu_cst_suspend(device_t dev
);
145 static int acpi_cpu_cst_resume(device_t dev
);
146 static struct resource_list
*acpi_cpu_cst_get_rlist(device_t dev
,
148 static device_t
acpi_cpu_cst_add_child(device_t bus
, device_t parent
,
149 int order
, const char *name
, int unit
);
150 static int acpi_cpu_cst_read_ivar(device_t dev
, device_t child
,
151 int index
, uintptr_t *result
);
152 static int acpi_cpu_cst_shutdown(device_t dev
);
153 static void acpi_cpu_cx_probe(struct acpi_cpu_softc
*sc
);
154 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc
*sc
);
155 static int acpi_cpu_cx_cst(struct acpi_cpu_softc
*sc
);
156 static void acpi_cpu_startup(void *arg
);
157 static void acpi_cpu_startup_cx(struct acpi_cpu_softc
*sc
);
158 static void acpi_cpu_cx_list(struct acpi_cpu_softc
*sc
);
159 static void acpi_cpu_idle(void);
160 static void acpi_cpu_cst_notify(device_t
);
161 static int acpi_cpu_quirks(void);
162 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS
);
163 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc
*sc
, int val
);
164 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS
);
165 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS
);
167 static void acpi_cpu_c1(void); /* XXX */
169 static device_method_t acpi_cpu_cst_methods
[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe
, acpi_cpu_cst_probe
),
172 DEVMETHOD(device_attach
, acpi_cpu_cst_attach
),
173 DEVMETHOD(device_detach
, bus_generic_detach
),
174 DEVMETHOD(device_shutdown
, acpi_cpu_cst_shutdown
),
175 DEVMETHOD(device_suspend
, acpi_cpu_cst_suspend
),
176 DEVMETHOD(device_resume
, acpi_cpu_cst_resume
),
179 DEVMETHOD(bus_add_child
, acpi_cpu_cst_add_child
),
180 DEVMETHOD(bus_read_ivar
, acpi_cpu_cst_read_ivar
),
181 DEVMETHOD(bus_get_resource_list
, acpi_cpu_cst_get_rlist
),
182 DEVMETHOD(bus_get_resource
, bus_generic_rl_get_resource
),
183 DEVMETHOD(bus_set_resource
, bus_generic_rl_set_resource
),
184 DEVMETHOD(bus_alloc_resource
, bus_generic_rl_alloc_resource
),
185 DEVMETHOD(bus_release_resource
, bus_generic_rl_release_resource
),
186 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
187 DEVMETHOD(bus_activate_resource
, bus_generic_activate_resource
),
188 DEVMETHOD(bus_deactivate_resource
, bus_generic_deactivate_resource
),
189 DEVMETHOD(bus_setup_intr
, bus_generic_setup_intr
),
190 DEVMETHOD(bus_teardown_intr
, bus_generic_teardown_intr
),
194 static driver_t acpi_cpu_cst_driver
= {
196 acpi_cpu_cst_methods
,
197 sizeof(struct acpi_cpu_softc
),
200 static devclass_t acpi_cpu_cst_devclass
;
201 DRIVER_MODULE(cpu_cst
, cpu
, acpi_cpu_cst_driver
, acpi_cpu_cst_devclass
, 0, 0);
202 MODULE_DEPEND(cpu_cst
, acpi
, 1, 1, 1);
205 acpi_cpu_cst_probe(device_t dev
)
209 if (acpi_disabled("cpu_cst") || acpi_get_type(dev
) != ACPI_TYPE_PROCESSOR
)
212 cpu_id
= acpi_get_magic(dev
);
214 if (cpu_softc
== NULL
)
215 cpu_softc
= kmalloc(sizeof(struct acpi_cpu_softc
*) *
216 SMP_MAXCPU
, M_TEMP
/* XXX */, M_INTWAIT
| M_ZERO
);
219 * Check if we already probed this processor. We scan the bus twice
220 * so it's possible we've already seen this one.
222 if (cpu_softc
[cpu_id
] != NULL
) {
223 device_printf(dev
, "CPU%d cstate already exist\n", cpu_id
);
227 /* Mark this processor as in-use and save our derived id for attach. */
228 cpu_softc
[cpu_id
] = (void *)1;
229 device_set_desc(dev
, "ACPI CPU C-State");
235 acpi_cpu_cst_attach(device_t dev
)
238 ACPI_OBJECT arg
[4], *obj
;
239 ACPI_OBJECT_LIST arglist
;
240 struct mdglobaldata
*md
;
241 struct acpi_cpu_softc
*sc
;
244 int cpu_id
, drv_count
, i
;
248 /* UUID needed by _OSC evaluation */
249 static uint8_t cpu_oscuuid
[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
250 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
251 0x58, 0x71, 0x39, 0x53 };
253 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__
);
255 sc
= device_get_softc(dev
);
257 sc
->cpu_parent
= device_get_softc(device_get_parent(dev
));
258 sc
->cpu_handle
= acpi_get_handle(dev
);
259 cpu_id
= acpi_get_magic(dev
);
260 cpu_softc
[cpu_id
] = sc
;
261 md
= (struct mdglobaldata
*)globaldata_find(device_get_unit(dev
));
263 cpu_smi_cmd
= AcpiGbl_FADT
.SmiCommand
;
264 cpu_cst_cnt
= AcpiGbl_FADT
.CstControl
;
267 buf
.Length
= ACPI_ALLOCATE_BUFFER
;
268 status
= AcpiEvaluateObject(sc
->cpu_handle
, NULL
, NULL
, &buf
);
269 if (ACPI_FAILURE(status
)) {
270 device_printf(dev
, "attach failed to get Processor obj - %s\n",
271 AcpiFormatException(status
));
274 obj
= (ACPI_OBJECT
*)buf
.Pointer
;
275 sc
->cpu_p_blk
= obj
->Processor
.PblkAddress
;
276 sc
->cpu_p_blk_len
= obj
->Processor
.PblkLength
;
277 sc
->cpu_acpi_id
= obj
->Processor
.ProcId
;
279 ACPI_DEBUG_PRINT((ACPI_DB_INFO
, "acpi_cpu%d: P_BLK at %#x/%d\n",
280 device_get_unit(dev
), sc
->cpu_p_blk
, sc
->cpu_p_blk_len
));
283 * If this is the first cpu we attach, create and initialize the generic
284 * resources that will be used by all acpi cpu devices.
286 if (device_get_unit(dev
) == 0) {
287 /* Assume we won't be using generic Cx mode by default */
288 cpu_cx_generic
= FALSE
;
290 /* Queue post cpu-probing task handler */
291 AcpiOsExecute(OSL_NOTIFY_HANDLER
, acpi_cpu_startup
, NULL
);
295 * Before calling any CPU methods, collect child driver feature hints
296 * and notify ACPI of them. We support unified SMP power control
297 * so advertise this ourselves. Note this is not the same as independent
298 * SMP control where each CPU can have different settings.
300 sc
->cpu_features
= ACPI_CAP_SMP_SAME
| ACPI_CAP_SMP_SAME_C3
;
301 if (devclass_get_drivers(acpi_cpu_cst_devclass
,
302 &drivers
, &drv_count
) == 0) {
303 for (i
= 0; i
< drv_count
; i
++) {
304 if (ACPI_GET_FEATURES(drivers
[i
], &features
) == 0)
305 sc
->cpu_features
|= features
;
307 kfree(drivers
, M_TEMP
);
311 * CPU capabilities are specified as a buffer of 32-bit integers:
312 * revision, count, and one or more capabilities. The revision of
313 * "1" is not specified anywhere but seems to match Linux.
315 if (sc
->cpu_features
) {
316 arglist
.Pointer
= arg
;
318 arg
[0].Type
= ACPI_TYPE_BUFFER
;
319 arg
[0].Buffer
.Length
= sizeof(cap_set
);
320 arg
[0].Buffer
.Pointer
= (uint8_t *)cap_set
;
321 cap_set
[0] = 1; /* revision */
322 cap_set
[1] = 1; /* number of capabilities integers */
323 cap_set
[2] = sc
->cpu_features
;
324 AcpiEvaluateObject(sc
->cpu_handle
, "_PDC", &arglist
, NULL
);
327 * On some systems we need to evaluate _OSC so that the ASL
328 * loads the _PSS and/or _PDC methods at runtime.
330 * TODO: evaluate failure of _OSC.
332 arglist
.Pointer
= arg
;
334 arg
[0].Type
= ACPI_TYPE_BUFFER
;
335 arg
[0].Buffer
.Length
= sizeof(cpu_oscuuid
);
336 arg
[0].Buffer
.Pointer
= cpu_oscuuid
; /* UUID */
337 arg
[1].Type
= ACPI_TYPE_INTEGER
;
338 arg
[1].Integer
.Value
= 1; /* revision */
339 arg
[2].Type
= ACPI_TYPE_INTEGER
;
340 arg
[2].Integer
.Value
= 1; /* count */
341 arg
[3].Type
= ACPI_TYPE_BUFFER
;
342 arg
[3].Buffer
.Length
= sizeof(cap_set
); /* Capabilities buffer */
343 arg
[3].Buffer
.Pointer
= (uint8_t *)cap_set
;
345 AcpiEvaluateObject(sc
->cpu_handle
, "_OSC", &arglist
, NULL
);
348 /* Probe for Cx state support. */
349 acpi_cpu_cx_probe(sc
);
351 /* Finally, call identify and probe/attach for child devices. */
352 bus_generic_probe(dev
);
353 bus_generic_attach(dev
);
359 * Disable any entry to the idle function during suspend and re-enable it
363 acpi_cpu_cst_suspend(device_t dev
)
367 error
= bus_generic_suspend(dev
);
370 cpu_disable_idle
= TRUE
;
375 acpi_cpu_cst_resume(device_t dev
)
378 cpu_disable_idle
= FALSE
;
379 return (bus_generic_resume(dev
));
382 static struct resource_list
*
383 acpi_cpu_cst_get_rlist(device_t dev
, device_t child
)
385 struct acpi_cpu_device
*ad
;
387 ad
= device_get_ivars(child
);
394 acpi_cpu_cst_add_child(device_t bus
, device_t parent
, int order
,
395 const char *name
, int unit
)
397 struct acpi_cpu_device
*ad
;
400 if ((ad
= kmalloc(sizeof(*ad
), M_TEMP
, M_NOWAIT
| M_ZERO
)) == NULL
)
403 resource_list_init(&ad
->ad_rl
);
405 child
= device_add_child_ordered(parent
, order
, name
, unit
);
407 device_set_ivars(child
, ad
);
414 acpi_cpu_cst_read_ivar(device_t dev
, device_t child
, int index
,
417 struct acpi_cpu_softc
*sc
;
419 sc
= device_get_softc(dev
);
421 case ACPI_IVAR_HANDLE
:
422 *result
= (uintptr_t)sc
->cpu_handle
;
426 *result
= (uintptr_t)sc
->cpu_pcpu
;
436 acpi_cpu_cst_shutdown(device_t dev
)
438 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__
);
440 /* Allow children to shutdown first. */
441 bus_generic_shutdown(dev
);
444 * Disable any entry to the idle function. There is a small race where
445 * an idle thread have passed this check but not gone to sleep. This
446 * is ok since device_shutdown() does not free the softc, otherwise
447 * we'd have to be sure all threads were evicted before returning.
449 cpu_disable_idle
= TRUE
;
455 acpi_cpu_cx_probe(struct acpi_cpu_softc
*sc
)
457 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__
);
459 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
460 sc
->cpu_prev_sleep
= 1000000;
461 sc
->cpu_cx_lowest
= 0;
464 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
465 * any, we'll revert to generic FADT/P_BLK Cx control method which will
466 * be handled by acpi_cpu_startup. We need to defer to after having
467 * probed all the cpus in the system before probing for generic Cx
468 * states as we may already have found cpus with valid _CST packages
470 if (!cpu_cx_generic
&& acpi_cpu_cx_cst(sc
) != 0) {
472 * We were unable to find a _CST package for this cpu or there
473 * was an error parsing it. Switch back to generic mode.
475 cpu_cx_generic
= TRUE
;
477 device_printf(sc
->cpu_dev
, "switching to generic Cx mode\n");
481 * TODO: _CSD Package should be checked here.
486 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc
*sc
)
488 ACPI_GENERIC_ADDRESS gas
;
489 struct acpi_cx
*cx_ptr
;
491 sc
->cpu_cx_count
= 0;
492 cx_ptr
= sc
->cpu_cx_states
;
494 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
495 sc
->cpu_prev_sleep
= 1000000;
497 /* C1 has been required since just after ACPI 1.0 */
498 cx_ptr
->type
= ACPI_STATE_C1
;
499 cx_ptr
->trans_lat
= 0;
504 * The spec says P_BLK must be 6 bytes long. However, some systems
505 * use it to indicate a fractional set of features present so we
506 * take 5 as C2. Some may also have a value of 7 to indicate
507 * another C3 but most use _CST for this (as required) and having
508 * "only" C1-C3 is not a hardship.
510 if (sc
->cpu_p_blk_len
< 5)
513 /* Validate and allocate resources for C2 (P_LVL2). */
514 gas
.SpaceId
= ACPI_ADR_SPACE_SYSTEM_IO
;
516 if (AcpiGbl_FADT
.C2Latency
<= 100) {
517 gas
.Address
= sc
->cpu_p_blk
+ 4;
519 cx_ptr
->rid
= sc
->cpu_parent
->cpux_next_rid
;
520 acpi_bus_alloc_gas(sc
->cpu_dev
, &cx_ptr
->type
, &cx_ptr
->rid
, &gas
, &cx_ptr
->p_lvlx
,
522 if (cx_ptr
->p_lvlx
!= NULL
) {
523 sc
->cpu_parent
->cpux_next_rid
++;
524 cx_ptr
->type
= ACPI_STATE_C2
;
525 cx_ptr
->trans_lat
= AcpiGbl_FADT
.C2Latency
;
530 if (sc
->cpu_p_blk_len
< 6)
533 /* Validate and allocate resources for C3 (P_LVL3). */
534 if (AcpiGbl_FADT
.C3Latency
<= 1000 && !(cpu_quirks
& CPU_QUIRK_NO_C3
)) {
535 gas
.Address
= sc
->cpu_p_blk
+ 5;
537 cx_ptr
->rid
= sc
->cpu_parent
->cpux_next_rid
;
538 acpi_bus_alloc_gas(sc
->cpu_dev
, &cx_ptr
->type
, &cx_ptr
->rid
, &gas
,
539 &cx_ptr
->p_lvlx
, RF_SHAREABLE
);
540 if (cx_ptr
->p_lvlx
!= NULL
) {
541 sc
->cpu_parent
->cpux_next_rid
++;
542 cx_ptr
->type
= ACPI_STATE_C3
;
543 cx_ptr
->trans_lat
= AcpiGbl_FADT
.C3Latency
;
551 * Parse a _CST package and set up its Cx states. Since the _CST object
552 * can change dynamically, our notify handler may call this function
553 * to clean up and probe the new _CST package.
556 acpi_cpu_cx_cst(struct acpi_cpu_softc
*sc
)
558 struct acpi_cx
*cx_ptr
;
566 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__
);
569 buf
.Length
= ACPI_ALLOCATE_BUFFER
;
570 status
= AcpiEvaluateObject(sc
->cpu_handle
, "_CST", NULL
, &buf
);
571 if (ACPI_FAILURE(status
))
574 /* _CST is a package with a count and at least one Cx package. */
575 top
= (ACPI_OBJECT
*)buf
.Pointer
;
576 if (!ACPI_PKG_VALID(top
, 2) || acpi_PkgInt32(top
, 0, &count
) != 0) {
577 device_printf(sc
->cpu_dev
, "invalid _CST package\n");
578 AcpiOsFree(buf
.Pointer
);
581 if (count
!= top
->Package
.Count
- 1) {
582 device_printf(sc
->cpu_dev
, "invalid _CST state count (%d != %d)\n",
583 count
, top
->Package
.Count
- 1);
584 count
= top
->Package
.Count
- 1;
586 if (count
> MAX_CX_STATES
) {
587 device_printf(sc
->cpu_dev
, "_CST has too many states (%d)\n", count
);
588 count
= MAX_CX_STATES
;
591 /* Set up all valid states. */
592 sc
->cpu_cx_count
= 0;
593 cx_ptr
= sc
->cpu_cx_states
;
594 for (i
= 0; i
< count
; i
++) {
595 pkg
= &top
->Package
.Elements
[i
+ 1];
596 if (!ACPI_PKG_VALID(pkg
, 4) ||
597 acpi_PkgInt32(pkg
, 1, &cx_ptr
->type
) != 0 ||
598 acpi_PkgInt32(pkg
, 2, &cx_ptr
->trans_lat
) != 0 ||
599 acpi_PkgInt32(pkg
, 3, &cx_ptr
->power
) != 0) {
601 device_printf(sc
->cpu_dev
, "skipping invalid Cx state package\n");
605 /* Validate the state to see if we should use it. */
606 switch (cx_ptr
->type
) {
613 if (cx_ptr
->trans_lat
> 100) {
614 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
615 "acpi_cpu%d: C2[%d] not available.\n",
616 device_get_unit(sc
->cpu_dev
), i
));
623 if (cx_ptr
->trans_lat
> 1000 ||
624 (cpu_quirks
& CPU_QUIRK_NO_C3
) != 0) {
626 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
627 "acpi_cpu%d: C3[%d] not available.\n",
628 device_get_unit(sc
->cpu_dev
), i
));
635 /* Free up any previous register. */
636 if (cx_ptr
->p_lvlx
!= NULL
) {
637 bus_release_resource(sc
->cpu_dev
, 0, 0, cx_ptr
->p_lvlx
);
638 cx_ptr
->p_lvlx
= NULL
;
642 /* Allocate the control register for C2 or C3. */
643 cx_ptr
->rid
= sc
->cpu_parent
->cpux_next_rid
;
644 acpi_PkgGas(sc
->cpu_dev
, pkg
, 0, &cx_ptr
->res_type
, &cx_ptr
->rid
, &cx_ptr
->p_lvlx
,
646 if (cx_ptr
->p_lvlx
) {
647 sc
->cpu_parent
->cpux_next_rid
++;
648 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
649 "acpi_cpu%d: Got C%d - %d latency\n",
650 device_get_unit(sc
->cpu_dev
), cx_ptr
->type
,
656 AcpiOsFree(buf
.Pointer
);
662 * Call this *after* all CPUs have been attached.
665 acpi_cpu_startup(void *arg
)
667 struct acpi_cpu_softc
*sc
;
670 /* Get set of CPU devices */
671 devclass_get_devices(acpi_cpu_cst_devclass
, &cpu_devices
, &cpu_ndevices
);
674 * Setup any quirks that might necessary now that we have probed
680 if (cpu_cx_generic
) {
682 * We are using generic Cx mode, probe for available Cx states
683 * for all processors.
685 for (i
= 0; i
< cpu_ndevices
; i
++) {
686 sc
= device_get_softc(cpu_devices
[i
]);
687 acpi_cpu_generic_cx_probe(sc
);
688 if (sc
->cpu_cx_count
> cpu_cx_count
)
689 cpu_cx_count
= sc
->cpu_cx_count
;
693 * Find the highest Cx state common to all CPUs
694 * in the system, taking quirks into account.
696 for (i
= 0; i
< cpu_ndevices
; i
++) {
697 sc
= device_get_softc(cpu_devices
[i
]);
698 if (sc
->cpu_cx_count
< cpu_cx_count
)
699 cpu_cx_count
= sc
->cpu_cx_count
;
703 * We are using _CST mode, remove C3 state if necessary.
704 * Update the largest Cx state supported in the global cpu_cx_count.
705 * It will be used in the global Cx sysctl handler.
706 * As we now know for sure that we will be using _CST mode
707 * install our notify handler.
709 for (i
= 0; i
< cpu_ndevices
; i
++) {
710 sc
= device_get_softc(cpu_devices
[i
]);
711 if (cpu_quirks
& CPU_QUIRK_NO_C3
) {
712 sc
->cpu_cx_count
= sc
->cpu_non_c3
+ 1;
714 if (sc
->cpu_cx_count
> cpu_cx_count
)
715 cpu_cx_count
= sc
->cpu_cx_count
;
716 sc
->cpu_parent
->cpux_cst_notify
= acpi_cpu_cst_notify
;
720 /* Perform Cx final initialization. */
721 for (i
= 0; i
< cpu_ndevices
; i
++) {
722 sc
= device_get_softc(cpu_devices
[i
]);
723 acpi_cpu_startup_cx(sc
);
725 if (sc
->cpu_parent
->glob_sysctl_tree
!= NULL
) {
726 struct acpi_cpux_softc
*cpux
= sc
->cpu_parent
;
728 /* Add a sysctl handler to handle global Cx lowest setting */
729 SYSCTL_ADD_PROC(&cpux
->glob_sysctl_ctx
,
730 SYSCTL_CHILDREN(cpux
->glob_sysctl_tree
),
731 OID_AUTO
, "cx_lowest",
732 CTLTYPE_STRING
| CTLFLAG_RW
, NULL
, 0,
733 acpi_cpu_global_cx_lowest_sysctl
, "A",
734 "Global lowest Cx sleep state to use");
738 /* Take over idling from cpu_idle_default(). */
740 cpu_disable_idle
= FALSE
;
741 cpu_idle_hook
= acpi_cpu_idle
;
745 acpi_cpu_cx_list(struct acpi_cpu_softc
*sc
)
751 * Set up the list of Cx states
754 sbuf_new(&sb
, sc
->cpu_cx_supported
, sizeof(sc
->cpu_cx_supported
),
756 for (i
= 0; i
< sc
->cpu_cx_count
; i
++) {
757 sbuf_printf(&sb
, "C%d/%d ", i
+ 1, sc
->cpu_cx_states
[i
].trans_lat
);
758 if (sc
->cpu_cx_states
[i
].type
< ACPI_STATE_C3
)
766 acpi_cpu_startup_cx(struct acpi_cpu_softc
*sc
)
768 struct acpi_cpux_softc
*cpux
= sc
->cpu_parent
;
770 acpi_cpu_cx_list(sc
);
772 SYSCTL_ADD_STRING(&cpux
->pcpu_sysctl_ctx
,
773 SYSCTL_CHILDREN(cpux
->pcpu_sysctl_tree
),
774 OID_AUTO
, "cx_supported", CTLFLAG_RD
,
775 sc
->cpu_cx_supported
, 0,
776 "Cx/microsecond values for supported Cx states");
777 SYSCTL_ADD_PROC(&cpux
->pcpu_sysctl_ctx
,
778 SYSCTL_CHILDREN(cpux
->pcpu_sysctl_tree
),
779 OID_AUTO
, "cx_lowest", CTLTYPE_STRING
| CTLFLAG_RW
,
780 (void *)sc
, 0, acpi_cpu_cx_lowest_sysctl
, "A",
781 "lowest Cx sleep state to use");
782 SYSCTL_ADD_PROC(&cpux
->pcpu_sysctl_ctx
,
783 SYSCTL_CHILDREN(cpux
->pcpu_sysctl_tree
),
784 OID_AUTO
, "cx_usage", CTLTYPE_STRING
| CTLFLAG_RD
,
785 (void *)sc
, 0, acpi_cpu_usage_sysctl
, "A",
786 "percent usage for each Cx state");
789 /* Signal platform that we can handle _CST notification. */
790 if (!cpu_cx_generic
&& cpu_cst_cnt
!= 0) {
792 AcpiOsWritePort(cpu_smi_cmd
, cpu_cst_cnt
, 8);
799 * Idle the CPU in the lowest state possible. This function is called with
800 * interrupts disabled. Note that once it re-enables interrupts, a task
801 * switch can occur so do not access shared data (i.e. the softc) after
802 * interrupts are re-enabled.
807 struct acpi_cpu_softc
*sc
;
808 struct acpi_cx
*cx_next
;
809 uint32_t start_time
, end_time
;
810 int bm_active
, cx_next_idx
, i
;
812 /* If disabled, return immediately. */
813 if (cpu_disable_idle
) {
819 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
820 * since there is no ACPI processor object for this CPU. This occurs
821 * for logical CPUs in the HTT case.
823 sc
= cpu_softc
[mdcpu
->mi
.gd_cpuid
];
829 /* Find the lowest state that has small enough latency. */
831 for (i
= sc
->cpu_cx_lowest
; i
>= 0; i
--) {
832 if (sc
->cpu_cx_states
[i
].trans_lat
* 3 <= sc
->cpu_prev_sleep
) {
839 * Check for bus master activity. If there was activity, clear
840 * the bit and use the lowest non-C3 state. Note that the USB
841 * driver polling for new devices keeps this bit set all the
842 * time if USB is loaded.
844 if ((cpu_quirks
& CPU_QUIRK_NO_BM_CTRL
) == 0) {
845 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS
, &bm_active
);
846 if (bm_active
!= 0) {
847 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS
, 1);
848 cx_next_idx
= min(cx_next_idx
, sc
->cpu_non_c3
);
852 /* Select the next state and update statistics. */
853 cx_next
= &sc
->cpu_cx_states
[cx_next_idx
];
854 sc
->cpu_cx_stats
[cx_next_idx
]++;
855 KASSERT(cx_next
->type
!= ACPI_STATE_C0
, ("acpi_cpu_idle: C0 sleep"));
858 * Execute HLT (or equivalent) and wait for an interrupt. We can't
859 * calculate the time spent in C1 since the place we wake up is an
860 * ISR. Assume we slept half of quantum and return.
862 if (cx_next
->type
== ACPI_STATE_C1
) {
863 sc
->cpu_prev_sleep
= (sc
->cpu_prev_sleep
* 3 + 500000 / hz
) / 4;
869 * For C3, disable bus master arbitration and enable bus master wake
870 * if BM control is available, otherwise flush the CPU cache.
872 if (cx_next
->type
== ACPI_STATE_C3
) {
873 if ((cpu_quirks
& CPU_QUIRK_NO_BM_CTRL
) == 0) {
874 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE
, 1);
875 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD
, 1);
877 ACPI_FLUSH_CPU_CACHE();
881 * Read from P_LVLx to enter C2(+), checking time spent asleep.
882 * Use the ACPI timer for measuring sleep time. Since we need to
883 * get the time very close to the CPU start/stop clock logic, this
884 * is the only reliable time source.
886 AcpiRead(&start_time
, &AcpiGbl_FADT
.XPmTimerBlock
);
887 CPU_GET_REG(cx_next
->p_lvlx
, 1);
890 * Read the end time twice. Since it may take an arbitrary time
891 * to enter the idle state, the first read may be executed before
892 * the processor has stopped. Doing it again provides enough
893 * margin that we are certain to have a correct value.
895 AcpiRead(&end_time
, &AcpiGbl_FADT
.XPmTimerBlock
);
896 AcpiRead(&end_time
, &AcpiGbl_FADT
.XPmTimerBlock
);
898 /* Enable bus master arbitration and disable bus master wakeup. */
899 if (cx_next
->type
== ACPI_STATE_C3
) {
900 if ((cpu_quirks
& CPU_QUIRK_NO_BM_CTRL
) == 0) {
901 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE
, 0);
902 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD
, 0);
907 /* Find the actual time asleep in microseconds. */
908 end_time
= acpi_TimerDelta(end_time
, start_time
);
909 sc
->cpu_prev_sleep
= (sc
->cpu_prev_sleep
* 3 + PM_USEC(end_time
)) / 4;
913 * Re-evaluate the _CST object when we are notified that it changed.
915 * XXX Re-evaluation disabled until locking is done.
918 acpi_cpu_cst_notify(device_t dev
)
920 struct acpi_cpu_softc
*sc
= device_get_softc(dev
);
921 struct acpi_cpu_softc
*isc
;
924 /* Update the list of Cx states. */
926 acpi_cpu_cx_list(sc
);
928 /* Update the new lowest useable Cx state for all CPUs. */
931 for (i
= 0; i
< cpu_ndevices
; i
++) {
932 isc
= device_get_softc(cpu_devices
[i
]);
933 if (isc
->cpu_cx_count
> cpu_cx_count
)
934 cpu_cx_count
= isc
->cpu_cx_count
;
940 acpi_cpu_quirks(void)
945 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__
);
948 * Bus mastering arbitration control is needed to keep caches coherent
949 * while sleeping in C3. If it's not present but a working flush cache
950 * instruction is present, flush the caches before entering C3 instead.
951 * Otherwise, just disable C3 completely.
953 if (AcpiGbl_FADT
.Pm2ControlBlock
== 0 ||
954 AcpiGbl_FADT
.Pm2ControlLength
== 0) {
955 if ((AcpiGbl_FADT
.Flags
& ACPI_FADT_WBINVD
) &&
956 (AcpiGbl_FADT
.Flags
& ACPI_FADT_WBINVD_FLUSH
) == 0) {
957 cpu_quirks
|= CPU_QUIRK_NO_BM_CTRL
;
958 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
959 "acpi_cpu: no BM control, using flush cache method\n"));
961 cpu_quirks
|= CPU_QUIRK_NO_C3
;
962 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
963 "acpi_cpu: no BM control, C3 not available\n"));
968 * If we are using generic Cx mode, C3 on multiple CPUs requires using
969 * the expensive flush cache instruction.
971 if (cpu_cx_generic
&& ncpus
> 1) {
972 cpu_quirks
|= CPU_QUIRK_NO_BM_CTRL
;
973 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
974 "acpi_cpu: SMP, using flush cache mode for C3\n"));
977 /* Look for various quirks of the PIIX4 part. */
978 acpi_dev
= pci_find_device(PCI_VENDOR_INTEL
, PCI_DEVICE_82371AB_3
);
979 if (acpi_dev
!= NULL
) {
980 switch (pci_get_revid(acpi_dev
)) {
982 * Disable C3 support for all PIIX4 chipsets. Some of these parts
983 * do not report the BMIDE status to the BM status register and
984 * others have a livelock bug if Type-F DMA is enabled. Linux
985 * works around the BMIDE bug by reading the BM status directly
986 * but we take the simpler approach of disabling C3 for these
989 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
990 * Livelock") from the January 2002 PIIX4 specification update.
991 * Applies to all PIIX4 models.
993 * Also, make sure that all interrupts cause a "Stop Break"
994 * event to exit from C2 state.
995 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
996 * should be set to zero, otherwise it causes C2 to short-sleep.
997 * PIIX4 doesn't properly support C3 and bus master activity
998 * need not break out of C2.
1000 case PCI_REVISION_A_STEP
:
1001 case PCI_REVISION_B_STEP
:
1002 case PCI_REVISION_4E
:
1003 case PCI_REVISION_4M
:
1004 cpu_quirks
|= CPU_QUIRK_NO_C3
;
1005 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1006 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1008 val
= pci_read_config(acpi_dev
, PIIX4_DEVACTB_REG
, 4);
1009 if ((val
& PIIX4_STOP_BREAK_MASK
) != PIIX4_STOP_BREAK_MASK
) {
1010 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1011 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1012 val
|= PIIX4_STOP_BREAK_MASK
;
1013 pci_write_config(acpi_dev
, PIIX4_DEVACTB_REG
, val
, 4);
1015 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD
, &val
);
1017 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1018 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1019 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD
, 0);
1031 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS
)
1033 struct acpi_cpu_softc
*sc
;
1037 uintmax_t fract
, sum
, whole
;
1039 sc
= (struct acpi_cpu_softc
*) arg1
;
1041 for (i
= 0; i
< sc
->cpu_cx_count
; i
++)
1042 sum
+= sc
->cpu_cx_stats
[i
];
1043 sbuf_new(&sb
, buf
, sizeof(buf
), SBUF_FIXEDLEN
);
1044 for (i
= 0; i
< sc
->cpu_cx_count
; i
++) {
1046 whole
= (uintmax_t)sc
->cpu_cx_stats
[i
] * 100;
1047 fract
= (whole
% sum
) * 100;
1048 sbuf_printf(&sb
, "%u.%02u%% ", (u_int
)(whole
/ sum
),
1049 (u_int
)(fract
/ sum
));
1051 sbuf_printf(&sb
, "0.00%% ");
1053 sbuf_printf(&sb
, "last %dus", sc
->cpu_prev_sleep
);
1056 sysctl_handle_string(oidp
, sbuf_data(&sb
), sbuf_len(&sb
), req
);
1063 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc
*sc
, int val
)
1065 int i
, old_lowest
, error
= 0;
1066 uint32_t old_type
, type
;
1070 old_lowest
= atomic_swap_int(&sc
->cpu_cx_lowest
, val
);
1072 old_type
= sc
->cpu_cx_states
[old_lowest
].type
;
1073 type
= sc
->cpu_cx_states
[val
].type
;
1074 if (old_type
== ACPI_STATE_C3
&& type
!= ACPI_STATE_C3
) {
1075 KKASSERT(cpu_c3_ncpus
> 0);
1076 if (atomic_fetchadd_int(&cpu_c3_ncpus
, -1) == 1) {
1078 * All of the CPUs exit C3 state, use a better
1081 error
= cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE
);
1083 cputimer_intr_restart();
1085 } else if (type
== ACPI_STATE_C3
&& old_type
!= ACPI_STATE_C3
) {
1086 if (atomic_fetchadd_int(&cpu_c3_ncpus
, 1) == 0) {
1088 * When the first CPU enters C3 state, switch
1089 * to an one shot timer, which could handle
1090 * C3 state, i.e. the timer will not hang.
1092 error
= cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS
);
1094 cputimer_intr_restart();
1096 kprintf("no suitable intr cuptimer found\n");
1099 sc
->cpu_cx_lowest
= old_lowest
;
1100 atomic_fetchadd_int(&cpu_c3_ncpus
, -1);
1110 /* If not disabling, cache the new lowest non-C3 state. */
1112 for (i
= sc
->cpu_cx_lowest
; i
>= 0; i
--) {
1113 if (sc
->cpu_cx_states
[i
].type
< ACPI_STATE_C3
) {
1119 /* Reset the statistics counters. */
1120 bzero(sc
->cpu_cx_stats
, sizeof(sc
->cpu_cx_stats
));
1125 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS
)
1127 struct acpi_cpu_softc
*sc
;
1131 sc
= (struct acpi_cpu_softc
*) arg1
;
1132 ksnprintf(state
, sizeof(state
), "C%d", sc
->cpu_cx_lowest
+ 1);
1133 error
= sysctl_handle_string(oidp
, state
, sizeof(state
), req
);
1134 if (error
!= 0 || req
->newptr
== NULL
)
1136 if (strlen(state
) < 2 || toupper(state
[0]) != 'C')
1138 val
= (int) strtol(state
+ 1, NULL
, 10) - 1;
1139 if (val
< 0 || val
> sc
->cpu_cx_count
- 1)
1143 error
= acpi_cpu_set_cx_lowest(sc
, val
);
1150 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS
)
1152 struct acpi_cpu_softc
*sc
;
1156 ksnprintf(state
, sizeof(state
), "C%d", cpu_cx_lowest
+ 1);
1157 error
= sysctl_handle_string(oidp
, state
, sizeof(state
), req
);
1158 if (error
!= 0 || req
->newptr
== NULL
)
1160 if (strlen(state
) < 2 || toupper(state
[0]) != 'C')
1162 val
= (int) strtol(state
+ 1, NULL
, 10) - 1;
1163 if (val
< 0 || val
> cpu_cx_count
- 1)
1165 cpu_cx_lowest
= val
;
1167 /* Update the new lowest useable Cx state for all CPUs. */
1169 for (i
= 0; i
< cpu_ndevices
; i
++) {
1170 sc
= device_get_softc(cpu_devices
[i
]);
1171 error
= acpi_cpu_set_cx_lowest(sc
, val
);
1183 * Put the CPU in C1 in a machine-dependant way.
1184 * XXX: shouldn't be here!
1190 ia64_call_pal_static(PAL_HALT_LIGHT
, 0, 0, 0);
1194 if (!lwkt_runnable())
1195 __asm
__volatile("sti; hlt");
1197 __asm
__volatile("sti; pause");
1199 if (!lwkt_runnable())
1200 __asm
__volatile("sti; hlt");
1202 __asm
__volatile("sti");
1204 #endif /* !__ia64__ */