Sync ACPICA with Intel's version 20180508 (from previously 20170831).
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_ipl.s
blob334327acf2fb1eaefe85dbc5bb5b116e7ba033d3
1 /*
2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
34 * Copyright (c) 1997, by Steve Passe, All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. The name of the developer may NOT be used to endorse or promote products
42 * derived from this software without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
56 * $FreeBSD: src/sys/i386/isa/apic_ipl.s,v 1.27.2.2 2000/09/30 02:49:35 ps Exp $
59 #include <machine/asmacros.h>
60 #include <machine/segments.h>
61 #include <machine/lock.h>
62 #include <machine/psl.h>
63 #include <machine/trap.h>
65 #include "apicreg.h"
66 #include <machine_base/apic/ioapic_ipl.h>
67 #include "assym.s"
69 .text
70 SUPERALIGN_TEXT
73 * Functions to enable and disable a hardware interrupt. The
74 * IRQ number is passed as an argument.
76 ENTRY(IOAPIC_INTRDIS)
77 IOAPIC_IMASK_LOCK /* enter critical reg */
78 movl %edi, %eax
80 shll $IOAPIC_IRQI_SZSHIFT, %eax
81 orl $IOAPIC_IRQI_FLAG_MASKED, CNAME(ioapic_irqs) + IOAPIC_IRQI_FLAGS(%rax)
82 movq CNAME(ioapic_irqs) + IOAPIC_IRQI_ADDR(%rax), %rdx
83 movl CNAME(ioapic_irqs) + IOAPIC_IRQI_IDX(%rax), %ecx
84 testq %rdx, %rdx
85 jz 2f
86 movl %ecx, (%rdx) /* target register index */
87 orl $IOART_INTMASK, IOAPIC_WINDOW(%rdx)
88 /* set intmask in target ioapic reg */
90 IOAPIC_IMASK_UNLOCK /* exit critical reg */
91 ret
93 ENTRY(IOAPIC_INTREN)
94 IOAPIC_IMASK_LOCK /* enter critical reg */
95 movl %edi, %eax
97 shll $IOAPIC_IRQI_SZSHIFT, %eax
98 andl $~IOAPIC_IRQI_FLAG_MASKED, CNAME(ioapic_irqs) + IOAPIC_IRQI_FLAGS(%rax)
99 movq CNAME(ioapic_irqs) + IOAPIC_IRQI_ADDR(%rax), %rdx
100 movl CNAME(ioapic_irqs) + IOAPIC_IRQI_IDX(%rax), %ecx
101 testq %rdx, %rdx
102 jz 2f
103 movl %ecx, (%rdx) /* write the target register index */
104 andl $~IOART_INTMASK, IOAPIC_WINDOW(%rdx)
105 /* clear mask bit */
107 IOAPIC_IMASK_UNLOCK /* exit critical reg */
110 /******************************************************************************
115 * u_int ioapic_read(volatile void *ioapic, int select);
117 ENTRY(ioapic_read)
118 movl %esi, (%rdi) /* write the target register index */
119 movl IOAPIC_WINDOW(%rdi), %eax /* read the IOAPIC register data */
120 ret /* %eax = register value */
123 * void ioapic_write(volatile void *ioapic, int select, u_int value);
125 ENTRY(ioapic_write)
126 movl %esi, (%rdi) /* write the target register index */
127 movl %edx, IOAPIC_WINDOW(%rdi) /* write the IOAPIC register data */
128 ret /* %eax = void */