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Sync ACPICA with Intel's version 20180508 (from previously 20170831).
[dragonfly.git] / sys / contrib / dev / acpica / source / common / dmtbinfo2.c
blob1efd3fd92a678b0e6a0efbd8d2748607a03c7d53
1 /******************************************************************************
2 *
3 * Module Name: dmtbinfo2 - Table info for non-AML tables
4 *
5 *****************************************************************************/
6
7 /******************************************************************************
8 *
9 * 1. Copyright Notice
10 *
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
12 * All rights reserved.
13 *
14 * 2. License
15 *
16 * 2.1. This is your license from Intel Corp. under its intellectual property
17 * rights. You may have additional license terms from the party that provided
18 * you this software, covering your right to use that party's intellectual
19 * property rights.
20 *
21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
22 * copy of the source code appearing in this file ("Covered Code") an
23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
24 * base code distributed originally by Intel ("Original Intel Code") to copy,
25 * make derivatives, distribute, use and display any portion of the Covered
26 * Code in any form, with the right to sublicense such rights; and
27 *
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
29 * license (with the right to sublicense), under only those claims of Intel
30 * patents that are infringed by the Original Intel Code, to make, use, sell,
31 * offer to sell, and import the Covered Code and derivative works thereof
32 * solely to the minimum extent necessary to exercise the above copyright
33 * license, and in no event shall the patent license extend to any additions
34 * to or modifications of the Original Intel Code. No other license or right
35 * is granted directly or by implication, estoppel or otherwise;
36 *
37 * The above copyright and patent license is granted only if the following
38 * conditions are met:
39 *
40 * 3. Conditions
41 *
42 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
43 * Redistribution of source code of any substantial portion of the Covered
44 * Code or modification with rights to further distribute source must include
45 * the above Copyright Notice, the above License, this list of Conditions,
46 * and the following Disclaimer and Export Compliance provision. In addition,
47 * Licensee must cause all Covered Code to which Licensee contributes to
48 * contain a file documenting the changes Licensee made to create that Covered
49 * Code and the date of any change. Licensee must include in that file the
50 * documentation of any changes made by any predecessor Licensee. Licensee
51 * must include a prominent statement that the modification is derived,
52 * directly or indirectly, from Original Intel Code.
53 *
54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
55 * Redistribution of source code of any substantial portion of the Covered
56 * Code or modification without rights to further distribute source must
57 * include the following Disclaimer and Export Compliance provision in the
58 * documentation and/or other materials provided with distribution. In
59 * addition, Licensee may not authorize further sublicense of source of any
60 * portion of the Covered Code, and must include terms to the effect that the
61 * license from Licensee to its licensee is limited to the intellectual
62 * property embodied in the software Licensee provides to its licensee, and
63 * not to intellectual property embodied in modifications its licensee may
64 * make.
65 *
66 * 3.3. Redistribution of Executable. Redistribution in executable form of any
67 * substantial portion of the Covered Code or modification must reproduce the
68 * above Copyright Notice, and the following Disclaimer and Export Compliance
69 * provision in the documentation and/or other materials provided with the
70 * distribution.
71 *
72 * 3.4. Intel retains all right, title, and interest in and to the Original
73 * Intel Code.
74 *
75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
76 * Intel shall be used in advertising or otherwise to promote the sale, use or
77 * other dealings in products derived from or relating to the Covered Code
78 * without prior written authorization from Intel.
79 *
80 * 4. Disclaimer and Export Compliance
81 *
82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
88 * PARTICULAR PURPOSE.
89 *
90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
97 * LIMITED REMEDY.
98 *
99 * 4.3. Licensee shall not export, either directly or indirectly, any of this
100 * software or system incorporating such software without first obtaining any
101 * required license or other approval from the U. S. Department of Commerce or
102 * any other agency or department of the United States Government. In the
103 * event Licensee exports any such software from the United States or
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
106 * compliance with all laws, regulations, orders, or other restrictions of the
107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
108 * any of its subsidiaries will export/re-export any technical data, process,
109 * software, or service, directly or indirectly, to any country for which the
110 * United States government or any agency thereof requires an export license,
111 * other governmental approval, or letter of assurance, without first obtaining
112 * such license, approval or letter.
113 *
114 *****************************************************************************
115 *
116 * Alternatively, you may choose to be licensed under the terms of the
117 * following license:
118 *
119 * Redistribution and use in source and binary forms, with or without
120 * modification, are permitted provided that the following conditions
121 * are met:
122 * 1. Redistributions of source code must retain the above copyright
123 * notice, this list of conditions, and the following disclaimer,
124 * without modification.
125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
126 * substantially similar to the "NO WARRANTY" disclaimer below
127 * ("Disclaimer") and any redistribution must be conditioned upon
128 * including a substantially similar Disclaimer requirement for further
129 * binary redistribution.
130 * 3. Neither the names of the above-listed copyright holders nor the names
131 * of any contributors may be used to endorse or promote products derived
132 * from this software without specific prior written permission.
133 *
134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
145 *
146 * Alternatively, you may choose to be licensed under the terms of the
147 * GNU General Public License ("GPL") version 2 as published by the Free
148 * Software Foundation.
149 *
150 *****************************************************************************/
151
152 #include "acpi.h"
153 #include "accommon.h"
154 #include "acdisasm.h"
155 #include "actbinfo.h"
156
157 /* This module used for application-level code only */
158
159 #define _COMPONENT ACPI_CA_DISASSEMBLER
160 ACPI_MODULE_NAME ("dmtbinfo2")
161
162 /*
163 * How to add a new table:
164 *
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
167 * - Define the table in this file (for the disassembler). If any
168 * new data types are required (ACPI_DMT_*), see below.
169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*)
170 * in acdisam.h
171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData)
172 * If a simple table (with no subtables), no disassembly code is needed.
173 * Otherwise, create the AcpiDmDump* function for to disassemble the table
174 * and add it to the dmtbdump.c file.
175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h
176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c
177 * - Create a template for the new table
178 * - Add data table compiler support
179 *
180 * How to add a new data type (ACPI_DMT_*):
181 *
182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h
183 * - Add length and implementation cases in dmtable.c (disassembler)
184 * - Add type and length cases in dtutils.c (DT compiler)
185 */
186
187 /*
188 * Remaining tables are not consumed directly by the ACPICA subsystem
189 */
190
191
192 /*******************************************************************************
193 *
194 * IORT - IO Remapping Table
195 *
196 ******************************************************************************/
197
198 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] =
199 {
200 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0},
201 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0},
202 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0},
203 ACPI_DMT_TERMINATOR
204 };
205
206 /* Optional padding field */
207
208 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] =
209 {
210 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL},
211 ACPI_DMT_TERMINATOR
212 };
213
214 /* Common Subtable header (one per Subtable) */
215
216 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] =
217 {
218 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0},
219 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH},
220 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0},
221 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Reserved), "Reserved", 0},
222 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0},
223 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0},
224 ACPI_DMT_TERMINATOR
225 };
226
227 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] =
228 {
229 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL},
230 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0},
231 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0},
232 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0},
233 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0},
234 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0},
235 ACPI_DMT_TERMINATOR
236 };
237
238 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] =
239 {
240 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0},
241 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0},
242 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0},
243 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0},
244 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0},
245 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0},
246 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0},
247 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0},
248 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0},
249 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0},
250 ACPI_DMT_TERMINATOR
251 };
252
253 /* IORT subtables */
254
255 /* 0x00: ITS Group */
256
257 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] =
258 {
259 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0},
260 ACPI_DMT_TERMINATOR
261 };
262
263 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] =
264 {
265 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL},
266 ACPI_DMT_TERMINATOR
267 };
268
269 /* 0x01: Named Component */
270
271 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] =
272 {
273 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0},
274 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0},
275 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0},
276 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0},
277 ACPI_DMT_TERMINATOR
278 };
279
280 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] =
281 {
282 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL},
283 ACPI_DMT_TERMINATOR
284 };
285
286 /* 0x02: PCI Root Complex */
287
288 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] =
289 {
290 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0},
291 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0},
292 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0},
293 ACPI_DMT_TERMINATOR
294 };
295
296 /* 0x03: SMMUv1/2 */
297
298 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] =
299 {
300 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0},
301 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0},
302 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0},
303 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0},
304 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0},
305 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0},
306 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0},
307 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0},
308 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0},
309 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0},
310 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0},
311 ACPI_DMT_TERMINATOR
312 };
313
314 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] =
315 {
316 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0},
317 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0},
318 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0},
319 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0},
320 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0},
321 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0},
322 ACPI_DMT_TERMINATOR
323 };
324
325 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] =
326 {
327 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL},
328 ACPI_DMT_TERMINATOR
329 };
330
331 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] =
332 {
333 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL},
334 ACPI_DMT_TERMINATOR
335 };
336
337 /* 0x04: SMMUv3 */
338
339 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] =
340 {
341 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0},
342 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0},
343 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0},
344 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0},
345 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0},
346 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0},
347 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0},
348 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0},
349 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0},
350 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0},
351 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0},
352 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0},
353 {ACPI_DMT_UINT8, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0},
354 {ACPI_DMT_UINT8, ACPI_IORT4_OFFSET (Reserved1), "Reserved", 0},
355 {ACPI_DMT_UINT16, ACPI_IORT4_OFFSET (Reserved2), "Reserved", 0},
356 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0},
357 ACPI_DMT_TERMINATOR
358 };
359
360
361 /*******************************************************************************
362 *
363 * IVRS - I/O Virtualization Reporting Structure
364 *
365 ******************************************************************************/
366
367 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] =
368 {
369 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0},
370 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0},
371 ACPI_DMT_TERMINATOR
372 };
373
374 /* Common Subtable header (one per Subtable) */
375
376 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHdr[] =
377 {
378 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0},
379 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags", 0},
380 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH},
381 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0},
382 ACPI_DMT_TERMINATOR
383 };
384
385 /* IVRS subtables */
386
387 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */
388
389 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs0[] =
390 {
391 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0},
392 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0},
393 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0},
394 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0},
395 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (Reserved), "Reserved", 0},
396 ACPI_DMT_TERMINATOR
397 };
398
399 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Block */
400
401 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs1[] =
402 {
403 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0},
404 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0},
405 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0},
406 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0},
407 ACPI_DMT_TERMINATOR
408 };
409
410 /* Device entry header for IVHD block */
411
412 #define ACPI_DMT_IVRS_DE_HEADER \
413 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (Type), "Entry Type", 0}, \
414 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \
415 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting", 0}
416
417 /* 4-byte device entry */
418
419 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] =
420 {
421 ACPI_DMT_IVRS_DE_HEADER,
422 {ACPI_DMT_EXIT, 0, NULL, 0},
423 };
424
425 /* 8-byte device entry */
426
427 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] =
428 {
429 ACPI_DMT_IVRS_DE_HEADER,
430 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0},
431 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0},
432 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0},
433 ACPI_DMT_TERMINATOR
434 };
435
436 /* 8-byte device entry */
437
438 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] =
439 {
440 ACPI_DMT_IVRS_DE_HEADER,
441 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0},
442 ACPI_DMT_TERMINATOR
443 };
444
445 /* 8-byte device entry */
446
447 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] =
448 {
449 ACPI_DMT_IVRS_DE_HEADER,
450 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0},
451 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0},
452 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0},
453 ACPI_DMT_TERMINATOR
454 };
455
456
457 /*******************************************************************************
458 *
459 * LPIT - Low Power Idle Table
460 *
461 ******************************************************************************/
462
463 /* Main table consists only of the standard ACPI table header */
464
465 /* Common Subtable header (one per Subtable) */
466
467 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] =
468 {
469 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0},
470 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH},
471 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0},
472 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0},
473 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
474 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0},
475 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0},
476 ACPI_DMT_TERMINATOR
477 };
478
479 /* LPIT Subtables */
480
481 /* 0: Native C-state */
482
483 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] =
484 {
485 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0},
486 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0},
487 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0},
488 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0},
489 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0},
490 ACPI_DMT_TERMINATOR
491 };
492
493
494 /*******************************************************************************
495 *
496 * MADT - Multiple APIC Description Table and subtables
497 *
498 ******************************************************************************/
499
500 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] =
501 {
502 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0},
503 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
504 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0},
505 ACPI_DMT_TERMINATOR
506 };
507
508 /* Common Subtable header (one per Subtable) */
509
510 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] =
511 {
512 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0},
513 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH},
514 ACPI_DMT_TERMINATOR
515 };
516
517 /* MADT Subtables */
518
519 /* 0: processor APIC */
520
521 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] =
522 {
523 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0},
524 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0},
525 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
526 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
527 ACPI_DMT_TERMINATOR
528 };
529
530 /* 1: IO APIC */
531
532 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] =
533 {
534 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0},
535 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0},
536 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0},
537 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0},
538 ACPI_DMT_TERMINATOR
539 };
540
541 /* 2: Interrupt Override */
542
543 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] =
544 {
545 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0},
546 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0},
547 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0},
548 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
549 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
550 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
551 ACPI_DMT_TERMINATOR
552 };
553
554 /* 3: NMI Sources */
555
556 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] =
557 {
558 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
559 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
560 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
561 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0},
562 ACPI_DMT_TERMINATOR
563 };
564
565 /* 4: Local APIC NMI */
566
567 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] =
568 {
569 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0},
570 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
571 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
572 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
573 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0},
574 ACPI_DMT_TERMINATOR
575 };
576
577 /* 5: Address Override */
578
579 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] =
580 {
581 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0},
582 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0},
583 ACPI_DMT_TERMINATOR
584 };
585
586 /* 6: I/O Sapic */
587
588 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] =
589 {
590 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0},
591 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0},
592 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
593 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0},
594 ACPI_DMT_TERMINATOR
595 };
596
597 /* 7: Local Sapic */
598
599 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] =
600 {
601 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0},
602 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0},
603 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0},
604 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0},
605 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
606 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
607 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0},
608 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0},
609 ACPI_DMT_TERMINATOR
610 };
611
612 /* 8: Platform Interrupt Source */
613
614 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] =
615 {
616 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
617 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
618 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
619 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0},
620 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0},
621 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0},
622 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0},
623 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0},
624 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
625 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0},
626 ACPI_DMT_TERMINATOR
627 };
628
629 /* 9: Processor Local X2_APIC (ACPI 4.0) */
630
631 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] =
632 {
633 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0},
634 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0},
635 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
636 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
637 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0},
638 ACPI_DMT_TERMINATOR
639 };
640
641 /* 10: Local X2_APIC NMI (ACPI 4.0) */
642
643 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] =
644 {
645 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
646 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
647 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
648 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0},
649 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0},
650 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0},
651 ACPI_DMT_TERMINATOR
652 };
653
654 /* 11: Generic Interrupt Controller (ACPI 5.0) */
655
656 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] =
657 {
658 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0},
659 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0},
660 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0},
661 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
662 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0},
663 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0},
664 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0},
665 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0},
666 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0},
667 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0},
668 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
669 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
670 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
671 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0},
672 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
673 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0},
674 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0},
675 {ACPI_DMT_UINT24, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0},
676 ACPI_DMT_TERMINATOR
677 };
678
679 /* 12: Generic Interrupt Distributor (ACPI 5.0) */
680
681 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] =
682 {
683 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0},
684 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0},
685 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0},
686 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
687 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0},
688 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0},
689 ACPI_DMT_TERMINATOR
690 };
691
692 /* 13: Generic MSI Frame (ACPI 5.1) */
693
694 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] =
695 {
696 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0},
697 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0},
698 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0},
699 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
700 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0},
701 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0},
702 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0},
703 ACPI_DMT_TERMINATOR
704 };
705
706 /* 14: Generic Redistributor (ACPI 5.1) */
707
708 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] =
709 {
710 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0},
711 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0},
712 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0},
713 ACPI_DMT_TERMINATOR
714 };
715
716 /* 15: Generic Translator (ACPI 6.0) */
717
718 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] =
719 {
720 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0},
721 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0},
722 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0},
723 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0},
724 ACPI_DMT_TERMINATOR
725 };
726
727
728 /*******************************************************************************
729 *
730 * MCFG - PCI Memory Mapped Configuration table and Subtable
731 *
732 ******************************************************************************/
733
734 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] =
735 {
736 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0},
737 ACPI_DMT_TERMINATOR
738 };
739
740 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] =
741 {
742 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0},
743 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0},
744 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0},
745 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0},
746 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0},
747 ACPI_DMT_TERMINATOR
748 };
749
750
751 /*******************************************************************************
752 *
753 * MCHI - Management Controller Host Interface table
754 *
755 ******************************************************************************/
756
757 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] =
758 {
759 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0},
760 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0},
761 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0},
762 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0},
763 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0},
764 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0},
765 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0},
766 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0},
767 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0},
768 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0},
769 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0},
770 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0},
771 ACPI_DMT_TERMINATOR
772 };
773
774
775 /*******************************************************************************
776 *
777 * MPST - Memory Power State Table
778 *
779 ******************************************************************************/
780
781 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] =
782 {
783 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0},
784 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0},
785 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0},
786 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0},
787 ACPI_DMT_TERMINATOR
788 };
789
790 /* MPST subtables */
791
792 /* 0: Memory Power Node Structure */
793
794 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] =
795 {
796 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
797 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0},
798 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0},
799 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0},
800
801 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0},
802 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0},
803 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0},
804 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0},
805 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0},
806 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0},
807 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0},
808 ACPI_DMT_TERMINATOR
809 };
810
811 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */
812
813 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] =
814 {
815 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0},
816 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0},
817 ACPI_DMT_TERMINATOR
818 };
819
820 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */
821
822 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] =
823 {
824 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0},
825 ACPI_DMT_TERMINATOR
826 };
827
828 /* 01: Power Characteristics Count (follows all Power Node(s) above) */
829
830 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] =
831 {
832 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0},
833 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0},
834 ACPI_DMT_TERMINATOR
835 };
836
837 /* 02: Memory Power State Characteristics Structure */
838
839 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] =
840 {
841 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0},
842 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
843 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0},
844 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0},
845 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0},
846
847 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0},
848 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0},
849 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0},
850 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0},
851 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0},
852 ACPI_DMT_TERMINATOR
853 };
854
855
856 /*******************************************************************************
857 *
858 * MSCT - Maximum System Characteristics Table (ACPI 4.0)
859 *
860 ******************************************************************************/
861
862 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] =
863 {
864 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0},
865 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0},
866 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0},
867 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0},
868 ACPI_DMT_TERMINATOR
869 };
870
871 /* Subtable - Maximum Proximity Domain Information. Version 1 */
872
873 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] =
874 {
875 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0},
876 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH},
877 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0},
878 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0},
879 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0},
880 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0},
881 ACPI_DMT_TERMINATOR
882 };
883
884
885 /*******************************************************************************
886 *
887 * MTMR - MID Timer Table
888 *
889 ******************************************************************************/
890
891 ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr[] =
892 {
893 ACPI_DMT_TERMINATOR
894 };
895
896 /* MTMR Subtables - MTMR Entry */
897
898 ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr0[] =
899 {
900 {ACPI_DMT_GAS, ACPI_MTMR0_OFFSET (PhysicalAddress), "PhysicalAddress", 0},
901 {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Frequency), "Frequency", 0},
902 {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Irq), "IRQ", 0},
903 ACPI_DMT_TERMINATOR
904 };
905
906
907 /*******************************************************************************
908 *
909 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0)
910 *
911 ******************************************************************************/
912
913 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] =
914 {
915 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0},
916 ACPI_DMT_TERMINATOR
917 };
918
919 /* Common Subtable header */
920
921 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] =
922 {
923 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0},
924 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH},
925 ACPI_DMT_TERMINATOR
926 };
927
928 /* 0: System Physical Address Range Structure */
929
930 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] =
931 {
932 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0},
933 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
934 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0},
935 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0},
936 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0},
937 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0},
938 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Address Range GUID", 0},
939 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0},
940 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0},
941 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0},
942 ACPI_DMT_TERMINATOR
943 };
944
945 /* 1: Memory Device to System Address Range Map Structure */
946
947 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] =
948 {
949 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0},
950 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0},
951 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0},
952 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0},
953 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0},
954 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0},
955 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0},
956 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0},
957 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0},
958 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0},
959 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG},
960 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0},
961 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0},
962 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0},
963 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0},
964 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0},
965 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0},
966 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0},
967 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0},
968 ACPI_DMT_TERMINATOR
969 };
970
971 /* 2: Interleave Structure */
972
973 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] =
974 {
975 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0},
976 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0},
977 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0},
978 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0},
979 ACPI_DMT_TERMINATOR
980 };
981
982 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] =
983 {
984 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL},
985 ACPI_DMT_TERMINATOR
986 };
987
988 /* 3: SMBIOS Management Information Structure */
989
990 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] =
991 {
992 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0},
993 ACPI_DMT_TERMINATOR
994 };
995
996 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] =
997 {
998 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL},
999 ACPI_DMT_TERMINATOR
1000 };
1001
1002 /* 4: NVDIMM Control Region Structure */
1003
1004 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] =
1005 {
1006 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0},
1007 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0},
1008 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0},
1009 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0},
1010 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0},
1011 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0},
1012 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0},
1013 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0},
1014 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0},
1015 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0},
1016 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0},
1017 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0},
1018 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0},
1019 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0},
1020 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0},
1021 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0},
1022 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0},
1023 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0},
1024 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0},
1025 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG},
1026 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0},
1027 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0},
1028 ACPI_DMT_TERMINATOR
1029 };
1030
1031 /* 5: NVDIMM Block Data Window Region Structure */
1032
1033 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] =
1034 {
1035 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0},
1036 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0},
1037 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0},
1038 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0},
1039 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0},
1040 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0},
1041 ACPI_DMT_TERMINATOR
1042 };
1043
1044 /* 6: Flush Hint Address Structure */
1045
1046 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] =
1047 {
1048 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0},
1049 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0},
1050 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0},
1051 ACPI_DMT_TERMINATOR
1052 };
1053
1054 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] =
1055 {
1056 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL},
1057 ACPI_DMT_TERMINATOR
1058 };
1059
1060 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] =
1061 {
1062 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0},
1063 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0},
1064 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG},
1065 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0},
1066 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0},
1067 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0},
1068 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0},
1069 ACPI_DMT_TERMINATOR
1070 };
1071
1072
1073 /*******************************************************************************
1074 *
1075 * PCCT - Platform Communications Channel Table (ACPI 5.0)
1076 *
1077 ******************************************************************************/
1078
1079 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] =
1080 {
1081 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
1082 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0},
1083 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0},
1084 ACPI_DMT_TERMINATOR
1085 };
1086
1087 /* PCCT subtables */
1088
1089 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] =
1090 {
1091 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0},
1092 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH},
1093 ACPI_DMT_TERMINATOR
1094 };
1095
1096 /* 0: Generic Communications Subspace */
1097
1098 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] =
1099 {
1100 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0},
1101 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0},
1102 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0},
1103 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0},
1104 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0},
1105 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0},
1106 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0},
1107 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0},
1108 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0},
1109 ACPI_DMT_TERMINATOR
1110 };
1111
1112 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */
1113
1114 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] =
1115 {
1116 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0},
1117 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG},
1118 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0},
1119 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0},
1120 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0},
1121 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0},
1122 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0},
1123 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0},
1124 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0},
1125 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0},
1126 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0},
1127 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0},
1128 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0},
1129 ACPI_DMT_TERMINATOR
1130 };
1131
1132 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */
1133
1134 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] =
1135 {
1136 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0},
1137 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG},
1138 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0},
1139 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0},
1140 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0},
1141 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0},
1142 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0},
1143 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0},
1144 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0},
1145 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0},
1146 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0},
1147 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0},
1148 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0},
1149 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0},
1150 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0},
1151 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0},
1152 ACPI_DMT_TERMINATOR
1153 };
1154
1155 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */
1156
1157 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] =
1158 {
1159 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0},
1160 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG},
1161 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0},
1162 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0},
1163 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0},
1164 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0},
1165 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0},
1166 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0},
1167 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0},
1168 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0},
1169 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0},
1170 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0},
1171 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0},
1172 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0},
1173 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0},
1174 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0},
1175 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0},
1176 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0},
1177 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0},
1178 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0},
1179 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0},
1180 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0},
1181 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0},
1182 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0},
1183 ACPI_DMT_TERMINATOR
1184 };
1185
1186 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */
1187
1188 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] =
1189 {
1190 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0},
1191 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG},
1192 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0},
1193 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0},
1194 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0},
1195 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0},
1196 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0},
1197 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0},
1198 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0},
1199 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0},
1200 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0},
1201 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0},
1202 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0},
1203 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0},
1204 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0},
1205 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0},
1206 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0},
1207 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0},
1208 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0},
1209 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0},
1210 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0},
1211 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0},
1212 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0},
1213 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0},
1214 ACPI_DMT_TERMINATOR
1215 };
1216
1217
1218 /*******************************************************************************
1219 *
1220 * PDTT - Platform Debug Trigger Table (ACPI 6.2)
1221 *
1222 ******************************************************************************/
1223
1224 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] =
1225 {
1226 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0},
1227 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0},
1228 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0},
1229 ACPI_DMT_TERMINATOR
1230 };
1231
1232 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] =
1233 {
1234 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0},
1235 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG},
1236 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0},
1237 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0},
1238 ACPI_DMT_TERMINATOR
1239 };
1240
1241
1242 /*******************************************************************************
1243 *
1244 * PMTT - Platform Memory Topology Table
1245 *
1246 ******************************************************************************/
1247
1248 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] =
1249 {
1250 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (Reserved), "Reserved", 0},
1251 ACPI_DMT_TERMINATOR
1252 };
1253
1254 /* Common Subtable header (one per Subtable) */
1255
1256 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttHdr[] =
1257 {
1258 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0},
1259 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0},
1260 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH},
1261 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
1262 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0},
1263 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0},
1264 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0},
1265 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0},
1266 ACPI_DMT_TERMINATOR
1267 };
1268
1269 /* PMTT Subtables */
1270
1271 /* 0: Socket */
1272
1273 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] =
1274 {
1275 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0},
1276 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0},
1277 ACPI_DMT_TERMINATOR
1278 };
1279
1280 /* 1: Memory Controller */
1281
1282 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] =
1283 {
1284 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (ReadLatency), "Read Latency", 0},
1285 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (WriteLatency), "Write Latency", 0},
1286 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (ReadBandwidth), "Read Bandwidth", 0},
1287 {ACPI_DMT_UINT32, ACPI_PMTT1_OFFSET (WriteBandwidth), "Write Bandwidth", 0},
1288 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (AccessWidth), "Access Width", 0},
1289 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Alignment), "Alignment", 0},
1290 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0},
1291 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (DomainCount), "Domain Count", 0},
1292 ACPI_DMT_TERMINATOR
1293 };
1294
1295 /* 1a: Proximity Domain */
1296
1297 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1a[] =
1298 {
1299 {ACPI_DMT_UINT32, ACPI_PMTT1A_OFFSET (ProximityDomain), "Proximity Domain", 0},
1300 ACPI_DMT_TERMINATOR
1301 };
1302
1303 /* 2: Physical Component */
1304
1305 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] =
1306 {
1307 {ACPI_DMT_UINT16, ACPI_PMTT2_OFFSET (ComponentId), "Component ID", 0},
1308 {ACPI_DMT_UINT16, ACPI_PMTT2_OFFSET (Reserved), "Reserved", 0},
1309 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (MemorySize), "Memory Size", 0},
1310 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0},
1311 ACPI_DMT_TERMINATOR
1312 };
1313
1314
1315 /*******************************************************************************
1316 *
1317 * PPTT - Processor Properties Topology Table (ACPI 6.2)
1318 *
1319 ******************************************************************************/
1320
1321 /* Main table consists of only the standard ACPI header - subtables follow */
1322
1323 /* Common Subtable header (one per Subtable) */
1324
1325 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] =
1326 {
1327 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0},
1328 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0},
1329 ACPI_DMT_TERMINATOR
1330 };
1331
1332 /* 0: Processor hierarchy node */
1333
1334 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] =
1335 {
1336 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0},
1337 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0},
1338 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0},
1339 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0},
1340 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0},
1341 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0},
1342 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0},
1343 ACPI_DMT_TERMINATOR
1344 };
1345
1346 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] =
1347 {
1348 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL},
1349 ACPI_DMT_TERMINATOR
1350 };
1351
1352 /* 1: Cache type */
1353
1354 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] =
1355 {
1356 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0},
1357 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0},
1358 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0},
1359 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0},
1360 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0},
1361 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0},
1362 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0},
1363 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0},
1364 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0},
1365 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0},
1366 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0},
1367 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0},
1368 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0},
1369 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0},
1370 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0},
1371 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0},
1372 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0},
1373 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0},
1374 ACPI_DMT_TERMINATOR
1375 };
1376
1377 /* 2: ID */
1378
1379 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] =
1380 {
1381 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0},
1382 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "VENDOR_ID", 0},
1383 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "LEVEL_1_ID", 0},
1384 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "LEVEL_2_ID", 0},
1385 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "MAJOR_REV", 0},
1386 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "MINOR_REV", 0},
1387 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "SPIN_REV", 0},
1388 ACPI_DMT_TERMINATOR
1389 };
1390
1391
1392 /*******************************************************************************
1393 *
1394 * RASF - RAS Feature table
1395 *
1396 ******************************************************************************/
1397
1398 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] =
1399 {
1400 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0},
1401 ACPI_DMT_TERMINATOR
1402 };
1403
1404
1405 /*******************************************************************************
1406 *
1407 * S3PT - S3 Performance Table
1408 *
1409 ******************************************************************************/
1410
1411 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] =
1412 {
1413 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0},
1414 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH},
1415 ACPI_DMT_TERMINATOR
1416 };
1417
1418 /* S3PT subtable header */
1419
1420 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] =
1421 {
1422 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0},
1423 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH},
1424 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0},
1425 ACPI_DMT_TERMINATOR
1426 };
1427
1428 /* 0: Basic S3 Resume Performance Record */
1429
1430 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] =
1431 {
1432 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0},
1433 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0},
1434 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0},
1435 ACPI_DMT_TERMINATOR
1436 };
1437
1438 /* 1: Basic S3 Suspend Performance Record */
1439
1440 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] =
1441 {
1442 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0},
1443 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0},
1444 ACPI_DMT_TERMINATOR
1445 };
1446
1447
1448 /*******************************************************************************
1449 *
1450 * SBST - Smart Battery Specification Table
1451 *
1452 ******************************************************************************/
1453
1454 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] =
1455 {
1456 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0},
1457 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0},
1458 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0},
1459 ACPI_DMT_TERMINATOR
1460 };
1461
1462
1463 /*******************************************************************************
1464 *
1465 * SDEI - Software Delegated Execption Interface Descriptor Table
1466 *
1467 ******************************************************************************/
1468
1469 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] =
1470 {
1471 ACPI_DMT_TERMINATOR
1472 };
1473
1474
1475 /*******************************************************************************
1476 *
1477 * SDEV - Secure Devices Table (ACPI 6.2)
1478 *
1479 ******************************************************************************/
1480
1481 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] =
1482 {
1483 ACPI_DMT_TERMINATOR
1484 };
1485
1486 /* Common Subtable header (one per Subtable) */
1487
1488 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] =
1489 {
1490 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0},
1491 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0},
1492 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0},
1493 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", 0},
1494 ACPI_DMT_TERMINATOR
1495 };
1496
1497 /* SDEV Subtables */
1498
1499 /* 0: Namespace Device Based Secure Device Structure */
1500
1501 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] =
1502 {
1503 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0},
1504 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0},
1505 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0},
1506 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0},
1507 ACPI_DMT_TERMINATOR
1508 };
1509
1510 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] =
1511 {
1512 {ACPI_DMT_STRING, 0, "Namepath", 0},
1513 ACPI_DMT_TERMINATOR
1514 };
1515
1516 /* 1: PCIe Endpoint Device Based Device Structure */
1517
1518 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] =
1519 {
1520 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0},
1521 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0},
1522 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0},
1523 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0},
1524 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0},
1525 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0},
1526 ACPI_DMT_TERMINATOR
1527 };
1528
1529 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] =
1530 {
1531 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0},
1532 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0},
1533 ACPI_DMT_TERMINATOR
1534 };
1535
1536 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] =
1537 {
1538 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */
1539 ACPI_DMT_TERMINATOR
1540 };
1541 /*! [End] no source code translation !*/
DragonFly BSD