sys/dev/netif/an/if_anreg.h

   1 /*
   2  * Copyright (c) 1997, 1998, 1999
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.1.2.8 2003/02/11 03:32:48 ambrisko Exp $
  33  * $DragonFly: src/sys/dev/netif/an/if_anreg.h,v 1.9 2008/05/23 15:34:03 sephe Exp $
  34  */
  35
  36 #define AN_TIMEOUT      65536
  37
  38 /* Default network name: <empty string> */
  39 #define AN_DEFAULT_NETNAME      ""
  40
  41 /* The nodename must be less than 16 bytes */
  42 #define AN_DEFAULT_NODENAME     "FreeBSD"
  43
  44 #define AN_DEFAULT_IBSS         "FreeBSD IBSS"
  45
  46 /*
  47  * register space access macros
  48  */
  49 #define CSR_WRITE_2(sc, reg, val)       \
  50         bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
  51
  52 #define CSR_READ_2(sc, reg)             \
  53         bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
  54
  55 #define CSR_WRITE_1(sc, reg, val)       \
  56         bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
  57
  58 #define CSR_READ_1(sc, reg)             \
  59         bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
  60
  61 /*
  62  * memory space access macros
  63  */
  64 #define CSR_MEM_WRITE_2(sc, reg, val)   \
  65         bus_space_write_2(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
  66
  67 #define CSR_MEM_READ_2(sc, reg)         \
  68         bus_space_read_2(sc->an_mem_btag, sc->an_mem_bhandle, reg)
  69
  70 #define CSR_MEM_WRITE_1(sc, reg, val)   \
  71         bus_space_write_1(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
  72
  73 #define CSR_MEM_READ_1(sc, reg)         \
  74         bus_space_read_1(sc->an_mem_btag, sc->an_mem_bhandle, reg)
  75
  76 /*
  77  * aux. memory space access macros
  78  */
  79 #define CSR_MEM_AUX_WRITE_4(sc, reg, val)       \
  80         bus_space_write_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
  81
  82 #define CSR_MEM_AUX_READ_4(sc, reg)             \
  83         bus_space_read_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
  84
  85 #define CSR_MEM_AUX_WRITE_1(sc, reg, val)       \
  86         bus_space_write_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
  87
  88 #define CSR_MEM_AUX_READ_1(sc, reg)             \
  89         bus_space_read_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
  90
  91 /*
  92  * Size of Aironet I/O space.
  93  */
  94 #define AN_IOSIZ                0x40
  95
  96 /*
  97  * Size of aux. memory space ... probably not needed DJA
  98  */
  99 #define AN_AUXMEMSIZE           (256 * 1024)
 100
 101 /*
 102  * Hermes register definitions and what little I know about them.
 103  */
 104
 105 /* Hermes command/status registers. */
 106 #define AN_COMMAND(x)           (x ? 0x00 : 0x00)
 107 #define AN_PARAM0(x)            (x ? 0x04 : 0x02)
 108 #define AN_PARAM1(x)            (x ? 0x08 : 0x04)
 109 #define AN_PARAM2(x)            (x ? 0x0c : 0x06)
 110 #define AN_STATUS(x)            (x ? 0x10 : 0x08)
 111 #define AN_RESP0(x)             (x ? 0x14 : 0x0A)
 112 #define AN_RESP1(x)             (x ? 0x18 : 0x0C)
 113 #define AN_RESP2(x)             (x ? 0x1c : 0x0E)
 114 #define AN_LINKSTAT(x)          (x ? 0x20 : 0x10)
 115
 116 /* Command register */
 117 #define AN_CMD_BUSY             0x8000 /* busy bit */
 118 #define AN_CMD_NO_ACK           0x0080 /* don't acknowledge command */
 119 #define AN_CMD_CODE_MASK        0x003F
 120 #define AN_CMD_QUAL_MASK        0x7F00
 121
 122 /* Command codes */
 123 #define AN_CMD_NOOP             0x0000 /* no-op */
 124 #define AN_CMD_ENABLE           0x0001 /* enable */
 125 #define AN_CMD_DISABLE          0x0002 /* disable */
 126 #define AN_CMD_FORCE_SYNCLOSS   0x0003 /* force loss of sync */
 127 #define AN_CMD_FW_RESTART       0x0004 /* firmware resrart */
 128 #define AN_CMD_HOST_SLEEP       0x0005
 129 #define AN_CMD_MAGIC_PKT        0x0006
 130 #define AN_CMD_READCFG          0x0008
 131 #define AN_CMD_SET_MODE         0x0009
 132 #define AN_CMD_ALLOC_MEM        0x000A /* allocate NIC memory */
 133 #define AN_CMD_TX               0x000B /* transmit */
 134 #define AN_CMD_DEALLOC_MEM      0x000C
 135 #define AN_CMD_NOOP2            0x0010
 136 #define AN_CMD_ALLOC_DESC       0x0020
 137 #define AN_CMD_ACCESS           0x0021
 138 #define AN_CMD_ALLOC_BUF        0x0028
 139 #define AN_CMD_PSP_NODES        0x0030
 140 #define AN_CMD_SET_PHYREG       0x003E
 141 #define AN_CMD_TX_TEST          0x003F
 142 #define AN_CMD_SLEEP            0x0085
 143 #define AN_CMD_SAVECFG          0x0108
 144
 145 /*
 146  * MPI 350 DMA descriptor information
 147  */
 148 #define AN_DESCRIPTOR_TX        0x01
 149 #define AN_DESCRIPTOR_RX        0x02
 150 #define AN_DESCRIPTOR_TXCMP     0x04
 151 #define AN_DESCRIPTOR_HOSTWRITE 0x08
 152 #define AN_DESCRIPTOR_HOSTREAD  0x10
 153 #define AN_DESCRIPTOR_HOSTRW    0x20
 154
 155 #define AN_MAX_RX_DESC 1
 156 #define AN_MAX_TX_DESC 1
 157 #define AN_HOSTBUFSIZ 1840
 158
 159 struct an_card_rid_desc
 160 {
 161         unsigned        an_rid:16;
 162         unsigned        an_len:15;
 163         unsigned        an_valid:1;
 164         u_int64_t       an_phys;
 165 };
 166
 167 struct an_card_rx_desc
 168 {
 169         unsigned        an_ctrl:15;
 170         unsigned        an_done:1;
 171         unsigned        an_len:15;
 172         unsigned        an_valid:1;
 173         u_int64_t       an_phys;
 174 };
 175
 176 struct an_card_tx_desc
 177 {
 178         unsigned        an_offset:15;
 179         unsigned        an_eoc:1;
 180         unsigned        an_len:15;
 181         unsigned        an_valid:1;
 182         u_int64_t       an_phys;
 183 };
 184
 185 #define AN_RID_BUFFER_SIZE      AN_MAX_DATALEN
 186 #define AN_RX_BUFFER_SIZE       AN_HOSTBUFSIZ
 187 #define AN_TX_BUFFER_SIZE       AN_HOSTBUFSIZ
 188 /*#define AN_HOST_DESC_OFFSET   0xC sort of works */
 189 #define AN_HOST_DESC_OFFSET     0x800
 190 #define AN_RX_DESC_OFFSET  (AN_HOST_DESC_OFFSET + \
 191     sizeof(struct an_card_rid_desc))
 192 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
 193     (AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
 194
 195 struct an_command {
 196         u_int16_t       an_cmd;
 197         u_int16_t       an_parm0;
 198         u_int16_t       an_parm1;
 199         u_int16_t       an_parm2;
 200 };
 201
 202 struct an_reply {
 203         u_int16_t       an_status;
 204         u_int16_t       an_resp0;
 205         u_int16_t       an_resp1;
 206         u_int16_t       an_resp2;
 207 };
 208
 209 /*
 210  * Reclaim qualifier bit, applicable to the
 211  * TX command.
 212  */
 213 #define AN_RECLAIM              0x0100 /* reclaim NIC memory */
 214
 215 /*
 216  * ACCESS command qualifier bits.
 217  */
 218 #define AN_ACCESS_READ          0x0000
 219 #define AN_ACCESS_WRITE         0x0100
 220
 221 /*
 222  * PROGRAM command qualifier bits.
 223  */
 224 #define AN_PROGRAM_DISABLE      0x0000
 225 #define AN_PROGRAM_ENABLE_RAM   0x0100
 226 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
 227 #define AN_PROGRAM_NVRAM        0x0300
 228
 229 /* Status register values */
 230 #define AN_STAT_CMD_CODE        0x003F
 231 #define AN_STAT_CMD_RESULT      0x7F00
 232
 233 /* Linkstat register */
 234 #define AN_LINKSTAT_ASSOCIATED          0x0400
 235 #define AN_LINKSTAT_AUTHFAIL            0x0300
 236 #define AN_LINKSTAT_ASSOC_FAIL          0x8400
 237 #define AN_LINKSTAT_DISASSOC            0x8200
 238 #define AN_LINKSTAT_DEAUTH              0x8100
 239 #define AN_LINKSTAT_SYNCLOST_TSF        0x8004
 240 #define AN_LINKSTAT_SYNCLOST_HOSTREQ    0x8003
 241 #define AN_LINKSTAT_SYNCLOST_AVGRETRY   0x8002
 242 #define AN_LINKSTAT_SYNCLOST_MAXRETRY   0x8001
 243 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
 244
 245 /* memory handle management registers */
 246 #define AN_RX_FID               0x20
 247 #define AN_ALLOC_FID            0x22
 248 #define AN_TX_CMP_FID(x)        (x ? 0x1a : 0x24)
 249
 250 /*
 251  * Buffer Access Path (BAP) registers.
 252  * These are I/O channels. I believe you can use each one for
 253  * any desired purpose independently of the other. In general
 254  * though, we use BAP1 for reading and writing LTV records and
 255  * reading received data frames, and BAP0 for writing transmit
 256  * frames. This is a convention though, not a rule.
 257  */
 258 #define AN_SEL0                 0x18
 259 #define AN_SEL1                 0x1A
 260 #define AN_OFF0                 0x1C
 261 #define AN_OFF1                 0x1E
 262 #define AN_DATA0                0x36
 263 #define AN_DATA1                0x38
 264 #define AN_BAP0                 AN_DATA0
 265 #define AN_BAP1                 AN_DATA1
 266
 267 #define AN_OFF_BUSY             0x8000
 268 #define AN_OFF_ERR              0x4000
 269 #define AN_OFF_DONE             0x2000
 270 #define AN_OFF_DATAOFF          0x0FFF
 271
 272 /* Event registers */
 273 #define AN_EVENT_STAT(x)        (x ? 0x60 : 0x30)       /* Event status */
 274 #define AN_INT_EN(x)            (x ? 0x64 : 0x32)       /* Interrupt enable/
 275                                                            disable */
 276 #define AN_EVENT_ACK(x)         (x ? 0x68 : 0x34)       /* Ack event */
 277
 278 /* Events */
 279 #define AN_EV_CLR_STUCK_BUSY    0x4000  /* clear stuck busy bit */
 280 #define AN_EV_WAKEREQUEST       0x2000  /* awaken from PSP mode */
 281 #define AN_EV_MIC               0x1000  /* Message Integrity Check*/
 282 #define AN_EV_AWAKE             0x0100  /* station woke up from PSP mode*/
 283 #define AN_EV_LINKSTAT          0x0080  /* link status available */
 284 #define AN_EV_CMD               0x0010  /* command completed */
 285 #define AN_EV_ALLOC             0x0008  /* async alloc/reclaim completed */
 286 #define AN_EV_TX_CPY            0x0400
 287 #define AN_EV_TX_EXC            0x0004  /* async xmit completed with failure */
 288 #define AN_EV_TX                0x0002  /* async xmit completed succesfully */
 289 #define AN_EV_RX                0x0001  /* async rx completed */
 290
 291 #define AN_INTRS(x)     \
 292         ( x ? (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_TX_CPY|AN_EV_ALLOC \
 293                |AN_EV_LINKSTAT|AN_EV_MIC) \
 294           : \
 295               (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC \
 296                |AN_EV_LINKSTAT|AN_EV_MIC) \
 297               )
 298
 299 /* Host software registers */
 300 #define AN_SW0(x)               (x ? 0x50 : 0x28)
 301 #define AN_SW1(x)               (x ? 0x54 : 0x2A)
 302 #define AN_SW2(x)               (x ? 0x58 : 0x2C)
 303 #define AN_SW3(x)               (x ? 0x5c : 0x2E)
 304
 305 #define AN_CNTL                 0x14
 306
 307 #define AN_CNTL_AUX_ENA         0xC000
 308 #define AN_CNTL_AUX_ENA_STAT    0xC000
 309 #define AN_CNTL_AUX_DIS_STAT    0x0000
 310 #define AN_CNTL_AUX_ENA_CNTL    0x8000
 311 #define AN_CNTL_AUX_DIS_CNTL    0x4000
 312
 313 #define AN_AUX_PAGE             0x3A
 314 #define AN_AUX_OFFSET           0x3C
 315 #define AN_AUX_DATA             0x3E
 316
 317 /*
 318  * Length, Type, Value (LTV) record definitions and RID values.
 319  */
 320 struct an_ltv_gen {
 321         u_int16_t               an_len;
 322         u_int16_t               an_type;
 323         u_int16_t               an_val;
 324 };
 325
 326 #define AN_DEF_SSID_LEN         7
 327 #define AN_DEF_SSID             "tsunami"
 328
 329 #define AN_RXGAP_MAX    8
 330
 331 /*
 332  * Transmit frame structure.
 333  */
 334 struct an_txframe {
 335         u_int32_t               an_tx_sw;               /* 0x00 */
 336         u_int16_t               an_tx_status;           /* 0x04 */
 337         u_int16_t               an_tx_payload_len;      /* 0x06 */
 338         u_int16_t               an_tx_ctl;              /* 0x08 */
 339         u_int16_t               an_tx_assoc_id;         /* 0x0A */
 340         u_int16_t               an_tx_retry;            /* 0x0C */
 341         u_int8_t                an_tx_assoc_cnt;        /* 0x0E */
 342         u_int8_t                an_tx_rate;             /* 0x0F */
 343         u_int8_t                an_tx_max_long_retries; /* 0x10 */
 344         u_int8_t                an_tx_max_short_retries; /*0x11 */
 345         u_int8_t                an_rsvd0[2];            /* 0x12 */
 346         u_int16_t               an_frame_ctl;           /* 0x14 */
 347         u_int16_t               an_duration;            /* 0x16 */
 348         u_int8_t                an_addr1[6];            /* 0x18 */
 349         u_int8_t                an_addr2[6];            /* 0x1E */
 350         u_int8_t                an_addr3[6];            /* 0x24 */
 351         u_int16_t               an_seq_ctl;             /* 0x2A */
 352         u_int8_t                an_addr4[6];            /* 0x2C */
 353         u_int8_t                an_gaplen;              /* 0x32 */
 354 } __attribute__ ((packed));
 355
 356 struct an_rxframe_802_3 {
 357         u_int16_t               an_rx_802_3_status;     /* 0x34 */
 358         u_int16_t               an_rx_802_3_payload_len;/* 0x36 */
 359         u_int8_t                an_rx_dst_addr[6];      /* 0x38 */
 360         u_int8_t                an_rx_src_addr[6];      /* 0x3E */
 361 };
 362 #define AN_RXGAP_MAX    8
 363
 364
 365 struct an_txframe_802_3 {
 366 /*
 367  * Transmit 802.3 header structure.
 368  */
 369         u_int16_t               an_tx_802_3_status;     /* 0x34 */
 370         u_int16_t               an_tx_802_3_payload_len;/* 0x36 */
 371         u_int8_t                an_tx_dst_addr[6];      /* 0x38 */
 372         u_int8_t                an_tx_src_addr[6];      /* 0x3E */
 373 };
 374
 375 #define AN_TXSTAT_EXCESS_RETRY  0x0002
 376 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
 377 #define AN_TXSTAT_AID_FAIL      0x0008
 378 #define AN_TXSTAT_MAC_DISABLED  0x0010
 379 #define AN_TXSTAT_ASSOC_LOST    0x0020
 380
 381 #define AN_TXCTL_RSVD           0x0001
 382 #define AN_TXCTL_TXOK_INTR      0x0002
 383 #define AN_TXCTL_TXERR_INTR     0x0004
 384 #define AN_TXCTL_HEADER_TYPE    0x0008
 385 #define AN_TXCTL_PAYLOAD_TYPE   0x0010
 386 #define AN_TXCTL_NORELEASE      0x0020
 387 #define AN_TXCTL_NORETRIES      0x0040
 388 #define AN_TXCTL_CLEAR_AID      0x0080
 389 #define AN_TXCTL_STRICT_ORDER   0x0100
 390 #define AN_TXCTL_USE_RTS        0x0200
 391
 392 #define AN_HEADERTYPE_8023      0x0000
 393 #define AN_HEADERTYPE_80211     0x0008
 394
 395 #define AN_PAYLOADTYPE_ETHER    0x0000
 396 #define AN_PAYLOADTYPE_LLC      0x0010
 397
 398 #define AN_TXCTL_80211          (AN_HEADERTYPE_80211|AN_PAYLOADTYPE_LLC)
 399
 400 #define AN_TXCTL_8023           (AN_HEADERTYPE_8023|AN_PAYLOADTYPE_ETHER)
 401
 402 /*
 403  * Additions to transmit control bits for MPI350
 404  */
 405
 406 #define AN_TXCTL_HW(x)          ( x ? (AN_TXCTL_NORELEASE) : \
 407         (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_TXCTL_NORELEASE))
 408
 409 #define AN_TXGAP_80211          0
 410 #define AN_TXGAP_8023           0
 411
 412 struct an_802_3_hdr {
 413         u_int16_t               an_8023_status;
 414         u_int16_t               an_8023_payload_len;
 415         u_int8_t                an_8023_dst_addr[6];
 416         u_int8_t                an_8023_src_addr[6];
 417         u_int16_t               an_8023_dat[3]; /* SNAP header */
 418         u_int16_t               an_8023_type;
 419 };
 420
 421 struct an_snap_hdr {
 422         u_int16_t               an_snap_dat[3]; /* SNAP header */
 423         u_int16_t               an_snap_type;
 424 };
 425
 426 struct an_dma_alloc {
 427         u_int32_t               an_dma_paddr;
 428         caddr_t                 an_dma_vaddr;
 429         bus_dmamap_t            an_dma_map;
 430         bus_dma_segment_t       an_dma_seg;
 431         bus_size_t              an_dma_size;
 432         int                     an_dma_nseg;
 433 };
 434
 435 #define AN_TX_RING_CNT          4
 436 #define AN_INC(x, y)            (x) = (x + 1) % y
 437
 438 struct an_tx_ring_data {
 439         u_int16_t               an_tx_fids[AN_TX_RING_CNT];
 440         u_int16_t               an_tx_ring[AN_TX_RING_CNT];
 441         int                     an_tx_prod;
 442         int                     an_tx_cons;
 443         int                     an_tx_empty;
 444 };
 445
 446 struct an_softc {
 447         struct arpcom           arpcom;
 448
 449         int     port_rid;       /* resource id for port range */
 450         struct resource* port_res; /* resource for port range */
 451         int     mem_rid;        /* resource id for memory range */
 452         int     mem_used;       /* nonzero if memory used */
 453         struct resource* mem_res; /* resource for memory range */
 454         int     mem_aux_rid;    /* resource id for memory range */
 455         int     mem_aux_used;   /* nonzero if memory used */
 456         struct resource* mem_aux_res; /* resource for memory range */
 457         int     irq_rid;        /* resource id for irq */
 458         void*   irq_handle;     /* handle for irq handler */
 459         struct resource* irq_res; /* resource for irq */
 460
 461         bus_space_handle_t      an_bhandle_p;
 462         bus_space_handle_t      an_bhandle;
 463         bus_space_tag_t         an_btag;
 464         bus_space_handle_t      an_mem_bhandle;
 465         bus_space_tag_t         an_mem_btag;
 466         bus_space_handle_t      an_mem_aux_bhandle;
 467         bus_space_tag_t         an_mem_aux_btag;
 468         bus_dma_tag_t           an_dtag;
 469         struct an_ltv_genconfig an_config;
 470         struct an_ltv_caps      an_caps;
 471         struct an_ltv_ssidlist_new      an_ssidlist;
 472         struct an_ltv_aplist    an_aplist;
 473         struct an_ltv_key       an_temp_keys[4];
 474         int                     an_tx_rate;
 475         int                     an_rxmode;
 476         int                     an_if_flags;
 477         u_int8_t                an_txbuf[1536];
 478         struct an_tx_ring_data  an_rdata;
 479         struct an_ltv_stats     an_stats;
 480         struct an_ltv_status    an_status;
 481         u_int8_t                an_associated;
 482 #ifdef ANCACHE
 483         int                     an_sigitems;
 484         struct an_sigcache      an_sigcache[MAXANCACHE];
 485         int                     an_nextitem;
 486         int                     an_have_rssimap;
 487         struct an_ltv_rssi_map  an_rssimap;
 488 #endif
 489         struct callout          an_stat_timer;
 490         struct ifmedia          an_ifmedia;
 491         int                     an_monitor;
 492         int                     an_was_monitor;
 493         u_char                  buf_802_11[MCLBYTES];
 494         struct an_req           areq;
 495         unsigned short*         an_flash_buffer;
 496         int                     mpi350;
 497         struct an_dma_alloc     an_rid_buffer;
 498         struct an_dma_alloc     an_rx_buffer[AN_MAX_RX_DESC];
 499         struct an_dma_alloc     an_tx_buffer[AN_MAX_TX_DESC];
 500 };
 501
 502 void    an_release_resources    (device_t);
 503 int     an_alloc_port           (device_t, int, int);
 504 int     an_alloc_memory         (device_t, int, int);
 505 int     an_alloc_aux_memory     (device_t, int, int);
 506 int     an_alloc_irq            (device_t, int, int);
 507 int     an_probe                (device_t);
 508 void    an_shutdown             (device_t);
 509 void    an_resume               (device_t);
 510 int     an_attach               (struct an_softc *, device_t, int);
 511 int     an_detach               (device_t);
 512 void    an_stop                 (struct an_softc *);
 513
 514 driver_intr_t   an_intr;
 515
 516 #define AN_802_3_OFFSET         0x2E
 517 #define AN_802_11_OFFSET        0x44
 518 #define AN_802_11_OFFSET_RAW    0x3C
 519
 520 #define AN_STAT_BADCRC          0x0001
 521 #define AN_STAT_UNDECRYPTABLE   0x0002
 522 #define AN_STAT_ERRSTAT         0x0003
 523 #define AN_STAT_MAC_PORT        0x0700
 524 #define AN_STAT_1042            0x2000  /* RFC1042 encoded */
 525 #define AN_STAT_TUNNEL          0x4000  /* Bridge-tunnel encoded */
 526 #define AN_STAT_WMP_MSG         0x6000  /* WaveLAN-II management protocol */
 527 #define AN_RXSTAT_MSG_TYPE      0xE000
 528
 529 #define AN_ENC_TX_802_3         0x00
 530 #define AN_ENC_TX_802_11        0x11
 531 #define AN_ENC_TX_E_II          0x0E
 532
 533 #define AN_ENC_TX_1042          0x00
 534 #define AN_ENC_TX_TUNNEL        0xF8
 535
 536 #define AN_TXCNTL_MACPORT       0x00FF
 537 #define AN_TXCNTL_STRUCTTYPE    0xFF00
 538
 539 /*
 540  * SNAP (sub-network access protocol) constants for transmission
 541  * of IP datagrams over IEEE 802 networks, taken from RFC1042.
 542  * We need these for the LLC/SNAP header fields in the TX/RX frame
 543  * structure.
 544  */
 545 #define AN_SNAP_K1              0xaa    /* assigned global SAP for SNAP */
 546 #define AN_SNAP_K2              0x00
 547 #define AN_SNAP_CONTROL         0x03    /* unnumbered information format */
 548 #define AN_SNAP_WORD0           (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
 549 #define AN_SNAP_WORD1           (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
 550 #define AN_SNAPHDR_LEN          0x6