sys/dev/raid/iir/iir.h

   1 /* $FreeBSD: src/sys/dev/iir/iir.h,v 1.16 2007/06/17 05:55:50 scottl Exp $ */
   2 /* $DragonFly: src/sys/dev/raid/iir/iir.h,v 1.7 2006/12/22 23:26:23 swildner Exp $ */
   3 /*-
   4  *       Copyright (c) 2000-04 ICP vortex GmbH
   5  *       Copyright (c) 2002-04 Intel Corporation
   6  *       Copyright (c) 2003-04 Adaptec Inc.
   7  *       All Rights Reserved
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification, immediately at the beginning of the file.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  */
  34
  35 /*
  36  *
  37  * iir.h:       Definitions/Constants used by the Intel Integrated RAID driver
  38  *
  39  * Written by:  Achim Leubner <achim_leubner@adaptec.com>
  40  * Fixes/Additions:     Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
  41  *
  42  * credits:     Niklas Hallqvist;       OpenBSD driver for the ICP Controllers.
  43  *              FreeBSD.ORG;            Great O/S to work on and for.
  44  *
  45  * $Id: iir.h 1.6 2004/03/30 10:19:44 achim Exp $"
  46  */
  47
  48 #ifndef _IIR_H
  49 #define _IIR_H
  50
  51 #include <sys/ioccom.h>
  52
  53 #define IIR_DRIVER_VERSION      1
  54 #define IIR_DRIVER_SUBVERSION   5
  55
  56 #define IIR_CDEV_MAJOR          164
  57
  58 /* OEM IDs */
  59 #define OEM_ID_ICP              0x941c
  60 #define OEM_ID_INTEL            0x8000
  61
  62 #define GDT_VENDOR_ID           0x1119
  63 #define GDT_DEVICE_ID_MIN       0x100
  64 #define GDT_DEVICE_ID_MAX       0x2ff
  65 #define GDT_DEVICE_ID_NEWRX     0x300
  66
  67 #define INTEL_VENDOR_ID         0x8086
  68 #define INTEL_DEVICE_ID_IIR     0x600
  69
  70 #define GDT_MAXBUS              6       /* XXX Why not 5? */
  71 #define GDT_MAX_HDRIVES         100     /* max 100 host drives */
  72 #define GDT_MAXID_FC            127     /* Fibre-channel IDs */
  73 #define GDT_MAXID               16      /* SCSI IDs */
  74 #define GDT_MAXOFFSETS          128
  75 #define GDT_MAXSG               32      /* Max. s/g elements */
  76 #define GDT_PROTOCOL_VERSION    1
  77 #define GDT_LINUX_OS            8       /* Used for cache optimization */
  78 #define GDT_SCATTER_GATHER      1       /* s/g feature */
  79 #define GDT_SECS32              0x1f    /* round capacity */
  80 #define GDT_LOCALBOARD          0       /* Board node always 0 */
  81 #define GDT_MAXCMDS             124
  82 #define GDT_SECTOR_SIZE         0x200   /* Always 512 bytes for cache devs */
  83 #define GDT_MAX_EVENTS          0x100   /* event buffer */
  84
  85 /* DPMEM constants */
  86 #define GDT_MPR_MAGIC           0xc0ffee11
  87 #define GDT_IC_HEADER_BYTES     48
  88 #define GDT_IC_QUEUE_BYTES      4
  89 #define GDT_DPMEM_COMMAND_OFFSET \
  90     (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
  91
  92 /* geometry constants */
  93 #define GDT_MAXCYLS             1024
  94 #define GDT_HEADS               64
  95 #define GDT_SECS                32      /* mapping 64*32 */
  96 #define GDT_MEDHEADS            127
  97 #define GDT_MEDSECS             63      /* mapping 127*63 */
  98 #define GDT_BIGHEADS            255
  99 #define GDT_BIGSECS             63      /* mapping 255*63 */
 100
 101 /* data direction raw service */
 102 #define GDT_DATA_IN             0x01000000L
 103 #define GDT_DATA_OUT            0x00000000L
 104
 105 /* Cache/raw service commands */
 106 #define GDT_INIT        0               /* service initialization */
 107 #define GDT_READ        1               /* read command */
 108 #define GDT_WRITE       2               /* write command */
 109 #define GDT_INFO        3               /* information about devices */
 110 #define GDT_FLUSH       4               /* flush dirty cache buffers */
 111 #define GDT_IOCTL       5               /* ioctl command */
 112 #define GDT_DEVTYPE     9               /* additional information */
 113 #define GDT_MOUNT       10              /* mount cache device */
 114 #define GDT_UNMOUNT     11              /* unmount cache device */
 115 #define GDT_SET_FEAT    12              /* set features (scatter/gather) */
 116 #define GDT_GET_FEAT    13              /* get features */
 117 #define GDT_WRITE_THR   16              /* write through */
 118 #define GDT_READ_THR    17              /* read through */
 119 #define GDT_EXT_INFO    18              /* extended info */
 120 #define GDT_RESET       19              /* controller reset */
 121 #define GDT_FREEZE_IO   25              /* freeze all IOs */
 122 #define GDT_UNFREEZE_IO 26              /* unfreeze all IOs */
 123
 124 /* Additional raw service commands */
 125 #define GDT_RESERVE     14              /* reserve device to raw service */
 126 #define GDT_RELEASE     15              /* release device */
 127 #define GDT_RESERVE_ALL 16              /* reserve all devices */
 128 #define GDT_RELEASE_ALL 17              /* release all devices */
 129 #define GDT_RESET_BUS   18              /* reset bus */
 130 #define GDT_SCAN_START  19              /* start device scan */
 131 #define GDT_SCAN_END    20              /* stop device scan */
 132
 133 /* IOCTL command defines */
 134 #define GDT_SCSI_DR_INFO        0x00    /* SCSI drive info */
 135 #define GDT_SCSI_CHAN_CNT       0x05    /* SCSI channel count */
 136 #define GDT_SCSI_DR_LIST        0x06    /* SCSI drive list */
 137 #define GDT_SCSI_DEF_CNT        0x15    /* grown/primary defects */
 138 #define GDT_DSK_STATISTICS      0x4b    /* SCSI disk statistics */
 139 #define GDT_IOCHAN_DESC         0x5d    /* description of IO channel */
 140 #define GDT_IOCHAN_RAW_DESC     0x5e    /* description of raw IO channel */
 141
 142 #define GDT_L_CTRL_PATTERN      0x20000000      /* SCSI IOCTL mask */
 143 #define GDT_ARRAY_INFO          0x12            /* array drive info */
 144 #define GDT_ARRAY_DRV_LIST      0x0f            /* array drive list */
 145 #define GDT_LA_CTRL_PATTERN     0x10000000      /* array IOCTL mask */
 146 #define GDT_CACHE_DRV_CNT       0x01            /* cache drive count */
 147 #define GDT_CACHE_DRV_LIST      0x02            /* cache drive list */
 148 #define GDT_CACHE_INFO          0x04            /* cache info */
 149 #define GDT_CACHE_CONFIG        0x05            /* cache configuration */
 150 #define GDT_CACHE_DRV_INFO      0x07            /* cache drive info */
 151 #define GDT_BOARD_FEATURES      0x15            /* controller features */
 152 #define GDT_BOARD_INFO          0x28            /* controller info */
 153 #define GDT_OEM_STR_RECORD      0x84            /* OEM info */
 154 #define GDT_HOST_GET            0x10001         /* get host drive list */
 155 #define GDT_IO_CHANNEL          0x20000         /* default IO channel */
 156 #define GDT_INVALID_CHANNEL     0xffff          /* invalid channel */
 157
 158 /* IOCTLs */
 159 #define GDT_IOCTL_GENERAL       _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
 160 #define GDT_IOCTL_DRVERS        _IOR('J', 1, int)      /* get driver version */
 161 #define GDT_IOCTL_CTRTYPE       _IOWR('J', 2, gdt_ctrt_t) /* get ctr. type */
 162 #define GDT_IOCTL_DRVERS_OLD    _IOWR('J', 1, int)      /* get driver version */
 163 #define GDT_IOCTL_CTRTYPE_OLD   _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
 164 #define GDT_IOCTL_OSVERS        _IOR('J', 3, gdt_osv_t) /* get OS version */
 165 #define GDT_IOCTL_CTRCNT        _IOR('J', 5, int)       /* get ctr. count */
 166 #define GDT_IOCTL_EVENT         _IOWR('J', 8, gdt_event_t) /* get event */
 167 #define GDT_IOCTL_STATIST       _IOR('J', 9, gdt_statist_t) /* get statistics */
 168
 169 /* Service errors */
 170 #define GDT_S_OK                1       /* no error */
 171 #define GDT_S_BSY               7       /* controller busy */
 172 #define GDT_S_RAW_SCSI          12      /* raw service: target error */
 173 #define GDT_S_RAW_ILL           0xff    /* raw service: illegal */
 174 #define GDT_S_NO_STATUS         0x1000  /* got no status (driver-generated) */
 175
 176 /* Controller services */
 177 #define GDT_SCSIRAWSERVICE      3
 178 #define GDT_CACHESERVICE        9
 179 #define GDT_SCREENSERVICE       11
 180
 181 /* Scatter/gather element */
 182 #define GDT_SG_PTR              0x00    /* u_int32_t, address */
 183 #define GDT_SG_LEN              0x04    /* u_int32_t, length */
 184 #define GDT_SG_SZ               0x08
 185
 186 /* Cache service command */
 187 #define GDT_CACHE_DEVICENO      0x00    /* u_int16_t, number of cache drive */
 188 #define GDT_CACHE_BLOCKNO       0x02    /* u_int32_t, block number */
 189 #define GDT_CACHE_BLOCKCNT      0x06    /* u_int32_t, block count */
 190 #define GDT_CACHE_DESTADDR      0x0a    /* u_int32_t, dest. addr. (-1: s/g) */
 191 #define GDT_CACHE_SG_CANZ       0x0e    /* u_int32_t, s/g element count */
 192 #define GDT_CACHE_SG_LST        0x12    /* [GDT_MAXSG], s/g list */
 193 #define GDT_CACHE_SZ            (0x12 + GDT_MAXSG * GDT_SG_SZ)
 194
 195 /* Ioctl command */
 196 #define GDT_IOCTL_PARAM_SIZE    0x00    /* u_int16_t, size of buffer */
 197 #define GDT_IOCTL_SUBFUNC       0x02    /* u_int32_t, ioctl function */
 198 #define GDT_IOCTL_CHANNEL       0x06    /* u_int32_t, device */
 199 #define GDT_IOCTL_P_PARAM       0x0a    /* u_int32_t, buffer */
 200 #define GDT_IOCTL_SZ            0x0e
 201
 202 /* Screen service defines */
 203 #define GDT_MSG_INV_HANDLE      -1      /* special message handle */
 204 #define GDT_MSGLEN              16      /* size of message text */
 205 #define GDT_MSG_SIZE            34      /* size of message structure */
 206 #define GDT_MSG_REQUEST         0       /* async. event. message */
 207
 208 /* Screen service command */
 209 #define GDT_SCREEN_MSG_HANDLE   0x02    /* u_int32_t, message handle */
 210 #define GDT_SCREEN_MSG_ADDR     0x06    /* u_int32_t, message buffer address */
 211 #define GDT_SCREEN_SZ           0x0a
 212
 213 /* Screen service message */
 214 #define GDT_SCR_MSG_HANDLE      0x00    /* u_int32_t, message handle */
 215 #define GDT_SCR_MSG_LEN         0x04    /* u_int32_t, size of message */
 216 #define GDT_SCR_MSG_ALEN        0x08    /* u_int32_t, answer length */
 217 #define GDT_SCR_MSG_ANSWER      0x0c    /* u_int8_t, answer flag */
 218 #define GDT_SCR_MSG_EXT         0x0d    /* u_int8_t, more messages? */
 219 #define GDT_SCR_MSG_RES         0x0e    /* u_int16_t, reserved */
 220 #define GDT_SCR_MSG_TEXT        0x10    /* GDT_MSGLEN+2, message text */
 221 #define GDT_SCR_MSG_SZ          (0x12 + GDT_MSGLEN)
 222
 223 /* Raw service command */
 224 #define GDT_RAW_DIRECTION       0x02    /* u_int32_t, data direction */
 225 #define GDT_RAW_MDISC_TIME      0x06    /* u_int32_t, disc. time (0: none) */
 226 #define GDT_RAW_MCON_TIME       0x0a    /* u_int32_t, conn. time (0: none) */
 227 #define GDT_RAW_SDATA           0x0e    /* u_int32_t, dest. addr. (-1: s/g) */
 228 #define GDT_RAW_SDLEN           0x12    /* u_int32_t, data length */
 229 #define GDT_RAW_CLEN            0x16    /* u_int32_t, SCSI cmd len (6/10/12) */
 230 #define GDT_RAW_CMD             0x1a    /* u_int8_t [12], SCSI command */
 231 #define GDT_RAW_TARGET          0x26    /* u_int8_t, target ID */
 232 #define GDT_RAW_LUN             0x27    /* u_int8_t, LUN */
 233 #define GDT_RAW_BUS             0x28    /* u_int8_t, SCSI bus number */
 234 #define GDT_RAW_PRIORITY        0x29    /* u_int8_t, only 0 used */
 235 #define GDT_RAW_SENSE_LEN       0x2a    /* u_int32_t, sense data length */
 236 #define GDT_RAW_SENSE_DATA      0x2e    /* u_int32_t, sense data address */
 237 #define GDT_RAW_SG_RANZ         0x36    /* u_int32_t, s/g element count */
 238 #define GDT_RAW_SG_LST          0x3a    /* [GDT_MAXSG], s/g list */
 239 #define GDT_RAW_SZ              (0x3a + GDT_MAXSG * GDT_SG_SZ)
 240
 241 /* Command structure */
 242 #define GDT_CMD_BOARDNODE       0x00    /* u_int32_t, board node (always 0) */
 243 #define GDT_CMD_COMMANDINDEX    0x04    /* u_int32_t, command number */
 244 #define GDT_CMD_OPCODE          0x08    /* u_int16_t, opcode (READ, ...) */
 245 #define GDT_CMD_UNION           0x0a    /* cache/screen/raw service command */
 246 #define GDT_CMD_UNION_SZ        GDT_RAW_SZ
 247 #define GDT_CMD_SZ              (0x0a + GDT_CMD_UNION_SZ)
 248
 249 /* Command queue entries */
 250 #define GDT_OFFSET      0x00    /* u_int16_t, command offset in the DP RAM */
 251 #define GDT_SERV_ID     0x02    /* u_int16_t, service */
 252 #define GDT_COMM_Q_SZ   0x04
 253
 254 /* Interface area */
 255 #define GDT_S_CMD_INDX  0x00    /* u_int8_t, special command */
 256 #define GDT_S_STATUS    0x01    /* volatile u_int8_t, status special command */
 257 #define GDT_S_INFO      0x04    /* u_int32_t [4], add. info special command */
 258 #define GDT_SEMA0       0x14    /* volatile u_int8_t, command semaphore */
 259 #define GDT_CMD_INDEX   0x18    /* u_int8_t, command number */
 260 #define GDT_STATUS      0x1c    /* volatile u_int16_t, command status */
 261 #define GDT_SERVICE     0x1e    /* u_int16_t, service (for asynch. events) */
 262 #define GDT_DPR_INFO    0x20    /* u_int32_t [2], additional info */
 263 #define GDT_COMM_QUEUE  0x28    /* command queue */
 264 #define GDT_DPR_CMD     (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
 265                                 /* u_int8_t [], commands */
 266
 267 /* I/O channel header */
 268 #define GDT_IOC_VERSION         0x00    /* u_int32_t, version (~0: newest) */
 269 #define GDT_IOC_LIST_ENTRIES    0x04    /* u_int8_t, list entry count */
 270 #define GDT_IOC_FIRST_CHAN      0x05    /* u_int8_t, first channel number */
 271 #define GDT_IOC_LAST_CHAN       0x06    /* u_int8_t, last channel number */
 272 #define GDT_IOC_CHAN_COUNT      0x07    /* u_int8_t, (R) channel count */
 273 #define GDT_IOC_LIST_OFFSET     0x08    /* u_int32_t, offset of list[0] */
 274 #define GDT_IOC_HDR_SZ          0x0c
 275
 276 #define GDT_IOC_NEWEST          0xffffffff      /* goes into GDT_IOC_VERSION */
 277
 278 /* Get I/O channel description */
 279 #define GDT_IOC_ADDRESS         0x00    /* u_int32_t, channel address */
 280 #define GDT_IOC_TYPE            0x04    /* u_int8_t, type (SCSI/FCSL) */
 281 #define GDT_IOC_LOCAL_NO        0x05    /* u_int8_t, local number */
 282 #define GDT_IOC_FEATURES        0x06    /* u_int16_t, channel features */
 283 #define GDT_IOC_SZ              0x08
 284
 285 /* Get raw I/O channel description */
 286 #define GDT_RAWIOC_PROC_ID      0x00    /* u_int8_t, processor id */
 287 #define GDT_RAWIOC_PROC_DEFECT  0x01    /* u_int8_t, defect? */
 288 #define GDT_RAWIOC_SZ           0x04
 289
 290 /* Get SCSI channel count */
 291 #define GDT_GETCH_CHANNEL_NO    0x00    /* u_int32_t, channel number */
 292 #define GDT_GETCH_DRIVE_CNT     0x04    /* u_int32_t, drive count */
 293 #define GDT_GETCH_SIOP_ID       0x08    /* u_int8_t, SCSI processor ID */
 294 #define GDT_GETCH_SIOP_STATE    0x09    /* u_int8_t, SCSI processor state */
 295 #define GDT_GETCH_SZ            0x0a
 296
 297 /* Cache info/config IOCTL structures */
 298 #define GDT_CPAR_VERSION        0x00    /* u_int32_t, firmware version */
 299 #define GDT_CPAR_STATE          0x04    /* u_int16_t, cache state (on/off) */
 300 #define GDT_CPAR_STRATEGY       0x06    /* u_int16_t, cache strategy */
 301 #define GDT_CPAR_WRITE_BACK     0x08    /* u_int16_t, write back (on/off) */
 302 #define GDT_CPAR_BLOCK_SIZE     0x0a    /* u_int16_t, cache block size */
 303 #define GDT_CPAR_SZ             0x0c
 304
 305 #define GDT_CSTAT_CSIZE         0x00    /* u_int32_t, cache size */
 306 #define GDT_CSTAT_READ_CNT      0x04    /* u_int32_t, read counter */
 307 #define GDT_CSTAT_WRITE_CNT     0x08    /* u_int32_t, write counter */
 308 #define GDT_CSTAT_TR_HITS       0x0c    /* u_int32_t, track hits */
 309 #define GDT_CSTAT_SEC_HITS      0x10    /* u_int32_t, sector hits */
 310 #define GDT_CSTAT_SEC_MISS      0x14    /* u_int32_t, sector misses */
 311 #define GDT_CSTAT_SZ            0x18
 312
 313 /* Get cache info */
 314 #define GDT_CINFO_CPAR          0x00
 315 #define GDT_CINFO_CSTAT         GDT_CPAR_SZ
 316 #define GDT_CINFO_SZ            (GDT_CPAR_SZ + GDT_CSTAT_SZ)
 317
 318 /* Get board info */
 319 #define GDT_BINFO_SER_NO        0x00    /* u_int32_t, serial number */
 320 #define GDT_BINFO_OEM_ID        0x04    /* u_int8_t [2], OEM ID */
 321 #define GDT_BINFO_EP_FLAGS      0x06    /* u_int16_t, eprom flags */
 322 #define GDT_BINFO_PROC_ID       0x08    /* u_int32_t, processor ID */
 323 #define GDT_BINFO_MEMSIZE       0x0c    /* u_int32_t, memory size (bytes) */
 324 #define GDT_BINFO_MEM_BANKS     0x10    /* u_int8_t, memory banks */
 325 #define GDT_BINFO_CHAN_TYPE     0x11    /* u_int8_t, channel type */
 326 #define GDT_BINFO_CHAN_COUNT    0x12    /* u_int8_t, channel count */
 327 #define GDT_BINFO_RDONGLE_PRES  0x13    /* u_int8_t, dongle present */
 328 #define GDT_BINFO_EPR_FW_VER    0x14    /* u_int32_t, (eprom) firmware ver */
 329 #define GDT_BINFO_UPD_FW_VER    0x18    /* u_int32_t, (update) firmware ver */
 330 #define GDT_BINFO_UPD_REVISION  0x1c    /* u_int32_t, update revision */
 331 #define GDT_BINFO_TYPE_STRING   0x20    /* char [16], controller name */
 332 #define GDT_BINFO_RAID_STRING   0x30    /* char [16], RAID firmware name */
 333 #define GDT_BINFO_UPDATE_PRES   0x40    /* u_int8_t, update present? */
 334 #define GDT_BINFO_XOR_PRES      0x41    /* u_int8_t, XOR engine present */
 335 #define GDT_BINFO_PROM_TYPE     0x42    /* u_int8_t, ROM type (eprom/flash) */
 336 #define GDT_BINFO_PROM_COUNT    0x43    /* u_int8_t, number of ROM devices */
 337 #define GDT_BINFO_DUP_PRES      0x44    /* u_int32_t, duplexing module pres? */
 338 #define GDT_BINFO_CHAN_PRES     0x48    /* u_int32_t, # of exp. channels */
 339 #define GDT_BINFO_MEM_PRES      0x4c    /* u_int32_t, memory expansion inst? */
 340 #define GDT_BINFO_FT_BUS_SYSTEM 0x50    /* u_int8_t, fault bus supported? */
 341 #define GDT_BINFO_SUBTYPE_VALID 0x51    /* u_int8_t, board_subtype valid */
 342 #define GDT_BINFO_BOARD_SUBTYPE 0x52    /* u_int8_t, subtype/hardware level */
 343 #define GDT_BINFO_RAMPAR_PRES   0x53    /* u_int8_t, RAM parity check hw? */
 344 #define GDT_BINFO_SZ            0x54
 345
 346 /* Get board features */
 347 #define GDT_BFEAT_CHAINING      0x00    /* u_int8_t, chaining supported */
 348 #define GDT_BFEAT_STRIPING      0x01    /* u_int8_t, striping (RAID-0) supp. */
 349 #define GDT_BFEAT_MIRRORING     0x02    /* u_int8_t, mirroring (RAID-1) supp */
 350 #define GDT_BFEAT_RAID          0x03    /* u_int8_t, RAID-4/5/10 supported */
 351 #define GDT_BFEAT_SZ            0x04
 352
 353 /* Other defines */
 354 #define GDT_ASYNCINDEX  0       /* command index asynchronous event */
 355 #define GDT_SPEZINDEX   1       /* command index unknown service */
 356
 357 /* Debugging */
 358 #ifdef GDT_DEBUG
 359 #define GDT_D_INTR      0x01
 360 #define GDT_D_MISC      0x02
 361 #define GDT_D_CMD       0x04
 362 #define GDT_D_QUEUE     0x08
 363 #define GDT_D_TIMEOUT   0x10
 364 #define GDT_D_INIT      0x20
 365 #define GDT_D_INVALID   0x40
 366 #define GDT_D_DEBUG     0x80
 367 extern int gdt_debug;
 368 #ifdef __SERIAL__
 369 extern int ser_printf(const char *fmt, ...);
 370 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_kprintf args
 371 #else
 372 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) kprintf args
 373 #endif
 374 #else
 375 #define GDT_DPRINTF(mask, args)
 376 #endif
 377
 378 /* Miscellaneous constants */
 379 #define GDT_RETRIES             100000000       /* 100000 * 1us = 100s */
 380 #define GDT_TIMEOUT             100000000       /* 100000 * 1us = 100s */
 381 #define GDT_POLL_TIMEOUT        10000000        /* 10000 * 1us = 10s */
 382 #define GDT_WATCH_TIMEOUT       10000000        /* 10000 * 1us = 10s */
 383 #define GDT_SCRATCH_SZ          3072            /* 3KB scratch buffer */
 384
 385 /* Map minor numbers to device identity */
 386 #define LUN_MASK                0x0007
 387 #define TARGET_MASK             0x03f8
 388 #define BUS_MASK                0x1c00
 389 #define HBA_MASK                0xe000
 390
 391 #define minor2lun(minor)        ( minor & LUN_MASK )
 392 #define minor2target(minor)     ( (minor & TARGET_MASK) >> 3 )
 393 #define minor2bus(minor)        ( (minor & BUS_MASK) >> 10 )
 394 #define minor2hba(minor)        ( (minor & HBA_MASK) >> 13 )
 395 #define hba2minor(hba)          ( (hba << 13) & HBA_MASK )
 396
 397
 398 /* struct for GDT_IOCTL_GENERAL */
 399 #pragma pack(1)
 400 typedef struct gdt_ucmd {
 401     u_int16_t   io_node;
 402     u_int16_t   service;
 403     u_int32_t   timeout;
 404     u_int16_t   status;
 405     u_int32_t   info;
 406
 407     u_int32_t   BoardNode;                      /* board node (always 0) */
 408     u_int32_t   CommandIndex;                   /* command number */
 409     u_int16_t   OpCode;                         /* the command (READ,..) */
 410     union {
 411         struct {
 412             u_int16_t   DeviceNo;               /* number of cache drive */
 413             u_int32_t   BlockNo;                /* block number */
 414             u_int32_t   BlockCnt;               /* block count */
 415             void        *DestAddr;              /* data */
 416         } cache;                                /* cache service cmd. str. */
 417         struct {
 418             u_int16_t   param_size;             /* size of p_param buffer */
 419             u_int32_t   subfunc;                /* IOCTL function */
 420             u_int32_t   channel;                /* device */
 421             void        *p_param;               /* data */
 422         } ioctl;                                /* IOCTL command structure */
 423         struct {
 424             u_int16_t   reserved;
 425             u_int32_t   direction;              /* data direction */
 426             u_int32_t   mdisc_time;             /* disc. time (0: no timeout)*/
 427             u_int32_t   mcon_time;              /* connect time(0: no to.) */
 428             void        *sdata;                 /* dest. addr. (if s/g: -1) */
 429             u_int32_t   sdlen;                  /* data length (bytes) */
 430             u_int32_t   clen;                   /* SCSI cmd. length(6,10,12) */
 431             u_int8_t    cmd[12];                /* SCSI command */
 432             u_int8_t    target;                 /* target ID */
 433             u_int8_t    lun;                    /* LUN */
 434             u_int8_t    bus;                    /* SCSI bus number */
 435             u_int8_t    priority;               /* only 0 used */
 436             u_int32_t   sense_len;              /* sense data length */
 437             void        *sense_data;            /* sense data addr. */
 438             u_int32_t   link_p;                 /* linked cmds (not supp.) */
 439         } raw;                                  /* raw service cmd. struct. */
 440     } u;
 441     u_int8_t            data[GDT_SCRATCH_SZ];
 442     int                 complete_flag;
 443     TAILQ_ENTRY(gdt_ucmd) links;
 444 } gdt_ucmd_t;
 445
 446 /* struct for GDT_IOCTL_CTRTYPE */
 447 typedef struct gdt_ctrt {
 448     u_int16_t io_node;
 449     u_int16_t oem_id;
 450     u_int16_t type;
 451     u_int32_t info;
 452     u_int8_t  access;
 453     u_int8_t  remote;
 454     u_int16_t ext_type;
 455     u_int16_t device_id;
 456     u_int16_t sub_device_id;
 457 } gdt_ctrt_t;
 458
 459 /* struct for GDT_IOCTL_OSVERS */
 460 typedef struct gdt_osv {
 461     u_int8_t  oscode;
 462     u_int8_t  version;
 463     u_int8_t  subversion;
 464     u_int16_t revision;
 465     char      name[64];
 466 } gdt_osv_t;
 467
 468 /* OEM */
 469 #define GDT_OEM_VERSION     0x00
 470 #define GDT_OEM_BUFSIZE     0x0c
 471 typedef struct {
 472     u_int32_t ctl_version;
 473     u_int32_t file_major_version;
 474     u_int32_t file_minor_version;
 475     u_int32_t buffer_size;
 476     u_int32_t cpy_count;
 477     u_int32_t ext_error;
 478     u_int32_t oem_id;
 479     u_int32_t board_id;
 480 } gdt_oem_param_t;
 481
 482 typedef struct {
 483     char      product_0_1_name[16];
 484     char      product_4_5_name[16];
 485     char      product_cluster_name[16];
 486     char      product_reserved[16];
 487     char      scsi_cluster_target_vendor_id[16];
 488     char      cluster_raid_fw_name[16];
 489     char      oem_brand_name[16];
 490     char      oem_raid_type[16];
 491     char      bios_type[13];
 492     char      bios_title[50];
 493     char      oem_company_name[37];
 494     u_int32_t pci_id_1;
 495     u_int32_t pci_id_2;
 496     char      validation_status[80];
 497     char      reserved_1[4];
 498     char      scsi_host_drive_inquiry_vendor_id[16];
 499     char      library_file_template[32];
 500     char      tool_name_1[32];
 501     char      tool_name_2[32];
 502     char      tool_name_3[32];
 503     char      oem_contact_1[84];
 504     char      oem_contact_2[84];
 505     char      oem_contact_3[84];
 506 } gdt_oem_record_t;
 507
 508 typedef struct {
 509     gdt_oem_param_t  parameters;
 510     gdt_oem_record_t text;
 511 } gdt_oem_str_record_t;
 512
 513
 514 /* controller event structure */
 515 #define GDT_ES_ASYNC    1
 516 #define GDT_ES_DRIVER   2
 517 #define GDT_ES_TEST     3
 518 #define GDT_ES_SYNC     4
 519 typedef struct {
 520     u_int16_t           size;               /* size of structure */
 521     union {
 522         char            stream[16];
 523         struct {
 524             u_int16_t   ionode;
 525             u_int16_t   service;
 526             u_int32_t   index;
 527         } driver;
 528         struct {
 529             u_int16_t   ionode;
 530             u_int16_t   service;
 531             u_int16_t   status;
 532             u_int32_t   info;
 533             u_int8_t    scsi_coord[3];
 534         } async;
 535         struct {
 536             u_int16_t   ionode;
 537             u_int16_t   service;
 538             u_int16_t   status;
 539             u_int32_t   info;
 540             u_int16_t   hostdrive;
 541             u_int8_t    scsi_coord[3];
 542             u_int8_t    sense_key;
 543         } sync;
 544         struct {
 545             u_int32_t   l1, l2, l3, l4;
 546         } test;
 547     } eu;
 548     u_int32_t           severity;
 549     u_int8_t            event_string[256];
 550 } gdt_evt_data;
 551
 552 /* dvrevt structure */
 553 typedef struct {
 554     u_int32_t           first_stamp;
 555     u_int32_t           last_stamp;
 556     u_int16_t           same_count;
 557     u_int16_t           event_source;
 558     u_int16_t           event_idx;
 559     u_int8_t            application;
 560     u_int8_t            reserved;
 561     gdt_evt_data        event_data;
 562 } gdt_evt_str;
 563
 564 /* struct for GDT_IOCTL_EVENT */
 565 typedef struct gdt_event {
 566     int erase;
 567     int handle;
 568     gdt_evt_str dvr;
 569 } gdt_event_t;
 570
 571 /* struct for GDT_IOCTL_STATIST */
 572 typedef struct gdt_statist {
 573     u_int16_t io_count_act;
 574     u_int16_t io_count_max;
 575     u_int16_t req_queue_act;
 576     u_int16_t req_queue_max;
 577     u_int16_t cmd_index_act;
 578     u_int16_t cmd_index_max;
 579     u_int16_t sg_count_act;
 580     u_int16_t sg_count_max;
 581 } gdt_statist_t;
 582
 583 #pragma pack()
 584
 585 /* Context structure for interrupt services */
 586 struct gdt_intr_ctx {
 587     u_int32_t info, info2;
 588     u_int16_t cmd_status, service;
 589     u_int8_t istatus;
 590 };
 591
 592 /* softc structure */
 593 struct gdt_softc {
 594     int sc_hanum;
 595     int sc_class;               /* Controller class */
 596 #define GDT_MPR         0x05
 597 #define GDT_CLASS_MASK  0x07
 598 #define GDT_FC          0x10
 599 #define GDT_CLASS(gdt)  ((gdt)->sc_class & GDT_CLASS_MASK)
 600     int sc_bus, sc_slot;
 601     u_int16_t sc_vendor;
 602     u_int16_t sc_device, sc_subdevice;
 603     u_int16_t sc_fw_vers;
 604     int sc_init_level;
 605     int sc_state;
 606 #define GDT_NORMAL      0x00
 607 #define GDT_POLLING     0x01
 608 #define GDT_SHUTDOWN    0x02
 609 #define GDT_POLL_WAIT   0x80
 610     struct callout watchdog_timer;
 611     cdev_t sc_dev;
 612     bus_space_tag_t sc_dpmemt;
 613     bus_space_handle_t sc_dpmemh;
 614     bus_addr_t sc_dpmembase;
 615     bus_dma_tag_t sc_parent_dmat;
 616     bus_dma_tag_t sc_buffer_dmat;
 617     bus_dma_tag_t sc_gcscratch_dmat;
 618     bus_dmamap_t sc_gcscratch_dmamap;
 619     bus_addr_t sc_gcscratch_busbase;
 620
 621     struct gdt_ccb *sc_gccbs;
 622     u_int8_t  *sc_gcscratch;
 623     SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
 624     TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
 625     TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
 626
 627     u_int16_t sc_ic_all_size;
 628     u_int16_t sc_cmd_off;
 629     u_int16_t sc_cmd_cnt;
 630
 631     u_int32_t sc_info;
 632     u_int32_t sc_info2;
 633     u_int16_t sc_status;
 634     u_int16_t sc_service;
 635
 636     u_int8_t sc_bus_cnt;
 637     u_int8_t sc_virt_bus;
 638     u_int8_t sc_bus_id[GDT_MAXBUS];
 639     u_int8_t sc_more_proc;
 640
 641     struct {
 642         u_int8_t hd_present;
 643         u_int8_t hd_is_logdrv;
 644         u_int8_t hd_is_arraydrv;
 645         u_int8_t hd_is_master;
 646         u_int8_t hd_is_parity;
 647         u_int8_t hd_is_hotfix;
 648         u_int8_t hd_master_no;
 649         u_int8_t hd_lock;
 650         u_int8_t hd_heads;
 651         u_int8_t hd_secs;
 652         u_int16_t hd_devtype;
 653         u_int32_t hd_size;
 654         u_int8_t hd_ldr_no;
 655         u_int8_t hd_rw_attribs;
 656         u_int32_t hd_start_sec;
 657     } sc_hdr[GDT_MAX_HDRIVES];
 658
 659     u_int16_t sc_raw_feat;
 660     u_int16_t sc_cache_feat;
 661
 662     gdt_evt_data sc_dvr;
 663     char oem_name[8];
 664
 665     struct cam_sim *sims[GDT_MAXBUS];
 666     struct cam_path *paths[GDT_MAXBUS];
 667
 668     void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
 669     u_int8_t (*sc_get_status)(struct gdt_softc *);
 670     void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
 671     void (*sc_release_event)(struct gdt_softc *);
 672     void (*sc_set_sema0)(struct gdt_softc *);
 673     int (*sc_test_busy)(struct gdt_softc *);
 674
 675     TAILQ_ENTRY(gdt_softc) links;
 676 };
 677
 678 /*
 679  * A command control block, one for each corresponding command index of the
 680  * controller.
 681  */
 682 struct gdt_ccb {
 683     u_int8_t    *gc_scratch;
 684     bus_addr_t  gc_scratch_busbase;
 685     union ccb   *gc_ccb;
 686     gdt_ucmd_t  *gc_ucmd;
 687     bus_dmamap_t gc_dmamap;
 688     int         gc_map_flag;
 689     int         gc_timeout;
 690     u_int8_t    gc_service;
 691     u_int8_t    gc_cmd_index;
 692     u_int8_t    gc_flags;
 693 #define GDT_GCF_UNUSED          0
 694 #define GDT_GCF_INTERNAL        1
 695 #define GDT_GCF_SCREEN          2
 696 #define GDT_GCF_SCSI            3
 697 #define GDT_GCF_IOCTL           4
 698     u_int16_t   gc_cmd_len;
 699     u_int8_t    gc_cmd[GDT_CMD_SZ];
 700     SLIST_ENTRY(gdt_ccb) sle;
 701 };
 702
 703
 704 int     iir_init(struct gdt_softc *);
 705 void    iir_free(struct gdt_softc *);
 706 void    iir_attach(struct gdt_softc *);
 707 void    iir_intr(void *arg);
 708
 709 #ifdef __GNUC__
 710 /* These all require correctly aligned buffers */
 711 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
 712 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
 713 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
 714 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
 715
 716 static __inline__ void
 717 gdt_enc16(u_int8_t *addr, u_int16_t value)
 718 {
 719         *(u_int16_t *)addr = htole16(value);
 720 }
 721
 722 static __inline__ void
 723 gdt_enc32(u_int8_t *addr, u_int32_t value)
 724 {
 725         *(u_int32_t *)addr = htole32(value);
 726 }
 727
 728 static __inline__ u_int16_t
 729 gdt_dec16(u_int8_t *addr)
 730 {
 731         return le16toh(*(u_int16_t *)addr);
 732 }
 733
 734 static __inline__ u_int32_t
 735 gdt_dec32(u_int8_t *addr)
 736 {
 737         return le32toh(*(u_int32_t *)addr);
 738 }
 739 #endif
 740
 741 extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
 742 extern u_int8_t gdt_polling;
 743
 744 cdev_t   gdt_make_dev(int unit);
 745 void    gdt_destroy_dev(cdev_t dev);
 746 void    gdt_next(struct gdt_softc *gdt);
 747 void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
 748
 749 gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
 750                              gdt_evt_data *evt);
 751 int gdt_read_event(int handle, gdt_evt_str *estr);
 752 void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
 753 void gdt_clear_events(void);
 754
 755 #endif