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kernel - AHCI - enable AHCI device initiated power management
[dragonfly.git] / sys / dev / drm / r600_cp.c
blob9af4b71f4d221186fcc34fe23f6c941114508602
1 /*-
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29 #include "dev/drm/drmP.h"
30 #include "dev/drm/drm.h"
31 #include "dev/drm/radeon_drm.h"
32 #include "dev/drm/radeon_drv.h"
33
34 #include "dev/drm/r600_microcode.h"
35
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
38
39 #define R600_PTE_VALID (1 << 0)
40 #define R600_PTE_SYSTEM (1 << 1)
41 #define R600_PTE_SNOOPED (1 << 2)
42 #define R600_PTE_READABLE (1 << 5)
43 #define R600_PTE_WRITEABLE (1 << 6)
44
45 /* MAX values used for gfx init */
46 #define R6XX_MAX_SH_GPRS 256
47 #define R6XX_MAX_TEMP_GPRS 16
48 #define R6XX_MAX_SH_THREADS 256
49 #define R6XX_MAX_SH_STACK_ENTRIES 4096
50 #define R6XX_MAX_BACKENDS 8
51 #define R6XX_MAX_BACKENDS_MASK 0xff
52 #define R6XX_MAX_SIMDS 8
53 #define R6XX_MAX_SIMDS_MASK 0xff
54 #define R6XX_MAX_PIPES 8
55 #define R6XX_MAX_PIPES_MASK 0xff
56
57 #define R7XX_MAX_SH_GPRS 256
58 #define R7XX_MAX_TEMP_GPRS 16
59 #define R7XX_MAX_SH_THREADS 256
60 #define R7XX_MAX_SH_STACK_ENTRIES 4096
61 #define R7XX_MAX_BACKENDS 8
62 #define R7XX_MAX_BACKENDS_MASK 0xff
63 #define R7XX_MAX_SIMDS 16
64 #define R7XX_MAX_SIMDS_MASK 0xffff
65 #define R7XX_MAX_PIPES 8
66 #define R7XX_MAX_PIPES_MASK 0xff
67
68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
69 {
70 int i;
71
72 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
73
74 for (i = 0; i < dev_priv->usec_timeout; i++) {
75 int slots;
76 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
77 slots = (RADEON_READ(R600_GRBM_STATUS)
78 & R700_CMDFIFO_AVAIL_MASK);
79 else
80 slots = (RADEON_READ(R600_GRBM_STATUS)
81 & R600_CMDFIFO_AVAIL_MASK);
82 if (slots >= entries)
83 return 0;
84 DRM_UDELAY(1);
85 }
86 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
87 RADEON_READ(R600_GRBM_STATUS),
88 RADEON_READ(R600_GRBM_STATUS2));
89
90 return -EBUSY;
91 }
92
93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
94 {
95 int i, ret;
96
97 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
98
99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
100 ret = r600_do_wait_for_fifo(dev_priv, 8);
101 else
102 ret = r600_do_wait_for_fifo(dev_priv, 16);
103 if (ret)
104 return ret;
105 for (i = 0; i < dev_priv->usec_timeout; i++) {
106 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
107 return 0;
108 DRM_UDELAY(1);
109 }
110 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
111 RADEON_READ(R600_GRBM_STATUS),
112 RADEON_READ(R600_GRBM_STATUS2));
113
114 return -EBUSY;
115 }
116
117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
118 {
119 #ifdef __linux__
120 struct drm_sg_mem *entry = dev->sg;
121 int max_pages;
122 int pages;
123 int i;
124 #endif
125 if (gart_info->bus_addr) {
126 #ifdef __linux__
127 max_pages = (gart_info->table_size / sizeof(u32));
128 pages = (entry->pages <= max_pages)
129 ? entry->pages : max_pages;
130
131 for (i = 0; i < pages; i++) {
132 if (!entry->busaddr[i])
133 break;
134 pci_unmap_single(dev->pdev, entry->busaddr[i],
135 PAGE_SIZE, PCI_DMA_TODEVICE);
136 }
137 #endif
138 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
139 gart_info->bus_addr = 0;
140 }
141 }
142
143 /* R600 has page table setup */
144 int r600_page_table_init(struct drm_device *dev)
145 {
146 drm_radeon_private_t *dev_priv = dev->dev_private;
147 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
148 struct drm_sg_mem *entry = dev->sg;
149 int ret = 0;
150 int i, j;
151 int max_pages, pages;
152 u64 *pci_gart, page_base;
153 dma_addr_t entry_addr;
154
155 /* okay page table is available - lets rock */
156
157 /* PTEs are 64-bits */
158 pci_gart = (u64 *)gart_info->addr;
159
160 max_pages = (gart_info->table_size / sizeof(u64));
161 pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
162
163 memset(pci_gart, 0, max_pages * sizeof(u64));
164
165 for (i = 0; i < pages; i++) {
166 #ifdef __linux__
167 entry->busaddr[i] = pci_map_single(dev->pdev,
168 page_address(entry->
169 pagelist[i]),
170 PAGE_SIZE, PCI_DMA_TODEVICE);
171 if (entry->busaddr[i] == 0) {
172 DRM_ERROR("unable to map PCIGART pages!\n");
173 r600_page_table_cleanup(dev, gart_info);
174 goto done;
175 }
176 #endif
177 entry_addr = entry->busaddr[i];
178 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
179 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
180 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
181 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
182
183 *pci_gart = page_base;
184
185 if ((i % 128) == 0)
186 DRM_DEBUG("page entry %d: 0x%016llx\n",
187 i, (unsigned long long)page_base);
188 pci_gart++;
189 entry_addr += ATI_PCIGART_PAGE_SIZE;
190 }
191 }
192 ret = 1;
193 #ifdef __linux__
194 done:
195 #endif
196 return ret;
197 }
198
199 static void r600_vm_flush_gart_range(struct drm_device *dev)
200 {
201 drm_radeon_private_t *dev_priv = dev->dev_private;
202 u32 resp, countdown = 1000;
203 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
204 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
205 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
206
207 do {
208 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
209 countdown--;
210 DRM_UDELAY(1);
211 } while (((resp & 0xf0) == 0) && countdown);
212 }
213
214 static void r600_vm_init(struct drm_device *dev)
215 {
216 drm_radeon_private_t *dev_priv = dev->dev_private;
217 /* initialise the VM to use the page table we constructed up there */
218 u32 vm_c0, i;
219 u32 mc_rd_a;
220 u32 vm_l2_cntl, vm_l2_cntl3;
221 /* okay set up the PCIE aperture type thingo */
222 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
223 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
224 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
225
226 /* setup MC RD a */
227 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
228 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
229 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
230
231 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
232 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
233
234 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
235 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
236
237 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
238 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
239
240 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
241 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
242
243 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
244 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
245
246 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
247 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
248
249 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
250 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
251
252 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
253 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
254 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
255
256 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
257 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
258 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
259 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
260 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
261
262 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
263
264 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
265
266 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
267
268 /* disable all other contexts */
269 for (i = 1; i < 8; i++)
270 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
271
272 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
273 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
274 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
275
276 r600_vm_flush_gart_range(dev);
277 }
278
279 /* load r600 microcode */
280 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
281 {
282 const u32 (*cp)[3];
283 const u32 *pfp;
284 int i;
285
286 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
287 case CHIP_R600:
288 DRM_INFO("Loading R600 Microcode\n");
289 cp = R600_cp_microcode;
290 pfp = R600_pfp_microcode;
291 break;
292 case CHIP_RV610:
293 DRM_INFO("Loading RV610 Microcode\n");
294 cp = RV610_cp_microcode;
295 pfp = RV610_pfp_microcode;
296 break;
297 case CHIP_RV630:
298 DRM_INFO("Loading RV630 Microcode\n");
299 cp = RV630_cp_microcode;
300 pfp = RV630_pfp_microcode;
301 break;
302 case CHIP_RV620:
303 DRM_INFO("Loading RV620 Microcode\n");
304 cp = RV620_cp_microcode;
305 pfp = RV620_pfp_microcode;
306 break;
307 case CHIP_RV635:
308 DRM_INFO("Loading RV635 Microcode\n");
309 cp = RV635_cp_microcode;
310 pfp = RV635_pfp_microcode;
311 break;
312 case CHIP_RV670:
313 DRM_INFO("Loading RV670 Microcode\n");
314 cp = RV670_cp_microcode;
315 pfp = RV670_pfp_microcode;
316 break;
317 case CHIP_RS780:
318 case CHIP_RS880:
319 DRM_INFO("Loading RS780/RS880 Microcode\n");
320 cp = RS780_cp_microcode;
321 pfp = RS780_pfp_microcode;
322 break;
323 default:
324 return;
325 }
326
327 r600_do_cp_stop(dev_priv);
328
329 RADEON_WRITE(R600_CP_RB_CNTL,
330 R600_RB_NO_UPDATE |
331 R600_RB_BLKSZ(15) |
332 R600_RB_BUFSZ(3));
333
334 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
335 RADEON_READ(R600_GRBM_SOFT_RESET);
336 DRM_UDELAY(15000);
337 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
338
339 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
340
341 for (i = 0; i < PM4_UCODE_SIZE; i++) {
342 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
343 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
344 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
345 }
346
347 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
348 for (i = 0; i < PFP_UCODE_SIZE; i++)
349 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
350
351 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
352 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
353 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
354 }
355
356 static void r700_vm_init(struct drm_device *dev)
357 {
358 drm_radeon_private_t *dev_priv = dev->dev_private;
359 /* initialise the VM to use the page table we constructed up there */
360 u32 vm_c0, i;
361 u32 mc_vm_md_l1;
362 u32 vm_l2_cntl, vm_l2_cntl3;
363 /* okay set up the PCIE aperture type thingo */
364 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
365 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
366 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
367
368 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
369 R700_ENABLE_L1_FRAGMENT_PROCESSING |
370 R700_SYSTEM_ACCESS_MODE_IN_SYS |
371 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
372 R700_EFFECTIVE_L1_TLB_SIZE(5) |
373 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
374
375 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
376 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
377 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
378 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
379 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
380 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
381 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
382
383 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
384 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
385 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
386
387 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
388 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
389 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
390
391 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
392
393 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
394
395 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
396
397 /* disable all other contexts */
398 for (i = 1; i < 8; i++)
399 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
400
401 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
402 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
403 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
404
405 r600_vm_flush_gart_range(dev);
406 }
407
408 /* load r600 microcode */
409 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
410 {
411 const u32 *pfp;
412 const u32 *cp;
413 int i;
414
415 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
416 case CHIP_RV770:
417 DRM_INFO("Loading RV770/RV790 Microcode\n");
418 pfp = RV770_pfp_microcode;
419 cp = RV770_cp_microcode;
420 break;
421 case CHIP_RV730:
422 case CHIP_RV740:
423 DRM_INFO("Loading RV730/RV740 Microcode\n");
424 pfp = RV730_pfp_microcode;
425 cp = RV730_cp_microcode;
426 break;
427 case CHIP_RV710:
428 DRM_INFO("Loading RV710 Microcode\n");
429 pfp = RV710_pfp_microcode;
430 cp = RV710_cp_microcode;
431 break;
432 default:
433 return;
434 }
435
436 r600_do_cp_stop(dev_priv);
437
438 RADEON_WRITE(R600_CP_RB_CNTL,
439 R600_RB_NO_UPDATE |
440 (15 << 8) |
441 (3 << 0));
442
443 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
444 RADEON_READ(R600_GRBM_SOFT_RESET);
445 DRM_UDELAY(15000);
446 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
447
448 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
449 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
450 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
451 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
452
453 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
454 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
455 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
456 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
457
458 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
459 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
460 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
461 }
462
463 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
464 {
465 u32 tmp;
466
467 /* Start with assuming that writeback doesn't work */
468 dev_priv->writeback_works = 0;
469
470 /* Writeback doesn't seem to work everywhere, test it here and possibly
471 * enable it if it appears to work
472 */
473 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
474
475 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
476
477 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
478 u32 val;
479
480 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
481 if (val == 0xdeadbeef)
482 break;
483 DRM_UDELAY(1);
484 }
485
486 if (tmp < dev_priv->usec_timeout) {
487 dev_priv->writeback_works = 1;
488 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
489 } else {
490 dev_priv->writeback_works = 0;
491 DRM_INFO("writeback test failed\n");
492 }
493 if (radeon_no_wb == 1) {
494 dev_priv->writeback_works = 0;
495 DRM_INFO("writeback forced off\n");
496 }
497
498 if (!dev_priv->writeback_works) {
499 /* Disable writeback to avoid unnecessary bus master transfer */
500 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
501 RADEON_RB_NO_UPDATE);
502 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
503 }
504 }
505
506 int r600_do_engine_reset(struct drm_device *dev)
507 {
508 drm_radeon_private_t *dev_priv = dev->dev_private;
509 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
510
511 DRM_INFO("Resetting GPU\n");
512
513 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
514 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
515 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
516
517 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
518 RADEON_READ(R600_GRBM_SOFT_RESET);
519 DRM_UDELAY(50);
520 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
521 RADEON_READ(R600_GRBM_SOFT_RESET);
522
523 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
524 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
525 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
526
527 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
528 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
529 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
530 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
531
532 /* Reset the CP ring */
533 r600_do_cp_reset(dev_priv);
534
535 /* The CP is no longer running after an engine reset */
536 dev_priv->cp_running = 0;
537
538 /* Reset any pending vertex, indirect buffers */
539 radeon_freelist_reset(dev);
540
541 return 0;
542
543 }
544
545 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
546 u32 num_backends,
547 u32 backend_disable_mask)
548 {
549 u32 backend_map = 0;
550 u32 enabled_backends_mask;
551 u32 enabled_backends_count;
552 u32 cur_pipe;
553 u32 swizzle_pipe[R6XX_MAX_PIPES];
554 u32 cur_backend;
555 u32 i;
556
557 if (num_tile_pipes > R6XX_MAX_PIPES)
558 num_tile_pipes = R6XX_MAX_PIPES;
559 if (num_tile_pipes < 1)
560 num_tile_pipes = 1;
561 if (num_backends > R6XX_MAX_BACKENDS)
562 num_backends = R6XX_MAX_BACKENDS;
563 if (num_backends < 1)
564 num_backends = 1;
565
566 enabled_backends_mask = 0;
567 enabled_backends_count = 0;
568 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
569 if (((backend_disable_mask >> i) & 1) == 0) {
570 enabled_backends_mask |= (1 << i);
571 ++enabled_backends_count;
572 }
573 if (enabled_backends_count == num_backends)
574 break;
575 }
576
577 if (enabled_backends_count == 0) {
578 enabled_backends_mask = 1;
579 enabled_backends_count = 1;
580 }
581
582 if (enabled_backends_count != num_backends)
583 num_backends = enabled_backends_count;
584
585 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
586 switch (num_tile_pipes) {
587 case 1:
588 swizzle_pipe[0] = 0;
589 break;
590 case 2:
591 swizzle_pipe[0] = 0;
592 swizzle_pipe[1] = 1;
593 break;
594 case 3:
595 swizzle_pipe[0] = 0;
596 swizzle_pipe[1] = 1;
597 swizzle_pipe[2] = 2;
598 break;
599 case 4:
600 swizzle_pipe[0] = 0;
601 swizzle_pipe[1] = 1;
602 swizzle_pipe[2] = 2;
603 swizzle_pipe[3] = 3;
604 break;
605 case 5:
606 swizzle_pipe[0] = 0;
607 swizzle_pipe[1] = 1;
608 swizzle_pipe[2] = 2;
609 swizzle_pipe[3] = 3;
610 swizzle_pipe[4] = 4;
611 break;
612 case 6:
613 swizzle_pipe[0] = 0;
614 swizzle_pipe[1] = 2;
615 swizzle_pipe[2] = 4;
616 swizzle_pipe[3] = 5;
617 swizzle_pipe[4] = 1;
618 swizzle_pipe[5] = 3;
619 break;
620 case 7:
621 swizzle_pipe[0] = 0;
622 swizzle_pipe[1] = 2;
623 swizzle_pipe[2] = 4;
624 swizzle_pipe[3] = 6;
625 swizzle_pipe[4] = 1;
626 swizzle_pipe[5] = 3;
627 swizzle_pipe[6] = 5;
628 break;
629 case 8:
630 swizzle_pipe[0] = 0;
631 swizzle_pipe[1] = 2;
632 swizzle_pipe[2] = 4;
633 swizzle_pipe[3] = 6;
634 swizzle_pipe[4] = 1;
635 swizzle_pipe[5] = 3;
636 swizzle_pipe[6] = 5;
637 swizzle_pipe[7] = 7;
638 break;
639 }
640
641 cur_backend = 0;
642 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
643 while (((1 << cur_backend) & enabled_backends_mask) == 0)
644 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
645
646 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
647
648 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
649 }
650
651 return backend_map;
652 }
653
654 static int r600_count_pipe_bits(uint32_t val)
655 {
656 int i, ret = 0;
657 for (i = 0; i < 32; i++) {
658 ret += val & 1;
659 val >>= 1;
660 }
661 return ret;
662 }
663
664 static void r600_gfx_init(struct drm_device *dev,
665 drm_radeon_private_t *dev_priv)
666 {
667 int i, j, num_qd_pipes;
668 u32 sx_debug_1;
669 u32 tc_cntl;
670 u32 arb_pop;
671 u32 num_gs_verts_per_thread;
672 u32 vgt_gs_per_es;
673 u32 gs_prim_buffer_depth = 0;
674 u32 sq_ms_fifo_sizes;
675 u32 sq_config;
676 u32 sq_gpr_resource_mgmt_1 = 0;
677 u32 sq_gpr_resource_mgmt_2 = 0;
678 u32 sq_thread_resource_mgmt = 0;
679 u32 sq_stack_resource_mgmt_1 = 0;
680 u32 sq_stack_resource_mgmt_2 = 0;
681 u32 hdp_host_path_cntl;
682 u32 backend_map;
683 u32 gb_tiling_config = 0;
684 u32 cc_rb_backend_disable = 0;
685 u32 cc_gc_shader_pipe_config = 0;
686 u32 ramcfg;
687
688 /* setup chip specs */
689 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
690 case CHIP_R600:
691 dev_priv->r600_max_pipes = 4;
692 dev_priv->r600_max_tile_pipes = 8;
693 dev_priv->r600_max_simds = 4;
694 dev_priv->r600_max_backends = 4;
695 dev_priv->r600_max_gprs = 256;
696 dev_priv->r600_max_threads = 192;
697 dev_priv->r600_max_stack_entries = 256;
698 dev_priv->r600_max_hw_contexts = 8;
699 dev_priv->r600_max_gs_threads = 16;
700 dev_priv->r600_sx_max_export_size = 128;
701 dev_priv->r600_sx_max_export_pos_size = 16;
702 dev_priv->r600_sx_max_export_smx_size = 128;
703 dev_priv->r600_sq_num_cf_insts = 2;
704 break;
705 case CHIP_RV630:
706 case CHIP_RV635:
707 dev_priv->r600_max_pipes = 2;
708 dev_priv->r600_max_tile_pipes = 2;
709 dev_priv->r600_max_simds = 3;
710 dev_priv->r600_max_backends = 1;
711 dev_priv->r600_max_gprs = 128;
712 dev_priv->r600_max_threads = 192;
713 dev_priv->r600_max_stack_entries = 128;
714 dev_priv->r600_max_hw_contexts = 8;
715 dev_priv->r600_max_gs_threads = 4;
716 dev_priv->r600_sx_max_export_size = 128;
717 dev_priv->r600_sx_max_export_pos_size = 16;
718 dev_priv->r600_sx_max_export_smx_size = 128;
719 dev_priv->r600_sq_num_cf_insts = 2;
720 break;
721 case CHIP_RV610:
722 case CHIP_RS780:
723 case CHIP_RS880:
724 case CHIP_RV620:
725 dev_priv->r600_max_pipes = 1;
726 dev_priv->r600_max_tile_pipes = 1;
727 dev_priv->r600_max_simds = 2;
728 dev_priv->r600_max_backends = 1;
729 dev_priv->r600_max_gprs = 128;
730 dev_priv->r600_max_threads = 192;
731 dev_priv->r600_max_stack_entries = 128;
732 dev_priv->r600_max_hw_contexts = 4;
733 dev_priv->r600_max_gs_threads = 4;
734 dev_priv->r600_sx_max_export_size = 128;
735 dev_priv->r600_sx_max_export_pos_size = 16;
736 dev_priv->r600_sx_max_export_smx_size = 128;
737 dev_priv->r600_sq_num_cf_insts = 1;
738 break;
739 case CHIP_RV670:
740 dev_priv->r600_max_pipes = 4;
741 dev_priv->r600_max_tile_pipes = 4;
742 dev_priv->r600_max_simds = 4;
743 dev_priv->r600_max_backends = 4;
744 dev_priv->r600_max_gprs = 192;
745 dev_priv->r600_max_threads = 192;
746 dev_priv->r600_max_stack_entries = 256;
747 dev_priv->r600_max_hw_contexts = 8;
748 dev_priv->r600_max_gs_threads = 16;
749 dev_priv->r600_sx_max_export_size = 128;
750 dev_priv->r600_sx_max_export_pos_size = 16;
751 dev_priv->r600_sx_max_export_smx_size = 128;
752 dev_priv->r600_sq_num_cf_insts = 2;
753 break;
754 default:
755 break;
756 }
757
758 /* Initialize HDP */
759 j = 0;
760 for (i = 0; i < 32; i++) {
761 RADEON_WRITE((0x2c14 + j), 0x00000000);
762 RADEON_WRITE((0x2c18 + j), 0x00000000);
763 RADEON_WRITE((0x2c1c + j), 0x00000000);
764 RADEON_WRITE((0x2c20 + j), 0x00000000);
765 RADEON_WRITE((0x2c24 + j), 0x00000000);
766 j += 0x18;
767 }
768
769 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
770
771 /* setup tiling, simd, pipe config */
772 ramcfg = RADEON_READ(R600_RAMCFG);
773
774 switch (dev_priv->r600_max_tile_pipes) {
775 case 1:
776 gb_tiling_config |= R600_PIPE_TILING(0);
777 break;
778 case 2:
779 gb_tiling_config |= R600_PIPE_TILING(1);
780 break;
781 case 4:
782 gb_tiling_config |= R600_PIPE_TILING(2);
783 break;
784 case 8:
785 gb_tiling_config |= R600_PIPE_TILING(3);
786 break;
787 default:
788 break;
789 }
790
791 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
792
793 gb_tiling_config |= R600_GROUP_SIZE(0);
794
795 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
796 gb_tiling_config |= R600_ROW_TILING(3);
797 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
798 } else {
799 gb_tiling_config |=
800 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
801 gb_tiling_config |=
802 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
803 }
804
805 gb_tiling_config |= R600_BANK_SWAPS(1);
806
807 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
808 dev_priv->r600_max_backends,
809 (0xff << dev_priv->r600_max_backends) & 0xff);
810 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
811
812 cc_gc_shader_pipe_config =
813 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
814 cc_gc_shader_pipe_config |=
815 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
816
817 cc_rb_backend_disable =
818 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
819
820 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
821 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
822 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
823
824 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
825 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
826 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
827
828 num_qd_pipes =
829 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
830 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
831 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
832
833 /* set HW defaults for 3D engine */
834 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
835 R600_ROQ_IB2_START(0x2b)));
836
837 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
838 R600_ROQ_END(0x40)));
839
840 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
841 R600_SYNC_GRADIENT |
842 R600_SYNC_WALKER |
843 R600_SYNC_ALIGNER));
844
845 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
846 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
847
848 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
849 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
850 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
851 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
852 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
853
854 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
855 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
856 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
857 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
858 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
859 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
860 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
861 else
862 RADEON_WRITE(R600_DB_DEBUG, 0);
863
864 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
865 R600_DEPTH_FLUSH(16) |
866 R600_DEPTH_PENDING_FREE(4) |
867 R600_DEPTH_CACHELINE_FREE(16)));
868 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
869 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
870
871 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
872 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
873
874 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
875 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
876 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
877 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
878 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
879 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
880 R600_FETCH_FIFO_HIWATER(0xa) |
881 R600_DONE_FIFO_HIWATER(0xe0) |
882 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
883 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
884 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
885 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
886 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
887 }
888 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
889
890 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
891 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
892 */
893 sq_config = RADEON_READ(R600_SQ_CONFIG);
894 sq_config &= ~(R600_PS_PRIO(3) |
895 R600_VS_PRIO(3) |
896 R600_GS_PRIO(3) |
897 R600_ES_PRIO(3));
898 sq_config |= (R600_DX9_CONSTS |
899 R600_VC_ENABLE |
900 R600_PS_PRIO(0) |
901 R600_VS_PRIO(1) |
902 R600_GS_PRIO(2) |
903 R600_ES_PRIO(3));
904
905 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
906 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
907 R600_NUM_VS_GPRS(124) |
908 R600_NUM_CLAUSE_TEMP_GPRS(4));
909 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
910 R600_NUM_ES_GPRS(0));
911 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
912 R600_NUM_VS_THREADS(48) |
913 R600_NUM_GS_THREADS(4) |
914 R600_NUM_ES_THREADS(4));
915 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
916 R600_NUM_VS_STACK_ENTRIES(128));
917 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
918 R600_NUM_ES_STACK_ENTRIES(0));
919 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
922 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
923 /* no vertex cache */
924 sq_config &= ~R600_VC_ENABLE;
925
926 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
927 R600_NUM_VS_GPRS(44) |
928 R600_NUM_CLAUSE_TEMP_GPRS(2));
929 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
930 R600_NUM_ES_GPRS(17));
931 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
932 R600_NUM_VS_THREADS(78) |
933 R600_NUM_GS_THREADS(4) |
934 R600_NUM_ES_THREADS(31));
935 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
936 R600_NUM_VS_STACK_ENTRIES(40));
937 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
938 R600_NUM_ES_STACK_ENTRIES(16));
939 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
941 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
942 R600_NUM_VS_GPRS(44) |
943 R600_NUM_CLAUSE_TEMP_GPRS(2));
944 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
945 R600_NUM_ES_GPRS(18));
946 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
947 R600_NUM_VS_THREADS(78) |
948 R600_NUM_GS_THREADS(4) |
949 R600_NUM_ES_THREADS(31));
950 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
951 R600_NUM_VS_STACK_ENTRIES(40));
952 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
953 R600_NUM_ES_STACK_ENTRIES(16));
954 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
955 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
956 R600_NUM_VS_GPRS(44) |
957 R600_NUM_CLAUSE_TEMP_GPRS(2));
958 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
959 R600_NUM_ES_GPRS(17));
960 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
961 R600_NUM_VS_THREADS(78) |
962 R600_NUM_GS_THREADS(4) |
963 R600_NUM_ES_THREADS(31));
964 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
965 R600_NUM_VS_STACK_ENTRIES(64));
966 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
967 R600_NUM_ES_STACK_ENTRIES(64));
968 }
969
970 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
971 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
972 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
973 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
974 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
975 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
976
977 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
978 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
979 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
980 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
981 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
982 else
983 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
984
985 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
986 R600_S0_Y(0x4) |
987 R600_S1_X(0x4) |
988 R600_S1_Y(0xc)));
989 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
990 R600_S0_Y(0xe) |
991 R600_S1_X(0x2) |
992 R600_S1_Y(0x2) |
993 R600_S2_X(0xa) |
994 R600_S2_Y(0x6) |
995 R600_S3_X(0x6) |
996 R600_S3_Y(0xa)));
997 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
998 R600_S0_Y(0xb) |
999 R600_S1_X(0x4) |
1000 R600_S1_Y(0xc) |
1001 R600_S2_X(0x1) |
1002 R600_S2_Y(0x6) |
1003 R600_S3_X(0xa) |
1004 R600_S3_Y(0xe)));
1005 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1006 R600_S4_Y(0x1) |
1007 R600_S5_X(0x0) |
1008 R600_S5_Y(0x0) |
1009 R600_S6_X(0xb) |
1010 R600_S6_Y(0x4) |
1011 R600_S7_X(0x7) |
1012 R600_S7_Y(0x8)));
1013
1014
1015 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1016 case CHIP_R600:
1017 case CHIP_RV630:
1018 case CHIP_RV635:
1019 gs_prim_buffer_depth = 0;
1020 break;
1021 case CHIP_RV610:
1022 case CHIP_RS780:
1023 case CHIP_RS880:
1024 case CHIP_RV620:
1025 gs_prim_buffer_depth = 32;
1026 break;
1027 case CHIP_RV670:
1028 gs_prim_buffer_depth = 128;
1029 break;
1030 default:
1031 break;
1032 }
1033
1034 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1035 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1036 /* Max value for this is 256 */
1037 if (vgt_gs_per_es > 256)
1038 vgt_gs_per_es = 256;
1039
1040 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1041 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1042 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1043 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1044
1045 /* more default values. 2D/3D driver should adjust as needed */
1046 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1047 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1048 RADEON_WRITE(R600_SX_MISC, 0);
1049 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1050 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1051 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1052 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1053 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1054 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1055
1056 /* clear render buffer base addresses */
1057 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1058 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1059 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1060 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1061 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1062 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1063 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1064 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1065
1066 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1067 case CHIP_RV610:
1068 case CHIP_RS780:
1069 case CHIP_RS880:
1070 case CHIP_RV620:
1071 tc_cntl = R600_TC_L2_SIZE(8);
1072 break;
1073 case CHIP_RV630:
1074 case CHIP_RV635:
1075 tc_cntl = R600_TC_L2_SIZE(4);
1076 break;
1077 case CHIP_R600:
1078 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1079 break;
1080 default:
1081 tc_cntl = R600_TC_L2_SIZE(0);
1082 break;
1083 }
1084
1085 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1086
1087 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1088 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1089
1090 arb_pop = RADEON_READ(R600_ARB_POP);
1091 arb_pop |= R600_ENABLE_TC128;
1092 RADEON_WRITE(R600_ARB_POP, arb_pop);
1093
1094 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1095 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1096 R600_NUM_CLIP_SEQ(3)));
1097 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1098
1099 }
1100
1101 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1102 u32 num_backends,
1103 u32 backend_disable_mask)
1104 {
1105 u32 backend_map = 0;
1106 u32 enabled_backends_mask;
1107 u32 enabled_backends_count;
1108 u32 cur_pipe;
1109 u32 swizzle_pipe[R7XX_MAX_PIPES];
1110 u32 cur_backend;
1111 u32 i;
1112
1113 if (num_tile_pipes > R7XX_MAX_PIPES)
1114 num_tile_pipes = R7XX_MAX_PIPES;
1115 if (num_tile_pipes < 1)
1116 num_tile_pipes = 1;
1117 if (num_backends > R7XX_MAX_BACKENDS)
1118 num_backends = R7XX_MAX_BACKENDS;
1119 if (num_backends < 1)
1120 num_backends = 1;
1121
1122 enabled_backends_mask = 0;
1123 enabled_backends_count = 0;
1124 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1125 if (((backend_disable_mask >> i) & 1) == 0) {
1126 enabled_backends_mask |= (1 << i);
1127 ++enabled_backends_count;
1128 }
1129 if (enabled_backends_count == num_backends)
1130 break;
1131 }
1132
1133 if (enabled_backends_count == 0) {
1134 enabled_backends_mask = 1;
1135 enabled_backends_count = 1;
1136 }
1137
1138 if (enabled_backends_count != num_backends)
1139 num_backends = enabled_backends_count;
1140
1141 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1142 switch (num_tile_pipes) {
1143 case 1:
1144 swizzle_pipe[0] = 0;
1145 break;
1146 case 2:
1147 swizzle_pipe[0] = 0;
1148 swizzle_pipe[1] = 1;
1149 break;
1150 case 3:
1151 swizzle_pipe[0] = 0;
1152 swizzle_pipe[1] = 2;
1153 swizzle_pipe[2] = 1;
1154 break;
1155 case 4:
1156 swizzle_pipe[0] = 0;
1157 swizzle_pipe[1] = 2;
1158 swizzle_pipe[2] = 3;
1159 swizzle_pipe[3] = 1;
1160 break;
1161 case 5:
1162 swizzle_pipe[0] = 0;
1163 swizzle_pipe[1] = 2;
1164 swizzle_pipe[2] = 4;
1165 swizzle_pipe[3] = 1;
1166 swizzle_pipe[4] = 3;
1167 break;
1168 case 6:
1169 swizzle_pipe[0] = 0;
1170 swizzle_pipe[1] = 2;
1171 swizzle_pipe[2] = 4;
1172 swizzle_pipe[3] = 5;
1173 swizzle_pipe[4] = 3;
1174 swizzle_pipe[5] = 1;
1175 break;
1176 case 7:
1177 swizzle_pipe[0] = 0;
1178 swizzle_pipe[1] = 2;
1179 swizzle_pipe[2] = 4;
1180 swizzle_pipe[3] = 6;
1181 swizzle_pipe[4] = 3;
1182 swizzle_pipe[5] = 1;
1183 swizzle_pipe[6] = 5;
1184 break;
1185 case 8:
1186 swizzle_pipe[0] = 0;
1187 swizzle_pipe[1] = 2;
1188 swizzle_pipe[2] = 4;
1189 swizzle_pipe[3] = 6;
1190 swizzle_pipe[4] = 3;
1191 swizzle_pipe[5] = 1;
1192 swizzle_pipe[6] = 7;
1193 swizzle_pipe[7] = 5;
1194 break;
1195 }
1196
1197 cur_backend = 0;
1198 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1199 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1200 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1201
1202 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1203
1204 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1205 }
1206
1207 return backend_map;
1208 }
1209
1210 static void r700_gfx_init(struct drm_device *dev,
1211 drm_radeon_private_t *dev_priv)
1212 {
1213 int i, j, num_qd_pipes;
1214 u32 sx_debug_1;
1215 u32 smx_dc_ctl0;
1216 u32 num_gs_verts_per_thread;
1217 u32 vgt_gs_per_es;
1218 u32 gs_prim_buffer_depth = 0;
1219 u32 sq_ms_fifo_sizes;
1220 u32 sq_config;
1221 u32 sq_thread_resource_mgmt;
1222 u32 hdp_host_path_cntl;
1223 u32 sq_dyn_gpr_size_simd_ab_0;
1224 u32 backend_map;
1225 u32 gb_tiling_config = 0;
1226 u32 cc_rb_backend_disable = 0;
1227 u32 cc_gc_shader_pipe_config = 0;
1228 u32 mc_arb_ramcfg;
1229 u32 db_debug4;
1230
1231 /* setup chip specs */
1232 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1233 case CHIP_RV770:
1234 dev_priv->r600_max_pipes = 4;
1235 dev_priv->r600_max_tile_pipes = 8;
1236 dev_priv->r600_max_simds = 10;
1237 dev_priv->r600_max_backends = 4;
1238 dev_priv->r600_max_gprs = 256;
1239 dev_priv->r600_max_threads = 248;
1240 dev_priv->r600_max_stack_entries = 512;
1241 dev_priv->r600_max_hw_contexts = 8;
1242 dev_priv->r600_max_gs_threads = 16 * 2;
1243 dev_priv->r600_sx_max_export_size = 128;
1244 dev_priv->r600_sx_max_export_pos_size = 16;
1245 dev_priv->r600_sx_max_export_smx_size = 112;
1246 dev_priv->r600_sq_num_cf_insts = 2;
1247
1248 dev_priv->r700_sx_num_of_sets = 7;
1249 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1250 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1251 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1252 break;
1253 case CHIP_RV740:
1254 dev_priv->r600_max_pipes = 4;
1255 dev_priv->r600_max_tile_pipes = 4;
1256 dev_priv->r600_max_simds = 8;
1257 dev_priv->r600_max_backends = 4;
1258 dev_priv->r600_max_gprs = 256;
1259 dev_priv->r600_max_threads = 248;
1260 dev_priv->r600_max_stack_entries = 512;
1261 dev_priv->r600_max_hw_contexts = 8;
1262 dev_priv->r600_max_gs_threads = 16 * 2;
1263 dev_priv->r600_sx_max_export_size = 256;
1264 dev_priv->r600_sx_max_export_pos_size = 32;
1265 dev_priv->r600_sx_max_export_smx_size = 224;
1266 dev_priv->r600_sq_num_cf_insts = 2;
1267
1268 dev_priv->r700_sx_num_of_sets = 7;
1269 dev_priv->r700_sc_prim_fifo_size = 0x100;
1270 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1271 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1272
1273 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1274 dev_priv->r600_sx_max_export_pos_size -= 16;
1275 dev_priv->r600_sx_max_export_smx_size += 16;
1276 }
1277 break;
1278 case CHIP_RV730:
1279 dev_priv->r600_max_pipes = 2;
1280 dev_priv->r600_max_tile_pipes = 4;
1281 dev_priv->r600_max_simds = 8;
1282 dev_priv->r600_max_backends = 2;
1283 dev_priv->r600_max_gprs = 128;
1284 dev_priv->r600_max_threads = 248;
1285 dev_priv->r600_max_stack_entries = 256;
1286 dev_priv->r600_max_hw_contexts = 8;
1287 dev_priv->r600_max_gs_threads = 16 * 2;
1288 dev_priv->r600_sx_max_export_size = 256;
1289 dev_priv->r600_sx_max_export_pos_size = 32;
1290 dev_priv->r600_sx_max_export_smx_size = 224;
1291 dev_priv->r600_sq_num_cf_insts = 2;
1292
1293 dev_priv->r700_sx_num_of_sets = 7;
1294 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1295 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1296 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1297
1298 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1299 dev_priv->r600_sx_max_export_pos_size -= 16;
1300 dev_priv->r600_sx_max_export_smx_size += 16;
1301 }
1302 break;
1303 case CHIP_RV710:
1304 dev_priv->r600_max_pipes = 2;
1305 dev_priv->r600_max_tile_pipes = 2;
1306 dev_priv->r600_max_simds = 2;
1307 dev_priv->r600_max_backends = 1;
1308 dev_priv->r600_max_gprs = 256;
1309 dev_priv->r600_max_threads = 192;
1310 dev_priv->r600_max_stack_entries = 256;
1311 dev_priv->r600_max_hw_contexts = 4;
1312 dev_priv->r600_max_gs_threads = 8 * 2;
1313 dev_priv->r600_sx_max_export_size = 128;
1314 dev_priv->r600_sx_max_export_pos_size = 16;
1315 dev_priv->r600_sx_max_export_smx_size = 112;
1316 dev_priv->r600_sq_num_cf_insts = 1;
1317
1318 dev_priv->r700_sx_num_of_sets = 7;
1319 dev_priv->r700_sc_prim_fifo_size = 0x40;
1320 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1321 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1322 break;
1323 default:
1324 break;
1325 }
1326
1327 /* Initialize HDP */
1328 j = 0;
1329 for (i = 0; i < 32; i++) {
1330 RADEON_WRITE((0x2c14 + j), 0x00000000);
1331 RADEON_WRITE((0x2c18 + j), 0x00000000);
1332 RADEON_WRITE((0x2c1c + j), 0x00000000);
1333 RADEON_WRITE((0x2c20 + j), 0x00000000);
1334 RADEON_WRITE((0x2c24 + j), 0x00000000);
1335 j += 0x18;
1336 }
1337
1338 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1339
1340 /* setup tiling, simd, pipe config */
1341 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1342
1343 switch (dev_priv->r600_max_tile_pipes) {
1344 case 1:
1345 gb_tiling_config |= R600_PIPE_TILING(0);
1346 break;
1347 case 2:
1348 gb_tiling_config |= R600_PIPE_TILING(1);
1349 break;
1350 case 4:
1351 gb_tiling_config |= R600_PIPE_TILING(2);
1352 break;
1353 case 8:
1354 gb_tiling_config |= R600_PIPE_TILING(3);
1355 break;
1356 default:
1357 break;
1358 }
1359
1360 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1361 gb_tiling_config |= R600_BANK_TILING(1);
1362 else
1363 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1364
1365 gb_tiling_config |= R600_GROUP_SIZE(0);
1366
1367 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1368 gb_tiling_config |= R600_ROW_TILING(3);
1369 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1370 } else {
1371 gb_tiling_config |=
1372 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1373 gb_tiling_config |=
1374 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1375 }
1376
1377 gb_tiling_config |= R600_BANK_SWAPS(1);
1378
1379 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1380 dev_priv->r600_max_backends,
1381 (0xff << dev_priv->r600_max_backends) & 0xff);
1382 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1383
1384 cc_gc_shader_pipe_config =
1385 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1386 cc_gc_shader_pipe_config |=
1387 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1388
1389 cc_rb_backend_disable =
1390 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1391
1392 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1393 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1394 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1395
1396 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1397 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1398 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1399
1400 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1401 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1402 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1403 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1404 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1405
1406 num_qd_pipes =
1407 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1408 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1409 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1410
1411 /* set HW defaults for 3D engine */
1412 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1413 R600_ROQ_IB2_START(0x2b)));
1414
1415 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1416
1417 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1418 R600_SYNC_GRADIENT |
1419 R600_SYNC_WALKER |
1420 R600_SYNC_ALIGNER));
1421
1422 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1423 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1424 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1425
1426 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1427 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1428 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1429 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1430
1431 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1432 R700_GS_FLUSH_CTL(4) |
1433 R700_ACK_FLUSH_CTL(3) |
1434 R700_SYNC_FLUSH_CTL));
1435
1436 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1437 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1438 else {
1439 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1440 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1441 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1442 }
1443
1444 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1445 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1446 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1447
1448 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1449 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1450 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1451
1452 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1453
1454 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1455
1456 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1457
1458 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1459
1460 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1461
1462 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1463 R600_DONE_FIFO_HIWATER(0xe0) |
1464 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1465 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1466 case CHIP_RV770:
1467 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1468 break;
1469 case CHIP_RV740:
1470 case CHIP_RV730:
1471 case CHIP_RV710:
1472 default:
1473 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1474 break;
1475 }
1476 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1477
1478 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1479 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1480 */
1481 sq_config = RADEON_READ(R600_SQ_CONFIG);
1482 sq_config &= ~(R600_PS_PRIO(3) |
1483 R600_VS_PRIO(3) |
1484 R600_GS_PRIO(3) |
1485 R600_ES_PRIO(3));
1486 sq_config |= (R600_DX9_CONSTS |
1487 R600_VC_ENABLE |
1488 R600_EXPORT_SRC_C |
1489 R600_PS_PRIO(0) |
1490 R600_VS_PRIO(1) |
1491 R600_GS_PRIO(2) |
1492 R600_ES_PRIO(3));
1493 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1494 /* no vertex cache */
1495 sq_config &= ~R600_VC_ENABLE;
1496
1497 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1498
1499 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1500 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1501 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1502
1503 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1504 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1505
1506 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1507 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1508 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1509 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1510 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1511 else
1512 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1513 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1514
1515 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1516 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1517
1518 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1519 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1520
1521 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1522 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1523 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1524 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1525
1526 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1527 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1528 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1529 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1530 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1531 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1532 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1533 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1534
1535 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1536 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1537
1538 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1539 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1540 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1541 else
1542 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1543 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1544
1545 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1546 case CHIP_RV770:
1547 case CHIP_RV740:
1548 case CHIP_RV730:
1549 gs_prim_buffer_depth = 384;
1550 break;
1551 case CHIP_RV710:
1552 gs_prim_buffer_depth = 128;
1553 break;
1554 default:
1555 break;
1556 }
1557
1558 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1559 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1560 /* Max value for this is 256 */
1561 if (vgt_gs_per_es > 256)
1562 vgt_gs_per_es = 256;
1563
1564 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1565 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1566 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1567
1568 /* more default values. 2D/3D driver should adjust as needed */
1569 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1570 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1571 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1572 RADEON_WRITE(R600_SX_MISC, 0);
1573 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1574 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1575 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1576 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1577 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1578 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1579 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1580 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1581
1582 /* clear render buffer base addresses */
1583 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1584 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1585 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1586 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1587 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1588 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1589 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1590 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1591
1592 RADEON_WRITE(R700_TCP_CNTL, 0);
1593
1594 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1595 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1596
1597 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1598
1599 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1600 R600_NUM_CLIP_SEQ(3)));
1601
1602 }
1603
1604 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1605 drm_radeon_private_t *dev_priv,
1606 struct drm_file *file_priv)
1607 {
1608 u32 ring_start;
1609 u64 rptr_addr;
1610
1611 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1612 r700_gfx_init(dev, dev_priv);
1613 else
1614 r600_gfx_init(dev, dev_priv);
1615
1616 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1617 RADEON_READ(R600_GRBM_SOFT_RESET);
1618 DRM_UDELAY(15000);
1619 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1620
1621
1622 /* Set ring buffer size */
1623 #ifdef __BIG_ENDIAN
1624 RADEON_WRITE(R600_CP_RB_CNTL,
1625 RADEON_BUF_SWAP_32BIT |
1626 RADEON_RB_NO_UPDATE |
1627 (dev_priv->ring.rptr_update_l2qw << 8) |
1628 dev_priv->ring.size_l2qw);
1629 #else
1630 RADEON_WRITE(R600_CP_RB_CNTL,
1631 RADEON_RB_NO_UPDATE |
1632 (dev_priv->ring.rptr_update_l2qw << 8) |
1633 dev_priv->ring.size_l2qw);
1634 #endif
1635
1636 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1637
1638 /* Set the write pointer delay */
1639 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1640
1641 #ifdef __BIG_ENDIAN
1642 RADEON_WRITE(R600_CP_RB_CNTL,
1643 RADEON_BUF_SWAP_32BIT |
1644 RADEON_RB_NO_UPDATE |
1645 RADEON_RB_RPTR_WR_ENA |
1646 (dev_priv->ring.rptr_update_l2qw << 8) |
1647 dev_priv->ring.size_l2qw);
1648 #else
1649 RADEON_WRITE(R600_CP_RB_CNTL,
1650 RADEON_RB_NO_UPDATE |
1651 RADEON_RB_RPTR_WR_ENA |
1652 (dev_priv->ring.rptr_update_l2qw << 8) |
1653 dev_priv->ring.size_l2qw);
1654 #endif
1655
1656 /* Initialize the ring buffer's read and write pointers */
1657 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1658 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1659 SET_RING_HEAD(dev_priv, 0);
1660 dev_priv->ring.tail = 0;
1661
1662 #if __OS_HAS_AGP
1663 if (dev_priv->flags & RADEON_IS_AGP) {
1664 rptr_addr = dev_priv->ring_rptr->offset
1665 - dev->agp->base +
1666 dev_priv->gart_vm_start;
1667 } else
1668 #endif
1669 {
1670 rptr_addr = dev_priv->ring_rptr->offset
1671 - ((unsigned long) dev->sg->virtual)
1672 + dev_priv->gart_vm_start;
1673 }
1674 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1675 rptr_addr & 0xffffffff);
1676 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1677 upper_32_bits(rptr_addr));
1678
1679 #ifdef __BIG_ENDIAN
1680 RADEON_WRITE(R600_CP_RB_CNTL,
1681 RADEON_BUF_SWAP_32BIT |
1682 (dev_priv->ring.rptr_update_l2qw << 8) |
1683 dev_priv->ring.size_l2qw);
1684 #else
1685 RADEON_WRITE(R600_CP_RB_CNTL,
1686 (dev_priv->ring.rptr_update_l2qw << 8) |
1687 dev_priv->ring.size_l2qw);
1688 #endif
1689
1690 #if __OS_HAS_AGP
1691 if (dev_priv->flags & RADEON_IS_AGP) {
1692 /* XXX */
1693 radeon_write_agp_base(dev_priv, dev->agp->base);
1694
1695 /* XXX */
1696 radeon_write_agp_location(dev_priv,
1697 (((dev_priv->gart_vm_start - 1 +
1698 dev_priv->gart_size) & 0xffff0000) |
1699 (dev_priv->gart_vm_start >> 16)));
1700
1701 ring_start = (dev_priv->cp_ring->offset
1702 - dev->agp->base
1703 + dev_priv->gart_vm_start);
1704 } else
1705 #endif
1706 ring_start = (dev_priv->cp_ring->offset
1707 - (unsigned long)dev->sg->virtual
1708 + dev_priv->gart_vm_start);
1709
1710 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1711
1712 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1713
1714 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1715
1716 /* Initialize the scratch register pointer. This will cause
1717 * the scratch register values to be written out to memory
1718 * whenever they are updated.
1719 *
1720 * We simply put this behind the ring read pointer, this works
1721 * with PCI GART as well as (whatever kind of) AGP GART
1722 */
1723 {
1724 u64 scratch_addr;
1725
1726 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1727 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1728 scratch_addr += R600_SCRATCH_REG_OFFSET;
1729 scratch_addr >>= 8;
1730 scratch_addr &= 0xffffffff;
1731
1732 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1733 }
1734
1735 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1736
1737 /* Turn on bus mastering */
1738 radeon_enable_bm(dev_priv);
1739
1740 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1741 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1742
1743 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1744 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1745
1746 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1747 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1748
1749 /* reset sarea copies of these */
1750 if (dev_priv->sarea_priv) {
1751 dev_priv->sarea_priv->last_frame = 0;
1752 dev_priv->sarea_priv->last_dispatch = 0;
1753 dev_priv->sarea_priv->last_clear = 0;
1754 }
1755
1756 r600_do_wait_for_idle(dev_priv);
1757
1758 }
1759
1760 int r600_do_cleanup_cp(struct drm_device *dev)
1761 {
1762 drm_radeon_private_t *dev_priv = dev->dev_private;
1763 DRM_DEBUG("\n");
1764
1765 /* Make sure interrupts are disabled here because the uninstall ioctl
1766 * may not have been called from userspace and after dev_private
1767 * is freed, it's too late.
1768 */
1769 if (dev->irq_enabled)
1770 drm_irq_uninstall(dev);
1771
1772 #if __OS_HAS_AGP
1773 if (dev_priv->flags & RADEON_IS_AGP) {
1774 if (dev_priv->cp_ring != NULL) {
1775 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1776 dev_priv->cp_ring = NULL;
1777 }
1778 if (dev_priv->ring_rptr != NULL) {
1779 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1780 dev_priv->ring_rptr = NULL;
1781 }
1782 if (dev->agp_buffer_map != NULL) {
1783 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1784 dev->agp_buffer_map = NULL;
1785 }
1786 } else
1787 #endif
1788 {
1789
1790 if (dev_priv->gart_info.bus_addr)
1791 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1792
1793 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1794 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1795 dev_priv->gart_info.addr = 0;
1796 }
1797 }
1798 /* only clear to the start of flags */
1799 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1800
1801 return 0;
1802 }
1803
1804 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1805 struct drm_file *file_priv)
1806 {
1807 drm_radeon_private_t *dev_priv = dev->dev_private;
1808
1809 DRM_DEBUG("\n");
1810
1811 /* if we require new memory map but we don't have it fail */
1812 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1813 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1814 r600_do_cleanup_cp(dev);
1815 return -EINVAL;
1816 }
1817
1818 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1819 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1820 dev_priv->flags &= ~RADEON_IS_AGP;
1821 /* The writeback test succeeds, but when writeback is enabled,
1822 * the ring buffer read ptr update fails after first 128 bytes.
1823 */
1824 radeon_no_wb = 1;
1825 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1826 && !init->is_pci) {
1827 DRM_DEBUG("Restoring AGP flag\n");
1828 dev_priv->flags |= RADEON_IS_AGP;
1829 }
1830
1831 dev_priv->usec_timeout = init->usec_timeout;
1832 if (dev_priv->usec_timeout < 1 ||
1833 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1834 DRM_DEBUG("TIMEOUT problem!\n");
1835 r600_do_cleanup_cp(dev);
1836 return -EINVAL;
1837 }
1838
1839 /* Enable vblank on CRTC1 for older X servers
1840 */
1841 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1842
1843 dev_priv->cp_mode = init->cp_mode;
1844
1845 /* We don't support anything other than bus-mastering ring mode,
1846 * but the ring can be in either AGP or PCI space for the ring
1847 * read pointer.
1848 */
1849 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1850 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1851 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1852 r600_do_cleanup_cp(dev);
1853 return -EINVAL;
1854 }
1855
1856 switch (init->fb_bpp) {
1857 case 16:
1858 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1859 break;
1860 case 32:
1861 default:
1862 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1863 break;
1864 }
1865 dev_priv->front_offset = init->front_offset;
1866 dev_priv->front_pitch = init->front_pitch;
1867 dev_priv->back_offset = init->back_offset;
1868 dev_priv->back_pitch = init->back_pitch;
1869
1870 dev_priv->ring_offset = init->ring_offset;
1871 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1872 dev_priv->buffers_offset = init->buffers_offset;
1873 dev_priv->gart_textures_offset = init->gart_textures_offset;
1874
1875 dev_priv->sarea = drm_getsarea(dev);
1876 if (!dev_priv->sarea) {
1877 DRM_ERROR("could not find sarea!\n");
1878 r600_do_cleanup_cp(dev);
1879 return -EINVAL;
1880 }
1881
1882 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1883 if (!dev_priv->cp_ring) {
1884 DRM_ERROR("could not find cp ring region!\n");
1885 r600_do_cleanup_cp(dev);
1886 return -EINVAL;
1887 }
1888 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1889 if (!dev_priv->ring_rptr) {
1890 DRM_ERROR("could not find ring read pointer!\n");
1891 r600_do_cleanup_cp(dev);
1892 return -EINVAL;
1893 }
1894 dev->agp_buffer_token = init->buffers_offset;
1895 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1896 if (!dev->agp_buffer_map) {
1897 DRM_ERROR("could not find dma buffer region!\n");
1898 r600_do_cleanup_cp(dev);
1899 return -EINVAL;
1900 }
1901
1902 if (init->gart_textures_offset) {
1903 dev_priv->gart_textures =
1904 drm_core_findmap(dev, init->gart_textures_offset);
1905 if (!dev_priv->gart_textures) {
1906 DRM_ERROR("could not find GART texture region!\n");
1907 r600_do_cleanup_cp(dev);
1908 return -EINVAL;
1909 }
1910 }
1911
1912 dev_priv->sarea_priv =
1913 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1914 init->sarea_priv_offset);
1915
1916 #if __OS_HAS_AGP
1917 /* XXX */
1918 if (dev_priv->flags & RADEON_IS_AGP) {
1919 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1920 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1921 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1922 if (!dev_priv->cp_ring->handle ||
1923 !dev_priv->ring_rptr->handle ||
1924 !dev->agp_buffer_map->handle) {
1925 DRM_ERROR("could not find ioremap agp regions!\n");
1926 r600_do_cleanup_cp(dev);
1927 return -EINVAL;
1928 }
1929 } else
1930 #endif
1931 {
1932 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1933 dev_priv->ring_rptr->handle =
1934 (void *)dev_priv->ring_rptr->offset;
1935 dev->agp_buffer_map->handle =
1936 (void *)dev->agp_buffer_map->offset;
1937
1938 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1939 dev_priv->cp_ring->handle);
1940 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1941 dev_priv->ring_rptr->handle);
1942 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1943 dev->agp_buffer_map->handle);
1944 }
1945
1946 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1947 dev_priv->fb_size =
1948 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1949 - dev_priv->fb_location;
1950
1951 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1952 ((dev_priv->front_offset
1953 + dev_priv->fb_location) >> 10));
1954
1955 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1956 ((dev_priv->back_offset
1957 + dev_priv->fb_location) >> 10));
1958
1959 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1960 ((dev_priv->depth_offset
1961 + dev_priv->fb_location) >> 10));
1962
1963 dev_priv->gart_size = init->gart_size;
1964
1965 /* New let's set the memory map ... */
1966 if (dev_priv->new_memmap) {
1967 u32 base = 0;
1968
1969 DRM_INFO("Setting GART location based on new memory map\n");
1970
1971 /* If using AGP, try to locate the AGP aperture at the same
1972 * location in the card and on the bus, though we have to
1973 * align it down.
1974 */
1975 #if __OS_HAS_AGP
1976 /* XXX */
1977 if (dev_priv->flags & RADEON_IS_AGP) {
1978 base = dev->agp->base;
1979 /* Check if valid */
1980 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1981 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1982 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1983 dev->agp->base);
1984 base = 0;
1985 }
1986 }
1987 #endif
1988 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1989 if (base == 0) {
1990 base = dev_priv->fb_location + dev_priv->fb_size;
1991 if (base < dev_priv->fb_location ||
1992 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1993 base = dev_priv->fb_location
1994 - dev_priv->gart_size;
1995 }
1996 dev_priv->gart_vm_start = base & 0xffc00000u;
1997 if (dev_priv->gart_vm_start != base)
1998 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1999 base, dev_priv->gart_vm_start);
2000 }
2001
2002 #if __OS_HAS_AGP
2003 /* XXX */
2004 if (dev_priv->flags & RADEON_IS_AGP)
2005 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2006 - dev->agp->base
2007 + dev_priv->gart_vm_start);
2008 else
2009 #endif
2010 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2011 - (unsigned long)dev->sg->virtual
2012 + dev_priv->gart_vm_start);
2013
2014 DRM_DEBUG("fb 0x%08x size %d\n",
2015 (unsigned int) dev_priv->fb_location,
2016 (unsigned int) dev_priv->fb_size);
2017 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2018 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2019 (unsigned int) dev_priv->gart_vm_start);
2020 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2021 dev_priv->gart_buffers_offset);
2022
2023 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2024 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2025 + init->ring_size / sizeof(u32));
2026 dev_priv->ring.size = init->ring_size;
2027 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2028
2029 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2030 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2031
2032 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2033 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2034
2035 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2036
2037 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2038
2039 #if __OS_HAS_AGP
2040 if (dev_priv->flags & RADEON_IS_AGP) {
2041 /* XXX turn off pcie gart */
2042 } else
2043 #endif
2044 {
2045 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2046 /* if we have an offset set from userspace */
2047 if (!dev_priv->pcigart_offset_set) {
2048 DRM_ERROR("Need gart offset from userspace\n");
2049 r600_do_cleanup_cp(dev);
2050 return -EINVAL;
2051 }
2052
2053 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2054
2055 dev_priv->gart_info.bus_addr =
2056 dev_priv->pcigart_offset + dev_priv->fb_location;
2057 dev_priv->gart_info.mapping.offset =
2058 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2059 dev_priv->gart_info.mapping.size =
2060 dev_priv->gart_info.table_size;
2061
2062 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2063 if (!dev_priv->gart_info.mapping.handle) {
2064 DRM_ERROR("ioremap failed.\n");
2065 r600_do_cleanup_cp(dev);
2066 return -EINVAL;
2067 }
2068
2069 dev_priv->gart_info.addr =
2070 dev_priv->gart_info.mapping.handle;
2071
2072 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2073 dev_priv->gart_info.addr,
2074 dev_priv->pcigart_offset);
2075
2076 if (!r600_page_table_init(dev)) {
2077 DRM_ERROR("Failed to init GART table\n");
2078 r600_do_cleanup_cp(dev);
2079 return -EINVAL;
2080 }
2081
2082 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2083 r700_vm_init(dev);
2084 else
2085 r600_vm_init(dev);
2086 }
2087
2088 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2089 r700_cp_load_microcode(dev_priv);
2090 else
2091 r600_cp_load_microcode(dev_priv);
2092
2093 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2094
2095 dev_priv->last_buf = 0;
2096
2097 r600_do_engine_reset(dev);
2098 r600_test_writeback(dev_priv);
2099
2100 return 0;
2101 }
2102
2103 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2104 {
2105 drm_radeon_private_t *dev_priv = dev->dev_private;
2106
2107 DRM_DEBUG("\n");
2108 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2109 r700_vm_init(dev);
2110 r700_cp_load_microcode(dev_priv);
2111 } else {
2112 r600_vm_init(dev);
2113 r600_cp_load_microcode(dev_priv);
2114 }
2115 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2116 r600_do_engine_reset(dev);
2117
2118 return 0;
2119 }
2120
2121 /* Wait for the CP to go idle.
2122 */
2123 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2124 {
2125 RING_LOCALS;
2126 DRM_DEBUG("\n");
2127
2128 BEGIN_RING(5);
2129 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2130 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2131 /* wait for 3D idle clean */
2132 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2133 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2134 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2135
2136 ADVANCE_RING();
2137 COMMIT_RING();
2138
2139 return r600_do_wait_for_idle(dev_priv);
2140 }
2141
2142 /* Start the Command Processor.
2143 */
2144 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2145 {
2146 u32 cp_me;
2147 RING_LOCALS;
2148 DRM_DEBUG("\n");
2149
2150 BEGIN_RING(7);
2151 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2152 OUT_RING(0x00000001);
2153 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2154 OUT_RING(0x00000003);
2155 else
2156 OUT_RING(0x00000000);
2157 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2158 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2159 OUT_RING(0x00000000);
2160 OUT_RING(0x00000000);
2161 ADVANCE_RING();
2162 COMMIT_RING();
2163
2164 /* set the mux and reset the halt bit */
2165 cp_me = 0xff;
2166 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2167
2168 dev_priv->cp_running = 1;
2169
2170 }
2171
2172 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2173 {
2174 u32 cur_read_ptr;
2175 DRM_DEBUG("\n");
2176
2177 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2178 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2179 SET_RING_HEAD(dev_priv, cur_read_ptr);
2180 dev_priv->ring.tail = cur_read_ptr;
2181 }
2182
2183 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2184 {
2185 uint32_t cp_me;
2186
2187 DRM_DEBUG("\n");
2188
2189 cp_me = 0xff | R600_CP_ME_HALT;
2190
2191 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2192
2193 dev_priv->cp_running = 0;
2194 }
2195
2196 int r600_cp_dispatch_indirect(struct drm_device *dev,
2197 struct drm_buf *buf, int start, int end)
2198 {
2199 drm_radeon_private_t *dev_priv = dev->dev_private;
2200 RING_LOCALS;
2201
2202 if (start != end) {
2203 unsigned long offset = (dev_priv->gart_buffers_offset
2204 + buf->offset + start);
2205 int dwords = (end - start + 3) / sizeof(u32);
2206
2207 DRM_DEBUG("dwords:%d\n", dwords);
2208 DRM_DEBUG("offset 0x%lx\n", offset);
2209
2210
2211 /* Indirect buffer data must be a multiple of 16 dwords.
2212 * pad the data with a Type-2 CP packet.
2213 */
2214 while (dwords & 0xf) {
2215 u32 *data = (u32 *)
2216 ((char *)dev->agp_buffer_map->handle
2217 + buf->offset + start);
2218 data[dwords++] = RADEON_CP_PACKET2;
2219 }
2220
2221 /* Fire off the indirect buffer */
2222 BEGIN_RING(4);
2223 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2224 OUT_RING((offset & 0xfffffffc));
2225 OUT_RING((upper_32_bits(offset) & 0xff));
2226 OUT_RING(dwords);
2227 ADVANCE_RING();
2228 }
2229
2230 return 0;
2231 }
DragonFly BSD