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kernel - AHCI - enable AHCI device initiated power management
[dragonfly.git] / sys / dev / drm / mga_dma.c
blobbec9cb5ba6b1d8558028375a8b126d1437b87925
1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 */
4 /* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 /**
29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400.
31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include "dev/drm/drmP.h"
39 #include "dev/drm/drm.h"
40 #include "dev/drm/drm_sarea.h"
41 #include "dev/drm/mga_drm.h"
42 #include "dev/drm/mga_drv.h"
43
44 #define MGA_DEFAULT_USEC_TIMEOUT 10000
45 #define MGA_FREELIST_DEBUG 0
46
47 #define MINIMAL_CLEANUP 0
48 #define FULL_CLEANUP 1
49 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
50
51 /* ================================================================
52 * Engine control
53 */
54
55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
56 {
57 u32 status = 0;
58 int i;
59 DRM_DEBUG("\n");
60
61 for (i = 0; i < dev_priv->usec_timeout; i++) {
62 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
63 if (status == MGA_ENDPRDMASTS) {
64 MGA_WRITE8(MGA_CRTC_INDEX, 0);
65 return 0;
66 }
67 DRM_UDELAY(1);
68 }
69
70 #if MGA_DMA_DEBUG
71 DRM_ERROR("failed!\n");
72 DRM_INFO(" status=0x%08x\n", status);
73 #endif
74 return -EBUSY;
75 }
76
77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
78 {
79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
80 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
81
82 DRM_DEBUG("\n");
83
84 /* The primary DMA stream should look like new right about now.
85 */
86 primary->tail = 0;
87 primary->space = primary->size;
88 primary->last_flush = 0;
89
90 sarea_priv->last_wrap = 0;
91
92 /* FIXME: Reset counters, buffer ages etc...
93 */
94
95 /* FIXME: What else do we need to reinitialize? WARP stuff?
96 */
97
98 return 0;
99 }
100
101 /* ================================================================
102 * Primary DMA stream
103 */
104
105 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
106 {
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
108 u32 head, tail;
109 u32 status = 0;
110 int i;
111 DMA_LOCALS;
112 DRM_DEBUG("\n");
113
114 /* We need to wait so that we can do an safe flush */
115 for (i = 0; i < dev_priv->usec_timeout; i++) {
116 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
117 if (status == MGA_ENDPRDMASTS)
118 break;
119 DRM_UDELAY(1);
120 }
121
122 if (primary->tail == primary->last_flush) {
123 DRM_DEBUG(" bailing out...\n");
124 return;
125 }
126
127 tail = primary->tail + dev_priv->primary->offset;
128
129 /* We need to pad the stream between flushes, as the card
130 * actually (partially?) reads the first of these commands.
131 * See page 4-16 in the G400 manual, middle of the page or so.
132 */
133 BEGIN_DMA(1);
134
135 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
136 MGA_DMAPAD, 0x00000000,
137 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
138
139 ADVANCE_DMA();
140
141 primary->last_flush = primary->tail;
142
143 head = MGA_READ(MGA_PRIMADDRESS);
144
145 if (head <= tail) {
146 primary->space = primary->size - primary->tail;
147 } else {
148 primary->space = head - tail;
149 }
150
151 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
152 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
153 DRM_DEBUG(" space = 0x%06x\n", primary->space);
154
155 mga_flush_write_combine();
156 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
157
158 DRM_DEBUG("done.\n");
159 }
160
161 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
162 {
163 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
164 u32 head, tail;
165 DMA_LOCALS;
166 DRM_DEBUG("\n");
167
168 BEGIN_DMA_WRAP();
169
170 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
171 MGA_DMAPAD, 0x00000000,
172 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
173
174 ADVANCE_DMA();
175
176 tail = primary->tail + dev_priv->primary->offset;
177
178 primary->tail = 0;
179 primary->last_flush = 0;
180 primary->last_wrap++;
181
182 head = MGA_READ(MGA_PRIMADDRESS);
183
184 if (head == dev_priv->primary->offset) {
185 primary->space = primary->size;
186 } else {
187 primary->space = head - dev_priv->primary->offset;
188 }
189
190 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
191 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
192 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
193 DRM_DEBUG(" space = 0x%06x\n", primary->space);
194
195 mga_flush_write_combine();
196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
197
198 set_bit(0, &primary->wrapped);
199 DRM_DEBUG("done.\n");
200 }
201
202 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
203 {
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset;
207 DRM_DEBUG("\n");
208
209 sarea_priv->last_wrap++;
210 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
211
212 mga_flush_write_combine();
213 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
214
215 clear_bit(0, &primary->wrapped);
216 DRM_DEBUG("done.\n");
217 }
218
219 /* ================================================================
220 * Freelist management
221 */
222
223 #define MGA_BUFFER_USED ~0
224 #define MGA_BUFFER_FREE 0
225
226 #if MGA_FREELIST_DEBUG
227 static void mga_freelist_print(struct drm_device * dev)
228 {
229 drm_mga_private_t *dev_priv = dev->dev_private;
230 drm_mga_freelist_t *entry;
231
232 DRM_INFO("\n");
233 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
234 dev_priv->sarea_priv->last_dispatch,
235 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
236 dev_priv->primary->offset));
237 DRM_INFO("current freelist:\n");
238
239 for (entry = dev_priv->head->next; entry; entry = entry->next) {
240 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
241 entry, entry->buf->idx, entry->age.head,
242 entry->age.head - dev_priv->primary->offset);
243 }
244 DRM_INFO("\n");
245 }
246 #endif
247
248 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
249 {
250 struct drm_device_dma *dma = dev->dma;
251 struct drm_buf *buf;
252 drm_mga_buf_priv_t *buf_priv;
253 drm_mga_freelist_t *entry;
254 int i;
255 DRM_DEBUG("count=%d\n", dma->buf_count);
256
257 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
258 if (dev_priv->head == NULL)
259 return -ENOMEM;
260
261 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
262 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
263
264 for (i = 0; i < dma->buf_count; i++) {
265 buf = dma->buflist[i];
266 buf_priv = buf->dev_private;
267
268 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
269 if (entry == NULL)
270 return -ENOMEM;
271
272 memset(entry, 0, sizeof(drm_mga_freelist_t));
273
274 entry->next = dev_priv->head->next;
275 entry->prev = dev_priv->head;
276 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
277 entry->buf = buf;
278
279 if (dev_priv->head->next != NULL)
280 dev_priv->head->next->prev = entry;
281 if (entry->next == NULL)
282 dev_priv->tail = entry;
283
284 buf_priv->list_entry = entry;
285 buf_priv->discard = 0;
286 buf_priv->dispatched = 0;
287
288 dev_priv->head->next = entry;
289 }
290
291 return 0;
292 }
293
294 static void mga_freelist_cleanup(struct drm_device * dev)
295 {
296 drm_mga_private_t *dev_priv = dev->dev_private;
297 drm_mga_freelist_t *entry;
298 drm_mga_freelist_t *next;
299 DRM_DEBUG("\n");
300
301 entry = dev_priv->head;
302 while (entry) {
303 next = entry->next;
304 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
305 entry = next;
306 }
307
308 dev_priv->head = dev_priv->tail = NULL;
309 }
310
311 #if 0
312 /* FIXME: Still needed?
313 */
314 static void mga_freelist_reset(struct drm_device * dev)
315 {
316 drm_device_dma_t *dma = dev->dma;
317 struct drm_buf *buf;
318 drm_mga_buf_priv_t *buf_priv;
319 int i;
320
321 for (i = 0; i < dma->buf_count; i++) {
322 buf = dma->buflist[i];
323 buf_priv = buf->dev_private;
324 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
325 }
326 }
327 #endif
328
329 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
330 {
331 drm_mga_private_t *dev_priv = dev->dev_private;
332 drm_mga_freelist_t *next;
333 drm_mga_freelist_t *prev;
334 drm_mga_freelist_t *tail = dev_priv->tail;
335 u32 head, wrap;
336 DRM_DEBUG("\n");
337
338 head = MGA_READ(MGA_PRIMADDRESS);
339 wrap = dev_priv->sarea_priv->last_wrap;
340
341 DRM_DEBUG(" tail=0x%06lx %d\n",
342 tail->age.head ?
343 tail->age.head - dev_priv->primary->offset : 0,
344 tail->age.wrap);
345 DRM_DEBUG(" head=0x%06lx %d\n",
346 head - dev_priv->primary->offset, wrap);
347
348 if (TEST_AGE(&tail->age, head, wrap)) {
349 prev = dev_priv->tail->prev;
350 next = dev_priv->tail;
351 prev->next = NULL;
352 next->prev = next->next = NULL;
353 dev_priv->tail = prev;
354 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
355 return next->buf;
356 }
357
358 DRM_DEBUG("returning NULL!\n");
359 return NULL;
360 }
361
362 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
363 {
364 drm_mga_private_t *dev_priv = dev->dev_private;
365 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
366 drm_mga_freelist_t *head, *entry, *prev;
367
368 DRM_DEBUG("age=0x%06lx wrap=%d\n",
369 buf_priv->list_entry->age.head -
370 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
371
372 entry = buf_priv->list_entry;
373 head = dev_priv->head;
374
375 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
376 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
377 prev = dev_priv->tail;
378 prev->next = entry;
379 entry->prev = prev;
380 entry->next = NULL;
381 } else {
382 prev = head->next;
383 head->next = entry;
384 prev->prev = entry;
385 entry->prev = head;
386 entry->next = prev;
387 }
388
389 return 0;
390 }
391
392 /* ================================================================
393 * DMA initialization, cleanup
394 */
395
396 int mga_driver_load(struct drm_device *dev, unsigned long flags)
397 {
398 drm_mga_private_t *dev_priv;
399 int ret;
400
401 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
402 if (!dev_priv)
403 return -ENOMEM;
404
405 dev->dev_private = (void *)dev_priv;
406 memset(dev_priv, 0, sizeof(drm_mga_private_t));
407
408 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
409 dev_priv->chipset = flags;
410
411 dev_priv->mmio_base = drm_get_resource_start(dev, 1);
412 dev_priv->mmio_size = drm_get_resource_len(dev, 1);
413
414 dev->counters += 3;
415 dev->types[6] = _DRM_STAT_IRQ;
416 dev->types[7] = _DRM_STAT_PRIMARY;
417 dev->types[8] = _DRM_STAT_SECONDARY;
418
419 ret = drm_vblank_init(dev, 1);
420
421 if (ret) {
422 (void) mga_driver_unload(dev);
423 return ret;
424 }
425
426 return 0;
427 }
428
429 /**
430 * Bootstrap the driver for AGP DMA.
431 *
432 * \todo
433 * Investigate whether there is any benifit to storing the WARP microcode in
434 * AGP memory. If not, the microcode may as well always be put in PCI
435 * memory.
436 *
437 * \todo
438 * This routine needs to set dma_bs->agp_mode to the mode actually configured
439 * in the hardware. Looking just at the Linux AGP driver code, I don't see
440 * an easy way to determine this.
441 *
442 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
443 */
444 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
445 drm_mga_dma_bootstrap_t * dma_bs)
446 {
447 drm_mga_private_t *const dev_priv =
448 (drm_mga_private_t *)dev->dev_private;
449 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
450 int err;
451 unsigned offset;
452 const unsigned secondary_size = dma_bs->secondary_bin_count
453 * dma_bs->secondary_bin_size;
454 const unsigned agp_size = (dma_bs->agp_size << 20);
455 struct drm_buf_desc req;
456 struct drm_agp_mode mode;
457 struct drm_agp_info info;
458 struct drm_agp_buffer agp_req;
459 struct drm_agp_binding bind_req;
460
461 /* Acquire AGP. */
462 err = drm_agp_acquire(dev);
463 if (err) {
464 DRM_ERROR("Unable to acquire AGP: %d\n", err);
465 return err;
466 }
467
468 err = drm_agp_info(dev, &info);
469 if (err) {
470 DRM_ERROR("Unable to get AGP info: %d\n", err);
471 return err;
472 }
473
474 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
475 err = drm_agp_enable(dev, mode);
476 if (err) {
477 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
478 return err;
479 }
480
481 /* In addition to the usual AGP mode configuration, the G200 AGP cards
482 * need to have the AGP mode "manually" set.
483 */
484
485 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
486 if (mode.mode & 0x02) {
487 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
488 } else {
489 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
490 }
491 }
492
493 /* Allocate and bind AGP memory. */
494 agp_req.size = agp_size;
495 agp_req.type = 0;
496 err = drm_agp_alloc(dev, &agp_req);
497 if (err) {
498 dev_priv->agp_size = 0;
499 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
500 dma_bs->agp_size);
501 return err;
502 }
503
504 dev_priv->agp_size = agp_size;
505 dev_priv->agp_handle = agp_req.handle;
506
507 bind_req.handle = agp_req.handle;
508 bind_req.offset = 0;
509 err = drm_agp_bind( dev, &bind_req );
510 if (err) {
511 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
512 return err;
513 }
514
515 /* Make drm_addbufs happy by not trying to create a mapping for less
516 * than a page.
517 */
518 if (warp_size < PAGE_SIZE)
519 warp_size = PAGE_SIZE;
520
521 offset = 0;
522 err = drm_addmap(dev, offset, warp_size,
523 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
524 if (err) {
525 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
526 return err;
527 }
528
529 offset += warp_size;
530 err = drm_addmap(dev, offset, dma_bs->primary_size,
531 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
532 if (err) {
533 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
534 return err;
535 }
536
537 offset += dma_bs->primary_size;
538 err = drm_addmap(dev, offset, secondary_size,
539 _DRM_AGP, 0, & dev->agp_buffer_map);
540 if (err) {
541 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
542 return err;
543 }
544
545 (void)memset( &req, 0, sizeof(req) );
546 req.count = dma_bs->secondary_bin_count;
547 req.size = dma_bs->secondary_bin_size;
548 req.flags = _DRM_AGP_BUFFER;
549 req.agp_start = offset;
550
551 err = drm_addbufs_agp(dev, &req);
552 if (err) {
553 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
554 return err;
555 }
556
557 #ifdef __linux__
558 {
559 struct drm_map_list *_entry;
560 unsigned long agp_token = 0;
561
562 list_for_each_entry(_entry, &dev->maplist, head) {
563 if (_entry->map == dev->agp_buffer_map)
564 agp_token = _entry->user_token;
565 }
566 if (!agp_token)
567 return -EFAULT;
568
569 dev->agp_buffer_token = agp_token;
570 }
571 #endif
572
573 offset += secondary_size;
574 err = drm_addmap(dev, offset, agp_size - offset,
575 _DRM_AGP, 0, & dev_priv->agp_textures);
576 if (err) {
577 DRM_ERROR("Unable to map AGP texture region: %d\n", err);
578 return err;
579 }
580
581 drm_core_ioremap(dev_priv->warp, dev);
582 drm_core_ioremap(dev_priv->primary, dev);
583 drm_core_ioremap(dev->agp_buffer_map, dev);
584
585 if (!dev_priv->warp->handle ||
586 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
587 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
588 dev_priv->warp->handle, dev_priv->primary->handle,
589 dev->agp_buffer_map->handle);
590 return -ENOMEM;
591 }
592
593 dev_priv->dma_access = MGA_PAGPXFER;
594 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
595
596 DRM_INFO("Initialized card for AGP DMA.\n");
597 return 0;
598 }
599
600 /**
601 * Bootstrap the driver for PCI DMA.
602 *
603 * \todo
604 * The algorithm for decreasing the size of the primary DMA buffer could be
605 * better. The size should be rounded up to the nearest page size, then
606 * decrease the request size by a single page each pass through the loop.
607 *
608 * \todo
609 * Determine whether the maximum address passed to drm_pci_alloc is correct.
610 * The same goes for drm_addbufs_pci.
611 *
612 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
613 */
614 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
615 drm_mga_dma_bootstrap_t * dma_bs)
616 {
617 drm_mga_private_t *const dev_priv =
618 (drm_mga_private_t *) dev->dev_private;
619 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
620 unsigned int primary_size;
621 unsigned int bin_count;
622 int err;
623 struct drm_buf_desc req;
624
625
626 if (dev->dma == NULL) {
627 DRM_ERROR("dev->dma is NULL\n");
628 return -EFAULT;
629 }
630
631 /* Make drm_addbufs happy by not trying to create a mapping for less
632 * than a page.
633 */
634 if (warp_size < PAGE_SIZE)
635 warp_size = PAGE_SIZE;
636
637 /* The proper alignment is 0x100 for this mapping */
638 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
639 _DRM_READ_ONLY, &dev_priv->warp);
640 if (err != 0) {
641 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
642 err);
643 return err;
644 }
645
646 /* Other than the bottom two bits being used to encode other
647 * information, there don't appear to be any restrictions on the
648 * alignment of the primary or secondary DMA buffers.
649 */
650
651 for (primary_size = dma_bs->primary_size; primary_size != 0;
652 primary_size >>= 1 ) {
653 /* The proper alignment for this mapping is 0x04 */
654 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
655 _DRM_READ_ONLY, &dev_priv->primary);
656 if (!err)
657 break;
658 }
659
660 if (err != 0) {
661 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
662 return -ENOMEM;
663 }
664
665 if (dev_priv->primary->size != dma_bs->primary_size) {
666 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
667 dma_bs->primary_size,
668 (unsigned)dev_priv->primary->size);
669 dma_bs->primary_size = dev_priv->primary->size;
670 }
671
672 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
673 bin_count-- ) {
674 (void)memset(&req, 0, sizeof(req));
675 req.count = bin_count;
676 req.size = dma_bs->secondary_bin_size;
677
678 err = drm_addbufs_pci(dev, &req);
679 if (!err) {
680 break;
681 }
682 }
683
684 if (bin_count == 0) {
685 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
686 return err;
687 }
688
689 if (bin_count != dma_bs->secondary_bin_count) {
690 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
691 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
692
693 dma_bs->secondary_bin_count = bin_count;
694 }
695
696 dev_priv->dma_access = 0;
697 dev_priv->wagp_enable = 0;
698
699 dma_bs->agp_mode = 0;
700
701 DRM_INFO("Initialized card for PCI DMA.\n");
702 return 0;
703 }
704
705
706 static int mga_do_dma_bootstrap(struct drm_device *dev,
707 drm_mga_dma_bootstrap_t *dma_bs)
708 {
709 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
710 int err;
711 drm_mga_private_t *const dev_priv =
712 (drm_mga_private_t *) dev->dev_private;
713
714
715 dev_priv->used_new_dma_init = 1;
716
717 /* The first steps are the same for both PCI and AGP based DMA. Map
718 * the cards MMIO registers and map a status page.
719 */
720 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
721 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
722 if (err) {
723 DRM_ERROR("Unable to map MMIO region: %d\n", err);
724 return err;
725 }
726
727
728 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
729 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
730 & dev_priv->status);
731 if (err) {
732 DRM_ERROR("Unable to map status region: %d\n", err);
733 return err;
734 }
735
736
737 /* The DMA initialization procedure is slightly different for PCI and
738 * AGP cards. AGP cards just allocate a large block of AGP memory and
739 * carve off portions of it for internal uses. The remaining memory
740 * is returned to user-mode to be used for AGP textures.
741 */
742
743 if (is_agp) {
744 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
745 }
746
747 /* If we attempted to initialize the card for AGP DMA but failed,
748 * clean-up any mess that may have been created.
749 */
750
751 if (err) {
752 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
753 }
754
755
756 /* Not only do we want to try and initialized PCI cards for PCI DMA,
757 * but we also try to initialized AGP cards that could not be
758 * initialized for AGP DMA. This covers the case where we have an AGP
759 * card in a system with an unsupported AGP chipset. In that case the
760 * card will be detected as AGP, but we won't be able to allocate any
761 * AGP memory, etc.
762 */
763
764 if (!is_agp || err) {
765 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
766 }
767
768
769 return err;
770 }
771
772 int mga_dma_bootstrap(struct drm_device *dev, void *data,
773 struct drm_file *file_priv)
774 {
775 drm_mga_dma_bootstrap_t *bootstrap = data;
776 int err;
777 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
778 const drm_mga_private_t *const dev_priv =
779 (drm_mga_private_t *) dev->dev_private;
780
781
782 err = mga_do_dma_bootstrap(dev, bootstrap);
783 if (err) {
784 mga_do_cleanup_dma(dev, FULL_CLEANUP);
785 return err;
786 }
787
788 if (dev_priv->agp_textures != NULL) {
789 bootstrap->texture_handle = dev_priv->agp_textures->offset;
790 bootstrap->texture_size = dev_priv->agp_textures->size;
791 } else {
792 bootstrap->texture_handle = 0;
793 bootstrap->texture_size = 0;
794 }
795
796 bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
797
798 return 0;
799 }
800
801
802 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
803 {
804 drm_mga_private_t *dev_priv;
805 int ret;
806 DRM_DEBUG("\n");
807
808
809 dev_priv = dev->dev_private;
810
811 if (init->sgram) {
812 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
813 } else {
814 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
815 }
816 dev_priv->maccess = init->maccess;
817
818 dev_priv->fb_cpp = init->fb_cpp;
819 dev_priv->front_offset = init->front_offset;
820 dev_priv->front_pitch = init->front_pitch;
821 dev_priv->back_offset = init->back_offset;
822 dev_priv->back_pitch = init->back_pitch;
823
824 dev_priv->depth_cpp = init->depth_cpp;
825 dev_priv->depth_offset = init->depth_offset;
826 dev_priv->depth_pitch = init->depth_pitch;
827
828 /* FIXME: Need to support AGP textures...
829 */
830 dev_priv->texture_offset = init->texture_offset[0];
831 dev_priv->texture_size = init->texture_size[0];
832
833 dev_priv->sarea = drm_getsarea(dev);
834 if (!dev_priv->sarea) {
835 DRM_ERROR("failed to find sarea!\n");
836 return -EINVAL;
837 }
838
839 if (!dev_priv->used_new_dma_init) {
840
841 dev_priv->dma_access = MGA_PAGPXFER;
842 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
843
844 dev_priv->status = drm_core_findmap(dev, init->status_offset);
845 if (!dev_priv->status) {
846 DRM_ERROR("failed to find status page!\n");
847 return -EINVAL;
848 }
849 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
850 if (!dev_priv->mmio) {
851 DRM_ERROR("failed to find mmio region!\n");
852 return -EINVAL;
853 }
854 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
855 if (!dev_priv->warp) {
856 DRM_ERROR("failed to find warp microcode region!\n");
857 return -EINVAL;
858 }
859 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
860 if (!dev_priv->primary) {
861 DRM_ERROR("failed to find primary dma region!\n");
862 return -EINVAL;
863 }
864 dev->agp_buffer_token = init->buffers_offset;
865 dev->agp_buffer_map =
866 drm_core_findmap(dev, init->buffers_offset);
867 if (!dev->agp_buffer_map) {
868 DRM_ERROR("failed to find dma buffer region!\n");
869 return -EINVAL;
870 }
871
872 drm_core_ioremap(dev_priv->warp, dev);
873 drm_core_ioremap(dev_priv->primary, dev);
874 drm_core_ioremap(dev->agp_buffer_map, dev);
875 }
876
877 dev_priv->sarea_priv =
878 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
879 init->sarea_priv_offset);
880
881 if (!dev_priv->warp->handle ||
882 !dev_priv->primary->handle ||
883 ((dev_priv->dma_access != 0) &&
884 ((dev->agp_buffer_map == NULL) ||
885 (dev->agp_buffer_map->handle == NULL)))) {
886 DRM_ERROR("failed to ioremap agp regions!\n");
887 return -ENOMEM;
888 }
889
890 ret = mga_warp_install_microcode(dev_priv);
891 if (ret != 0) {
892 DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
893 return ret;
894 }
895
896 ret = mga_warp_init(dev_priv);
897 if (ret != 0) {
898 DRM_ERROR("failed to init WARP engine: %d!\n", ret);
899 return ret;
900 }
901
902 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
903
904 mga_do_wait_for_idle(dev_priv);
905
906 /* Init the primary DMA registers.
907 */
908 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
909
910 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
911 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
912 + dev_priv->primary->size);
913 dev_priv->prim.size = dev_priv->primary->size;
914
915 dev_priv->prim.tail = 0;
916 dev_priv->prim.space = dev_priv->prim.size;
917 dev_priv->prim.wrapped = 0;
918
919 dev_priv->prim.last_flush = 0;
920 dev_priv->prim.last_wrap = 0;
921
922 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
923
924 dev_priv->prim.status[0] = dev_priv->primary->offset;
925 dev_priv->prim.status[1] = 0;
926
927 dev_priv->sarea_priv->last_wrap = 0;
928 dev_priv->sarea_priv->last_frame.head = 0;
929 dev_priv->sarea_priv->last_frame.wrap = 0;
930
931 if (mga_freelist_init(dev, dev_priv) < 0) {
932 DRM_ERROR("could not initialize freelist\n");
933 return -ENOMEM;
934 }
935
936 return 0;
937 }
938
939 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
940 {
941 int err = 0;
942 DRM_DEBUG("\n");
943
944 /* Make sure interrupts are disabled here because the uninstall ioctl
945 * may not have been called from userspace and after dev_private
946 * is freed, it's too late.
947 */
948 if (dev->irq_enabled)
949 drm_irq_uninstall(dev);
950
951 if (dev->dev_private) {
952 drm_mga_private_t *dev_priv = dev->dev_private;
953
954 if ((dev_priv->warp != NULL)
955 && (dev_priv->warp->type != _DRM_CONSISTENT))
956 drm_core_ioremapfree(dev_priv->warp, dev);
957
958 if ((dev_priv->primary != NULL)
959 && (dev_priv->primary->type != _DRM_CONSISTENT))
960 drm_core_ioremapfree(dev_priv->primary, dev);
961
962 if (dev->agp_buffer_map != NULL)
963 drm_core_ioremapfree(dev->agp_buffer_map, dev);
964
965 if (dev_priv->used_new_dma_init) {
966 if (dev_priv->agp_handle != 0) {
967 struct drm_agp_binding unbind_req;
968 struct drm_agp_buffer free_req;
969
970 unbind_req.handle = dev_priv->agp_handle;
971 drm_agp_unbind(dev, &unbind_req);
972
973 free_req.handle = dev_priv->agp_handle;
974 drm_agp_free(dev, &free_req);
975
976 dev_priv->agp_textures = NULL;
977 dev_priv->agp_size = 0;
978 dev_priv->agp_handle = 0;
979 }
980
981 if ((dev->agp != NULL) && dev->agp->acquired) {
982 err = drm_agp_release(dev);
983 }
984 }
985
986 dev_priv->warp = NULL;
987 dev_priv->primary = NULL;
988 dev_priv->sarea = NULL;
989 dev_priv->sarea_priv = NULL;
990 dev->agp_buffer_map = NULL;
991
992 if (full_cleanup) {
993 dev_priv->mmio = NULL;
994 dev_priv->status = NULL;
995 dev_priv->used_new_dma_init = 0;
996 }
997
998 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
999 dev_priv->warp_pipe = 0;
1000 memset(dev_priv->warp_pipe_phys, 0,
1001 sizeof(dev_priv->warp_pipe_phys));
1002
1003 if (dev_priv->head != NULL) {
1004 mga_freelist_cleanup(dev);
1005 }
1006 }
1007
1008 return err;
1009 }
1010
1011 int mga_dma_init(struct drm_device *dev, void *data,
1012 struct drm_file *file_priv)
1013 {
1014 drm_mga_init_t *init = data;
1015 int err;
1016
1017 LOCK_TEST_WITH_RETURN(dev, file_priv);
1018
1019 switch (init->func) {
1020 case MGA_INIT_DMA:
1021 err = mga_do_init_dma(dev, init);
1022 if (err) {
1023 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1024 }
1025 return err;
1026 case MGA_CLEANUP_DMA:
1027 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1028 }
1029
1030 return -EINVAL;
1031 }
1032
1033 /* ================================================================
1034 * Primary DMA stream management
1035 */
1036
1037 int mga_dma_flush(struct drm_device *dev, void *data,
1038 struct drm_file *file_priv)
1039 {
1040 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1041 struct drm_lock *lock = data;
1042
1043 LOCK_TEST_WITH_RETURN(dev, file_priv);
1044
1045 DRM_DEBUG("%s%s%s\n",
1046 (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1047 (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1048 (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1049
1050 WRAP_WAIT_WITH_RETURN(dev_priv);
1051
1052 if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1053 mga_do_dma_flush(dev_priv);
1054 }
1055
1056 if (lock->flags & _DRM_LOCK_QUIESCENT) {
1057 #if MGA_DMA_DEBUG
1058 int ret = mga_do_wait_for_idle(dev_priv);
1059 if (ret < 0)
1060 DRM_INFO("-EBUSY\n");
1061 return ret;
1062 #else
1063 return mga_do_wait_for_idle(dev_priv);
1064 #endif
1065 } else {
1066 return 0;
1067 }
1068 }
1069
1070 int mga_dma_reset(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv)
1072 {
1073 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1074
1075 LOCK_TEST_WITH_RETURN(dev, file_priv);
1076
1077 return mga_do_dma_reset(dev_priv);
1078 }
1079
1080 /* ================================================================
1081 * DMA buffer management
1082 */
1083
1084 static int mga_dma_get_buffers(struct drm_device * dev,
1085 struct drm_file *file_priv, struct drm_dma * d)
1086 {
1087 struct drm_buf *buf;
1088 int i;
1089
1090 for (i = d->granted_count; i < d->request_count; i++) {
1091 buf = mga_freelist_get(dev);
1092 if (!buf)
1093 return -EAGAIN;
1094
1095 buf->file_priv = file_priv;
1096
1097 if (DRM_COPY_TO_USER(&d->request_indices[i],
1098 &buf->idx, sizeof(buf->idx)))
1099 return -EFAULT;
1100 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1101 &buf->total, sizeof(buf->total)))
1102 return -EFAULT;
1103
1104 d->granted_count++;
1105 }
1106 return 0;
1107 }
1108
1109 int mga_dma_buffers(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1111 {
1112 struct drm_device_dma *dma = dev->dma;
1113 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1114 struct drm_dma *d = data;
1115 int ret = 0;
1116
1117 LOCK_TEST_WITH_RETURN(dev, file_priv);
1118
1119 /* Please don't send us buffers.
1120 */
1121 if (d->send_count != 0) {
1122 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1123 DRM_CURRENTPID, d->send_count);
1124 return -EINVAL;
1125 }
1126
1127 /* We'll send you buffers.
1128 */
1129 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1130 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1131 DRM_CURRENTPID, d->request_count, dma->buf_count);
1132 return -EINVAL;
1133 }
1134
1135 WRAP_TEST_WITH_RETURN(dev_priv);
1136
1137 d->granted_count = 0;
1138
1139 if (d->request_count) {
1140 ret = mga_dma_get_buffers(dev, file_priv, d);
1141 }
1142
1143 return ret;
1144 }
1145
1146 /**
1147 * Called just before the module is unloaded.
1148 */
1149 int mga_driver_unload(struct drm_device * dev)
1150 {
1151 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1152 dev->dev_private = NULL;
1153
1154 return 0;
1155 }
1156
1157 /**
1158 * Called when the last opener of the device is closed.
1159 */
1160 void mga_driver_lastclose(struct drm_device * dev)
1161 {
1162 mga_do_cleanup_dma(dev, FULL_CLEANUP);
1163 }
1164
1165 int mga_driver_dma_quiescent(struct drm_device * dev)
1166 {
1167 drm_mga_private_t *dev_priv = dev->dev_private;
1168 return mga_do_wait_for_idle(dev_priv);
1169 }
DragonFly BSD