sys/dev/drm/i915_drm.h

   1 /*-
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 /* Please note that modifications to all structs defined here are
  31  * subject to backwards-compatibility constraints.
  32  */
  33
  34 #include "dev/drm/drm.h"
  35
  36 /* Each region is a minimum of 16k, and there are at most 255 of them.
  37  */
  38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  39                                  * of chars for next/prev indices */
  40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  41
  42 typedef struct _drm_i915_init {
  43         enum {
  44                 I915_INIT_DMA = 0x01,
  45                 I915_CLEANUP_DMA = 0x02,
  46                 I915_RESUME_DMA = 0x03,
  47
  48                 /* Since this struct isn't versioned, just used a new
  49                  * 'func' code to indicate the presence of dri2 sarea
  50                  * info. */
  51                 I915_INIT_DMA2 = 0x04
  52         } func;
  53         unsigned int mmio_offset;
  54         int sarea_priv_offset;
  55         unsigned int ring_start;
  56         unsigned int ring_end;
  57         unsigned int ring_size;
  58         unsigned int front_offset;
  59         unsigned int back_offset;
  60         unsigned int depth_offset;
  61         unsigned int w;
  62         unsigned int h;
  63         unsigned int pitch;
  64         unsigned int pitch_bits;
  65         unsigned int back_pitch;
  66         unsigned int depth_pitch;
  67         unsigned int cpp;
  68         unsigned int chipset;
  69         unsigned int sarea_handle;
  70 } drm_i915_init_t;
  71
  72 typedef struct drm_i915_sarea {
  73         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  74         int last_upload;        /* last time texture was uploaded */
  75         int last_enqueue;       /* last time a buffer was enqueued */
  76         int last_dispatch;      /* age of the most recently dispatched buffer */
  77         int ctxOwner;           /* last context to upload state */
  78         int texAge;
  79         int pf_enabled;         /* is pageflipping allowed? */
  80         int pf_active;
  81         int pf_current_page;    /* which buffer is being displayed? */
  82         int perf_boxes;         /* performance boxes to be displayed */
  83         int width, height;      /* screen size in pixels */
  84
  85         drm_handle_t front_handle;
  86         int front_offset;
  87         int front_size;
  88
  89         drm_handle_t back_handle;
  90         int back_offset;
  91         int back_size;
  92
  93         drm_handle_t depth_handle;
  94         int depth_offset;
  95         int depth_size;
  96
  97         drm_handle_t tex_handle;
  98         int tex_offset;
  99         int tex_size;
 100         int log_tex_granularity;
 101         int pitch;
 102         int rotation;           /* 0, 90, 180 or 270 */
 103         int rotated_offset;
 104         int rotated_size;
 105         int rotated_pitch;
 106         int virtualX, virtualY;
 107
 108         unsigned int front_tiled;
 109         unsigned int back_tiled;
 110         unsigned int depth_tiled;
 111         unsigned int rotated_tiled;
 112         unsigned int rotated2_tiled;
 113
 114         int planeA_x;
 115         int planeA_y;
 116         int planeA_w;
 117         int planeA_h;
 118         int planeB_x;
 119         int planeB_y;
 120         int planeB_w;
 121         int planeB_h;
 122
 123         /* Triple buffering */
 124         drm_handle_t third_handle;
 125         int third_offset;
 126         int third_size;
 127         unsigned int third_tiled;
 128
 129         /* buffer object handles for the static buffers.  May change
 130          * over the lifetime of the client, though it doesn't in our current
 131          * implementation.
 132          */
 133         unsigned int front_bo_handle;
 134         unsigned int back_bo_handle;
 135         unsigned int third_bo_handle;
 136         unsigned int depth_bo_handle;
 137 } drm_i915_sarea_t;
 138
 139 /* Driver specific fence types and classes.
 140  */
 141
 142 /* The only fence class we support */
 143 #define DRM_I915_FENCE_CLASS_ACCEL 0
 144 /* Fence type that guarantees read-write flush */
 145 #define DRM_I915_FENCE_TYPE_RW 2
 146 /* MI_FLUSH programmed just before the fence */
 147 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
 148
 149 /* Flags for perf_boxes
 150  */
 151 #define I915_BOX_RING_EMPTY    0x1
 152 #define I915_BOX_FLIP          0x2
 153 #define I915_BOX_WAIT          0x4
 154 #define I915_BOX_TEXTURE_LOAD  0x8
 155 #define I915_BOX_LOST_CONTEXT  0x10
 156
 157 /* I915 specific ioctls
 158  * The device specific ioctl range is 0x40 to 0x79.
 159  */
 160 #define DRM_I915_INIT           0x00
 161 #define DRM_I915_FLUSH          0x01
 162 #define DRM_I915_FLIP           0x02
 163 #define DRM_I915_BATCHBUFFER    0x03
 164 #define DRM_I915_IRQ_EMIT       0x04
 165 #define DRM_I915_IRQ_WAIT       0x05
 166 #define DRM_I915_GETPARAM       0x06
 167 #define DRM_I915_SETPARAM       0x07
 168 #define DRM_I915_ALLOC          0x08
 169 #define DRM_I915_FREE           0x09
 170 #define DRM_I915_INIT_HEAP      0x0a
 171 #define DRM_I915_CMDBUFFER      0x0b
 172 #define DRM_I915_DESTROY_HEAP   0x0c
 173 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 174 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 175 #define DRM_I915_VBLANK_SWAP    0x0f
 176 #define DRM_I915_MMIO           0x10
 177 #define DRM_I915_HWS_ADDR       0x11
 178 #define DRM_I915_EXECBUFFER     0x12
 179 #define DRM_I915_GEM_INIT       0x13
 180 #define DRM_I915_GEM_EXECBUFFER 0x14
 181 #define DRM_I915_GEM_PIN        0x15
 182 #define DRM_I915_GEM_UNPIN      0x16
 183 #define DRM_I915_GEM_BUSY       0x17
 184 #define DRM_I915_GEM_THROTTLE   0x18
 185 #define DRM_I915_GEM_ENTERVT    0x19
 186 #define DRM_I915_GEM_LEAVEVT    0x1a
 187 #define DRM_I915_GEM_CREATE     0x1b
 188 #define DRM_I915_GEM_PREAD      0x1c
 189 #define DRM_I915_GEM_PWRITE     0x1d
 190 #define DRM_I915_GEM_MMAP       0x1e
 191 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 192 #define DRM_I915_GEM_SW_FINISH  0x20
 193 #define DRM_I915_GEM_SET_TILING 0x21
 194 #define DRM_I915_GEM_GET_TILING 0x22
 195
 196 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 197 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 198 #define DRM_IOCTL_I915_FLIP             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
 199 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 200 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 201 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 202 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 203 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 204 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 205 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 206 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 207 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 208 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 209 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 210 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 211 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 212 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 213 #define DRM_IOCTL_I915_EXECBUFFER       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
 214 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 215 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 216 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 217 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 218 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 219 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 220 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 221 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 222 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 223 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 224 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 225 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 226 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 227 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 228 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 229 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 230
 231 /* Asynchronous page flipping:
 232  */
 233 typedef struct drm_i915_flip {
 234         /*
 235          * This is really talking about planes, and we could rename it
 236          * except for the fact that some of the duplicated i915_drm.h files
 237          * out there check for HAVE_I915_FLIP and so might pick up this
 238          * version.
 239          */
 240         int pipes;
 241 } drm_i915_flip_t;
 242
 243 /* Allow drivers to submit batchbuffers directly to hardware, relying
 244  * on the security mechanisms provided by hardware.
 245  */
 246 typedef struct drm_i915_batchbuffer {
 247         int start;              /* agp offset */
 248         int used;               /* nr bytes in use */
 249         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 250         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 251         int num_cliprects;      /* mulitpass with multiple cliprects? */
 252         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 253 } drm_i915_batchbuffer_t;
 254
 255 /* As above, but pass a pointer to userspace buffer which can be
 256  * validated by the kernel prior to sending to hardware.
 257  */
 258 typedef struct _drm_i915_cmdbuffer {
 259         char __user *buf;       /* pointer to userspace command buffer */
 260         int sz;                 /* nr bytes in buf */
 261         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 262         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 263         int num_cliprects;      /* mulitpass with multiple cliprects? */
 264         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 265 } drm_i915_cmdbuffer_t;
 266
 267 /* Userspace can request & wait on irq's:
 268  */
 269 typedef struct drm_i915_irq_emit {
 270         int __user *irq_seq;
 271 } drm_i915_irq_emit_t;
 272
 273 typedef struct drm_i915_irq_wait {
 274         int irq_seq;
 275 } drm_i915_irq_wait_t;
 276
 277 /* Ioctl to query kernel params:
 278  */
 279 #define I915_PARAM_IRQ_ACTIVE            1
 280 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 281 #define I915_PARAM_LAST_DISPATCH         3
 282 #define I915_PARAM_CHIPSET_ID            4
 283 #define I915_PARAM_HAS_GEM               5
 284
 285 typedef struct drm_i915_getparam {
 286         int param;
 287         int __user *value;
 288 } drm_i915_getparam_t;
 289
 290 /* Ioctl to set kernel params:
 291  */
 292 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 293 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 294 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 295
 296 typedef struct drm_i915_setparam {
 297         int param;
 298         int value;
 299 } drm_i915_setparam_t;
 300
 301 /* A memory manager for regions of shared memory:
 302  */
 303 #define I915_MEM_REGION_AGP 1
 304
 305 typedef struct drm_i915_mem_alloc {
 306         int region;
 307         int alignment;
 308         int size;
 309         int __user *region_offset;      /* offset from start of fb or agp */
 310 } drm_i915_mem_alloc_t;
 311
 312 typedef struct drm_i915_mem_free {
 313         int region;
 314         int region_offset;
 315 } drm_i915_mem_free_t;
 316
 317 typedef struct drm_i915_mem_init_heap {
 318         int region;
 319         int size;
 320         int start;
 321 } drm_i915_mem_init_heap_t;
 322
 323 /* Allow memory manager to be torn down and re-initialized (eg on
 324  * rotate):
 325  */
 326 typedef struct drm_i915_mem_destroy_heap {
 327         int region;
 328 } drm_i915_mem_destroy_heap_t;
 329
 330 /* Allow X server to configure which pipes to monitor for vblank signals
 331  */
 332 #define DRM_I915_VBLANK_PIPE_A  1
 333 #define DRM_I915_VBLANK_PIPE_B  2
 334
 335 typedef struct drm_i915_vblank_pipe {
 336         int pipe;
 337 } drm_i915_vblank_pipe_t;
 338
 339 /* Schedule buffer swap at given vertical blank:
 340  */
 341 typedef struct drm_i915_vblank_swap {
 342         drm_drawable_t drawable;
 343         enum drm_vblank_seq_type seqtype;
 344         unsigned int sequence;
 345 } drm_i915_vblank_swap_t;
 346
 347 #define I915_MMIO_READ  0
 348 #define I915_MMIO_WRITE 1
 349
 350 #define I915_MMIO_MAY_READ      0x1
 351 #define I915_MMIO_MAY_WRITE     0x2
 352
 353 #define MMIO_REGS_IA_PRIMATIVES_COUNT           0
 354 #define MMIO_REGS_IA_VERTICES_COUNT             1
 355 #define MMIO_REGS_VS_INVOCATION_COUNT           2
 356 #define MMIO_REGS_GS_PRIMITIVES_COUNT           3
 357 #define MMIO_REGS_GS_INVOCATION_COUNT           4
 358 #define MMIO_REGS_CL_PRIMITIVES_COUNT           5
 359 #define MMIO_REGS_CL_INVOCATION_COUNT           6
 360 #define MMIO_REGS_PS_INVOCATION_COUNT           7
 361 #define MMIO_REGS_PS_DEPTH_COUNT                8
 362
 363 typedef struct drm_i915_mmio_entry {
 364         unsigned int flag;
 365         unsigned int offset;
 366         unsigned int size;
 367 } drm_i915_mmio_entry_t;
 368
 369 typedef struct drm_i915_mmio {
 370         unsigned int read_write:1;
 371         unsigned int reg:31;
 372         void __user *data;
 373 } drm_i915_mmio_t;
 374
 375 typedef struct drm_i915_hws_addr {
 376         uint64_t addr;
 377 } drm_i915_hws_addr_t;
 378
 379 /*
 380  * Relocation header is 4 uint32_ts
 381  * 0 - 32 bit reloc count
 382  * 1 - 32-bit relocation type
 383  * 2-3 - 64-bit user buffer handle ptr for another list of relocs.
 384  */
 385 #define I915_RELOC_HEADER 4
 386
 387 /*
 388  * type 0 relocation has 4-uint32_t stride
 389  * 0 - offset into buffer
 390  * 1 - delta to add in
 391  * 2 - buffer handle
 392  * 3 - reserved (for optimisations later).
 393  */
 394 /*
 395  * type 1 relocation has 4-uint32_t stride.
 396  * Hangs off the first item in the op list.
 397  * Performed after all valiations are done.
 398  * Try to group relocs into the same relocatee together for
 399  * performance reasons.
 400  * 0 - offset into buffer
 401  * 1 - delta to add in
 402  * 2 - buffer index in op list.
 403  * 3 - relocatee index in op list.
 404  */
 405 #define I915_RELOC_TYPE_0 0
 406 #define I915_RELOC0_STRIDE 4
 407 #define I915_RELOC_TYPE_1 1
 408 #define I915_RELOC1_STRIDE 4
 409
 410
 411 struct drm_i915_op_arg {
 412         uint64_t next;
 413         uint64_t reloc_ptr;
 414         int handled;
 415         unsigned int pad64;
 416         union {
 417                 struct drm_bo_op_req req;
 418                 struct drm_bo_arg_rep rep;
 419         } d;
 420
 421 };
 422
 423 struct drm_i915_execbuffer {
 424         uint64_t ops_list;
 425         uint32_t num_buffers;
 426         struct drm_i915_batchbuffer batch;
 427         drm_context_t context; /* for lockless use in the future */
 428         struct drm_fence_arg fence_arg;
 429 };
 430
 431 struct drm_i915_gem_init {
 432         /**
 433          * Beginning offset in the GTT to be managed by the DRM memory
 434          * manager.
 435          */
 436         uint64_t gtt_start;
 437         /**
 438          * Ending offset in the GTT to be managed by the DRM memory
 439          * manager.
 440          */
 441         uint64_t gtt_end;
 442 };
 443
 444 struct drm_i915_gem_create {
 445         /**
 446          * Requested size for the object.
 447          *
 448          * The (page-aligned) allocated size for the object will be returned.
 449          */
 450         uint64_t size;
 451         /**
 452          * Returned handle for the object.
 453          *
 454          * Object handles are nonzero.
 455          */
 456         uint32_t handle;
 457         uint32_t pad;
 458 };
 459
 460 struct drm_i915_gem_pread {
 461         /** Handle for the object being read. */
 462         uint32_t handle;
 463         uint32_t pad;
 464         /** Offset into the object to read from */
 465         uint64_t offset;
 466         /** Length of data to read */
 467         uint64_t size;
 468         /** Pointer to write the data into. */
 469         uint64_t data_ptr;      /* void *, but pointers are not 32/64 compatible */
 470 };
 471
 472 struct drm_i915_gem_pwrite {
 473         /** Handle for the object being written to. */
 474         uint32_t handle;
 475         uint32_t pad;
 476         /** Offset into the object to write to */
 477         uint64_t offset;
 478         /** Length of data to write */
 479         uint64_t size;
 480         /** Pointer to read the data from. */
 481         uint64_t data_ptr;      /* void *, but pointers are not 32/64 compatible */
 482 };
 483
 484 struct drm_i915_gem_mmap {
 485         /** Handle for the object being mapped. */
 486         uint32_t handle;
 487         uint32_t pad;
 488         /** Offset in the object to map. */
 489         uint64_t offset;
 490         /**
 491          * Length of data to map.
 492          *
 493          * The value will be page-aligned.
 494          */
 495         uint64_t size;
 496         /** Returned pointer the data was mapped at */
 497         uint64_t addr_ptr;      /* void *, but pointers are not 32/64 compatible */
 498 };
 499
 500 struct drm_i915_gem_set_domain {
 501         /** Handle for the object */
 502         uint32_t handle;
 503
 504         /** New read domains */
 505         uint32_t read_domains;
 506
 507         /** New write domain */
 508         uint32_t write_domain;
 509 };
 510
 511 struct drm_i915_gem_sw_finish {
 512         /** Handle for the object */
 513         uint32_t handle;
 514 };
 515
 516 struct drm_i915_gem_relocation_entry {
 517         /**
 518          * Handle of the buffer being pointed to by this relocation entry.
 519          *
 520          * It's appealing to make this be an index into the mm_validate_entry
 521          * list to refer to the buffer, but this allows the driver to create
 522          * a relocation list for state buffers and not re-write it per
 523          * exec using the buffer.
 524          */
 525         uint32_t target_handle;
 526
 527         /**
 528          * Value to be added to the offset of the target buffer to make up
 529          * the relocation entry.
 530          */
 531         uint32_t delta;
 532
 533         /** Offset in the buffer the relocation entry will be written into */
 534         uint64_t offset;
 535
 536         /**
 537          * Offset value of the target buffer that the relocation entry was last
 538          * written as.
 539          *
 540          * If the buffer has the same offset as last time, we can skip syncing
 541          * and writing the relocation.  This value is written back out by
 542          * the execbuffer ioctl when the relocation is written.
 543          */
 544         uint64_t presumed_offset;
 545
 546         /**
 547          * Target memory domains read by this operation.
 548          */
 549         uint32_t read_domains;
 550
 551         /**
 552          * Target memory domains written by this operation.
 553          *
 554          * Note that only one domain may be written by the whole
 555          * execbuffer operation, so that where there are conflicts,
 556          * the application will get -EINVAL back.
 557          */
 558         uint32_t write_domain;
 559 };
 560
 561 /** @{
 562  * Intel memory domains
 563  *
 564  * Most of these just align with the various caches in
 565  * the system and are used to flush and invalidate as
 566  * objects end up cached in different domains.
 567  */
 568 /** CPU cache */
 569 #define I915_GEM_DOMAIN_CPU             0x00000001
 570 /** Render cache, used by 2D and 3D drawing */
 571 #define I915_GEM_DOMAIN_RENDER          0x00000002
 572 /** Sampler cache, used by texture engine */
 573 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 574 /** Command queue, used to load batch buffers */
 575 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 576 /** Instruction cache, used by shader programs */
 577 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 578 /** Vertex address cache */
 579 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 580 /** GTT domain - aperture and scanout */
 581 #define I915_GEM_DOMAIN_GTT             0x00000040
 582 /** @} */
 583
 584 struct drm_i915_gem_exec_object {
 585         /**
 586          * User's handle for a buffer to be bound into the GTT for this
 587          * operation.
 588          */
 589         uint32_t handle;
 590
 591         /** Number of relocations to be performed on this buffer */
 592         uint32_t relocation_count;
 593         /**
 594          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 595          * the relocations to be performed in this buffer.
 596          */
 597         uint64_t relocs_ptr;
 598
 599         /** Required alignment in graphics aperture */
 600         uint64_t alignment;
 601
 602         /**
 603          * Returned value of the updated offset of the object, for future
 604          * presumed_offset writes.
 605          */
 606         uint64_t offset;
 607 };
 608
 609 struct drm_i915_gem_execbuffer {
 610         /**
 611          * List of buffers to be validated with their relocations to be
 612          * performend on them.
 613          *
 614          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 615          *
 616          * These buffers must be listed in an order such that all relocations
 617          * a buffer is performing refer to buffers that have already appeared
 618          * in the validate list.
 619          */
 620         uint64_t buffers_ptr;
 621         uint32_t buffer_count;
 622
 623         /** Offset in the batchbuffer to start execution from. */
 624         uint32_t batch_start_offset;
 625         /** Bytes used in batchbuffer from batch_start_offset */
 626         uint32_t batch_len;
 627         uint32_t DR1;
 628         uint32_t DR4;
 629         uint32_t num_cliprects;
 630         uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
 631 };
 632
 633 struct drm_i915_gem_pin {
 634         /** Handle of the buffer to be pinned. */
 635         uint32_t handle;
 636         uint32_t pad;
 637
 638         /** alignment required within the aperture */
 639         uint64_t alignment;
 640
 641         /** Returned GTT offset of the buffer. */
 642         uint64_t offset;
 643 };
 644
 645 struct drm_i915_gem_unpin {
 646         /** Handle of the buffer to be unpinned. */
 647         uint32_t handle;
 648         uint32_t pad;
 649 };
 650
 651 struct drm_i915_gem_busy {
 652         /** Handle of the buffer to check for busy */
 653         uint32_t handle;
 654
 655         /** Return busy status (1 if busy, 0 if idle) */
 656         uint32_t busy;
 657 };
 658
 659 #define I915_TILING_NONE        0
 660 #define I915_TILING_X           1
 661 #define I915_TILING_Y           2
 662
 663 #define I915_BIT_6_SWIZZLE_NONE         0
 664 #define I915_BIT_6_SWIZZLE_9            1
 665 #define I915_BIT_6_SWIZZLE_9_10         2
 666 #define I915_BIT_6_SWIZZLE_9_11         3
 667 #define I915_BIT_6_SWIZZLE_9_10_11      4
 668 /* Not seen by userland */
 669 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 670
 671 struct drm_i915_gem_set_tiling {
 672         /** Handle of the buffer to have its tiling state updated */
 673         uint32_t handle;
 674
 675         /**
 676          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 677          * I915_TILING_Y).
 678          *
 679          * This value is to be set on request, and will be updated by the
 680          * kernel on successful return with the actual chosen tiling layout.
 681          *
 682          * The tiling mode may be demoted to I915_TILING_NONE when the system
 683          * has bit 6 swizzling that can't be managed correctly by GEM.
 684          *
 685          * Buffer contents become undefined when changing tiling_mode.
 686          */
 687         uint32_t tiling_mode;
 688
 689         /**
 690          * Stride in bytes for the object when in I915_TILING_X or
 691          * I915_TILING_Y.
 692          */
 693         uint32_t stride;
 694
 695         /**
 696          * Returned address bit 6 swizzling required for CPU access through
 697          * mmap mapping.
 698          */
 699         uint32_t swizzle_mode;
 700 };
 701
 702 struct drm_i915_gem_get_tiling {
 703         /** Handle of the buffer to get tiling state for. */
 704         uint32_t handle;
 705
 706         /**
 707          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 708          * I915_TILING_Y).
 709          */
 710         uint32_t tiling_mode;
 711
 712         /**
 713          * Returned address bit 6 swizzling required for CPU access through
 714          * mmap mapping.
 715          */
 716         uint32_t swizzle_mode;
 717 };
 718
 719 #endif                          /* _I915_DRM_H_ */