sys/dev/netif/ic_layer/hd64570.h

   1 /*
   2  * Copyright (c) 1995 John Hay.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  * 3. All advertising materials mentioning features or use of this software
  13  *    must display the following acknowledgement:
  14  *      This product includes software developed by [your name]
  15  *      and [any other names deserving credit ]
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  * $FreeBSD: src/sys/dev/ic/hd64570.h,v 1.6.4.1 2002/06/17 15:10:57 jhay Exp $
  33  * $DragonFly: src/sys/dev/netif/ic_layer/hd64570.h,v 1.2 2003/06/17 04:28:27 dillon Exp $
  34  */
  35 #ifndef _HD64570_H_
  36 #define _HD64570_H_
  37
  38 typedef struct msci_channel
  39   {
  40   union
  41     {
  42     unsigned short us_trb;    /* rw */
  43     struct
  44       {
  45       unsigned char uc_trbl;
  46       unsigned char uc_trbh;
  47       }uc_trb;
  48     }u_trb;
  49   unsigned char st0;          /* ro */
  50   unsigned char st1;          /* rw */
  51   unsigned char st2;          /* rw */
  52   unsigned char st3;          /* ro */
  53   unsigned char fst;          /* rw */
  54   unsigned char unused0;
  55   unsigned char ie0;          /* rw */
  56   unsigned char ie1;          /* rw */
  57   unsigned char ie2;          /* rw */
  58   unsigned char fie;          /* rw */
  59   unsigned char cmd;          /* wo */
  60   unsigned char unused1;
  61   unsigned char md0;          /* rw */
  62   unsigned char md1;          /* rw */
  63   unsigned char md2;          /* rw */
  64   unsigned char ctl;          /* rw */
  65   unsigned char sa0;          /* rw */
  66   unsigned char sa1;          /* rw */
  67   unsigned char idl;          /* rw */
  68   unsigned char tmc;          /* rw */
  69   unsigned char rxs;          /* rw */
  70   unsigned char txs;          /* rw */
  71   unsigned char trc0;         /* rw */
  72   unsigned char trc1;         /* rw */
  73   unsigned char rrc;          /* rw */
  74   unsigned char unused2;
  75   unsigned char cst0;         /* rw */
  76   unsigned char cst1;         /* rw */
  77   unsigned char unused3[2];
  78   }msci_channel;
  79
  80 #define trb     u_trb.us_trb
  81 #define trbl    u_trb.uc_trb.uc_trbl
  82 #define trbh    u_trb.uc_trb.uc_trbh
  83
  84 typedef struct timer_channel
  85   {
  86   unsigned short tcnt;        /* rw */
  87   unsigned short tconr;       /* wo */
  88   unsigned char tcsr;         /* rw */
  89   unsigned char tepr;         /* rw */
  90   unsigned char unused[2];
  91   }timer_channel;
  92
  93 typedef struct dmac_channel
  94   {
  95   unsigned short dar;         /* rw */
  96   unsigned char darb;         /* rw */
  97   unsigned char unused0;
  98   unsigned short sar;         /* rw On odd numbered dmacs (tx) only */
  99   unsigned char sarb;         /* rw */
 100 #define cpb sarb
 101   unsigned char unused1;
 102   unsigned short cda;         /* rw */
 103   unsigned short eda;         /* rw */
 104   unsigned short bfl;         /* rw On even numbered dmacs (rx) only */
 105   unsigned short bcr;         /* rw */
 106   unsigned char dsr;          /* rw */
 107   unsigned char dmr;          /* rw */
 108   unsigned char unused2;
 109   unsigned char fct;          /* rw */
 110   unsigned char dir;          /* rw */
 111   unsigned char dcr;          /* rw */
 112   unsigned char unused3[10];
 113   }dmac_channel;
 114
 115 /* x is the channel number. rx channels are even numbered and tx, odd. */
 116 #define DMAC_RXCH(x)            ((x*2) + 0)
 117 #define DMAC_TXCH(x)            ((x*2) + 1)
 118
 119 typedef struct sca_regs
 120   {
 121   unsigned char lpr;          /* rw */
 122   unsigned char unused0;      /* -- */
 123   /* Wait system */
 124   unsigned char pabr0;        /* rw */
 125   unsigned char pabr1;        /* rw */
 126   unsigned char wcrl;         /* rw */
 127   unsigned char wcrm;         /* rw */
 128   unsigned char wcrh;         /* rw */
 129   unsigned char unused1;
 130   /* DMAC */
 131   unsigned char pcr;          /* rw */
 132   unsigned char dmer;         /* rw */
 133   unsigned char unused2[6];
 134   /* Interrupt */
 135   unsigned char isr0;          /* ro */
 136   unsigned char isr1;          /* ro */
 137   unsigned char isr2;          /* ro */
 138   unsigned char unused3;
 139   unsigned char ier0;          /* rw */
 140   unsigned char ier1;          /* rw */
 141   unsigned char ier2;          /* rw */
 142   unsigned char unused4;
 143   unsigned char itcr;          /* rw */
 144   unsigned char unused5;
 145   unsigned char ivr;           /* rw */
 146   unsigned char unused6;
 147   unsigned char imvr;          /* rw */
 148   unsigned char unused7[3];
 149   /* MSCI Channel 0 */
 150   msci_channel  msci[2];
 151   timer_channel timer[4];
 152   dmac_channel  dmac[4];
 153   }sca_regs;
 154
 155 #define SCA_CMD_TXRESET         0x01
 156 #define SCA_CMD_TXENABLE        0x02
 157 #define SCA_CMD_TXDISABLE       0x03
 158 #define SCA_CMD_TXCRCINIT       0x04
 159 #define SCA_CMD_TXCRCEXCL       0x05
 160 #define SCA_CMS_TXEOM           0x06
 161 #define SCA_CMD_TXABORT         0x07
 162 #define SCA_CMD_MPON            0x08
 163 #define SCA_CMD_TXBCLEAR        0x09
 164
 165 #define SCA_CMD_RXRESET         0x11
 166 #define SCA_CMD_RXENABLE        0x12
 167 #define SCA_CMD_RXDISABLE       0x13
 168 #define SCA_CMD_RXCRCINIT       0x14
 169 #define SCA_CMD_RXMSGREJ        0x15
 170 #define SCA_CMD_MPSEARCH        0x16
 171 #define SCA_CMD_RXCRCEXCL       0x17
 172 #define SCA_CMD_RXCRCCALC       0x18
 173
 174 #define SCA_CMD_NOP             0x00
 175 #define SCA_CMD_RESET           0x21
 176 #define SCA_CMD_SEARCH          0x31
 177
 178 #define SCA_MD0_CRC_1           0x01
 179 #define SCA_MD0_CRC_CCITT       0x02
 180 #define SCA_MD0_CRC_ENABLE      0x04
 181 #define SCA_MD0_AUTO_ENABLE     0x10
 182 #define SCA_MD0_MODE_ASYNC      0x00
 183 #define SCA_MD0_MODE_BYTESYNC1  0x20
 184 #define SCA_MD0_MODE_BISYNC     0x40
 185 #define SCA_MD0_MODE_BYTESYNC2  0x60
 186 #define SCA_MD0_MODE_HDLC       0x80
 187
 188 #define SCA_MD1_NOADDRCHK       0x00
 189 #define SCA_MD1_SNGLADDR1       0x40
 190 #define SCA_MD1_SNGLADDR2       0x80
 191 #define SCA_MD1_DUALADDR        0xC0
 192
 193 #define SCA_MD2_DUPLEX          0x00
 194 #define SCA_MD2_ECHO            0x01
 195 #define SCA_MD2_LOOPBACK        0x03
 196 #define SCA_MD2_ADPLLx8         0x00
 197 #define SCA_MD2_ADPLLx16        0x08
 198 #define SCA_MD2_ADPLLx32        0x10
 199 #define SCA_MD2_NRZ             0x00
 200 #define SCA_MD2_NRZI            0x20
 201 #define SCA_MD2_MANCHESTER      0x80
 202 #define SCA_MD2_FM0             0xC0
 203 #define SCA_MD2_FM1             0xA0
 204
 205 #define SCA_CTL_RTS             0x01
 206 #define SCA_CTL_IDLPAT          0x10
 207 #define SCA_CTL_UDRNC           0x20
 208
 209 #define SCA_RXS_DIV_MASK        0x0F
 210 #define SCA_RXS_DIV1            0x00
 211 #define SCA_RXS_DIV2            0x01
 212 #define SCA_RXS_DIV4            0x02
 213 #define SCA_RXS_DIV8            0x03
 214 #define SCA_RXS_DIV16           0x04
 215 #define SCA_RXS_DIV32           0x05
 216 #define SCA_RXS_DIV64           0x06
 217 #define SCA_RXS_DIV128          0x07
 218 #define SCA_RXS_DIV256          0x08
 219 #define SCA_RXS_DIV512          0x09
 220 #define SCA_RXS_CLK_RXC0        0x00
 221 #define SCA_RXS_CLK_RXC1        0x20
 222 #define SCA_RXS_CLK_INT         0x40
 223 #define SCA_RXS_CLK_ADPLL_OUT   0x60
 224 #define SCA_RXS_CLK_ADPLL_IN    0x70
 225
 226 #define SCA_TXS_DIV_MASK        0x0F
 227 #define SCA_TXS_DIV1            0x00
 228 #define SCA_TXS_DIV2            0x01
 229 #define SCA_TXS_DIV4            0x02
 230 #define SCA_TXS_DIV8            0x03
 231 #define SCA_TXS_DIV16           0x04
 232 #define SCA_TXS_DIV32           0x05
 233 #define SCA_TXS_DIV64           0x06
 234 #define SCA_TXS_DIV128          0x07
 235 #define SCA_TXS_DIV256          0x08
 236 #define SCA_TXS_DIV512          0x09
 237 #define SCA_TXS_CLK_TXC         0x00
 238 #define SCA_TXS_CLK_INT         0x40
 239 #define SCA_TXS_CLK_RX          0x60
 240
 241 #define SCA_ST0_RXRDY           0x01
 242 #define SCA_ST0_TXRDY           0x02
 243 #define SCA_ST0_RXINT           0x40
 244 #define SCA_ST0_TXINT           0x80
 245
 246 #define SCA_ST1_IDLST           0x01
 247 #define SCA_ST1_ABTST           0x02
 248 #define SCA_ST1_DCDCHG          0x04
 249 #define SCA_ST1_CTSCHG          0x08
 250 #define SCA_ST1_FLAG            0x10
 251 #define SCA_ST1_TXIDL           0x40
 252 #define SCA_ST1_UDRN            0x80
 253
 254 /* ST2 and FST look the same */
 255 #define SCA_FST_CRCERR          0x04
 256 #define SCA_FST_OVRN            0x08
 257 #define SCA_FST_RESFRM          0x10
 258 #define SCA_FST_ABRT            0x20
 259 #define SCA_FST_SHRT            0x40
 260 #define SCA_FST_EOM             0x80
 261
 262 #define SCA_ST3_RXENA           0x01
 263 #define SCA_ST3_TXENA           0x02
 264 #define SCA_ST3_DCD             0x04
 265 #define SCA_ST3_CTS             0x08
 266 #define SCA_ST3_ADPLLSRCH       0x10
 267 #define SCA_ST3_TXDATA          0x20
 268
 269 #define SCA_FIE_EOMFE           0x80
 270
 271 #define SCA_IE0_RXRDY           0x01
 272 #define SCA_IE0_TXRDY           0x02
 273 #define SCA_IE0_RXINT           0x40
 274 #define SCA_IE0_TXINT           0x80
 275
 276 #define SCA_IE1_IDLDE           0x01
 277 #define SCA_IE1_ABTDE           0x02
 278 #define SCA_IE1_DCD             0x04
 279 #define SCA_IE1_CTS             0x08
 280 #define SCA_IE1_FLAG            0x10
 281 #define SCA_IE1_IDL             0x40
 282 #define SCA_IE1_UDRN            0x80
 283
 284 #define SCA_IE2_CRCERR          0x04
 285 #define SCA_IE2_OVRN            0x08
 286 #define SCA_IE2_RESFRM          0x10
 287 #define SCA_IE2_ABRT            0x20
 288 #define SCA_IE2_SHRT            0x40
 289 #define SCA_IE2_EOM             0x80
 290
 291 /* This is for RRC, TRC0 and TRC1. */
 292 #define SCA_RCR_MASK            0x1F
 293
 294 #define SCA_IE1_
 295
 296 #define SCA_IV_CHAN0            0x00
 297 #define SCA_IV_CHAN1            0x20
 298
 299 #define SCA_IV_RXRDY            0x04
 300 #define SCA_IV_TXRDY            0x06
 301 #define SCA_IV_RXINT            0x08
 302 #define SCA_IV_TXINT            0x0A
 303
 304 #define SCA_IV_DMACH0           0x00
 305 #define SCA_IV_DMACH1           0x08
 306 #define SCA_IV_DMACH2           0x20
 307 #define SCA_IV_DMACH3           0x28
 308
 309 #define SCA_IV_DMIA             0x14
 310 #define SCA_IV_DMIB             0x16
 311
 312 #define SCA_IV_TIMER0           0x1C
 313 #define SCA_IV_TIMER1           0x1E
 314 #define SCA_IV_TIMER2           0x3C
 315 #define SCA_IV_TIMER3           0x3E
 316
 317 /*
 318  * DMA registers
 319  */
 320 #define SCA_DSR_EOT             0x80
 321 #define SCA_DSR_EOM             0x40
 322 #define SCA_DSR_BOF             0x20
 323 #define SCA_DSR_COF             0x10
 324 #define SCA_DSR_DE              0x02
 325 #define SCA_DSR_DWE             0x01
 326
 327 #define SCA_DMR_TMOD            0x10
 328 #define SCA_DMR_NF              0x04
 329 #define SCA_DMR_CNTE            0x02
 330
 331 #define SCA_DMER_EN             0x80
 332
 333 #define SCA_DCR_ABRT            0x01
 334 #define SCA_DCR_FCCLR           0x02  /* Clear frame end intr counter */
 335
 336 #define SCA_DIR_EOT             0x80
 337 #define SCA_DIR_EOM             0x40
 338 #define SCA_DIR_BOF             0x20
 339 #define SCA_DIR_COF             0x10
 340
 341 #define SCA_PCR_BRC             0x10
 342 #define SCA_PCR_CCC             0x08
 343 #define SCA_PCR_PR2             0x04
 344 #define SCA_PCR_PR1             0x02
 345 #define SCA_PCR_PR0             0x01
 346
 347 typedef struct sca_descriptor
 348   {
 349   unsigned short cp;
 350   unsigned short bp;
 351   unsigned char  bpb;
 352   unsigned char  unused0;
 353   unsigned short len;
 354   unsigned char  stat;
 355   unsigned char  unused1;
 356   }sca_descriptor;
 357
 358 #define SCA_DESC_EOT            0x01
 359 #define SCA_DESC_CRC            0x04
 360 #define SCA_DESC_OVRN           0x08
 361 #define SCA_DESC_RESD           0x10
 362 #define SCA_DESC_ABORT          0x20
 363 #define SCA_DESC_SHRTFRM        0x40
 364 #define SCA_DESC_EOM            0x80
 365 #define SCA_DESC_ERRORS         0x7C
 366
 367 /*
 368 ***************************************************************************
 369 **                                 END
 370 ***************************************************************************
 371 **/
 372 #endif /* _HD64570_H_ */
 373