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Prepare to rework nfe_start():
[dragonfly.git] / sys / dev / netif / nfe / if_nfe.c
blobf5ff2059f2fea89df8fe0d76bc9c6b0154ddc8e9
1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.38 2008/07/12 06:50:04 sephe Exp $ */
3
4 /*
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
42 *
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
46 *
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 */
55
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
57
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
60
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
64 #include <sys/bus.h>
65 #include <sys/interrupt.h>
66 #include <sys/proc.h>
67 #include <sys/rman.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
72
73 #include <net/ethernet.h>
74 #include <net/if.h>
75 #include <net/bpf.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
88
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
96
97 #define NFE_CSUM
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
106
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
110
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 #endif
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static int nfe_rxeof(struct nfe_softc *);
117 static int nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 struct mbuf *);
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
146 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
147 int);
148 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 int, bus_addr_t);
150 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
151 int);
152 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
153 int);
154 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 int);
156 static void nfe_enable_intrs(struct nfe_softc *);
157 static void nfe_disable_intrs(struct nfe_softc *);
158
159 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
160
161 #define NFE_DEBUG
162 #ifdef NFE_DEBUG
163
164 static int nfe_debug = 0;
165 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
166 static int nfe_imtime = 0; /* Disable interrupt moderation */
167
168 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
169 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
170 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
171
172 #define DPRINTF(sc, fmt, ...) do { \
173 if ((sc)->sc_debug) { \
174 if_printf(&(sc)->arpcom.ac_if, \
175 fmt, __VA_ARGS__); \
176 } \
177 } while (0)
178
179 #define DPRINTFN(sc, lv, fmt, ...) do { \
180 if ((sc)->sc_debug >= (lv)) { \
181 if_printf(&(sc)->arpcom.ac_if, \
182 fmt, __VA_ARGS__); \
183 } \
184 } while (0)
185
186 #else /* !NFE_DEBUG */
187
188 #define DPRINTF(sc, fmt, ...)
189 #define DPRINTFN(sc, lv, fmt, ...)
190
191 #endif /* NFE_DEBUG */
192
193 struct nfe_dma_ctx {
194 int nsegs;
195 bus_dma_segment_t *segs;
196 };
197
198 static const struct nfe_dev {
199 uint16_t vid;
200 uint16_t did;
201 const char *desc;
202 } nfe_devices[] = {
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
204 "NVIDIA nForce Fast Ethernet" },
205
206 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
207 "NVIDIA nForce2 Fast Ethernet" },
208
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
210 "NVIDIA nForce3 Gigabit Ethernet" },
211
212 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
213 chipset, and possibly also the 400R; it might be both nForce2- and
214 nForce3-based boards can use the same MCPs (= southbridges) */
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
216 "NVIDIA nForce3 Gigabit Ethernet" },
217
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
219 "NVIDIA nForce3 Gigabit Ethernet" },
220
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
222 "NVIDIA nForce3 Gigabit Ethernet" },
223
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
225 "NVIDIA nForce3 Gigabit Ethernet" },
226
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
228 "NVIDIA CK804 Gigabit Ethernet" },
229
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
231 "NVIDIA CK804 Gigabit Ethernet" },
232
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
234 "NVIDIA MCP04 Gigabit Ethernet" },
235
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
237 "NVIDIA MCP04 Gigabit Ethernet" },
238
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
240 "NVIDIA MCP51 Gigabit Ethernet" },
241
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
243 "NVIDIA MCP51 Gigabit Ethernet" },
244
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
246 "NVIDIA MCP55 Gigabit Ethernet" },
247
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
249 "NVIDIA MCP55 Gigabit Ethernet" },
250
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
252 "NVIDIA MCP61 Gigabit Ethernet" },
253
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
255 "NVIDIA MCP61 Gigabit Ethernet" },
256
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
258 "NVIDIA MCP61 Gigabit Ethernet" },
259
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
261 "NVIDIA MCP61 Gigabit Ethernet" },
262
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
264 "NVIDIA MCP65 Gigabit Ethernet" },
265
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
267 "NVIDIA MCP65 Gigabit Ethernet" },
268
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
270 "NVIDIA MCP65 Gigabit Ethernet" },
271
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
273 "NVIDIA MCP65 Gigabit Ethernet" },
274
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
276 "NVIDIA MCP67 Gigabit Ethernet" },
277
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
279 "NVIDIA MCP67 Gigabit Ethernet" },
280
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
282 "NVIDIA MCP67 Gigabit Ethernet" },
283
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
285 "NVIDIA MCP67 Gigabit Ethernet" },
286
287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
288 "NVIDIA MCP73 Gigabit Ethernet" },
289
290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
291 "NVIDIA MCP73 Gigabit Ethernet" },
292
293 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
294 "NVIDIA MCP73 Gigabit Ethernet" },
295
296 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
297 "NVIDIA MCP73 Gigabit Ethernet" },
298
299 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
300 "NVIDIA MCP77 Gigabit Ethernet" },
301
302 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
303 "NVIDIA MCP77 Gigabit Ethernet" },
304
305 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
306 "NVIDIA MCP77 Gigabit Ethernet" },
307
308 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
309 "NVIDIA MCP77 Gigabit Ethernet" },
310
311 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
312 "NVIDIA MCP79 Gigabit Ethernet" },
313
314 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
315 "NVIDIA MCP79 Gigabit Ethernet" },
316
317 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
318 "NVIDIA MCP79 Gigabit Ethernet" },
319
320 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
321 "NVIDIA MCP79 Gigabit Ethernet" },
322
323 { 0, 0, NULL }
324 };
325
326 static device_method_t nfe_methods[] = {
327 /* Device interface */
328 DEVMETHOD(device_probe, nfe_probe),
329 DEVMETHOD(device_attach, nfe_attach),
330 DEVMETHOD(device_detach, nfe_detach),
331 DEVMETHOD(device_suspend, nfe_suspend),
332 DEVMETHOD(device_resume, nfe_resume),
333 DEVMETHOD(device_shutdown, nfe_shutdown),
334
335 /* Bus interface */
336 DEVMETHOD(bus_print_child, bus_generic_print_child),
337 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
338
339 /* MII interface */
340 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
341 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
342 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
343
344 { 0, 0 }
345 };
346
347 static driver_t nfe_driver = {
348 "nfe",
349 nfe_methods,
350 sizeof(struct nfe_softc)
351 };
352
353 static devclass_t nfe_devclass;
354
355 DECLARE_DUMMY_MODULE(if_nfe);
356 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
357 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
358 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
359
360 static int
361 nfe_probe(device_t dev)
362 {
363 const struct nfe_dev *n;
364 uint16_t vid, did;
365
366 vid = pci_get_vendor(dev);
367 did = pci_get_device(dev);
368 for (n = nfe_devices; n->desc != NULL; ++n) {
369 if (vid == n->vid && did == n->did) {
370 struct nfe_softc *sc = device_get_softc(dev);
371
372 switch (did) {
373 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
374 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
376 sc->sc_caps = NFE_NO_PWRCTL |
377 NFE_FIX_EADDR;
378 break;
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
380 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
381 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
382 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
383 sc->sc_caps = NFE_JUMBO_SUP |
384 NFE_HW_CSUM |
385 NFE_NO_PWRCTL |
386 NFE_FIX_EADDR;
387 break;
388 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
389 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
390 sc->sc_caps = NFE_FIX_EADDR;
391 /* FALL THROUGH */
392 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
395 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
396 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
397 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
398 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
399 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
400 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
403 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
404 sc->sc_caps |= NFE_40BIT_ADDR;
405 break;
406 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
407 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
408 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
409 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
410 sc->sc_caps = NFE_JUMBO_SUP |
411 NFE_40BIT_ADDR |
412 NFE_HW_CSUM |
413 NFE_NO_PWRCTL |
414 NFE_FIX_EADDR;
415 break;
416 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
417 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
418 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
419 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
420 sc->sc_caps = NFE_JUMBO_SUP |
421 NFE_40BIT_ADDR;
422 break;
423 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
424 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
425 sc->sc_caps = NFE_JUMBO_SUP |
426 NFE_40BIT_ADDR |
427 NFE_HW_CSUM |
428 NFE_HW_VLAN |
429 NFE_FIX_EADDR;
430 break;
431 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
432 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
433 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
434 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
435 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
436 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
437 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
438 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
439 sc->sc_caps = NFE_40BIT_ADDR |
440 NFE_HW_CSUM;
441 break;
442 }
443
444 device_set_desc(dev, n->desc);
445 device_set_async_attach(dev, TRUE);
446 return 0;
447 }
448 }
449 return ENXIO;
450 }
451
452 static int
453 nfe_attach(device_t dev)
454 {
455 struct nfe_softc *sc = device_get_softc(dev);
456 struct ifnet *ifp = &sc->arpcom.ac_if;
457 uint8_t eaddr[ETHER_ADDR_LEN];
458 int error;
459
460 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
461 lwkt_serialize_init(&sc->sc_jbuf_serializer);
462
463 /*
464 * Initialize sysctl variables
465 */
466 sc->sc_rx_ring_count = nfe_rx_ring_count;
467 sc->sc_debug = nfe_debug;
468 if (nfe_imtime < 0) {
469 sc->sc_flags |= NFE_F_DYN_IM;
470 sc->sc_imtime = -nfe_imtime;
471 } else {
472 sc->sc_imtime = nfe_imtime;
473 }
474 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
475
476 sc->sc_mem_rid = PCIR_BAR(0);
477
478 if (sc->sc_caps & NFE_40BIT_ADDR)
479 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
480 else if (sc->sc_caps & NFE_JUMBO_SUP)
481 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
482
483 #ifndef BURN_BRIDGES
484 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
485 uint32_t mem, irq;
486
487 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
488 irq = pci_read_config(dev, PCIR_INTLINE, 4);
489
490 device_printf(dev, "chip is in D%d power mode "
491 "-- setting to D0\n", pci_get_powerstate(dev));
492
493 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
494
495 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
496 pci_write_config(dev, PCIR_INTLINE, irq, 4);
497 }
498 #endif /* !BURN_BRIDGE */
499
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
502
503 /* Allocate IO memory */
504 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
505 &sc->sc_mem_rid, RF_ACTIVE);
506 if (sc->sc_mem_res == NULL) {
507 device_printf(dev, "cound not allocate io memory\n");
508 return ENXIO;
509 }
510 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
511 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
512
513 /* Allocate IRQ */
514 sc->sc_irq_rid = 0;
515 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
516 &sc->sc_irq_rid,
517 RF_SHAREABLE | RF_ACTIVE);
518 if (sc->sc_irq_res == NULL) {
519 device_printf(dev, "could not allocate irq\n");
520 error = ENXIO;
521 goto fail;
522 }
523
524 /* Disable WOL */
525 NFE_WRITE(sc, NFE_WOL_CTL, 0);
526
527 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
528 nfe_powerup(dev);
529
530 nfe_get_macaddr(sc, eaddr);
531
532 /*
533 * Allocate Tx and Rx rings.
534 */
535 error = nfe_alloc_tx_ring(sc, &sc->txq);
536 if (error) {
537 device_printf(dev, "could not allocate Tx ring\n");
538 goto fail;
539 }
540
541 error = nfe_alloc_rx_ring(sc, &sc->rxq);
542 if (error) {
543 device_printf(dev, "could not allocate Rx ring\n");
544 goto fail;
545 }
546
547 /*
548 * Create sysctl tree
549 */
550 sysctl_ctx_init(&sc->sc_sysctl_ctx);
551 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
552 SYSCTL_STATIC_CHILDREN(_hw),
553 OID_AUTO,
554 device_get_nameunit(dev),
555 CTLFLAG_RD, 0, "");
556 if (sc->sc_sysctl_tree == NULL) {
557 device_printf(dev, "can't add sysctl node\n");
558 error = ENXIO;
559 goto fail;
560 }
561 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
562 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
563 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
564 sc, 0, nfe_sysctl_imtime, "I",
565 "Interrupt moderation time (usec). "
566 "0 to disable interrupt moderation.");
567 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
568 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
569 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
570 0, "RX ring count");
571 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
572 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
573 "debug", CTLFLAG_RW, &sc->sc_debug,
574 0, "control debugging printfs");
575
576 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
577 nfe_ifmedia_sts);
578 if (error) {
579 device_printf(dev, "MII without any phy\n");
580 goto fail;
581 }
582
583 ifp->if_softc = sc;
584 ifp->if_mtu = ETHERMTU;
585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
586 ifp->if_ioctl = nfe_ioctl;
587 ifp->if_start = nfe_start;
588 #ifdef DEVICE_POLLING
589 ifp->if_poll = nfe_poll;
590 #endif
591 ifp->if_watchdog = nfe_watchdog;
592 ifp->if_init = nfe_init;
593 ifq_set_maxlen(&ifp->if_snd, NFE_TX_RING_COUNT - 1);
594 ifq_set_ready(&ifp->if_snd);
595
596 ifp->if_capabilities = IFCAP_VLAN_MTU;
597
598 if (sc->sc_caps & NFE_HW_VLAN)
599 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
600
601 #ifdef NFE_CSUM
602 if (sc->sc_caps & NFE_HW_CSUM) {
603 ifp->if_capabilities |= IFCAP_HWCSUM;
604 ifp->if_hwassist = NFE_CSUM_FEATURES;
605 }
606 #else
607 sc->sc_caps &= ~NFE_HW_CSUM;
608 #endif
609 ifp->if_capenable = ifp->if_capabilities;
610
611 callout_init(&sc->sc_tick_ch);
612
613 ether_ifattach(ifp, eaddr, NULL);
614
615 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
616 &sc->sc_ih, ifp->if_serializer);
617 if (error) {
618 device_printf(dev, "could not setup intr\n");
619 ether_ifdetach(ifp);
620 goto fail;
621 }
622
623 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
624 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
625
626 return 0;
627 fail:
628 nfe_detach(dev);
629 return error;
630 }
631
632 static int
633 nfe_detach(device_t dev)
634 {
635 struct nfe_softc *sc = device_get_softc(dev);
636
637 if (device_is_attached(dev)) {
638 struct ifnet *ifp = &sc->arpcom.ac_if;
639
640 lwkt_serialize_enter(ifp->if_serializer);
641 nfe_stop(sc);
642 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
643 lwkt_serialize_exit(ifp->if_serializer);
644
645 ether_ifdetach(ifp);
646 }
647
648 if (sc->sc_miibus != NULL)
649 device_delete_child(dev, sc->sc_miibus);
650 bus_generic_detach(dev);
651
652 if (sc->sc_sysctl_tree != NULL)
653 sysctl_ctx_free(&sc->sc_sysctl_ctx);
654
655 if (sc->sc_irq_res != NULL) {
656 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
657 sc->sc_irq_res);
658 }
659
660 if (sc->sc_mem_res != NULL) {
661 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
662 sc->sc_mem_res);
663 }
664
665 nfe_free_tx_ring(sc, &sc->txq);
666 nfe_free_rx_ring(sc, &sc->rxq);
667
668 return 0;
669 }
670
671 static void
672 nfe_shutdown(device_t dev)
673 {
674 struct nfe_softc *sc = device_get_softc(dev);
675 struct ifnet *ifp = &sc->arpcom.ac_if;
676
677 lwkt_serialize_enter(ifp->if_serializer);
678 nfe_stop(sc);
679 lwkt_serialize_exit(ifp->if_serializer);
680 }
681
682 static int
683 nfe_suspend(device_t dev)
684 {
685 struct nfe_softc *sc = device_get_softc(dev);
686 struct ifnet *ifp = &sc->arpcom.ac_if;
687
688 lwkt_serialize_enter(ifp->if_serializer);
689 nfe_stop(sc);
690 lwkt_serialize_exit(ifp->if_serializer);
691
692 return 0;
693 }
694
695 static int
696 nfe_resume(device_t dev)
697 {
698 struct nfe_softc *sc = device_get_softc(dev);
699 struct ifnet *ifp = &sc->arpcom.ac_if;
700
701 lwkt_serialize_enter(ifp->if_serializer);
702 if (ifp->if_flags & IFF_UP)
703 nfe_init(sc);
704 lwkt_serialize_exit(ifp->if_serializer);
705
706 return 0;
707 }
708
709 static void
710 nfe_miibus_statchg(device_t dev)
711 {
712 struct nfe_softc *sc = device_get_softc(dev);
713 struct mii_data *mii = device_get_softc(sc->sc_miibus);
714 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
715
716 phy = NFE_READ(sc, NFE_PHY_IFACE);
717 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
718
719 seed = NFE_READ(sc, NFE_RNDSEED);
720 seed &= ~NFE_SEED_MASK;
721
722 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
723 phy |= NFE_PHY_HDX; /* half-duplex */
724 misc |= NFE_MISC1_HDX;
725 }
726
727 switch (IFM_SUBTYPE(mii->mii_media_active)) {
728 case IFM_1000_T: /* full-duplex only */
729 link |= NFE_MEDIA_1000T;
730 seed |= NFE_SEED_1000T;
731 phy |= NFE_PHY_1000T;
732 break;
733 case IFM_100_TX:
734 link |= NFE_MEDIA_100TX;
735 seed |= NFE_SEED_100TX;
736 phy |= NFE_PHY_100TX;
737 break;
738 case IFM_10_T:
739 link |= NFE_MEDIA_10T;
740 seed |= NFE_SEED_10T;
741 break;
742 }
743
744 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
745
746 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
747 NFE_WRITE(sc, NFE_MISC1, misc);
748 NFE_WRITE(sc, NFE_LINKSPEED, link);
749 }
750
751 static int
752 nfe_miibus_readreg(device_t dev, int phy, int reg)
753 {
754 struct nfe_softc *sc = device_get_softc(dev);
755 uint32_t val;
756 int ntries;
757
758 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
759
760 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
761 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
762 DELAY(100);
763 }
764
765 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
766
767 for (ntries = 0; ntries < 1000; ntries++) {
768 DELAY(100);
769 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
770 break;
771 }
772 if (ntries == 1000) {
773 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
774 return 0;
775 }
776
777 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
778 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
779 return 0;
780 }
781
782 val = NFE_READ(sc, NFE_PHY_DATA);
783 if (val != 0xffffffff && val != 0)
784 sc->mii_phyaddr = phy;
785
786 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
787
788 return val;
789 }
790
791 static void
792 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
793 {
794 struct nfe_softc *sc = device_get_softc(dev);
795 uint32_t ctl;
796 int ntries;
797
798 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
799
800 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
801 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
802 DELAY(100);
803 }
804
805 NFE_WRITE(sc, NFE_PHY_DATA, val);
806 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
807 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
808
809 for (ntries = 0; ntries < 1000; ntries++) {
810 DELAY(100);
811 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
812 break;
813 }
814
815 #ifdef NFE_DEBUG
816 if (ntries == 1000)
817 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
818 #endif
819 }
820
821 #ifdef DEVICE_POLLING
822
823 static void
824 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
825 {
826 struct nfe_softc *sc = ifp->if_softc;
827
828 ASSERT_SERIALIZED(ifp->if_serializer);
829
830 switch(cmd) {
831 case POLL_REGISTER:
832 nfe_disable_intrs(sc);
833 break;
834
835 case POLL_DEREGISTER:
836 nfe_enable_intrs(sc);
837 break;
838
839 case POLL_AND_CHECK_STATUS:
840 /* fall through */
841 case POLL_ONLY:
842 if (ifp->if_flags & IFF_RUNNING) {
843 nfe_rxeof(sc);
844 nfe_txeof(sc);
845 }
846 break;
847 }
848 }
849
850 #endif
851
852 static void
853 nfe_intr(void *arg)
854 {
855 struct nfe_softc *sc = arg;
856 struct ifnet *ifp = &sc->arpcom.ac_if;
857 uint32_t r;
858
859 r = NFE_READ(sc, NFE_IRQ_STATUS);
860 if (r == 0)
861 return; /* not for us */
862 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
863
864 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
865
866 if (r & NFE_IRQ_LINK) {
867 NFE_READ(sc, NFE_PHY_STATUS);
868 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
869 DPRINTF(sc, "link state changed %s\n", "");
870 }
871
872 if (ifp->if_flags & IFF_RUNNING) {
873 int ret;
874
875 /* check Rx ring */
876 ret = nfe_rxeof(sc);
877
878 /* check Tx ring */
879 ret |= nfe_txeof(sc);
880
881 if (sc->sc_flags & NFE_F_DYN_IM) {
882 if (ret && (sc->sc_flags & NFE_F_IRQ_TIMER) == 0) {
883 /*
884 * Assume that using hardware timer could reduce
885 * the interrupt rate.
886 */
887 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
888 sc->sc_flags |= NFE_F_IRQ_TIMER;
889 } else if (!ret && (sc->sc_flags & NFE_F_IRQ_TIMER)) {
890 /*
891 * Nothing needs to be processed, fall back to
892 * use TX/RX interrupts.
893 */
894 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
895 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
896 }
897 }
898 }
899 }
900
901 static int
902 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
903 {
904 struct nfe_softc *sc = ifp->if_softc;
905 struct ifreq *ifr = (struct ifreq *)data;
906 struct mii_data *mii;
907 int error = 0, mask, jumbo_cap;
908
909 switch (cmd) {
910 case SIOCSIFMTU:
911 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
912 jumbo_cap = 1;
913 else
914 jumbo_cap = 0;
915
916 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
917 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
918 return EINVAL;
919 } else if (ifp->if_mtu != ifr->ifr_mtu) {
920 ifp->if_mtu = ifr->ifr_mtu;
921 if (ifp->if_flags & IFF_RUNNING)
922 nfe_init(sc);
923 }
924 break;
925 case SIOCSIFFLAGS:
926 if (ifp->if_flags & IFF_UP) {
927 /*
928 * If only the PROMISC or ALLMULTI flag changes, then
929 * don't do a full re-init of the chip, just update
930 * the Rx filter.
931 */
932 if ((ifp->if_flags & IFF_RUNNING) &&
933 ((ifp->if_flags ^ sc->sc_if_flags) &
934 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
935 nfe_setmulti(sc);
936 } else {
937 if (!(ifp->if_flags & IFF_RUNNING))
938 nfe_init(sc);
939 }
940 } else {
941 if (ifp->if_flags & IFF_RUNNING)
942 nfe_stop(sc);
943 }
944 sc->sc_if_flags = ifp->if_flags;
945 break;
946 case SIOCADDMULTI:
947 case SIOCDELMULTI:
948 if (ifp->if_flags & IFF_RUNNING)
949 nfe_setmulti(sc);
950 break;
951 case SIOCSIFMEDIA:
952 case SIOCGIFMEDIA:
953 mii = device_get_softc(sc->sc_miibus);
954 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
955 break;
956 case SIOCSIFCAP:
957 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
958 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
959 ifp->if_capenable ^= mask;
960 if (IFCAP_TXCSUM & ifp->if_capenable)
961 ifp->if_hwassist = NFE_CSUM_FEATURES;
962 else
963 ifp->if_hwassist = 0;
964
965 if (ifp->if_flags & IFF_RUNNING)
966 nfe_init(sc);
967 }
968 break;
969 default:
970 error = ether_ioctl(ifp, cmd, data);
971 break;
972 }
973 return error;
974 }
975
976 static int
977 nfe_rxeof(struct nfe_softc *sc)
978 {
979 struct ifnet *ifp = &sc->arpcom.ac_if;
980 struct nfe_rx_ring *ring = &sc->rxq;
981 int reap;
982 #ifdef ETHER_INPUT_CHAIN
983 struct mbuf_chain chain[MAXCPU];
984 #endif
985
986 reap = 0;
987 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
988
989 #ifdef ETHER_INPUT_CHAIN
990 ether_input_chain_init(chain);
991 #endif
992
993 for (;;) {
994 struct nfe_rx_data *data = &ring->data[ring->cur];
995 struct mbuf *m;
996 uint16_t flags;
997 int len, error;
998
999 if (sc->sc_caps & NFE_40BIT_ADDR) {
1000 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1001
1002 flags = le16toh(desc64->flags);
1003 len = le16toh(desc64->length) & 0x3fff;
1004 } else {
1005 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1006
1007 flags = le16toh(desc32->flags);
1008 len = le16toh(desc32->length) & 0x3fff;
1009 }
1010
1011 if (flags & NFE_RX_READY)
1012 break;
1013
1014 reap = 1;
1015
1016 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1017 if (!(flags & NFE_RX_VALID_V1))
1018 goto skip;
1019
1020 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1021 flags &= ~NFE_RX_ERROR;
1022 len--; /* fix buffer length */
1023 }
1024 } else {
1025 if (!(flags & NFE_RX_VALID_V2))
1026 goto skip;
1027
1028 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1029 flags &= ~NFE_RX_ERROR;
1030 len--; /* fix buffer length */
1031 }
1032 }
1033
1034 if (flags & NFE_RX_ERROR) {
1035 ifp->if_ierrors++;
1036 goto skip;
1037 }
1038
1039 m = data->m;
1040
1041 if (sc->sc_flags & NFE_F_USE_JUMBO)
1042 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1043 else
1044 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1045 if (error) {
1046 ifp->if_ierrors++;
1047 goto skip;
1048 }
1049
1050 /* finalize mbuf */
1051 m->m_pkthdr.len = m->m_len = len;
1052 m->m_pkthdr.rcvif = ifp;
1053
1054 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1055 (flags & NFE_RX_CSUMOK)) {
1056 if (flags & NFE_RX_IP_CSUMOK_V2) {
1057 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1058 CSUM_IP_VALID;
1059 }
1060
1061 if (flags &
1062 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1063 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1064 CSUM_PSEUDO_HDR |
1065 CSUM_FRAG_NOT_CHECKED;
1066 m->m_pkthdr.csum_data = 0xffff;
1067 }
1068 }
1069
1070 ifp->if_ipackets++;
1071 #ifdef ETHER_INPUT_CHAIN
1072 #ifdef ETHER_INPUT2
1073 ether_input_chain2(ifp, m, chain);
1074 #else
1075 ether_input_chain(ifp, m, chain);
1076 #endif
1077 #else
1078 ifp->if_input(ifp, m);
1079 #endif
1080 skip:
1081 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1082 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1083 }
1084
1085 if (reap) {
1086 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1087 #ifdef ETHER_INPUT_CHAIN
1088 ether_input_dispatch(chain);
1089 #endif
1090 }
1091 return reap;
1092 }
1093
1094 static int
1095 nfe_txeof(struct nfe_softc *sc)
1096 {
1097 struct ifnet *ifp = &sc->arpcom.ac_if;
1098 struct nfe_tx_ring *ring = &sc->txq;
1099 struct nfe_tx_data *data = NULL;
1100
1101 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1102 while (ring->next != ring->cur) {
1103 uint16_t flags;
1104
1105 if (sc->sc_caps & NFE_40BIT_ADDR)
1106 flags = le16toh(ring->desc64[ring->next].flags);
1107 else
1108 flags = le16toh(ring->desc32[ring->next].flags);
1109
1110 if (flags & NFE_TX_VALID)
1111 break;
1112
1113 data = &ring->data[ring->next];
1114
1115 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1116 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1117 goto skip;
1118
1119 if ((flags & NFE_TX_ERROR_V1) != 0) {
1120 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1121 NFE_V1_TXERR);
1122 ifp->if_oerrors++;
1123 } else {
1124 ifp->if_opackets++;
1125 }
1126 } else {
1127 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1128 goto skip;
1129
1130 if ((flags & NFE_TX_ERROR_V2) != 0) {
1131 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1132 NFE_V2_TXERR);
1133 ifp->if_oerrors++;
1134 } else {
1135 ifp->if_opackets++;
1136 }
1137 }
1138
1139 if (data->m == NULL) { /* should not get there */
1140 if_printf(ifp,
1141 "last fragment bit w/o associated mbuf!\n");
1142 goto skip;
1143 }
1144
1145 /* last fragment of the mbuf chain transmitted */
1146 bus_dmamap_sync(ring->data_tag, data->map,
1147 BUS_DMASYNC_POSTWRITE);
1148 bus_dmamap_unload(ring->data_tag, data->map);
1149 m_freem(data->m);
1150 data->m = NULL;
1151
1152 ifp->if_timer = 0;
1153 skip:
1154 ring->queued--;
1155 KKASSERT(ring->queued >= 0);
1156 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1157 }
1158
1159 if (data != NULL) { /* at least one slot freed */
1160 ifp->if_flags &= ~IFF_OACTIVE;
1161 if_devstart(ifp);
1162 return 1;
1163 }
1164 return 0;
1165 }
1166
1167 static int
1168 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1169 {
1170 struct nfe_dma_ctx ctx;
1171 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1172 struct nfe_tx_data *data, *data_map;
1173 bus_dmamap_t map;
1174 struct nfe_desc64 *desc64 = NULL;
1175 struct nfe_desc32 *desc32 = NULL;
1176 uint16_t flags = 0;
1177 uint32_t vtag = 0;
1178 int error, i, j;
1179
1180 data = &ring->data[ring->cur];
1181 map = data->map;
1182 data_map = data; /* Remember who owns the DMA map */
1183
1184 ctx.nsegs = NFE_MAX_SCATTER;
1185 ctx.segs = segs;
1186 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1187 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1188 if (!error && ctx.nsegs == 0) {
1189 bus_dmamap_unload(ring->data_tag, map);
1190 error = EFBIG;
1191 }
1192 if (error && error != EFBIG) {
1193 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1194 goto back;
1195 }
1196 if (error) { /* error == EFBIG */
1197 struct mbuf *m_new;
1198
1199 m_new = m_defrag(m0, MB_DONTWAIT);
1200 if (m_new == NULL) {
1201 if_printf(&sc->arpcom.ac_if,
1202 "could not defrag TX mbuf\n");
1203 error = ENOBUFS;
1204 goto back;
1205 } else {
1206 m0 = m_new;
1207 }
1208
1209 ctx.nsegs = NFE_MAX_SCATTER;
1210 ctx.segs = segs;
1211 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1212 nfe_buf_dma_addr, &ctx,
1213 BUS_DMA_NOWAIT);
1214 if (error || ctx.nsegs == 0) {
1215 if (!error) {
1216 bus_dmamap_unload(ring->data_tag, map);
1217 error = EFBIG;
1218 }
1219 if_printf(&sc->arpcom.ac_if,
1220 "could not map defraged TX mbuf\n");
1221 goto back;
1222 }
1223 }
1224
1225 error = 0;
1226
1227 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1228 bus_dmamap_unload(ring->data_tag, map);
1229 error = ENOBUFS;
1230 goto back;
1231 }
1232
1233 /* setup h/w VLAN tagging */
1234 if (m0->m_flags & M_VLANTAG)
1235 vtag = m0->m_pkthdr.ether_vlantag;
1236
1237 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1238 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1239 flags |= NFE_TX_IP_CSUM;
1240 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1241 flags |= NFE_TX_TCP_CSUM;
1242 }
1243
1244 /*
1245 * XXX urm. somebody is unaware of how hardware works. You
1246 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1247 * the ring until the entire chain is actually *VALID*. Otherwise
1248 * the hardware may encounter a partially initialized chain that
1249 * is marked as being ready to go when it in fact is not ready to
1250 * go.
1251 */
1252
1253 for (i = 0; i < ctx.nsegs; i++) {
1254 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1255 data = &ring->data[j];
1256
1257 if (sc->sc_caps & NFE_40BIT_ADDR) {
1258 desc64 = &ring->desc64[j];
1259 #if defined(__LP64__)
1260 desc64->physaddr[0] =
1261 htole32(segs[i].ds_addr >> 32);
1262 #endif
1263 desc64->physaddr[1] =
1264 htole32(segs[i].ds_addr & 0xffffffff);
1265 desc64->length = htole16(segs[i].ds_len - 1);
1266 desc64->vtag = htole32(vtag);
1267 desc64->flags = htole16(flags);
1268 } else {
1269 desc32 = &ring->desc32[j];
1270 desc32->physaddr = htole32(segs[i].ds_addr);
1271 desc32->length = htole16(segs[i].ds_len - 1);
1272 desc32->flags = htole16(flags);
1273 }
1274
1275 /* csum flags and vtag belong to the first fragment only */
1276 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1277 vtag = 0;
1278
1279 ring->queued++;
1280 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1281 }
1282
1283 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1284 if (sc->sc_caps & NFE_40BIT_ADDR) {
1285 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1286 } else {
1287 if (sc->sc_caps & NFE_JUMBO_SUP)
1288 flags = NFE_TX_LASTFRAG_V2;
1289 else
1290 flags = NFE_TX_LASTFRAG_V1;
1291 desc32->flags |= htole16(flags);
1292 }
1293
1294 /*
1295 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1296 * whole mess until the first descriptor in the map is flagged.
1297 */
1298 for (i = ctx.nsegs - 1; i >= 0; --i) {
1299 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1300 if (sc->sc_caps & NFE_40BIT_ADDR) {
1301 desc64 = &ring->desc64[j];
1302 desc64->flags |= htole16(NFE_TX_VALID);
1303 } else {
1304 desc32 = &ring->desc32[j];
1305 desc32->flags |= htole16(NFE_TX_VALID);
1306 }
1307 }
1308 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1309
1310 /* Exchange DMA map */
1311 data_map->map = data->map;
1312 data->map = map;
1313 data->m = m0;
1314
1315 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1316 back:
1317 if (error)
1318 m_freem(m0);
1319 return error;
1320 }
1321
1322 static void
1323 nfe_start(struct ifnet *ifp)
1324 {
1325 struct nfe_softc *sc = ifp->if_softc;
1326 struct nfe_tx_ring *ring = &sc->txq;
1327 int count = 0;
1328 struct mbuf *m0;
1329
1330 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1331 return;
1332
1333 for (;;) {
1334 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1335 if (m0 == NULL)
1336 break;
1337
1338 ETHER_BPF_MTAP(ifp, m0);
1339
1340 if (nfe_encap(sc, ring, m0) != 0) {
1341 ifp->if_flags |= IFF_OACTIVE;
1342 break;
1343 }
1344 ++count;
1345
1346 /*
1347 * NOTE:
1348 * `m0' may be freed in nfe_encap(), so
1349 * it should not be touched any more.
1350 */
1351 }
1352 if (count == 0) /* nothing sent */
1353 return;
1354
1355 /* Sync TX descriptor ring */
1356 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1357
1358 /* Kick Tx */
1359 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1360
1361 /*
1362 * Set a timeout in case the chip goes out to lunch.
1363 */
1364 ifp->if_timer = 5;
1365 }
1366
1367 static void
1368 nfe_watchdog(struct ifnet *ifp)
1369 {
1370 struct nfe_softc *sc = ifp->if_softc;
1371
1372 if (ifp->if_flags & IFF_RUNNING) {
1373 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1374 nfe_txeof(sc);
1375 return;
1376 }
1377
1378 if_printf(ifp, "watchdog timeout\n");
1379
1380 nfe_init(ifp->if_softc);
1381
1382 ifp->if_oerrors++;
1383 }
1384
1385 static void
1386 nfe_init(void *xsc)
1387 {
1388 struct nfe_softc *sc = xsc;
1389 struct ifnet *ifp = &sc->arpcom.ac_if;
1390 uint32_t tmp;
1391 int error;
1392
1393 nfe_stop(sc);
1394
1395 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1396 nfe_mac_reset(sc);
1397
1398 /*
1399 * NOTE:
1400 * Switching between jumbo frames and normal frames should
1401 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1402 */
1403 if (ifp->if_mtu > ETHERMTU) {
1404 sc->sc_flags |= NFE_F_USE_JUMBO;
1405 sc->rxq.bufsz = NFE_JBYTES;
1406 if (bootverbose)
1407 if_printf(ifp, "use jumbo frames\n");
1408 } else {
1409 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1410 sc->rxq.bufsz = MCLBYTES;
1411 if (bootverbose)
1412 if_printf(ifp, "use non-jumbo frames\n");
1413 }
1414
1415 error = nfe_init_tx_ring(sc, &sc->txq);
1416 if (error) {
1417 nfe_stop(sc);
1418 return;
1419 }
1420
1421 error = nfe_init_rx_ring(sc, &sc->rxq);
1422 if (error) {
1423 nfe_stop(sc);
1424 return;
1425 }
1426
1427 NFE_WRITE(sc, NFE_TX_POLL, 0);
1428 NFE_WRITE(sc, NFE_STATUS, 0);
1429
1430 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1431
1432 if (ifp->if_capenable & IFCAP_RXCSUM)
1433 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1434
1435 /*
1436 * Although the adapter is capable of stripping VLAN tags from received
1437 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1438 * purpose. This will be done in software by our network stack.
1439 */
1440 if (sc->sc_caps & NFE_HW_VLAN)
1441 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1442
1443 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1444 DELAY(10);
1445 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1446
1447 if (sc->sc_caps & NFE_HW_VLAN)
1448 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1449
1450 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1451
1452 /* set MAC address */
1453 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1454
1455 /* tell MAC where rings are in memory */
1456 #ifdef __LP64__
1457 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1458 #endif
1459 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1460 #ifdef __LP64__
1461 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1462 #endif
1463 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1464
1465 NFE_WRITE(sc, NFE_RING_SIZE,
1466 (sc->sc_rx_ring_count - 1) << 16 |
1467 (NFE_TX_RING_COUNT - 1));
1468
1469 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1470
1471 /* force MAC to wakeup */
1472 tmp = NFE_READ(sc, NFE_PWR_STATE);
1473 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1474 DELAY(10);
1475 tmp = NFE_READ(sc, NFE_PWR_STATE);
1476 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1477
1478 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1479 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1480 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1481
1482 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1483 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1484
1485 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1486
1487 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1488 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1489 DELAY(10);
1490 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1491
1492 /* set Rx filter */
1493 nfe_setmulti(sc);
1494
1495 nfe_ifmedia_upd(ifp);
1496
1497 /* enable Rx */
1498 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1499
1500 /* enable Tx */
1501 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1502
1503 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1504
1505 #ifdef DEVICE_POLLING
1506 if ((ifp->if_flags & IFF_POLLING))
1507 nfe_disable_intrs(sc);
1508 else
1509 #endif
1510 nfe_enable_intrs(sc);
1511
1512 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1513
1514 ifp->if_flags |= IFF_RUNNING;
1515 ifp->if_flags &= ~IFF_OACTIVE;
1516
1517 /*
1518 * If we had stuff in the tx ring before its all cleaned out now
1519 * so we are not going to get an interrupt, jump-start any pending
1520 * output.
1521 */
1522 if_devstart(ifp);
1523 }
1524
1525 static void
1526 nfe_stop(struct nfe_softc *sc)
1527 {
1528 struct ifnet *ifp = &sc->arpcom.ac_if;
1529 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1530 int i;
1531
1532 callout_stop(&sc->sc_tick_ch);
1533
1534 ifp->if_timer = 0;
1535 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1536 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1537
1538 #define WAITMAX 50000
1539
1540 /*
1541 * Abort Tx
1542 */
1543 NFE_WRITE(sc, NFE_TX_CTL, 0);
1544 for (i = 0; i < WAITMAX; ++i) {
1545 DELAY(100);
1546 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1547 break;
1548 }
1549 if (i == WAITMAX)
1550 if_printf(ifp, "can't stop TX\n");
1551 DELAY(100);
1552
1553 /*
1554 * Disable Rx
1555 */
1556 NFE_WRITE(sc, NFE_RX_CTL, 0);
1557 for (i = 0; i < WAITMAX; ++i) {
1558 DELAY(100);
1559 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1560 break;
1561 }
1562 if (i == WAITMAX)
1563 if_printf(ifp, "can't stop RX\n");
1564 DELAY(100);
1565
1566 #undef WAITMAX
1567
1568 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1569 DELAY(10);
1570 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1571
1572 /* Disable interrupts */
1573 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1574
1575 /* Reset Tx and Rx rings */
1576 nfe_reset_tx_ring(sc, &sc->txq);
1577 nfe_reset_rx_ring(sc, &sc->rxq);
1578 }
1579
1580 static int
1581 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1582 {
1583 int i, j, error, descsize;
1584 void **desc;
1585
1586 if (sc->sc_caps & NFE_40BIT_ADDR) {
1587 desc = (void **)&ring->desc64;
1588 descsize = sizeof(struct nfe_desc64);
1589 } else {
1590 desc = (void **)&ring->desc32;
1591 descsize = sizeof(struct nfe_desc32);
1592 }
1593
1594 ring->bufsz = MCLBYTES;
1595 ring->cur = ring->next = 0;
1596
1597 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1598 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1599 NULL, NULL,
1600 sc->sc_rx_ring_count * descsize, 1,
1601 BUS_SPACE_MAXSIZE_32BIT,
1602 0, &ring->tag);
1603 if (error) {
1604 if_printf(&sc->arpcom.ac_if,
1605 "could not create desc RX DMA tag\n");
1606 return error;
1607 }
1608
1609 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1610 &ring->map);
1611 if (error) {
1612 if_printf(&sc->arpcom.ac_if,
1613 "could not allocate RX desc DMA memory\n");
1614 bus_dma_tag_destroy(ring->tag);
1615 ring->tag = NULL;
1616 return error;
1617 }
1618
1619 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1620 sc->sc_rx_ring_count * descsize,
1621 nfe_ring_dma_addr, &ring->physaddr,
1622 BUS_DMA_WAITOK);
1623 if (error) {
1624 if_printf(&sc->arpcom.ac_if,
1625 "could not load RX desc DMA map\n");
1626 bus_dmamem_free(ring->tag, *desc, ring->map);
1627 bus_dma_tag_destroy(ring->tag);
1628 ring->tag = NULL;
1629 return error;
1630 }
1631
1632 if (sc->sc_caps & NFE_JUMBO_SUP) {
1633 ring->jbuf =
1634 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1635 M_DEVBUF, M_WAITOK | M_ZERO);
1636
1637 error = nfe_jpool_alloc(sc, ring);
1638 if (error) {
1639 if_printf(&sc->arpcom.ac_if,
1640 "could not allocate jumbo frames\n");
1641 kfree(ring->jbuf, M_DEVBUF);
1642 ring->jbuf = NULL;
1643 /* Allow jumbo frame allocation to fail */
1644 }
1645 }
1646
1647 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1648 M_DEVBUF, M_WAITOK | M_ZERO);
1649
1650 error = bus_dma_tag_create(NULL, 1, 0,
1651 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1652 NULL, NULL,
1653 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT,
1654 BUS_DMA_ALLOCNOW, &ring->data_tag);
1655 if (error) {
1656 if_printf(&sc->arpcom.ac_if,
1657 "could not create RX mbuf DMA tag\n");
1658 return error;
1659 }
1660
1661 /* Create a spare RX mbuf DMA map */
1662 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1663 if (error) {
1664 if_printf(&sc->arpcom.ac_if,
1665 "could not create spare RX mbuf DMA map\n");
1666 bus_dma_tag_destroy(ring->data_tag);
1667 ring->data_tag = NULL;
1668 return error;
1669 }
1670
1671 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1672 error = bus_dmamap_create(ring->data_tag, 0,
1673 &ring->data[i].map);
1674 if (error) {
1675 if_printf(&sc->arpcom.ac_if,
1676 "could not create %dth RX mbuf DMA mapn", i);
1677 goto fail;
1678 }
1679 }
1680 return 0;
1681 fail:
1682 for (j = 0; j < i; ++j)
1683 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1684 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1685 bus_dma_tag_destroy(ring->data_tag);
1686 ring->data_tag = NULL;
1687 return error;
1688 }
1689
1690 static void
1691 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1692 {
1693 int i;
1694
1695 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1696 struct nfe_rx_data *data = &ring->data[i];
1697
1698 if (data->m != NULL) {
1699 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1700 bus_dmamap_unload(ring->data_tag, data->map);
1701 m_freem(data->m);
1702 data->m = NULL;
1703 }
1704 }
1705 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1706
1707 ring->cur = ring->next = 0;
1708 }
1709
1710 static int
1711 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1712 {
1713 int i;
1714
1715 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1716 int error;
1717
1718 /* XXX should use a function pointer */
1719 if (sc->sc_flags & NFE_F_USE_JUMBO)
1720 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1721 else
1722 error = nfe_newbuf_std(sc, ring, i, 1);
1723 if (error) {
1724 if_printf(&sc->arpcom.ac_if,
1725 "could not allocate RX buffer\n");
1726 return error;
1727 }
1728
1729 nfe_set_ready_rxdesc(sc, ring, i);
1730 }
1731 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1732
1733 return 0;
1734 }
1735
1736 static void
1737 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1738 {
1739 if (ring->data_tag != NULL) {
1740 struct nfe_rx_data *data;
1741 int i;
1742
1743 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1744 data = &ring->data[i];
1745
1746 if (data->m != NULL) {
1747 bus_dmamap_unload(ring->data_tag, data->map);
1748 m_freem(data->m);
1749 }
1750 bus_dmamap_destroy(ring->data_tag, data->map);
1751 }
1752 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1753 bus_dma_tag_destroy(ring->data_tag);
1754 }
1755
1756 nfe_jpool_free(sc, ring);
1757
1758 if (ring->jbuf != NULL)
1759 kfree(ring->jbuf, M_DEVBUF);
1760 if (ring->data != NULL)
1761 kfree(ring->data, M_DEVBUF);
1762
1763 if (ring->tag != NULL) {
1764 void *desc;
1765
1766 if (sc->sc_caps & NFE_40BIT_ADDR)
1767 desc = ring->desc64;
1768 else
1769 desc = ring->desc32;
1770
1771 bus_dmamap_unload(ring->tag, ring->map);
1772 bus_dmamem_free(ring->tag, desc, ring->map);
1773 bus_dma_tag_destroy(ring->tag);
1774 }
1775 }
1776
1777 static struct nfe_jbuf *
1778 nfe_jalloc(struct nfe_softc *sc)
1779 {
1780 struct ifnet *ifp = &sc->arpcom.ac_if;
1781 struct nfe_jbuf *jbuf;
1782
1783 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1784
1785 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1786 if (jbuf != NULL) {
1787 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1788 jbuf->inuse = 1;
1789 } else {
1790 if_printf(ifp, "no free jumbo buffer\n");
1791 }
1792
1793 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1794
1795 return jbuf;
1796 }
1797
1798 static void
1799 nfe_jfree(void *arg)
1800 {
1801 struct nfe_jbuf *jbuf = arg;
1802 struct nfe_softc *sc = jbuf->sc;
1803 struct nfe_rx_ring *ring = jbuf->ring;
1804
1805 if (&ring->jbuf[jbuf->slot] != jbuf)
1806 panic("%s: free wrong jumbo buffer\n", __func__);
1807 else if (jbuf->inuse == 0)
1808 panic("%s: jumbo buffer already freed\n", __func__);
1809
1810 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1811 atomic_subtract_int(&jbuf->inuse, 1);
1812 if (jbuf->inuse == 0)
1813 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1814 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1815 }
1816
1817 static void
1818 nfe_jref(void *arg)
1819 {
1820 struct nfe_jbuf *jbuf = arg;
1821 struct nfe_rx_ring *ring = jbuf->ring;
1822
1823 if (&ring->jbuf[jbuf->slot] != jbuf)
1824 panic("%s: ref wrong jumbo buffer\n", __func__);
1825 else if (jbuf->inuse == 0)
1826 panic("%s: jumbo buffer already freed\n", __func__);
1827
1828 atomic_add_int(&jbuf->inuse, 1);
1829 }
1830
1831 static int
1832 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1833 {
1834 struct nfe_jbuf *jbuf;
1835 bus_addr_t physaddr;
1836 caddr_t buf;
1837 int i, error;
1838
1839 /*
1840 * Allocate a big chunk of DMA'able memory.
1841 */
1842 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1843 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1844 NULL, NULL,
1845 NFE_JPOOL_SIZE(sc), 1,
1846 BUS_SPACE_MAXSIZE_32BIT,
1847 0, &ring->jtag);
1848 if (error) {
1849 if_printf(&sc->arpcom.ac_if,
1850 "could not create jumbo DMA tag\n");
1851 return error;
1852 }
1853
1854 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1855 BUS_DMA_WAITOK, &ring->jmap);
1856 if (error) {
1857 if_printf(&sc->arpcom.ac_if,
1858 "could not allocate jumbo DMA memory\n");
1859 bus_dma_tag_destroy(ring->jtag);
1860 ring->jtag = NULL;
1861 return error;
1862 }
1863
1864 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1865 NFE_JPOOL_SIZE(sc),
1866 nfe_ring_dma_addr, &physaddr, BUS_DMA_WAITOK);
1867 if (error) {
1868 if_printf(&sc->arpcom.ac_if,
1869 "could not load jumbo DMA map\n");
1870 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1871 bus_dma_tag_destroy(ring->jtag);
1872 ring->jtag = NULL;
1873 return error;
1874 }
1875
1876 /* ..and split it into 9KB chunks */
1877 SLIST_INIT(&ring->jfreelist);
1878
1879 buf = ring->jpool;
1880 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1881 jbuf = &ring->jbuf[i];
1882
1883 jbuf->sc = sc;
1884 jbuf->ring = ring;
1885 jbuf->inuse = 0;
1886 jbuf->slot = i;
1887 jbuf->buf = buf;
1888 jbuf->physaddr = physaddr;
1889
1890 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1891
1892 buf += NFE_JBYTES;
1893 physaddr += NFE_JBYTES;
1894 }
1895
1896 return 0;
1897 }
1898
1899 static void
1900 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1901 {
1902 if (ring->jtag != NULL) {
1903 bus_dmamap_unload(ring->jtag, ring->jmap);
1904 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1905 bus_dma_tag_destroy(ring->jtag);
1906 }
1907 }
1908
1909 static int
1910 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1911 {
1912 int i, j, error, descsize;
1913 void **desc;
1914
1915 if (sc->sc_caps & NFE_40BIT_ADDR) {
1916 desc = (void **)&ring->desc64;
1917 descsize = sizeof(struct nfe_desc64);
1918 } else {
1919 desc = (void **)&ring->desc32;
1920 descsize = sizeof(struct nfe_desc32);
1921 }
1922
1923 ring->queued = 0;
1924 ring->cur = ring->next = 0;
1925
1926 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1927 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1928 NULL, NULL,
1929 NFE_TX_RING_COUNT * descsize, 1,
1930 BUS_SPACE_MAXSIZE_32BIT,
1931 0, &ring->tag);
1932 if (error) {
1933 if_printf(&sc->arpcom.ac_if,
1934 "could not create TX desc DMA map\n");
1935 return error;
1936 }
1937
1938 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1939 &ring->map);
1940 if (error) {
1941 if_printf(&sc->arpcom.ac_if,
1942 "could not allocate TX desc DMA memory\n");
1943 bus_dma_tag_destroy(ring->tag);
1944 ring->tag = NULL;
1945 return error;
1946 }
1947
1948 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1949 NFE_TX_RING_COUNT * descsize,
1950 nfe_ring_dma_addr, &ring->physaddr,
1951 BUS_DMA_WAITOK);
1952 if (error) {
1953 if_printf(&sc->arpcom.ac_if,
1954 "could not load TX desc DMA map\n");
1955 bus_dmamem_free(ring->tag, *desc, ring->map);
1956 bus_dma_tag_destroy(ring->tag);
1957 ring->tag = NULL;
1958 return error;
1959 }
1960
1961 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1962 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1963 NULL, NULL,
1964 NFE_JBYTES, NFE_MAX_SCATTER,
1965 BUS_SPACE_MAXSIZE_32BIT,
1966 BUS_DMA_ALLOCNOW, &ring->data_tag);
1967 if (error) {
1968 if_printf(&sc->arpcom.ac_if,
1969 "could not create TX buf DMA tag\n");
1970 return error;
1971 }
1972
1973 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1974 error = bus_dmamap_create(ring->data_tag, 0,
1975 &ring->data[i].map);
1976 if (error) {
1977 if_printf(&sc->arpcom.ac_if,
1978 "could not create %dth TX buf DMA map\n", i);
1979 goto fail;
1980 }
1981 }
1982
1983 return 0;
1984 fail:
1985 for (j = 0; j < i; ++j)
1986 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1987 bus_dma_tag_destroy(ring->data_tag);
1988 ring->data_tag = NULL;
1989 return error;
1990 }
1991
1992 static void
1993 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1994 {
1995 int i;
1996
1997 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1998 struct nfe_tx_data *data = &ring->data[i];
1999
2000 if (sc->sc_caps & NFE_40BIT_ADDR)
2001 ring->desc64[i].flags = 0;
2002 else
2003 ring->desc32[i].flags = 0;
2004
2005 if (data->m != NULL) {
2006 bus_dmamap_sync(ring->data_tag, data->map,
2007 BUS_DMASYNC_POSTWRITE);
2008 bus_dmamap_unload(ring->data_tag, data->map);
2009 m_freem(data->m);
2010 data->m = NULL;
2011 }
2012 }
2013 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
2014
2015 ring->queued = 0;
2016 ring->cur = ring->next = 0;
2017 }
2018
2019 static int
2020 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2021 struct nfe_tx_ring *ring __unused)
2022 {
2023 return 0;
2024 }
2025
2026 static void
2027 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2028 {
2029 if (ring->data_tag != NULL) {
2030 struct nfe_tx_data *data;
2031 int i;
2032
2033 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
2034 data = &ring->data[i];
2035
2036 if (data->m != NULL) {
2037 bus_dmamap_unload(ring->data_tag, data->map);
2038 m_freem(data->m);
2039 }
2040 bus_dmamap_destroy(ring->data_tag, data->map);
2041 }
2042
2043 bus_dma_tag_destroy(ring->data_tag);
2044 }
2045
2046 if (ring->tag != NULL) {
2047 void *desc;
2048
2049 if (sc->sc_caps & NFE_40BIT_ADDR)
2050 desc = ring->desc64;
2051 else
2052 desc = ring->desc32;
2053
2054 bus_dmamap_unload(ring->tag, ring->map);
2055 bus_dmamem_free(ring->tag, desc, ring->map);
2056 bus_dma_tag_destroy(ring->tag);
2057 }
2058 }
2059
2060 static int
2061 nfe_ifmedia_upd(struct ifnet *ifp)
2062 {
2063 struct nfe_softc *sc = ifp->if_softc;
2064 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2065
2066 if (mii->mii_instance != 0) {
2067 struct mii_softc *miisc;
2068
2069 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2070 mii_phy_reset(miisc);
2071 }
2072 mii_mediachg(mii);
2073
2074 return 0;
2075 }
2076
2077 static void
2078 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2079 {
2080 struct nfe_softc *sc = ifp->if_softc;
2081 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2082
2083 mii_pollstat(mii);
2084 ifmr->ifm_status = mii->mii_media_status;
2085 ifmr->ifm_active = mii->mii_media_active;
2086 }
2087
2088 static void
2089 nfe_setmulti(struct nfe_softc *sc)
2090 {
2091 struct ifnet *ifp = &sc->arpcom.ac_if;
2092 struct ifmultiaddr *ifma;
2093 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2094 uint32_t filter = NFE_RXFILTER_MAGIC;
2095 int i;
2096
2097 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2098 bzero(addr, ETHER_ADDR_LEN);
2099 bzero(mask, ETHER_ADDR_LEN);
2100 goto done;
2101 }
2102
2103 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2104 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2105
2106 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2107 caddr_t maddr;
2108
2109 if (ifma->ifma_addr->sa_family != AF_LINK)
2110 continue;
2111
2112 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2113 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2114 addr[i] &= maddr[i];
2115 mask[i] &= ~maddr[i];
2116 }
2117 }
2118
2119 for (i = 0; i < ETHER_ADDR_LEN; i++)
2120 mask[i] |= addr[i];
2121
2122 done:
2123 addr[0] |= 0x01; /* make sure multicast bit is set */
2124
2125 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2126 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2127 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2128 addr[5] << 8 | addr[4]);
2129 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2130 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2131 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2132 mask[5] << 8 | mask[4]);
2133
2134 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2135 NFE_WRITE(sc, NFE_RXFILTER, filter);
2136 }
2137
2138 static void
2139 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2140 {
2141 uint32_t lo, hi;
2142
2143 lo = NFE_READ(sc, NFE_MACADDR_LO);
2144 hi = NFE_READ(sc, NFE_MACADDR_HI);
2145 if (sc->sc_caps & NFE_FIX_EADDR) {
2146 addr[0] = (lo >> 8) & 0xff;
2147 addr[1] = (lo & 0xff);
2148
2149 addr[2] = (hi >> 24) & 0xff;
2150 addr[3] = (hi >> 16) & 0xff;
2151 addr[4] = (hi >> 8) & 0xff;
2152 addr[5] = (hi & 0xff);
2153 } else {
2154 addr[0] = (hi & 0xff);
2155 addr[1] = (hi >> 8) & 0xff;
2156 addr[2] = (hi >> 16) & 0xff;
2157 addr[3] = (hi >> 24) & 0xff;
2158
2159 addr[4] = (lo & 0xff);
2160 addr[5] = (lo >> 8) & 0xff;
2161 }
2162 }
2163
2164 static void
2165 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2166 {
2167 NFE_WRITE(sc, NFE_MACADDR_LO,
2168 addr[5] << 8 | addr[4]);
2169 NFE_WRITE(sc, NFE_MACADDR_HI,
2170 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2171 }
2172
2173 static void
2174 nfe_tick(void *arg)
2175 {
2176 struct nfe_softc *sc = arg;
2177 struct ifnet *ifp = &sc->arpcom.ac_if;
2178 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2179
2180 lwkt_serialize_enter(ifp->if_serializer);
2181
2182 mii_tick(mii);
2183 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2184
2185 lwkt_serialize_exit(ifp->if_serializer);
2186 }
2187
2188 static void
2189 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2190 {
2191 if (error)
2192 return;
2193
2194 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2195
2196 *((uint32_t *)arg) = seg->ds_addr;
2197 }
2198
2199 static void
2200 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2201 bus_size_t mapsz __unused, int error)
2202 {
2203 struct nfe_dma_ctx *ctx = arg;
2204 int i;
2205
2206 if (error)
2207 return;
2208
2209 if (nsegs > ctx->nsegs) {
2210 ctx->nsegs = 0;
2211 return;
2212 }
2213
2214 ctx->nsegs = nsegs;
2215 for (i = 0; i < nsegs; ++i)
2216 ctx->segs[i] = segs[i];
2217 }
2218
2219 static int
2220 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2221 int wait)
2222 {
2223 struct nfe_rx_data *data = &ring->data[idx];
2224 struct nfe_dma_ctx ctx;
2225 bus_dma_segment_t seg;
2226 bus_dmamap_t map;
2227 struct mbuf *m;
2228 int error;
2229
2230 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2231 if (m == NULL)
2232 return ENOBUFS;
2233 m->m_len = m->m_pkthdr.len = MCLBYTES;
2234
2235 ctx.nsegs = 1;
2236 ctx.segs = &seg;
2237 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2238 m, nfe_buf_dma_addr, &ctx,
2239 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2240 if (error || ctx.nsegs == 0) {
2241 if (!error) {
2242 bus_dmamap_unload(ring->data_tag, ring->data_tmpmap);
2243 error = EFBIG;
2244 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2245 }
2246 m_freem(m);
2247
2248 if (wait) {
2249 if_printf(&sc->arpcom.ac_if,
2250 "could map RX mbuf %d\n", error);
2251 }
2252 return error;
2253 }
2254
2255 /* Unload originally mapped mbuf */
2256 bus_dmamap_unload(ring->data_tag, data->map);
2257
2258 /* Swap this DMA map with tmp DMA map */
2259 map = data->map;
2260 data->map = ring->data_tmpmap;
2261 ring->data_tmpmap = map;
2262
2263 /* Caller is assumed to have collected the old mbuf */
2264 data->m = m;
2265
2266 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2267
2268 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2269 return 0;
2270 }
2271
2272 static int
2273 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2274 int wait)
2275 {
2276 struct nfe_rx_data *data = &ring->data[idx];
2277 struct nfe_jbuf *jbuf;
2278 struct mbuf *m;
2279
2280 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2281 if (m == NULL)
2282 return ENOBUFS;
2283
2284 jbuf = nfe_jalloc(sc);
2285 if (jbuf == NULL) {
2286 m_freem(m);
2287 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2288 "-- packet dropped!\n");
2289 return ENOBUFS;
2290 }
2291
2292 m->m_ext.ext_arg = jbuf;
2293 m->m_ext.ext_buf = jbuf->buf;
2294 m->m_ext.ext_free = nfe_jfree;
2295 m->m_ext.ext_ref = nfe_jref;
2296 m->m_ext.ext_size = NFE_JBYTES;
2297
2298 m->m_data = m->m_ext.ext_buf;
2299 m->m_flags |= M_EXT;
2300 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2301
2302 /* Caller is assumed to have collected the old mbuf */
2303 data->m = m;
2304
2305 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2306
2307 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2308 return 0;
2309 }
2310
2311 static void
2312 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2313 bus_addr_t physaddr)
2314 {
2315 if (sc->sc_caps & NFE_40BIT_ADDR) {
2316 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2317
2318 #if defined(__LP64__)
2319 desc64->physaddr[0] = htole32(physaddr >> 32);
2320 #endif
2321 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2322 } else {
2323 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2324
2325 desc32->physaddr = htole32(physaddr);
2326 }
2327 }
2328
2329 static void
2330 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2331 {
2332 if (sc->sc_caps & NFE_40BIT_ADDR) {
2333 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2334
2335 desc64->length = htole16(ring->bufsz);
2336 desc64->flags = htole16(NFE_RX_READY);
2337 } else {
2338 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2339
2340 desc32->length = htole16(ring->bufsz);
2341 desc32->flags = htole16(NFE_RX_READY);
2342 }
2343 }
2344
2345 static int
2346 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2347 {
2348 struct nfe_softc *sc = arg1;
2349 struct ifnet *ifp = &sc->arpcom.ac_if;
2350 uint32_t flags;
2351 int error, v;
2352
2353 lwkt_serialize_enter(ifp->if_serializer);
2354
2355 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2356 v = sc->sc_imtime;
2357 if (sc->sc_flags & NFE_F_DYN_IM)
2358 v = -v;
2359
2360 error = sysctl_handle_int(oidp, &v, 0, req);
2361 if (error || req->newptr == NULL)
2362 goto back;
2363
2364 if (v < 0) {
2365 flags |= NFE_F_DYN_IM;
2366 v = -v;
2367 }
2368
2369 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2370 int old_imtime = sc->sc_imtime;
2371 uint32_t old_flags = sc->sc_flags;
2372
2373 sc->sc_imtime = v;
2374 sc->sc_flags = flags;
2375 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2376
2377 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2378 == IFF_RUNNING) {
2379 if (old_imtime * sc->sc_imtime == 0 ||
2380 (old_flags ^ sc->sc_flags)) {
2381 ifp->if_init(sc);
2382 } else {
2383 NFE_WRITE(sc, NFE_IMTIMER,
2384 NFE_IMTIME(sc->sc_imtime));
2385 }
2386 }
2387 }
2388 back:
2389 lwkt_serialize_exit(ifp->if_serializer);
2390 return error;
2391 }
2392
2393 static void
2394 nfe_powerup(device_t dev)
2395 {
2396 struct nfe_softc *sc = device_get_softc(dev);
2397 uint32_t pwr_state;
2398 uint16_t did;
2399
2400 /*
2401 * Bring MAC and PHY out of low power state
2402 */
2403
2404 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2405
2406 did = pci_get_device(dev);
2407 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2408 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2409 pci_get_revid(dev) >= 0xa3)
2410 pwr_state |= NFE_PWRUP_REV_A3;
2411
2412 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2413 }
2414
2415 static void
2416 nfe_mac_reset(struct nfe_softc *sc)
2417 {
2418 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2419 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2420
2421 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2422
2423 /* Save several registers for later restoration */
2424 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2425 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2426 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2427
2428 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2429 DELAY(100);
2430
2431 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2432 DELAY(100);
2433
2434 /* Restore saved registers */
2435 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2436 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2437 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2438
2439 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2440 }
2441
2442 static void
2443 nfe_enable_intrs(struct nfe_softc *sc)
2444 {
2445 /*
2446 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2447 * It is unclear how wide the timer is. Base programming does
2448 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2449 * we don't get any interrupt moderation. TX moderation is
2450 * possible by using the timer interrupt instead of TX_DONE.
2451 *
2452 * It is unclear whether there are other bits that can be
2453 * set to make the NFE device actually do interrupt moderation
2454 * on the RX side.
2455 *
2456 * For now set a 128uS interval as a placemark, but don't use
2457 * the timer.
2458 */
2459 if (sc->sc_imtime == 0)
2460 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2461 else
2462 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2463
2464 /* Enable interrupts */
2465 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2466
2467 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2468 sc->sc_flags |= NFE_F_IRQ_TIMER;
2469 else
2470 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2471 }
2472
2473 static void
2474 nfe_disable_intrs(struct nfe_softc *sc)
2475 {
2476 /* Disable interrupts */
2477 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2478 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2479 }
DragonFly BSD