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kprintf to device_printf conversion.
[dragonfly.git] / sys / bus / usb / ehci.c
blob047f0a872a6f18ac46e47b651d8190d83f1db38f
1 /* $NetBSD: ehci.c,v 1.91 2005/02/27 00:27:51 perry Exp $ */
2 /* $FreeBSD: src/sys/dev/usb/ehci.c,v 1.36.2.3 2006/09/24 13:39:04 iedowse Exp $ */
3 /* $DragonFly: src/sys/bus/usb/ehci.c,v 1.33 2008/05/21 19:56:46 mneumann Exp $ */
4
5 /*
6 * Copyright (c) 2004 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Lennart Augustsson (lennart@augustsson.net) and by Charles M. Hannum.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
43 *
44 * The EHCI 1.0 spec can be found at
45 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
46 * and the USB 2.0 spec at
47 * http://www.usb.org/developers/docs/usb_20.zip
48 *
49 */
50
51 /*
52 * TODO:
53 * 1) The EHCI driver lacks support for isochronous transfers, so
54 * devices using them don't work.
55 *
56 * 2) Interrupt transfer scheduling does not manage the time available
57 * in each frame, so it is possible for the transfers to overrun
58 * the end of the frame.
59 *
60 * 3) Command failures are not recovered correctly.
61 */
62
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/malloc.h>
66 #include <sys/kernel.h>
67 #include <sys/endian.h>
68 #include <sys/module.h>
69 #include <sys/bus.h>
70 #include <sys/lock.h>
71 #include <sys/proc.h>
72 #include <sys/queue.h>
73 #include <sys/sysctl.h>
74 #include <sys/thread2.h>
75
76 #include <machine/cpu.h>
77 #include <machine/endian.h>
78
79 #include <bus/usb/usb.h>
80 #include <bus/usb/usbdi.h>
81 #include <bus/usb/usbdivar.h>
82 #include <bus/usb/usb_mem.h>
83 #include <bus/usb/usb_quirks.h>
84
85 #include <bus/usb/ehcireg.h>
86 #include <bus/usb/ehcivar.h>
87
88 #define delay(d) DELAY(d)
89
90 #ifdef USB_DEBUG
91 #define EHCI_DEBUG USB_DEBUG
92 #define DPRINTF(x) do { if (ehcidebug) kprintf x; } while (0)
93 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) kprintf x; } while (0)
94 int ehcidebug = 0;
95 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
96 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
97 &ehcidebug, 0, "ehci debug level");
98 #define bitmask_snprintf(q,f,b,l) ksnprintf((b), (l), "%b", (q), (f))
99 #else
100 #define DPRINTF(x)
101 #define DPRINTFN(n,x)
102 #endif
103
104 struct ehci_pipe {
105 struct usbd_pipe pipe;
106
107 ehci_soft_qh_t *sqh;
108 union {
109 ehci_soft_qtd_t *qtd;
110 /* ehci_soft_itd_t *itd; */
111 } tail;
112 union {
113 /* Control pipe */
114 struct {
115 usb_dma_t reqdma;
116 u_int length;
117 /*ehci_soft_qtd_t *setup, *data, *stat;*/
118 } ctl;
119 /* Interrupt pipe */
120 struct {
121 u_int length;
122 } intr;
123 /* Bulk pipe */
124 struct {
125 u_int length;
126 } bulk;
127 /* Iso pipe */
128 /* XXX */
129 } u;
130 };
131
132 static usbd_status ehci_open(usbd_pipe_handle);
133 static void ehci_poll(struct usbd_bus *);
134 static void ehci_softintr(void *);
135 static int ehci_intr1(ehci_softc_t *);
136 static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
137 static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
138 static void ehci_idone(struct ehci_xfer *);
139 static void ehci_timeout(void *);
140 static void ehci_timeout_task(void *);
141 static void ehci_intrlist_timeout(void *);
142
143 static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
144 static void ehci_freem(struct usbd_bus *, usb_dma_t *);
145
146 static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
147 static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
148
149 static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
150 static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
151 static void ehci_root_ctrl_abort(usbd_xfer_handle);
152 static void ehci_root_ctrl_close(usbd_pipe_handle);
153 static void ehci_root_ctrl_done(usbd_xfer_handle);
154
155 static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
156 static usbd_status ehci_root_intr_start(usbd_xfer_handle);
157 static void ehci_root_intr_abort(usbd_xfer_handle);
158 static void ehci_root_intr_close(usbd_pipe_handle);
159 static void ehci_root_intr_done(usbd_xfer_handle);
160
161 static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
162 static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
163 static void ehci_device_ctrl_abort(usbd_xfer_handle);
164 static void ehci_device_ctrl_close(usbd_pipe_handle);
165 static void ehci_device_ctrl_done(usbd_xfer_handle);
166
167 static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
168 static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
169 static void ehci_device_bulk_abort(usbd_xfer_handle);
170 static void ehci_device_bulk_close(usbd_pipe_handle);
171 static void ehci_device_bulk_done(usbd_xfer_handle);
172
173 static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
174 static usbd_status ehci_device_intr_start(usbd_xfer_handle);
175 static void ehci_device_intr_abort(usbd_xfer_handle);
176 static void ehci_device_intr_close(usbd_pipe_handle);
177 static void ehci_device_intr_done(usbd_xfer_handle);
178
179 static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
180 static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
181 static void ehci_device_isoc_abort(usbd_xfer_handle);
182 static void ehci_device_isoc_close(usbd_pipe_handle);
183 static void ehci_device_isoc_done(usbd_xfer_handle);
184
185 static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
186 static void ehci_noop(usbd_pipe_handle pipe);
187
188 static int ehci_str(usb_string_descriptor_t *, int, char *);
189 static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
190 static void ehci_pcd_able(ehci_softc_t *, int);
191 static void ehci_pcd_enable(void *);
192 static void ehci_disown(ehci_softc_t *, int, int);
193
194 static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
195 static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
196
197 static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
198 static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
199 static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
200 ehci_softc_t *, int, int, usbd_xfer_handle,
201 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
202 static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
203 ehci_soft_qtd_t *);
204
205 static usbd_status ehci_device_request(usbd_xfer_handle xfer);
206
207 static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
208 int ival);
209
210 static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
211 static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
212 ehci_soft_qh_t *);
213 static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
214 static void ehci_sync_hc(ehci_softc_t *);
215
216 static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
217 static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
218
219 #ifdef EHCI_DEBUG
220 static void ehci_dump_regs(ehci_softc_t *);
221 void ehci_dump(void);
222 static ehci_softc_t *theehci;
223 static void ehci_dump_link(ehci_link_t, int);
224 static void ehci_dump_sqtds(ehci_soft_qtd_t *);
225 static void ehci_dump_sqtd(ehci_soft_qtd_t *);
226 static void ehci_dump_qtd(ehci_qtd_t *);
227 static void ehci_dump_sqh(ehci_soft_qh_t *);
228 #ifdef DIAGNOSTIC
229 static void ehci_dump_exfer(struct ehci_xfer *);
230 #endif
231 #endif
232
233 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
234
235 #define EHCI_INTR_ENDPT 1
236
237 #define ehci_add_intr_list(sc, ex) \
238 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
239 #define ehci_del_intr_list(ex) \
240 do { \
241 LIST_REMOVE((ex), inext); \
242 (ex)->inext.le_prev = NULL; \
243 } while (0)
244 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL)
245
246 static struct usbd_bus_methods ehci_bus_methods = {
247 ehci_open,
248 ehci_softintr,
249 ehci_poll,
250 ehci_allocm,
251 ehci_freem,
252 ehci_allocx,
253 ehci_freex,
254 };
255
256 static struct usbd_pipe_methods ehci_root_ctrl_methods = {
257 ehci_root_ctrl_transfer,
258 ehci_root_ctrl_start,
259 ehci_root_ctrl_abort,
260 ehci_root_ctrl_close,
261 ehci_noop,
262 ehci_root_ctrl_done,
263 };
264
265 static struct usbd_pipe_methods ehci_root_intr_methods = {
266 ehci_root_intr_transfer,
267 ehci_root_intr_start,
268 ehci_root_intr_abort,
269 ehci_root_intr_close,
270 ehci_noop,
271 ehci_root_intr_done,
272 };
273
274 static struct usbd_pipe_methods ehci_device_ctrl_methods = {
275 ehci_device_ctrl_transfer,
276 ehci_device_ctrl_start,
277 ehci_device_ctrl_abort,
278 ehci_device_ctrl_close,
279 ehci_noop,
280 ehci_device_ctrl_done,
281 };
282
283 static struct usbd_pipe_methods ehci_device_intr_methods = {
284 ehci_device_intr_transfer,
285 ehci_device_intr_start,
286 ehci_device_intr_abort,
287 ehci_device_intr_close,
288 ehci_device_clear_toggle,
289 ehci_device_intr_done,
290 };
291
292 static struct usbd_pipe_methods ehci_device_bulk_methods = {
293 ehci_device_bulk_transfer,
294 ehci_device_bulk_start,
295 ehci_device_bulk_abort,
296 ehci_device_bulk_close,
297 ehci_device_clear_toggle,
298 ehci_device_bulk_done,
299 };
300
301 static struct usbd_pipe_methods ehci_device_isoc_methods = {
302 ehci_device_isoc_transfer,
303 ehci_device_isoc_start,
304 ehci_device_isoc_abort,
305 ehci_device_isoc_close,
306 ehci_noop,
307 ehci_device_isoc_done,
308 };
309
310 usbd_status
311 ehci_init(ehci_softc_t *sc)
312 {
313 u_int32_t vers, sparams, cparams, hcr;
314 u_int i;
315 usbd_status err;
316 ehci_soft_qh_t *sqh;
317 u_int ncomp;
318 int lev;
319
320 DPRINTF(("ehci_init: start\n"));
321 #ifdef EHCI_DEBUG
322 theehci = sc;
323 #endif
324
325 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
326
327 vers = EREAD2(sc, EHCI_HCIVERSION);
328 device_printf(sc->sc_bus.bdev,
329 "EHCI version %x.%x\n", vers >> 8, vers & 0xff);
330
331 sparams = EREAD4(sc, EHCI_HCSPARAMS);
332 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
333 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
334 ncomp = EHCI_HCS_N_CC(sparams);
335 if (ncomp != sc->sc_ncomp) {
336 device_printf(sc->sc_bus.bdev,
337 "wrong number of companions (%d != %d)\n",
338 ncomp, sc->sc_ncomp);
339 if (ncomp < sc->sc_ncomp)
340 sc->sc_ncomp = ncomp;
341 }
342 if (sc->sc_ncomp > 0) {
343 device_printf(sc->sc_bus.bdev,
344 "companion controller%s, %d port%s each:",
345 sc->sc_ncomp!=1 ? "s" : "",
346 EHCI_HCS_N_PCC(sparams),
347 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
348 for (i = 0; i < sc->sc_ncomp; i++)
349 kprintf(" %s", device_get_nameunit(sc->sc_comps[i]->bdev));
350 kprintf("\n");
351 }
352 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
353 cparams = EREAD4(sc, EHCI_HCCPARAMS);
354 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
355
356 if (EHCI_HCC_64BIT(cparams)) {
357 /* MUST clear segment register if 64 bit capable. */
358 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
359 }
360
361 sc->sc_bus.usbrev = USBREV_2_0;
362
363 /* Reset the controller */
364 DPRINTF(("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)));
365 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
366 usb_delay_ms(&sc->sc_bus, 1);
367 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
368 for (i = 0; i < 100; i++) {
369 usb_delay_ms(&sc->sc_bus, 1);
370 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
371 if (!hcr)
372 break;
373 }
374 if (hcr) {
375 device_printf(sc->sc_bus.bdev, "reset timeout\n");
376 return (USBD_IOERROR);
377 }
378
379 /* frame list size at default, read back what we got and use that */
380 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
381 case 0: sc->sc_flsize = 1024; break;
382 case 1: sc->sc_flsize = 512; break;
383 case 2: sc->sc_flsize = 256; break;
384 case 3: return (USBD_IOERROR);
385 }
386 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
387 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
388 if (err)
389 return (err);
390 DPRINTF(("%s: flsize=%d\n", device_get_nameunit(sc->sc_bus.bdev),sc->sc_flsize));
391 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
392 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
393
394 /* Set up the bus struct. */
395 sc->sc_bus.methods = &ehci_bus_methods;
396 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
397
398 sc->sc_eintrs = EHCI_NORMAL_INTRS;
399
400 /*
401 * Allocate the interrupt dummy QHs. These are arranged to give
402 * poll intervals that are powers of 2 times 1ms.
403 */
404 for (i = 0; i < EHCI_INTRQHS; i++) {
405 sqh = ehci_alloc_sqh(sc);
406 if (sqh == NULL) {
407 err = USBD_NOMEM;
408 goto bad1;
409 }
410 sc->sc_islots[i].sqh = sqh;
411 }
412 lev = 0;
413 for (i = 0; i < EHCI_INTRQHS; i++) {
414 if (i == EHCI_IQHIDX(lev + 1, 0))
415 lev++;
416 sqh = sc->sc_islots[i].sqh;
417 if (i == 0) {
418 /* The last (1ms) QH terminates. */
419 sqh->qh.qh_link = EHCI_NULL;
420 sqh->next = NULL;
421 } else {
422 /* Otherwise the next QH has half the poll interval */
423 sqh->next =
424 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh;
425 sqh->qh.qh_link = htole32(sqh->next->physaddr |
426 EHCI_LINK_QH);
427 }
428 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
429 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
430 sqh->qh.qh_curqtd = EHCI_NULL;
431 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
432 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
433 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
434 sqh->sqtd = NULL;
435 }
436 /* Point the frame list at the last level (128ms). */
437 for (i = 0; i < sc->sc_flsize; i++) {
438 sc->sc_flist[i] = htole32(EHCI_LINK_QH |
439 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
440 i)].sqh->physaddr);
441 }
442
443 /* Allocate dummy QH that starts the async list. */
444 sqh = ehci_alloc_sqh(sc);
445 if (sqh == NULL) {
446 err = USBD_NOMEM;
447 goto bad1;
448 }
449 /* Fill the QH */
450 sqh->qh.qh_endp =
451 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
452 sqh->qh.qh_link =
453 htole32(sqh->physaddr | EHCI_LINK_QH);
454 sqh->qh.qh_curqtd = EHCI_NULL;
455 sqh->prev = sqh; /*It's a circular list.. */
456 sqh->next = sqh;
457 /* Fill the overlay qTD */
458 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
459 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
460 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
461 sqh->sqtd = NULL;
462 #ifdef EHCI_DEBUG
463 if (ehcidebug) {
464 ehci_dump_sqh(sqh);
465 }
466 #endif
467
468 /* Point to async list */
469 sc->sc_async_head = sqh;
470 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
471
472 callout_init(&sc->sc_tmo_pcd);
473 callout_init(&sc->sc_tmo_intrlist);
474
475 lockinit(&sc->sc_doorbell_lock, "ehcidb", 0, 0);
476
477 /* Enable interrupts */
478 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
479
480 /* Turn on controller */
481 EOWRITE4(sc, EHCI_USBCMD,
482 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
483 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
484 EHCI_CMD_ASE |
485 EHCI_CMD_PSE |
486 EHCI_CMD_RS);
487
488 /* Take over port ownership */
489 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
490
491 for (i = 0; i < 100; i++) {
492 usb_delay_ms(&sc->sc_bus, 1);
493 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
494 if (!hcr)
495 break;
496 }
497 if (hcr) {
498 device_printf(sc->sc_bus.bdev, "run timeout\n");
499 return (USBD_IOERROR);
500 }
501
502 return (USBD_NORMAL_COMPLETION);
503
504 #if 0
505 bad2:
506 ehci_free_sqh(sc, sc->sc_async_head);
507 #endif
508 bad1:
509 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
510 return (err);
511 }
512
513 int
514 ehci_intr(void *v)
515 {
516 ehci_softc_t *sc = v;
517
518 if (sc->sc_dying || (sc->sc_flags & EHCI_SCFLG_DONEINIT) == 0)
519 return (0);
520
521 /* If we get an interrupt while polling, then just ignore it. */
522 if (sc->sc_bus.use_polling) {
523 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
524
525 if (intrs)
526 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
527 #ifdef DIAGNOSTIC
528 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
529 #endif
530 return (0);
531 }
532
533 return (ehci_intr1(sc));
534 }
535
536 static int
537 ehci_intr1(ehci_softc_t *sc)
538 {
539 u_int32_t intrs, eintrs;
540
541 DPRINTFN(20,("ehci_intr1: enter\n"));
542
543 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
544 if (!intrs)
545 return (0);
546
547 eintrs = intrs & sc->sc_eintrs;
548 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
549 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
550 (u_int)eintrs));
551 if (!eintrs)
552 return (0);
553
554 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
555 sc->sc_bus.intr_context++;
556 sc->sc_bus.no_intrs++;
557 if (eintrs & EHCI_STS_IAA) {
558 DPRINTF(("ehci_intr1: door bell\n"));
559 wakeup(&sc->sc_async_head);
560 eintrs &= ~EHCI_STS_IAA;
561 }
562 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
563 DPRINTFN(5,("ehci_intr1: %s %s\n",
564 eintrs & EHCI_STS_INT ? "INT" : "",
565 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
566 usb_schedsoftintr(&sc->sc_bus);
567 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
568 }
569 if (eintrs & EHCI_STS_HSE) {
570 device_printf(sc->sc_bus.bdev,
571 "unrecoverable error, controller halted\n");
572 /* XXX what else */
573 }
574 if (eintrs & EHCI_STS_PCD) {
575 ehci_pcd(sc, sc->sc_intrxfer);
576 /*
577 * Disable PCD interrupt for now, because it will be
578 * on until the port has been reset.
579 */
580 ehci_pcd_able(sc, 0);
581 /* Do not allow RHSC interrupts > 1 per second */
582 callout_reset(&sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc);
583 eintrs &= ~EHCI_STS_PCD;
584 }
585
586 sc->sc_bus.intr_context--;
587
588 if (eintrs != 0) {
589 /* Block unprocessed interrupts. */
590 sc->sc_eintrs &= ~eintrs;
591 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
592 device_printf(sc->sc_bus.bdev,
593 "blocking intrs 0x%x\n", eintrs);
594 }
595
596 return (1);
597 }
598
599 void
600 ehci_pcd_able(ehci_softc_t *sc, int on)
601 {
602 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on));
603 if (on)
604 sc->sc_eintrs |= EHCI_STS_PCD;
605 else
606 sc->sc_eintrs &= ~EHCI_STS_PCD;
607 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
608 }
609
610 void
611 ehci_pcd_enable(void *v_sc)
612 {
613 ehci_softc_t *sc = v_sc;
614
615 ehci_pcd_able(sc, 1);
616 }
617
618 void
619 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
620 {
621 usbd_pipe_handle pipe;
622 u_char *p;
623 int i, m;
624
625 if (xfer == NULL) {
626 /* Just ignore the change. */
627 return;
628 }
629
630 pipe = xfer->pipe;
631
632 p = KERNADDR(&xfer->dmabuf, 0);
633 m = min(sc->sc_noport, xfer->length * 8 - 1);
634 memset(p, 0, xfer->length);
635 for (i = 1; i <= m; i++) {
636 /* Pick out CHANGE bits from the status reg. */
637 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
638 p[i/8] |= 1 << (i%8);
639 }
640 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
641 xfer->actlen = xfer->length;
642 xfer->status = USBD_NORMAL_COMPLETION;
643
644 usb_transfer_complete(xfer);
645 }
646
647 void
648 ehci_softintr(void *v)
649 {
650 ehci_softc_t *sc = v;
651 struct ehci_xfer *ex, *nextex;
652
653 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_get_nameunit(sc->sc_bus.bdev),
654 sc->sc_bus.intr_context));
655
656 sc->sc_bus.intr_context++;
657
658 /*
659 * The only explanation I can think of for why EHCI is as brain dead
660 * as UHCI interrupt-wise is that Intel was involved in both.
661 * An interrupt just tells us that something is done, we have no
662 * clue what, so we need to scan through all active transfers. :-(
663 */
664 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
665 nextex = LIST_NEXT(ex, inext);
666 ehci_check_intr(sc, ex);
667 }
668
669 /* Schedule a callout to catch any dropped transactions. */
670 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) &&
671 !LIST_EMPTY(&sc->sc_intrhead))
672 callout_reset(&sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout,
673 sc);
674
675 #ifdef USB_USE_SOFTINTR
676 if (sc->sc_softwake) {
677 sc->sc_softwake = 0;
678 wakeup(&sc->sc_softwake);
679 }
680 #endif /* USB_USE_SOFTINTR */
681
682 sc->sc_bus.intr_context--;
683 }
684
685 /* Check for an interrupt. */
686 void
687 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
688 {
689 ehci_soft_qtd_t *sqtd, *lsqtd;
690 u_int32_t status;
691
692 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
693
694 if (ex->sqtdstart == NULL) {
695 kprintf("ehci_check_intr: sqtdstart=NULL\n");
696 return;
697 }
698 lsqtd = ex->sqtdend;
699 #ifdef DIAGNOSTIC
700 if (lsqtd == NULL) {
701 kprintf("ehci_check_intr: lsqtd==0\n");
702 return;
703 }
704 #endif
705 /*
706 * If the last TD is still active we need to check whether there
707 * is a an error somewhere in the middle, or whether there was a
708 * short packet (SPD and not ACTIVE).
709 */
710 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
711 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
712 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
713 status = le32toh(sqtd->qtd.qtd_status);
714 /* If there's an active QTD the xfer isn't done. */
715 if (status & EHCI_QTD_ACTIVE)
716 break;
717 /* Any kind of error makes the xfer done. */
718 if (status & EHCI_QTD_HALTED)
719 goto done;
720 /* We want short packets, and it is short: it's done */
721 if (EHCI_QTD_GET_BYTES(status) != 0)
722 goto done;
723 }
724 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
725 ex, ex->sqtdstart));
726 return;
727 }
728 done:
729 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
730 callout_stop(&ex->xfer.timeout_handle);
731 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task);
732 ehci_idone(ex);
733 }
734
735 void
736 ehci_idone(struct ehci_xfer *ex)
737 {
738 usbd_xfer_handle xfer = &ex->xfer;
739 #ifdef USB_DEBUG
740 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
741 #endif
742 ehci_soft_qtd_t *sqtd, *lsqtd;
743 u_int32_t status = 0, nstatus = 0;
744 int actlen, cerr;
745
746 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
747 #ifdef DIAGNOSTIC
748 {
749 crit_enter();
750 if (ex->isdone) {
751 crit_exit();
752 #ifdef EHCI_DEBUG
753 kprintf("ehci_idone: ex is done!\n ");
754 ehci_dump_exfer(ex);
755 #else
756 kprintf("ehci_idone: ex=%p is done!\n", ex);
757 #endif
758 return;
759 }
760 ex->isdone = 1;
761 crit_exit();
762 }
763 #endif
764
765 if (xfer->status == USBD_CANCELLED ||
766 xfer->status == USBD_TIMEOUT) {
767 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
768 return;
769 }
770
771 #ifdef EHCI_DEBUG
772 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
773 if (ehcidebug > 10)
774 ehci_dump_sqtds(ex->sqtdstart);
775 #endif
776
777 /* The transfer is done, compute actual length and status. */
778 lsqtd = ex->sqtdend;
779 actlen = 0;
780 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) {
781 nstatus = le32toh(sqtd->qtd.qtd_status);
782 if (nstatus & EHCI_QTD_ACTIVE)
783 break;
784
785 status = nstatus;
786 /* halt is ok if descriptor is last, and complete */
787 if (sqtd->qtd.qtd_next == EHCI_NULL &&
788 EHCI_QTD_GET_BYTES(status) == 0)
789 status &= ~EHCI_QTD_HALTED;
790 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
791 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
792 }
793
794 cerr = EHCI_QTD_GET_CERR(status);
795 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, "
796 "status=0x%x\n", xfer->length, actlen, cerr, status));
797 xfer->actlen = actlen;
798 if ((status & EHCI_QTD_HALTED) != 0) {
799 #ifdef EHCI_DEBUG
800 char sbuf[128];
801
802 bitmask_snprintf((u_int32_t)status,
803 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR"
804 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
805
806 DPRINTFN(2,
807 ("ehci_idone: error, addr=%d, endpt=0x%02x, "
808 "status 0x%s\n",
809 xfer->pipe->device->address,
810 xfer->pipe->endpoint->edesc->bEndpointAddress,
811 sbuf));
812 if (ehcidebug > 2) {
813 ehci_dump_sqh(epipe->sqh);
814 ehci_dump_sqtds(ex->sqtdstart);
815 }
816 #endif
817 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0)
818 xfer->status = USBD_STALLED;
819 else
820 xfer->status = USBD_IOERROR; /* more info XXX */
821 } else {
822 xfer->status = USBD_NORMAL_COMPLETION;
823 }
824
825 usb_transfer_complete(xfer);
826 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
827 }
828
829 /*
830 * Wait here until controller claims to have an interrupt.
831 * Then call ehci_intr and return. Use timeout to avoid waiting
832 * too long.
833 */
834 void
835 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
836 {
837 int timo = xfer->timeout;
838 int usecs;
839 u_int32_t intrs;
840
841 xfer->status = USBD_IN_PROGRESS;
842 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
843 usb_delay_ms(&sc->sc_bus, 1);
844 if (sc->sc_dying)
845 break;
846 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
847 sc->sc_eintrs;
848 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
849 #ifdef EHCI_DEBUG
850 if (ehcidebug > 15)
851 ehci_dump_regs(sc);
852 #endif
853 if (intrs) {
854 ehci_intr1(sc);
855 if (xfer->status != USBD_IN_PROGRESS)
856 return;
857 }
858 }
859
860 /* Timeout */
861 DPRINTF(("ehci_waitintr: timeout\n"));
862 xfer->status = USBD_TIMEOUT;
863 usb_transfer_complete(xfer);
864 /* XXX should free TD */
865 }
866
867 void
868 ehci_poll(struct usbd_bus *bus)
869 {
870 ehci_softc_t *sc = (ehci_softc_t *)bus;
871 #ifdef EHCI_DEBUG
872 static int last;
873 int new;
874 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
875 if (new != last) {
876 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
877 last = new;
878 }
879 #endif
880
881 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
882 ehci_intr1(sc);
883 }
884
885 int
886 ehci_detach(struct ehci_softc *sc, int flags)
887 {
888 int rv = 0;
889
890 sc->sc_dying = 1;
891
892 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
893 EOWRITE4(sc, EHCI_USBCMD, 0);
894 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
895 callout_stop(&sc->sc_tmo_intrlist);
896 callout_stop(&sc->sc_tmo_pcd);
897
898 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
899
900 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
901 /* XXX free other data structures XXX */
902
903 return (rv);
904 }
905
906 /*
907 * Handle suspend/resume.
908 *
909 * We need to switch to polling mode here, because this routine is
910 * called from an interrupt context. This is all right since we
911 * are almost suspended anyway.
912 */
913 void
914 ehci_power(int why, void *v)
915 {
916 ehci_softc_t *sc = v;
917 u_int32_t cmd, hcr;
918 int i;
919
920 #ifdef EHCI_DEBUG
921 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
922 if (ehcidebug > 0)
923 ehci_dump_regs(sc);
924 #endif
925
926 crit_enter();
927
928 switch (why) {
929 case PWR_SUSPEND:
930 sc->sc_bus.use_polling++;
931
932 for (i = 1; i <= sc->sc_noport; i++) {
933 cmd = EOREAD4(sc, EHCI_PORTSC(i));
934 if ((cmd & EHCI_PS_PO) == 0 &&
935 (cmd & EHCI_PS_PE) == EHCI_PS_PE)
936 EOWRITE4(sc, EHCI_PORTSC(i),
937 cmd | EHCI_PS_SUSP);
938 }
939
940 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
941
942 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
943 EOWRITE4(sc, EHCI_USBCMD, cmd);
944
945 for (i = 0; i < 100; i++) {
946 hcr = EOREAD4(sc, EHCI_USBSTS) &
947 (EHCI_STS_ASS | EHCI_STS_PSS);
948 if (hcr == 0)
949 break;
950
951 usb_delay_ms(&sc->sc_bus, 1);
952 }
953 if (hcr != 0) {
954 device_printf(sc->sc_bus.bdev, "reset timeout\n");
955 }
956
957 cmd &= ~EHCI_CMD_RS;
958 EOWRITE4(sc, EHCI_USBCMD, cmd);
959
960 for (i = 0; i < 100; i++) {
961 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
962 if (hcr == EHCI_STS_HCH)
963 break;
964
965 usb_delay_ms(&sc->sc_bus, 1);
966 }
967 if (hcr != EHCI_STS_HCH) {
968 device_printf(sc->sc_bus.bdev, "config timeout\n");
969 }
970
971 sc->sc_bus.use_polling--;
972 break;
973
974 case PWR_RESUME:
975 sc->sc_bus.use_polling++;
976
977 /* restore things in case the bios sucks */
978 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
979 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
980 EOWRITE4(sc, EHCI_ASYNCLISTADDR,
981 sc->sc_async_head->physaddr | EHCI_LINK_QH);
982 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
983
984 hcr = 0;
985 for (i = 1; i <= sc->sc_noport; i++) {
986 cmd = EOREAD4(sc, EHCI_PORTSC(i));
987 if ((cmd & EHCI_PS_PO) == 0 &&
988 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
989 EOWRITE4(sc, EHCI_PORTSC(i),
990 cmd | EHCI_PS_FPR);
991 hcr = 1;
992 }
993 }
994
995 if (hcr) {
996 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
997
998 for (i = 1; i <= sc->sc_noport; i++) {
999 cmd = EOREAD4(sc, EHCI_PORTSC(i));
1000 if ((cmd & EHCI_PS_PO) == 0 &&
1001 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1002 EOWRITE4(sc, EHCI_PORTSC(i),
1003 cmd & ~EHCI_PS_FPR);
1004 }
1005 }
1006
1007 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1008
1009 for (i = 0; i < 100; i++) {
1010 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1011 if (hcr != EHCI_STS_HCH)
1012 break;
1013
1014 usb_delay_ms(&sc->sc_bus, 1);
1015 }
1016 if (hcr == EHCI_STS_HCH) {
1017 device_printf(sc->sc_bus.bdev, "config timeout\n");
1018 }
1019
1020 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1021
1022 sc->sc_bus.use_polling--;
1023 break;
1024 }
1025 crit_exit();
1026
1027 #ifdef EHCI_DEBUG
1028 DPRINTF(("ehci_power: sc=%p\n", sc));
1029 if (ehcidebug > 0)
1030 ehci_dump_regs(sc);
1031 #endif
1032 }
1033
1034 /*
1035 * Shut down the controller when the system is going down.
1036 */
1037 void
1038 ehci_shutdown(void *v)
1039 {
1040 ehci_softc_t *sc = v;
1041
1042 DPRINTF(("ehci_shutdown: stopping the HC\n"));
1043 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1044 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1045 }
1046
1047 usbd_status
1048 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1049 {
1050 usbd_status err;
1051
1052 err = usb_allocmem(bus, size, 0, dma);
1053 #ifdef EHCI_DEBUG
1054 if (err)
1055 kprintf("ehci_allocm: usb_allocmem()=%d\n", err);
1056 #endif
1057 return (err);
1058 }
1059
1060 void
1061 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1062 {
1063 usb_freemem(bus, dma);
1064 }
1065
1066 usbd_xfer_handle
1067 ehci_allocx(struct usbd_bus *bus)
1068 {
1069 struct ehci_softc *sc = (struct ehci_softc *)bus;
1070 usbd_xfer_handle xfer;
1071
1072 xfer = STAILQ_FIRST(&sc->sc_free_xfers);
1073 if (xfer != NULL) {
1074 STAILQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1075 #ifdef DIAGNOSTIC
1076 if (xfer->busy_free != XFER_FREE) {
1077 kprintf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer,
1078 xfer->busy_free);
1079 }
1080 #endif
1081 } else {
1082 xfer = kmalloc(sizeof(struct ehci_xfer), M_USB, M_INTWAIT);
1083 }
1084 if (xfer != NULL) {
1085 memset(xfer, 0, sizeof(struct ehci_xfer));
1086 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task,
1087 xfer);
1088 EXFER(xfer)->ehci_xfer_flags = 0;
1089 #ifdef DIAGNOSTIC
1090 EXFER(xfer)->isdone = 1;
1091 xfer->busy_free = XFER_BUSY;
1092 #endif
1093 }
1094 return (xfer);
1095 }
1096
1097 void
1098 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1099 {
1100 struct ehci_softc *sc = (struct ehci_softc *)bus;
1101
1102 #ifdef DIAGNOSTIC
1103 if (xfer->busy_free != XFER_BUSY) {
1104 kprintf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1105 xfer->busy_free);
1106 return;
1107 }
1108 xfer->busy_free = XFER_FREE;
1109 if (!EXFER(xfer)->isdone) {
1110 kprintf("ehci_freex: !isdone\n");
1111 return;
1112 }
1113 #endif
1114 STAILQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1115 }
1116
1117 static void
1118 ehci_device_clear_toggle(usbd_pipe_handle pipe)
1119 {
1120 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1121
1122 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1123 epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1124 #ifdef USB_DEBUG
1125 if (ehcidebug)
1126 usbd_dump_pipe(pipe);
1127 #endif
1128 KASSERT((epipe->sqh->qh.qh_qtd.qtd_status &
1129 htole32(EHCI_QTD_ACTIVE)) == 0,
1130 ("ehci_device_clear_toggle: queue active"));
1131 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK);
1132 }
1133
1134 static void
1135 ehci_noop(usbd_pipe_handle pipe)
1136 {
1137 }
1138
1139 #ifdef EHCI_DEBUG
1140 void
1141 ehci_dump_regs(ehci_softc_t *sc)
1142 {
1143 int i;
1144 kprintf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1145 EOREAD4(sc, EHCI_USBCMD),
1146 EOREAD4(sc, EHCI_USBSTS),
1147 EOREAD4(sc, EHCI_USBINTR));
1148 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1149 EOREAD4(sc, EHCI_FRINDEX),
1150 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1151 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1152 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1153 for (i = 1; i <= sc->sc_noport; i++)
1154 kprintf("port %d status=0x%08x\n", i,
1155 EOREAD4(sc, EHCI_PORTSC(i)));
1156 }
1157
1158 /*
1159 * Unused function - this is meant to be called from a kernel
1160 * debugger.
1161 */
1162 void
1163 ehci_dump(void)
1164 {
1165 ehci_dump_regs(theehci);
1166 }
1167
1168 void
1169 ehci_dump_link(ehci_link_t link, int type)
1170 {
1171 link = le32toh(link);
1172 kprintf("0x%08x", link);
1173 if (link & EHCI_LINK_TERMINATE)
1174 kprintf("<T>");
1175 else {
1176 kprintf("<");
1177 if (type) {
1178 switch (EHCI_LINK_TYPE(link)) {
1179 case EHCI_LINK_ITD: kprintf("ITD"); break;
1180 case EHCI_LINK_QH: kprintf("QH"); break;
1181 case EHCI_LINK_SITD: kprintf("SITD"); break;
1182 case EHCI_LINK_FSTN: kprintf("FSTN"); break;
1183 }
1184 }
1185 kprintf(">");
1186 }
1187 }
1188
1189 void
1190 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1191 {
1192 int i;
1193 u_int32_t stop;
1194
1195 stop = 0;
1196 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1197 ehci_dump_sqtd(sqtd);
1198 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1199 }
1200 if (sqtd)
1201 kprintf("dump aborted, too many TDs\n");
1202 }
1203
1204 void
1205 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1206 {
1207 kprintf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1208 ehci_dump_qtd(&sqtd->qtd);
1209 }
1210
1211 void
1212 ehci_dump_qtd(ehci_qtd_t *qtd)
1213 {
1214 u_int32_t s;
1215 char sbuf[128];
1216
1217 kprintf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1218 kprintf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1219 kprintf("\n");
1220 s = le32toh(qtd->qtd_status);
1221 bitmask_snprintf(EHCI_QTD_GET_STATUS(s),
1222 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1223 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
1224 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1225 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1226 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1227 kprintf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1228 EHCI_QTD_GET_PID(s), sbuf);
1229 for (s = 0; s < 5; s++)
1230 kprintf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1231 }
1232
1233 void
1234 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1235 {
1236 ehci_qh_t *qh = &sqh->qh;
1237 u_int32_t endp, endphub;
1238
1239 kprintf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1240 kprintf(" link="); ehci_dump_link(qh->qh_link, 1); kprintf("\n");
1241 endp = le32toh(qh->qh_endp);
1242 kprintf(" endp=0x%08x\n", endp);
1243 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1244 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1245 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1246 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1247 kprintf(" mpl=0x%x ctl=%d nrl=%d\n",
1248 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1249 EHCI_QH_GET_NRL(endp));
1250 endphub = le32toh(qh->qh_endphub);
1251 kprintf(" endphub=0x%08x\n", endphub);
1252 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1253 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1254 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1255 EHCI_QH_GET_MULT(endphub));
1256 kprintf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); kprintf("\n");
1257 kprintf("Overlay qTD:\n");
1258 ehci_dump_qtd(&qh->qh_qtd);
1259 }
1260
1261 #ifdef DIAGNOSTIC
1262 static void
1263 ehci_dump_exfer(struct ehci_xfer *ex)
1264 {
1265 kprintf("ehci_dump_exfer: ex=%p\n", ex);
1266 }
1267 #endif
1268 #endif
1269
1270 usbd_status
1271 ehci_open(usbd_pipe_handle pipe)
1272 {
1273 usbd_device_handle dev = pipe->device;
1274 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1275 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1276 u_int8_t addr = dev->address;
1277 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1278 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1279 ehci_soft_qh_t *sqh;
1280 usbd_status err;
1281 int ival, speed, naks;
1282 int hshubaddr, hshubport;
1283
1284 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1285 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1286
1287 if (dev->myhsport) {
1288 hshubaddr = dev->myhsport->parent->address;
1289 hshubport = dev->myhsport->portno;
1290 } else {
1291 hshubaddr = 0;
1292 hshubport = 0;
1293 }
1294
1295 if (sc->sc_dying)
1296 return (USBD_IOERROR);
1297
1298 if (addr == sc->sc_addr) {
1299 switch (ed->bEndpointAddress) {
1300 case USB_CONTROL_ENDPOINT:
1301 pipe->methods = &ehci_root_ctrl_methods;
1302 break;
1303 case UE_DIR_IN | EHCI_INTR_ENDPT:
1304 pipe->methods = &ehci_root_intr_methods;
1305 break;
1306 default:
1307 return (USBD_INVAL);
1308 }
1309 return (USBD_NORMAL_COMPLETION);
1310 }
1311
1312 /* XXX All this stuff is only valid for async. */
1313 switch (dev->speed) {
1314 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1315 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1316 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1317 default: panic("ehci_open: bad device speed %d", dev->speed);
1318 }
1319 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1320 device_printf(sc->sc_bus.bdev,
1321 "*** WARNING: opening low/full speed device, this "
1322 "does not work yet.\n");
1323 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1324 hshubaddr, hshubport));
1325 return USBD_INVAL;
1326 }
1327
1328 naks = 8; /* XXX */
1329 sqh = ehci_alloc_sqh(sc);
1330 if (sqh == NULL)
1331 goto bad0;
1332 /* qh_link filled when the QH is added */
1333 sqh->qh.qh_endp = htole32(
1334 EHCI_QH_SET_ADDR(addr) |
1335 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1336 EHCI_QH_SET_EPS(speed) |
1337 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) |
1338 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1339 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1340 EHCI_QH_CTL : 0) |
1341 EHCI_QH_SET_NRL(naks)
1342 );
1343 sqh->qh.qh_endphub = htole32(
1344 EHCI_QH_SET_MULT(1) |
1345 EHCI_QH_SET_HUBA(hshubaddr) |
1346 EHCI_QH_SET_PORT(hshubport) |
1347 EHCI_QH_SET_CMASK(0x1c) |
1348 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0)
1349 );
1350 sqh->qh.qh_curqtd = EHCI_NULL;
1351 /* Fill the overlay qTD */
1352 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1353 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1354 sqh->qh.qh_qtd.qtd_status =
1355 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle));
1356
1357 epipe->sqh = sqh;
1358
1359 switch (xfertype) {
1360 case UE_CONTROL:
1361 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1362 0, &epipe->u.ctl.reqdma);
1363 #ifdef EHCI_DEBUG
1364 if (err)
1365 kprintf("ehci_open: usb_allocmem()=%d\n", err);
1366 #endif
1367 if (err)
1368 goto bad1;
1369 pipe->methods = &ehci_device_ctrl_methods;
1370 crit_enter();
1371 ehci_add_qh(sqh, sc->sc_async_head);
1372 crit_exit();
1373 break;
1374 case UE_BULK:
1375 pipe->methods = &ehci_device_bulk_methods;
1376 crit_enter();
1377 ehci_add_qh(sqh, sc->sc_async_head);
1378 crit_exit();
1379 break;
1380 case UE_INTERRUPT:
1381 pipe->methods = &ehci_device_intr_methods;
1382 ival = pipe->interval;
1383 if (ival == USBD_DEFAULT_INTERVAL)
1384 ival = ed->bInterval;
1385 return (ehci_device_setintr(sc, sqh, ival));
1386 case UE_ISOCHRONOUS:
1387 pipe->methods = &ehci_device_isoc_methods;
1388 return (USBD_INVAL);
1389 default:
1390 return (USBD_INVAL);
1391 }
1392 return (USBD_NORMAL_COMPLETION);
1393
1394 bad1:
1395 ehci_free_sqh(sc, sqh);
1396 bad0:
1397 return (USBD_NOMEM);
1398 }
1399
1400 /*
1401 * Add an ED to the schedule. Called while in a critical section.
1402 * If in the async schedule, it will always have a next.
1403 * If in the intr schedule it may not.
1404 */
1405 void
1406 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1407 {
1408 sqh->next = head->next;
1409 sqh->prev = head;
1410 sqh->qh.qh_link = head->qh.qh_link;
1411 head->next = sqh;
1412 if (sqh->next)
1413 sqh->next->prev = sqh;
1414 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1415
1416 #ifdef EHCI_DEBUG
1417 if (ehcidebug > 5) {
1418 kprintf("ehci_add_qh:\n");
1419 ehci_dump_sqh(sqh);
1420 }
1421 #endif
1422 }
1423
1424 /*
1425 * Remove an ED from the schedule. Called while in a critical section.
1426 * Will always have a 'next' if it's in the async list as it's circular.
1427 */
1428 void
1429 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1430 {
1431 /* XXX */
1432 sqh->prev->qh.qh_link = sqh->qh.qh_link;
1433 sqh->prev->next = sqh->next;
1434 if (sqh->next)
1435 sqh->next->prev = sqh->prev;
1436 ehci_sync_hc(sc);
1437 }
1438
1439 void
1440 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1441 {
1442 int i;
1443 u_int32_t status;
1444
1445 /* Save toggle bit and ping status. */
1446 status = sqh->qh.qh_qtd.qtd_status &
1447 htole32(EHCI_QTD_TOGGLE_MASK |
1448 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1449 /* Set HALTED to make hw leave it alone. */
1450 sqh->qh.qh_qtd.qtd_status =
1451 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1452 sqh->qh.qh_curqtd = 0;
1453 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1454 sqh->qh.qh_qtd.qtd_altnext = 0;
1455 for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1456 sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1457 sqh->sqtd = sqtd;
1458 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1459 sqh->qh.qh_qtd.qtd_status = status;
1460 }
1461
1462 /*
1463 * Ensure that the HC has released all references to the QH. We do this
1464 * by asking for a Async Advance Doorbell interrupt and then we wait for
1465 * the interrupt.
1466 * To make this easier we first obtain exclusive use of the doorbell.
1467 */
1468 void
1469 ehci_sync_hc(ehci_softc_t *sc)
1470 {
1471 int error;
1472
1473 if (sc->sc_dying) {
1474 DPRINTFN(2,("ehci_sync_hc: dying\n"));
1475 return;
1476 }
1477 DPRINTFN(2,("ehci_sync_hc: enter\n"));
1478 /* get doorbell */
1479 lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE);
1480 crit_enter();
1481 /* ask for doorbell */
1482 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1483 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1484 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1485 error = tsleep(&sc->sc_async_head, 0, "ehcidi", hz); /* bell wait */
1486 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1487 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1488 crit_exit();
1489 /* release doorbell */
1490 lockmgr(&sc->sc_doorbell_lock, LK_RELEASE);
1491 #ifdef DIAGNOSTIC
1492 if (error)
1493 kprintf("ehci_sync_hc: tsleep() = %d\n", error);
1494 #endif
1495 DPRINTFN(2,("ehci_sync_hc: exit\n"));
1496 }
1497
1498 /***********/
1499
1500 /*
1501 * Data structures and routines to emulate the root hub.
1502 */
1503 static usb_device_descriptor_t ehci_devd = {
1504 USB_DEVICE_DESCRIPTOR_SIZE,
1505 UDESC_DEVICE, /* type */
1506 {0x00, 0x02}, /* USB version */
1507 UDCLASS_HUB, /* class */
1508 UDSUBCLASS_HUB, /* subclass */
1509 UDPROTO_HSHUBSTT, /* protocol */
1510 64, /* max packet */
1511 {0},{0},{0x00,0x01}, /* device id */
1512 1,2,0, /* string indicies */
1513 1 /* # of configurations */
1514 };
1515
1516 static usb_device_qualifier_t ehci_odevd = {
1517 USB_DEVICE_DESCRIPTOR_SIZE,
1518 UDESC_DEVICE_QUALIFIER, /* type */
1519 {0x00, 0x02}, /* USB version */
1520 UDCLASS_HUB, /* class */
1521 UDSUBCLASS_HUB, /* subclass */
1522 UDPROTO_FSHUB, /* protocol */
1523 64, /* max packet */
1524 1, /* # of configurations */
1525 0
1526 };
1527
1528 static usb_config_descriptor_t ehci_confd = {
1529 USB_CONFIG_DESCRIPTOR_SIZE,
1530 UDESC_CONFIG,
1531 {USB_CONFIG_DESCRIPTOR_SIZE +
1532 USB_INTERFACE_DESCRIPTOR_SIZE +
1533 USB_ENDPOINT_DESCRIPTOR_SIZE},
1534 1,
1535 1,
1536 0,
1537 UC_SELF_POWERED,
1538 0 /* max power */
1539 };
1540
1541 static usb_interface_descriptor_t ehci_ifcd = {
1542 USB_INTERFACE_DESCRIPTOR_SIZE,
1543 UDESC_INTERFACE,
1544 0,
1545 0,
1546 1,
1547 UICLASS_HUB,
1548 UISUBCLASS_HUB,
1549 UIPROTO_HSHUBSTT,
1550 0
1551 };
1552
1553 static usb_endpoint_descriptor_t ehci_endpd = {
1554 USB_ENDPOINT_DESCRIPTOR_SIZE,
1555 UDESC_ENDPOINT,
1556 UE_DIR_IN | EHCI_INTR_ENDPT,
1557 UE_INTERRUPT,
1558 {8, 0}, /* max packet */
1559 255
1560 };
1561
1562 static usb_hub_descriptor_t ehci_hubd = {
1563 USB_HUB_DESCRIPTOR_SIZE,
1564 UDESC_HUB,
1565 0,
1566 {0,0},
1567 0,
1568 0,
1569 {0},
1570 };
1571
1572 static int
1573 ehci_str(usb_string_descriptor_t *p, int l, char *s)
1574 {
1575 int i;
1576
1577 if (l == 0)
1578 return (0);
1579 p->bLength = 2 * strlen(s) + 2;
1580 if (l == 1)
1581 return (1);
1582 p->bDescriptorType = UDESC_STRING;
1583 l -= 2;
1584 for (i = 0; s[i] && l > 1; i++, l -= 2)
1585 USETW2(p->bString[i], 0, s[i]);
1586 return (2*i+2);
1587 }
1588
1589 /*
1590 * Simulate a hardware hub by handling all the necessary requests.
1591 */
1592 static usbd_status
1593 ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1594 {
1595 usbd_status err;
1596
1597 /* Insert last in queue. */
1598 err = usb_insert_transfer(xfer);
1599 if (err)
1600 return (err);
1601
1602 /* Pipe isn't running, start first */
1603 return (ehci_root_ctrl_start(STAILQ_FIRST(&xfer->pipe->queue)));
1604 }
1605
1606 static usbd_status
1607 ehci_root_ctrl_start(usbd_xfer_handle xfer)
1608 {
1609 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
1610 usb_device_request_t *req;
1611 void *buf = NULL;
1612 int port, i;
1613 int len, value, index, l, totlen = 0;
1614 usb_port_status_t ps;
1615 usb_hub_descriptor_t hubd;
1616 usbd_status err;
1617 u_int32_t v;
1618
1619 if (sc->sc_dying)
1620 return (USBD_IOERROR);
1621
1622 #ifdef DIAGNOSTIC
1623 if (!(xfer->rqflags & URQ_REQUEST))
1624 /* XXX panic */
1625 return (USBD_INVAL);
1626 #endif
1627 req = &xfer->request;
1628
1629 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1630 req->bmRequestType, req->bRequest));
1631
1632 len = UGETW(req->wLength);
1633 value = UGETW(req->wValue);
1634 index = UGETW(req->wIndex);
1635
1636 if (len != 0)
1637 buf = KERNADDR(&xfer->dmabuf, 0);
1638
1639 #define C(x,y) ((x) | ((y) << 8))
1640 switch(C(req->bRequest, req->bmRequestType)) {
1641 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1642 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1643 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1644 /*
1645 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1646 * for the integrated root hub.
1647 */
1648 break;
1649 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1650 if (len > 0) {
1651 *(u_int8_t *)buf = sc->sc_conf;
1652 totlen = 1;
1653 }
1654 break;
1655 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1656 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
1657 switch(value >> 8) {
1658 case UDESC_DEVICE:
1659 if ((value & 0xff) != 0) {
1660 err = USBD_IOERROR;
1661 goto ret;
1662 }
1663 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1664 USETW(ehci_devd.idVendor, sc->sc_id_vendor);
1665 memcpy(buf, &ehci_devd, l);
1666 break;
1667 /*
1668 * We can't really operate at another speed, but the spec says
1669 * we need this descriptor.
1670 */
1671 case UDESC_DEVICE_QUALIFIER:
1672 if ((value & 0xff) != 0) {
1673 err = USBD_IOERROR;
1674 goto ret;
1675 }
1676 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1677 memcpy(buf, &ehci_odevd, l);
1678 break;
1679 /*
1680 * We can't really operate at another speed, but the spec says
1681 * we need this descriptor.
1682 */
1683 case UDESC_OTHER_SPEED_CONFIGURATION:
1684 case UDESC_CONFIG:
1685 if ((value & 0xff) != 0) {
1686 err = USBD_IOERROR;
1687 goto ret;
1688 }
1689 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1690 memcpy(buf, &ehci_confd, l);
1691 ((usb_config_descriptor_t *)buf)->bDescriptorType =
1692 value >> 8;
1693 buf = (char *)buf + l;
1694 len -= l;
1695 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1696 totlen += l;
1697 memcpy(buf, &ehci_ifcd, l);
1698 buf = (char *)buf + l;
1699 len -= l;
1700 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1701 totlen += l;
1702 memcpy(buf, &ehci_endpd, l);
1703 break;
1704 case UDESC_STRING:
1705 if (len == 0)
1706 break;
1707 *(u_int8_t *)buf = 0;
1708 totlen = 1;
1709 switch (value & 0xff) {
1710 case 0: /* Language table */
1711 totlen = ehci_str(buf, len, "\001");
1712 break;
1713 case 1: /* Vendor */
1714 totlen = ehci_str(buf, len, sc->sc_vendor);
1715 break;
1716 case 2: /* Product */
1717 totlen = ehci_str(buf, len, "EHCI root hub");
1718 break;
1719 }
1720 break;
1721 default:
1722 err = USBD_IOERROR;
1723 goto ret;
1724 }
1725 break;
1726 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1727 if (len > 0) {
1728 *(u_int8_t *)buf = 0;
1729 totlen = 1;
1730 }
1731 break;
1732 case C(UR_GET_STATUS, UT_READ_DEVICE):
1733 if (len > 1) {
1734 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1735 totlen = 2;
1736 }
1737 break;
1738 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1739 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1740 if (len > 1) {
1741 USETW(((usb_status_t *)buf)->wStatus, 0);
1742 totlen = 2;
1743 }
1744 break;
1745 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1746 if (value >= USB_MAX_DEVICES) {
1747 err = USBD_IOERROR;
1748 goto ret;
1749 }
1750 sc->sc_addr = value;
1751 break;
1752 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1753 if (value != 0 && value != 1) {
1754 err = USBD_IOERROR;
1755 goto ret;
1756 }
1757 sc->sc_conf = value;
1758 break;
1759 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1760 break;
1761 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1762 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1763 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1764 err = USBD_IOERROR;
1765 goto ret;
1766 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1767 break;
1768 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1769 break;
1770 /* Hub requests */
1771 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1772 break;
1773 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1774 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
1775 "port=%d feature=%d\n",
1776 index, value));
1777 if (index < 1 || index > sc->sc_noport) {
1778 err = USBD_IOERROR;
1779 goto ret;
1780 }
1781 port = EHCI_PORTSC(index);
1782 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1783 switch(value) {
1784 case UHF_PORT_ENABLE:
1785 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
1786 break;
1787 case UHF_PORT_SUSPEND:
1788 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
1789 break;
1790 case UHF_PORT_POWER:
1791 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1792 break;
1793 case UHF_PORT_TEST:
1794 DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
1795 "%d\n", index));
1796 break;
1797 case UHF_PORT_INDICATOR:
1798 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
1799 "%d\n", index));
1800 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
1801 break;
1802 case UHF_C_PORT_CONNECTION:
1803 EOWRITE4(sc, port, v | EHCI_PS_CSC);
1804 break;
1805 case UHF_C_PORT_ENABLE:
1806 EOWRITE4(sc, port, v | EHCI_PS_PEC);
1807 break;
1808 case UHF_C_PORT_SUSPEND:
1809 /* how? */
1810 break;
1811 case UHF_C_PORT_OVER_CURRENT:
1812 EOWRITE4(sc, port, v | EHCI_PS_OCC);
1813 break;
1814 case UHF_C_PORT_RESET:
1815 sc->sc_isreset = 0;
1816 break;
1817 default:
1818 err = USBD_IOERROR;
1819 goto ret;
1820 }
1821 #if 0
1822 switch(value) {
1823 case UHF_C_PORT_CONNECTION:
1824 case UHF_C_PORT_ENABLE:
1825 case UHF_C_PORT_SUSPEND:
1826 case UHF_C_PORT_OVER_CURRENT:
1827 case UHF_C_PORT_RESET:
1828 /* Enable RHSC interrupt if condition is cleared. */
1829 if ((OREAD4(sc, port) >> 16) == 0)
1830 ehci_pcd_able(sc, 1);
1831 break;
1832 default:
1833 break;
1834 }
1835 #endif
1836 break;
1837 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1838 if ((value & 0xff) != 0) {
1839 err = USBD_IOERROR;
1840 goto ret;
1841 }
1842 hubd = ehci_hubd;
1843 hubd.bNbrPorts = sc->sc_noport;
1844 v = EOREAD4(sc, EHCI_HCSPARAMS);
1845 USETW(hubd.wHubCharacteristics,
1846 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1847 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1848 ? UHD_PORT_IND : 0);
1849 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1850 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1851 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
1852 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1853 l = min(len, hubd.bDescLength);
1854 totlen = l;
1855 memcpy(buf, &hubd, l);
1856 break;
1857 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1858 if (len != 4) {
1859 err = USBD_IOERROR;
1860 goto ret;
1861 }
1862 memset(buf, 0, len); /* ? XXX */
1863 totlen = len;
1864 break;
1865 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1866 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
1867 index));
1868 if (index < 1 || index > sc->sc_noport) {
1869 err = USBD_IOERROR;
1870 goto ret;
1871 }
1872 if (len != 4) {
1873 err = USBD_IOERROR;
1874 goto ret;
1875 }
1876 v = EOREAD4(sc, EHCI_PORTSC(index));
1877 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
1878 i = UPS_HIGH_SPEED;
1879 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
1880 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
1881 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
1882 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
1883 if (v & EHCI_PS_PR) i |= UPS_RESET;
1884 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1885 USETW(ps.wPortStatus, i);
1886 i = 0;
1887 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
1888 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
1889 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1890 if (sc->sc_isreset) i |= UPS_C_PORT_RESET;
1891 USETW(ps.wPortChange, i);
1892 l = min(len, sizeof ps);
1893 memcpy(buf, &ps, l);
1894 totlen = l;
1895 break;
1896 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1897 err = USBD_IOERROR;
1898 goto ret;
1899 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1900 break;
1901 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1902 if (index < 1 || index > sc->sc_noport) {
1903 err = USBD_IOERROR;
1904 goto ret;
1905 }
1906 port = EHCI_PORTSC(index);
1907 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1908 switch(value) {
1909 case UHF_PORT_ENABLE:
1910 EOWRITE4(sc, port, v | EHCI_PS_PE);
1911 break;
1912 case UHF_PORT_SUSPEND:
1913 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
1914 break;
1915 case UHF_PORT_RESET:
1916 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
1917 index));
1918 if (EHCI_PS_IS_LOWSPEED(v)) {
1919 /* Low speed device, give up ownership. */
1920 ehci_disown(sc, index, 1);
1921 break;
1922 }
1923 /* Start reset sequence. */
1924 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1925 EOWRITE4(sc, port, v | EHCI_PS_PR);
1926 /* Wait for reset to complete. */
1927 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1928 if (sc->sc_dying) {
1929 err = USBD_IOERROR;
1930 goto ret;
1931 }
1932 /* Terminate reset sequence. */
1933 EOWRITE4(sc, port, v);
1934 /* Wait for HC to complete reset. */
1935 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
1936 if (sc->sc_dying) {
1937 err = USBD_IOERROR;
1938 goto ret;
1939 }
1940 v = EOREAD4(sc, port);
1941 DPRINTF(("ehci after reset, status=0x%08x\n", v));
1942 if (v & EHCI_PS_PR) {
1943 device_printf(sc->sc_bus.bdev,
1944 "port reset timeout\n");
1945 return (USBD_TIMEOUT);
1946 }
1947 if (!(v & EHCI_PS_PE)) {
1948 /* Not a high speed device, give up ownership.*/
1949 ehci_disown(sc, index, 0);
1950 break;
1951 }
1952 sc->sc_isreset = 1;
1953 DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1954 index, v));
1955 break;
1956 case UHF_PORT_POWER:
1957 DPRINTFN(2,("ehci_root_ctrl_start: set port power "
1958 "%d\n", index));
1959 EOWRITE4(sc, port, v | EHCI_PS_PP);
1960 break;
1961 case UHF_PORT_TEST:
1962 DPRINTFN(2,("ehci_root_ctrl_start: set port test "
1963 "%d\n", index));
1964 break;
1965 case UHF_PORT_INDICATOR:
1966 DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
1967 "%d\n", index));
1968 EOWRITE4(sc, port, v | EHCI_PS_PIC);
1969 break;
1970 default:
1971 err = USBD_IOERROR;
1972 goto ret;
1973 }
1974 break;
1975 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
1976 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
1977 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
1978 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
1979 break;
1980 default:
1981 err = USBD_IOERROR;
1982 goto ret;
1983 }
1984 xfer->actlen = totlen;
1985 err = USBD_NORMAL_COMPLETION;
1986 ret:
1987 xfer->status = err;
1988 crit_enter();
1989 usb_transfer_complete(xfer);
1990 crit_exit();
1991 return (USBD_IN_PROGRESS);
1992 }
1993
1994 void
1995 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1996 {
1997 int port;
1998 u_int32_t v;
1999
2000 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2001 #ifdef DIAGNOSTIC
2002 if (sc->sc_npcomp != 0) {
2003 int i = (index-1) / sc->sc_npcomp;
2004 if (i >= sc->sc_ncomp)
2005 device_printf(sc->sc_bus.bdev, "strange port\n");
2006 else
2007 device_printf(sc->sc_bus.bdev,
2008 "handing over %s speed device on port %d to %s\n",
2009 lowspeed ? "low" : "full",
2010 index, device_get_nameunit(sc->sc_comps[i]->bdev));
2011 } else {
2012 device_printf(sc->sc_bus.bdev, "npcomp == 0\n");
2013 }
2014 #endif
2015 port = EHCI_PORTSC(index);
2016 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2017 EOWRITE4(sc, port, v | EHCI_PS_PO);
2018 }
2019
2020 /* Abort a root control request. */
2021 static void
2022 ehci_root_ctrl_abort(usbd_xfer_handle xfer)
2023 {
2024 /* Nothing to do, all transfers are synchronous. */
2025 }
2026
2027 /* Close the root pipe. */
2028 static void
2029 ehci_root_ctrl_close(usbd_pipe_handle pipe)
2030 {
2031 DPRINTF(("ehci_root_ctrl_close\n"));
2032 /* Nothing to do. */
2033 }
2034
2035 void
2036 ehci_root_intr_done(usbd_xfer_handle xfer)
2037 {
2038 }
2039
2040 static usbd_status
2041 ehci_root_intr_transfer(usbd_xfer_handle xfer)
2042 {
2043 usbd_status err;
2044
2045 /* Insert last in queue. */
2046 err = usb_insert_transfer(xfer);
2047 if (err)
2048 return (err);
2049
2050 /* Pipe isn't running, start first */
2051 return (ehci_root_intr_start(STAILQ_FIRST(&xfer->pipe->queue)));
2052 }
2053
2054 static usbd_status
2055 ehci_root_intr_start(usbd_xfer_handle xfer)
2056 {
2057 usbd_pipe_handle pipe = xfer->pipe;
2058 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2059
2060 if (sc->sc_dying)
2061 return (USBD_IOERROR);
2062
2063 sc->sc_intrxfer = xfer;
2064
2065 return (USBD_IN_PROGRESS);
2066 }
2067
2068 /* Abort a root interrupt request. */
2069 static void
2070 ehci_root_intr_abort(usbd_xfer_handle xfer)
2071 {
2072 if (xfer->pipe->intrxfer == xfer) {
2073 DPRINTF(("ehci_root_intr_abort: remove\n"));
2074 xfer->pipe->intrxfer = NULL;
2075 }
2076 xfer->status = USBD_CANCELLED;
2077 crit_enter();
2078 usb_transfer_complete(xfer);
2079 crit_exit();
2080 }
2081
2082 /* Close the root pipe. */
2083 static void
2084 ehci_root_intr_close(usbd_pipe_handle pipe)
2085 {
2086 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2087
2088 DPRINTF(("ehci_root_intr_close\n"));
2089
2090 sc->sc_intrxfer = NULL;
2091 }
2092
2093 void
2094 ehci_root_ctrl_done(usbd_xfer_handle xfer)
2095 {
2096 }
2097
2098 /************************/
2099
2100 ehci_soft_qh_t *
2101 ehci_alloc_sqh(ehci_softc_t *sc)
2102 {
2103 ehci_soft_qh_t *sqh;
2104 usbd_status err;
2105 int i, offs;
2106 usb_dma_t dma;
2107
2108 if (sc->sc_freeqhs == NULL) {
2109 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2110 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2111 EHCI_PAGE_SIZE, &dma);
2112 #ifdef EHCI_DEBUG
2113 if (err)
2114 kprintf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2115 #endif
2116 if (err)
2117 return (NULL);
2118 for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2119 offs = i * EHCI_SQH_SIZE;
2120 sqh = KERNADDR(&dma, offs);
2121 sqh->physaddr = DMAADDR(&dma, offs);
2122 sqh->next = sc->sc_freeqhs;
2123 sc->sc_freeqhs = sqh;
2124 }
2125 }
2126 sqh = sc->sc_freeqhs;
2127 sc->sc_freeqhs = sqh->next;
2128 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2129 sqh->next = NULL;
2130 sqh->prev = NULL;
2131 return (sqh);
2132 }
2133
2134 void
2135 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2136 {
2137 sqh->next = sc->sc_freeqhs;
2138 sc->sc_freeqhs = sqh;
2139 }
2140
2141 ehci_soft_qtd_t *
2142 ehci_alloc_sqtd(ehci_softc_t *sc)
2143 {
2144 ehci_soft_qtd_t *sqtd;
2145 usbd_status err;
2146 int i, offs;
2147 usb_dma_t dma;
2148
2149 if (sc->sc_freeqtds == NULL) {
2150 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2151 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2152 EHCI_PAGE_SIZE, &dma);
2153 #ifdef EHCI_DEBUG
2154 if (err)
2155 kprintf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2156 #endif
2157 if (err)
2158 return (NULL);
2159 crit_enter();
2160 for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2161 offs = i * EHCI_SQTD_SIZE;
2162 sqtd = KERNADDR(&dma, offs);
2163 sqtd->physaddr = DMAADDR(&dma, offs);
2164 sqtd->nextqtd = sc->sc_freeqtds;
2165 sc->sc_freeqtds = sqtd;
2166 }
2167 crit_exit();
2168 }
2169
2170 crit_enter();
2171 sqtd = sc->sc_freeqtds;
2172 sc->sc_freeqtds = sqtd->nextqtd;
2173 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2174 sqtd->nextqtd = NULL;
2175 sqtd->xfer = NULL;
2176 crit_exit();
2177
2178 return (sqtd);
2179 }
2180
2181 void
2182 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2183 {
2184 crit_enter();
2185 sqtd->nextqtd = sc->sc_freeqtds;
2186 sc->sc_freeqtds = sqtd;
2187 crit_exit();
2188 }
2189
2190 usbd_status
2191 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2192 int alen, int rd, usbd_xfer_handle xfer,
2193 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2194 {
2195 ehci_soft_qtd_t *next, *cur;
2196 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2197 u_int32_t qtdstatus;
2198 int len, curlen, mps, offset;
2199 int i, iscontrol;
2200 usb_dma_t *dma = &xfer->dmabuf;
2201
2202 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2203
2204 offset = 0;
2205 len = alen;
2206 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) ==
2207 UE_CONTROL;
2208 dataphys = DMAADDR(dma, 0);
2209 dataphyslastpage = EHCI_PAGE(DMAADDR(dma, len - 1));
2210 qtdstatus = EHCI_QTD_ACTIVE |
2211 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2212 EHCI_QTD_SET_CERR(3)
2213 /* IOC set below */
2214 /* BYTES set below */
2215 ;
2216 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2217 /*
2218 * The control transfer data stage always starts with a toggle of 1.
2219 * For other transfers we let the hardware track the toggle state.
2220 */
2221 if (iscontrol)
2222 qtdstatus |= EHCI_QTD_SET_TOGGLE(1);
2223
2224 cur = ehci_alloc_sqtd(sc);
2225 *sp = cur;
2226 if (cur == NULL)
2227 goto nomem;
2228 for (;;) {
2229 dataphyspage = EHCI_PAGE(dataphys);
2230 /* XXX This is pretty broken: Because we do not allocate
2231 * a contiguous buffer (contiguous in physical pages) we
2232 * can only transfer one page in one go.
2233 * So check whether the start and end of the buffer are on
2234 * the same page.
2235 */
2236 if (dataphyspage == dataphyslastpage) {
2237 curlen = len;
2238 }
2239 else {
2240 /* See comment above (XXX) */
2241 curlen = EHCI_PAGE_SIZE -
2242 EHCI_PAGE_MASK(dataphys);
2243 /* the length must be a multiple of the max size */
2244 curlen -= curlen % mps;
2245 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2246 "curlen=%d\n", curlen));
2247 KASSERT(curlen != 0, ("ehci_alloc_std: curlen == 0"));
2248 }
2249 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
2250 "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2251 dataphys, dataphyslastpage,
2252 len, curlen));
2253 len -= curlen;
2254
2255 if (len != 0) {
2256 next = ehci_alloc_sqtd(sc);
2257 if (next == NULL)
2258 goto nomem;
2259 nextphys = htole32(next->physaddr);
2260 } else {
2261 next = NULL;
2262 nextphys = EHCI_NULL;
2263 }
2264
2265 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) {
2266 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2267 if (i != 0) /* use offset only in first buffer */
2268 a = EHCI_PAGE(a);
2269 cur->qtd.qtd_buffer[i] = htole32(a);
2270 cur->qtd.qtd_buffer_hi[i] = 0;
2271 #ifdef DIAGNOSTIC
2272 if (i >= EHCI_QTD_NBUFFERS) {
2273 kprintf("ehci_alloc_sqtd_chain: i=%d\n", i);
2274 goto nomem;
2275 }
2276 #endif
2277 }
2278 cur->nextqtd = next;
2279 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
2280 cur->qtd.qtd_status =
2281 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
2282 cur->xfer = xfer;
2283 cur->len = curlen;
2284 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2285 dataphys, dataphys + curlen));
2286 if (iscontrol) {
2287 /*
2288 * adjust the toggle based on the number of packets
2289 * in this qtd
2290 */
2291 if (((curlen + mps - 1) / mps) & 1)
2292 qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
2293 }
2294 if (len == 0)
2295 break;
2296 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2297 offset += curlen;
2298 dataphys = DMAADDR(dma, offset);
2299 cur = next;
2300 }
2301 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2302 *ep = cur;
2303
2304 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2305 *sp, *ep));
2306
2307 return (USBD_NORMAL_COMPLETION);
2308
2309 nomem:
2310 /* XXX free chain */
2311 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
2312 return (USBD_NOMEM);
2313 }
2314
2315 static void
2316 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2317 ehci_soft_qtd_t *sqtdend)
2318 {
2319 ehci_soft_qtd_t *p;
2320 int i;
2321
2322 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2323 sqtd, sqtdend));
2324
2325 for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
2326 p = sqtd->nextqtd;
2327 ehci_free_sqtd(sc, sqtd);
2328 }
2329 }
2330
2331 /****************/
2332
2333 /*
2334 * Close a reqular pipe.
2335 * Assumes that there are no pending transactions.
2336 */
2337 void
2338 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2339 {
2340 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2341 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2342 ehci_soft_qh_t *sqh = epipe->sqh;
2343
2344 crit_enter();
2345 ehci_rem_qh(sc, sqh, head);
2346 crit_exit();
2347 pipe->endpoint->savedtoggle =
2348 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status));
2349 ehci_free_sqh(sc, epipe->sqh);
2350 }
2351
2352 /*
2353 * Abort a device request.
2354 * If this routine is called from a critical section it guarantees that the
2355 * request will be removed from the hardware scheduling and that the callback
2356 * for it will be called with USBD_CANCELLED status.
2357 * It's impossible to guarantee that the requested transfer will not
2358 * have happened since the hardware runs concurrently.
2359 * If the transaction has already happened we rely on the ordinary
2360 * interrupt processing to process it.
2361 * XXX This is most probably wrong.
2362 */
2363 void
2364 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2365 {
2366 #define exfer EXFER(xfer)
2367 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2368 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2369 ehci_soft_qh_t *sqh = epipe->sqh;
2370 ehci_soft_qtd_t *sqtd, *snext, **psqtd;
2371 ehci_physaddr_t cur, us, next;
2372 int hit;
2373 /* int count = 0; */
2374 ehci_soft_qh_t *psqh;
2375
2376 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
2377
2378 if (sc->sc_dying) {
2379 /* If we're dying, just do the software part. */
2380 crit_enter();
2381 xfer->status = status; /* make software ignore it */
2382 callout_stop(&xfer->timeout_handle);
2383 usb_rem_task(epipe->pipe.device, &exfer->abort_task);
2384 usb_transfer_complete(xfer);
2385 crit_exit();
2386 return;
2387 }
2388
2389 if (xfer->device->bus->intr_context /* || !curproc REMOVED DFly */)
2390 panic("ehci_abort_xfer: not in process context");
2391
2392 /*
2393 * If an abort is already in progress then just wait for it to
2394 * complete and return.
2395 */
2396 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) {
2397 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
2398 /* No need to wait if we're aborting from a timeout. */
2399 if (status == USBD_TIMEOUT)
2400 return;
2401 /* Override the status which might be USBD_TIMEOUT. */
2402 xfer->status = status;
2403 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
2404 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT;
2405 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING)
2406 tsleep(&exfer->ehci_xfer_flags, 0, "ehciaw", 0);
2407 return;
2408 }
2409
2410 /*
2411 * Step 1: Make interrupt routine and timeouts ignore xfer.
2412 */
2413 crit_enter();
2414 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING;
2415 xfer->status = status; /* make software ignore it */
2416 callout_stop(&xfer->timeout_handle);
2417 usb_rem_task(epipe->pipe.device, &exfer->abort_task);
2418 crit_exit();
2419
2420 /*
2421 * Step 2: Wait until we know hardware has finished any possible
2422 * use of the xfer. We do this by removing the entire
2423 * queue from the async schedule and waiting for the doorbell.
2424 * Nothing else should be touching the queue now.
2425 */
2426 psqh = sqh->prev;
2427 ehci_rem_qh(sc, sqh, psqh);
2428
2429 /*
2430 * Step 3: make sure the soft interrupt routine
2431 * has run. This should remove any completed items off the queue.
2432 * The hardware has no reference to completed items (TDs).
2433 * It's safe to remove them at any time.
2434 */
2435 crit_enter();
2436 #ifdef USB_USE_SOFTINTR
2437 sc->sc_softwake = 1;
2438 #endif /* USB_USE_SOFTINTR */
2439 usb_schedsoftintr(&sc->sc_bus);
2440 #ifdef USB_USE_SOFTINTR
2441 tsleep(&sc->sc_softwake, 0, "ehciab", 0);
2442 #endif /* USB_USE_SOFTINTR */
2443
2444 /*
2445 * Step 4: Remove any vestiges of the xfer from the hardware.
2446 * The complication here is that the hardware may have executed
2447 * into or even beyond the xfer we're trying to abort.
2448 * So as we're scanning the TDs of this xfer we check if
2449 * the hardware points to any of them.
2450 *
2451 * first we need to see if there are any transfers
2452 * on this queue before the xfer we are aborting.. we need
2453 * to update any pointers that point to us to point past
2454 * the aborting xfer. (If there is something past us).
2455 * Hardware and software.
2456 */
2457 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
2458 hit = 0;
2459
2460 /* If they initially point here. */
2461 us = exfer->sqtdstart->physaddr;
2462
2463 /* We will change them to point here */
2464 snext = exfer->sqtdend->nextqtd;
2465 next = snext ? htole32(snext->physaddr) : EHCI_NULL;
2466
2467 /*
2468 * Now loop through any qTDs before us and keep track of the pointer
2469 * that points to us for the end.
2470 */
2471 psqtd = &sqh->sqtd;
2472 sqtd = sqh->sqtd;
2473 while (sqtd && sqtd != exfer->sqtdstart) {
2474 hit |= (cur == sqtd->physaddr);
2475 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us)
2476 sqtd->qtd.qtd_next = next;
2477 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us)
2478 sqtd->qtd.qtd_altnext = next;
2479 psqtd = &sqtd->nextqtd;
2480 sqtd = sqtd->nextqtd;
2481 }
2482 /* make the software pointer bypass us too */
2483 *psqtd = exfer->sqtdend->nextqtd;
2484
2485 /*
2486 * If we already saw the active one then we are pretty much done.
2487 * We've done all the relinking we need to do.
2488 */
2489 if (!hit) {
2490
2491 /*
2492 * Now reinitialise the QH to point to the next qTD
2493 * (if there is one). We only need to do this if
2494 * it was previously pointing to us.
2495 */
2496 sqtd = exfer->sqtdstart;
2497 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2498 if (cur == sqtd->physaddr) {
2499 hit++;
2500 }
2501 if (sqtd == exfer->sqtdend)
2502 break;
2503 }
2504 sqtd = sqtd->nextqtd;
2505 /*
2506 * Only need to alter the QH if it was pointing at a qTD
2507 * that we are removing.
2508 */
2509 if (hit) {
2510 if (snext) {
2511 ehci_set_qh_qtd(sqh, snext);
2512 } else {
2513
2514 sqh->qh.qh_curqtd = 0; /* unlink qTDs */
2515 sqh->qh.qh_qtd.qtd_status &=
2516 htole32(EHCI_QTD_TOGGLE_MASK);
2517 sqh->qh.qh_qtd.qtd_next =
2518 sqh->qh.qh_qtd.qtd_altnext
2519 = EHCI_NULL;
2520 DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
2521 }
2522 }
2523 }
2524 ehci_add_qh(sqh, psqh);
2525 /*
2526 * Step 5: Execute callback.
2527 */
2528 #ifdef DIAGNOSTIC
2529 exfer->isdone = 1;
2530 #endif
2531 /* Do the wakeup first to avoid touching the xfer after the callback. */
2532 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING;
2533 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) {
2534 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT;
2535 wakeup(&exfer->ehci_xfer_flags);
2536 }
2537 usb_transfer_complete(xfer);
2538
2539 /* kprintf("%s: %d TDs aborted\n", __func__, count); */
2540 crit_exit();
2541 #undef exfer
2542 }
2543
2544 void
2545 ehci_timeout(void *addr)
2546 {
2547 struct ehci_xfer *exfer = addr;
2548 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
2549 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2550
2551 DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
2552 #ifdef USB_DEBUG
2553 if (ehcidebug > 1)
2554 usbd_dump_pipe(exfer->xfer.pipe);
2555 #endif
2556
2557 if (sc->sc_dying) {
2558 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
2559 return;
2560 }
2561
2562 /* Execute the abort in a process context. */
2563 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
2564 USB_TASKQ_HC);
2565 }
2566
2567 void
2568 ehci_timeout_task(void *addr)
2569 {
2570 usbd_xfer_handle xfer = addr;
2571
2572 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
2573 crit_enter();
2574 ehci_abort_xfer(xfer, USBD_TIMEOUT);
2575 crit_exit();
2576 }
2577
2578 /*
2579 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing
2580 * back the qTD status, or miss signalling occasionally under heavy load.
2581 * If the host machine is too fast, we can miss transaction completion - when
2582 * we scan the active list the transaction still seems to be active. This
2583 * generally exhibits itself as a umass stall that never recovers.
2584 *
2585 * We work around this behaviour by setting up this callback after any softintr
2586 * that completes with transactions still pending, giving us another chance to
2587 * check for completion after the writeback has taken place.
2588 */
2589 void
2590 ehci_intrlist_timeout(void *arg)
2591 {
2592 ehci_softc_t *sc = arg;
2593
2594 DPRINTFN(3, ("ehci_intrlist_timeout\n"));
2595 usb_schedsoftintr(&sc->sc_bus);
2596 }
2597
2598 /************************/
2599
2600 static usbd_status
2601 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
2602 {
2603 usbd_status err;
2604
2605 /* Insert last in queue. */
2606 err = usb_insert_transfer(xfer);
2607 if (err)
2608 return (err);
2609
2610 /* Pipe isn't running, start first */
2611 return (ehci_device_ctrl_start(STAILQ_FIRST(&xfer->pipe->queue)));
2612 }
2613
2614 static usbd_status
2615 ehci_device_ctrl_start(usbd_xfer_handle xfer)
2616 {
2617 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2618 usbd_status err;
2619
2620 if (sc->sc_dying)
2621 return (USBD_IOERROR);
2622
2623 #ifdef DIAGNOSTIC
2624 if (!(xfer->rqflags & URQ_REQUEST)) {
2625 /* XXX panic */
2626 kprintf("ehci_device_ctrl_transfer: not a request\n");
2627 return (USBD_INVAL);
2628 }
2629 #endif
2630
2631 err = ehci_device_request(xfer);
2632 if (err)
2633 return (err);
2634
2635 if (sc->sc_bus.use_polling)
2636 ehci_waitintr(sc, xfer);
2637 return (USBD_IN_PROGRESS);
2638 }
2639
2640 void
2641 ehci_device_ctrl_done(usbd_xfer_handle xfer)
2642 {
2643 struct ehci_xfer *ex = EXFER(xfer);
2644 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2645 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2646
2647 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
2648
2649 #ifdef DIAGNOSTIC
2650 if (!(xfer->rqflags & URQ_REQUEST)) {
2651 panic("ehci_ctrl_done: not a request");
2652 }
2653 #endif
2654
2655 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2656 ehci_del_intr_list(ex); /* remove from active list */
2657 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2658 }
2659
2660 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
2661 }
2662
2663 /* Abort a device control request. */
2664 static void
2665 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
2666 {
2667 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
2668 ehci_abort_xfer(xfer, USBD_CANCELLED);
2669 }
2670
2671 /* Close a device control pipe. */
2672 static void
2673 ehci_device_ctrl_close(usbd_pipe_handle pipe)
2674 {
2675 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2676 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
2677
2678 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
2679 ehci_close_pipe(pipe, sc->sc_async_head);
2680 }
2681
2682 usbd_status
2683 ehci_device_request(usbd_xfer_handle xfer)
2684 {
2685 #define exfer EXFER(xfer)
2686 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2687 usb_device_request_t *req = &xfer->request;
2688 usbd_device_handle dev = epipe->pipe.device;
2689 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2690 int addr = dev->address;
2691 ehci_soft_qtd_t *setup, *stat, *next;
2692 ehci_soft_qh_t *sqh;
2693 int isread;
2694 int len;
2695 usbd_status err;
2696
2697 isread = req->bmRequestType & UT_READ;
2698 len = UGETW(req->wLength);
2699
2700 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
2701 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2702 req->bmRequestType, req->bRequest, UGETW(req->wValue),
2703 UGETW(req->wIndex), len, addr,
2704 epipe->pipe.endpoint->edesc->bEndpointAddress));
2705
2706 setup = ehci_alloc_sqtd(sc);
2707 if (setup == NULL) {
2708 err = USBD_NOMEM;
2709 goto bad1;
2710 }
2711 stat = ehci_alloc_sqtd(sc);
2712 if (stat == NULL) {
2713 err = USBD_NOMEM;
2714 goto bad2;
2715 }
2716
2717 sqh = epipe->sqh;
2718 epipe->u.ctl.length = len;
2719
2720 /* Update device address and length since they may have changed
2721 during the setup of the control pipe in usbd_new_device(). */
2722 /* XXX This only needs to be done once, but it's too early in open. */
2723 /* XXXX Should not touch ED here! */
2724 sqh->qh.qh_endp =
2725 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) |
2726 htole32(
2727 EHCI_QH_SET_ADDR(addr) |
2728 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
2729 );
2730
2731 /* Set up data transaction */
2732 if (len != 0) {
2733 ehci_soft_qtd_t *end;
2734
2735 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
2736 &next, &end);
2737 if (err)
2738 goto bad3;
2739 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
2740 end->nextqtd = stat;
2741 end->qtd.qtd_next =
2742 end->qtd.qtd_altnext = htole32(stat->physaddr);
2743 } else {
2744 next = stat;
2745 }
2746
2747 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
2748
2749 /* Clear toggle */
2750 setup->qtd.qtd_status = htole32(
2751 EHCI_QTD_ACTIVE |
2752 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
2753 EHCI_QTD_SET_CERR(3) |
2754 EHCI_QTD_SET_TOGGLE(0) |
2755 EHCI_QTD_SET_BYTES(sizeof *req)
2756 );
2757 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
2758 setup->qtd.qtd_buffer_hi[0] = 0;
2759 setup->nextqtd = next;
2760 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
2761 setup->xfer = xfer;
2762 setup->len = sizeof *req;
2763
2764 stat->qtd.qtd_status = htole32(
2765 EHCI_QTD_ACTIVE |
2766 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
2767 EHCI_QTD_SET_CERR(3) |
2768 EHCI_QTD_SET_TOGGLE(1) |
2769 EHCI_QTD_IOC
2770 );
2771 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
2772 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
2773 stat->nextqtd = NULL;
2774 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
2775 stat->xfer = xfer;
2776 stat->len = 0;
2777
2778 #ifdef EHCI_DEBUG
2779 if (ehcidebug > 5) {
2780 DPRINTF(("ehci_device_request:\n"));
2781 ehci_dump_sqh(sqh);
2782 ehci_dump_sqtds(setup);
2783 }
2784 #endif
2785
2786 exfer->sqtdstart = setup;
2787 exfer->sqtdend = stat;
2788 #ifdef DIAGNOSTIC
2789 if (!exfer->isdone) {
2790 kprintf("ehci_device_request: not done, exfer=%p\n", exfer);
2791 }
2792 exfer->isdone = 0;
2793 #endif
2794
2795 /* Insert qTD in QH list. */
2796 crit_enter();
2797 ehci_set_qh_qtd(sqh, setup);
2798 if (xfer->timeout && !sc->sc_bus.use_polling) {
2799 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2800 ehci_timeout, xfer);
2801 }
2802 ehci_add_intr_list(sc, exfer);
2803 xfer->status = USBD_IN_PROGRESS;
2804 crit_exit();
2805
2806 #ifdef EHCI_DEBUG
2807 if (ehcidebug > 10) {
2808 DPRINTF(("ehci_device_request: status=%x\n",
2809 EOREAD4(sc, EHCI_USBSTS)));
2810 delay(10000);
2811 ehci_dump_regs(sc);
2812 ehci_dump_sqh(sc->sc_async_head);
2813 ehci_dump_sqh(sqh);
2814 ehci_dump_sqtds(setup);
2815 }
2816 #endif
2817
2818 return (USBD_NORMAL_COMPLETION);
2819
2820 bad3:
2821 ehci_free_sqtd(sc, stat);
2822 bad2:
2823 ehci_free_sqtd(sc, setup);
2824 bad1:
2825 DPRINTFN(-1,("ehci_device_request: no memory\n"));
2826 xfer->status = err;
2827 usb_transfer_complete(xfer);
2828 return (err);
2829 #undef exfer
2830 }
2831
2832 /************************/
2833
2834 static usbd_status
2835 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
2836 {
2837 usbd_status err;
2838
2839 /* Insert last in queue. */
2840 err = usb_insert_transfer(xfer);
2841 if (err)
2842 return (err);
2843
2844 /* Pipe isn't running, start first */
2845 return (ehci_device_bulk_start(STAILQ_FIRST(&xfer->pipe->queue)));
2846 }
2847
2848 usbd_status
2849 ehci_device_bulk_start(usbd_xfer_handle xfer)
2850 {
2851 #define exfer EXFER(xfer)
2852 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2853 usbd_device_handle dev = epipe->pipe.device;
2854 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2855 ehci_soft_qtd_t *data, *dataend;
2856 ehci_soft_qh_t *sqh;
2857 usbd_status err;
2858 int len, isread, endpt;
2859
2860 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
2861 xfer, xfer->length, xfer->flags));
2862
2863 if (sc->sc_dying)
2864 return (USBD_IOERROR);
2865
2866 #ifdef DIAGNOSTIC
2867 if (xfer->rqflags & URQ_REQUEST)
2868 panic("ehci_device_bulk_start: a request");
2869 #endif
2870
2871 len = xfer->length;
2872 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2873 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2874 sqh = epipe->sqh;
2875
2876 epipe->u.bulk.length = len;
2877
2878 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
2879 &dataend);
2880 if (err) {
2881 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n"));
2882 xfer->status = err;
2883 usb_transfer_complete(xfer);
2884 return (err);
2885 }
2886
2887 #ifdef EHCI_DEBUG
2888 if (ehcidebug > 5) {
2889 DPRINTF(("ehci_device_bulk_start: data(1)\n"));
2890 ehci_dump_sqh(sqh);
2891 ehci_dump_sqtds(data);
2892 }
2893 #endif
2894
2895 /* Set up interrupt info. */
2896 exfer->sqtdstart = data;
2897 exfer->sqtdend = dataend;
2898 #ifdef DIAGNOSTIC
2899 if (!exfer->isdone) {
2900 kprintf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
2901 }
2902 exfer->isdone = 0;
2903 #endif
2904
2905 crit_enter();
2906 ehci_set_qh_qtd(sqh, data);
2907 if (xfer->timeout && !sc->sc_bus.use_polling) {
2908 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2909 ehci_timeout, xfer);
2910 }
2911 ehci_add_intr_list(sc, exfer);
2912 xfer->status = USBD_IN_PROGRESS;
2913 crit_exit();
2914
2915 #ifdef EHCI_DEBUG
2916 if (ehcidebug > 10) {
2917 DPRINTF(("ehci_device_bulk_start: data(2)\n"));
2918 delay(10000);
2919 DPRINTF(("ehci_device_bulk_start: data(3)\n"));
2920 ehci_dump_regs(sc);
2921 #if 0
2922 kprintf("async_head:\n");
2923 ehci_dump_sqh(sc->sc_async_head);
2924 #endif
2925 kprintf("sqh:\n");
2926 ehci_dump_sqh(sqh);
2927 ehci_dump_sqtds(data);
2928 }
2929 #endif
2930
2931 if (sc->sc_bus.use_polling)
2932 ehci_waitintr(sc, xfer);
2933
2934 return (USBD_IN_PROGRESS);
2935 #undef exfer
2936 }
2937
2938 static void
2939 ehci_device_bulk_abort(usbd_xfer_handle xfer)
2940 {
2941 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
2942 ehci_abort_xfer(xfer, USBD_CANCELLED);
2943 }
2944
2945 /*
2946 * Close a device bulk pipe.
2947 */
2948 static void
2949 ehci_device_bulk_close(usbd_pipe_handle pipe)
2950 {
2951 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2952
2953 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
2954 ehci_close_pipe(pipe, sc->sc_async_head);
2955 }
2956
2957 void
2958 ehci_device_bulk_done(usbd_xfer_handle xfer)
2959 {
2960 struct ehci_xfer *ex = EXFER(xfer);
2961 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2962 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2963
2964 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
2965 xfer, xfer->actlen));
2966
2967 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2968 ehci_del_intr_list(ex); /* remove from active list */
2969 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2970 }
2971
2972 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
2973 }
2974
2975 /************************/
2976
2977 static usbd_status
2978 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
2979 {
2980 struct ehci_soft_islot *isp;
2981 int islot, lev;
2982
2983 /* Find a poll rate that is large enough. */
2984 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
2985 if (EHCI_ILEV_IVAL(lev) <= ival)
2986 break;
2987
2988 /* Pick an interrupt slot at the right level. */
2989 /* XXX could do better than picking at random. */
2990 islot = EHCI_IQHIDX(lev, karc4random());
2991
2992 sqh->islot = islot;
2993 isp = &sc->sc_islots[islot];
2994 ehci_add_qh(sqh, isp->sqh);
2995
2996 return (USBD_NORMAL_COMPLETION);
2997 }
2998
2999 static usbd_status
3000 ehci_device_intr_transfer(usbd_xfer_handle xfer)
3001 {
3002 usbd_status err;
3003
3004 /* Insert last in queue. */
3005 err = usb_insert_transfer(xfer);
3006 if (err)
3007 return (err);
3008
3009 /*
3010 * Pipe isn't running (otherwise err would be USBD_INPROG),
3011 * so start it first.
3012 */
3013 return (ehci_device_intr_start(STAILQ_FIRST(&xfer->pipe->queue)));
3014 }
3015
3016 static usbd_status
3017 ehci_device_intr_start(usbd_xfer_handle xfer)
3018 {
3019 #define exfer EXFER(xfer)
3020 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3021 usbd_device_handle dev = xfer->pipe->device;
3022 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
3023 ehci_soft_qtd_t *data, *dataend;
3024 ehci_soft_qh_t *sqh;
3025 usbd_status err;
3026 int len, isread, endpt;
3027
3028 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
3029 xfer, xfer->length, xfer->flags));
3030
3031 if (sc->sc_dying)
3032 return (USBD_IOERROR);
3033
3034 #ifdef DIAGNOSTIC
3035 if (xfer->rqflags & URQ_REQUEST)
3036 panic("ehci_device_intr_start: a request");
3037 #endif
3038
3039 len = xfer->length;
3040 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3041 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3042 sqh = epipe->sqh;
3043
3044 epipe->u.intr.length = len;
3045
3046 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3047 &dataend);
3048 if (err) {
3049 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3050 xfer->status = err;
3051 usb_transfer_complete(xfer);
3052 return (err);
3053 }
3054
3055 #ifdef EHCI_DEBUG
3056 if (ehcidebug > 5) {
3057 DPRINTF(("ehci_device_intr_start: data(1)\n"));
3058 ehci_dump_sqh(sqh);
3059 ehci_dump_sqtds(data);
3060 }
3061 #endif
3062
3063 /* Set up interrupt info. */
3064 exfer->sqtdstart = data;
3065 exfer->sqtdend = dataend;
3066 #ifdef DIAGNOSTIC
3067 if (!exfer->isdone) {
3068 kprintf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3069 }
3070 exfer->isdone = 0;
3071 #endif
3072
3073 crit_enter();
3074 ehci_set_qh_qtd(sqh, data);
3075 if (xfer->timeout && !sc->sc_bus.use_polling) {
3076 callout_reset(&xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
3077 ehci_timeout, xfer);
3078 }
3079 ehci_add_intr_list(sc, exfer);
3080 xfer->status = USBD_IN_PROGRESS;
3081 crit_exit();
3082
3083 #ifdef EHCI_DEBUG
3084 if (ehcidebug > 10) {
3085 DPRINTF(("ehci_device_intr_start: data(2)\n"));
3086 delay(10000);
3087 DPRINTF(("ehci_device_intr_start: data(3)\n"));
3088 ehci_dump_regs(sc);
3089 kprintf("sqh:\n");
3090 ehci_dump_sqh(sqh);
3091 ehci_dump_sqtds(data);
3092 }
3093 #endif
3094
3095 if (sc->sc_bus.use_polling)
3096 ehci_waitintr(sc, xfer);
3097
3098 return (USBD_IN_PROGRESS);
3099 #undef exfer
3100 }
3101
3102 static void
3103 ehci_device_intr_abort(usbd_xfer_handle xfer)
3104 {
3105 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3106 if (xfer->pipe->intrxfer == xfer) {
3107 DPRINTFN(1, ("ehci_device_intr_abort: remove\n"));
3108 xfer->pipe->intrxfer = NULL;
3109 }
3110 ehci_abort_xfer(xfer, USBD_CANCELLED);
3111 }
3112
3113 static void
3114 ehci_device_intr_close(usbd_pipe_handle pipe)
3115 {
3116 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3117 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3118 struct ehci_soft_islot *isp;
3119
3120 isp = &sc->sc_islots[epipe->sqh->islot];
3121 ehci_close_pipe(pipe, isp->sqh);
3122 }
3123
3124 static void
3125 ehci_device_intr_done(usbd_xfer_handle xfer)
3126 {
3127 #define exfer EXFER(xfer)
3128 struct ehci_xfer *ex = EXFER(xfer);
3129 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3130 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3131 ehci_soft_qtd_t *data, *dataend;
3132 ehci_soft_qh_t *sqh;
3133 usbd_status err;
3134 int len, isread, endpt;
3135
3136 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3137 xfer, xfer->actlen));
3138
3139 if (xfer->pipe->repeat) {
3140 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3141
3142 len = epipe->u.intr.length;
3143 xfer->length = len;
3144 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3145 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3146 sqh = epipe->sqh;
3147
3148 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3149 &data, &dataend);
3150 if (err) {
3151 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3152 xfer->status = err;
3153 return;
3154 }
3155
3156 /* Set up interrupt info. */
3157 exfer->sqtdstart = data;
3158 exfer->sqtdend = dataend;
3159 #ifdef DIAGNOSTIC
3160 if (!exfer->isdone) {
3161 kprintf("ehci_device_intr_done: not done, ex=%p\n",
3162 exfer);
3163 }
3164 exfer->isdone = 0;
3165 #endif
3166
3167 crit_enter();
3168 ehci_set_qh_qtd(sqh, data);
3169 if (xfer->timeout && !sc->sc_bus.use_polling) {
3170 callout_reset(&xfer->timeout_handle,
3171 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer);
3172 }
3173 crit_exit();
3174
3175 xfer->status = USBD_IN_PROGRESS;
3176 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3177 ehci_del_intr_list(ex); /* remove from active list */
3178 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3179 }
3180 #undef exfer
3181 }
3182
3183 /************************/
3184
3185 static usbd_status
3186 ehci_device_isoc_transfer(usbd_xfer_handle xfer)
3187 {
3188 return USBD_IOERROR;
3189 }
3190
3191 static usbd_status
3192 ehci_device_isoc_start(usbd_xfer_handle xfer)
3193 {
3194 return USBD_IOERROR;
3195 }
3196
3197 static void
3198 ehci_device_isoc_abort(usbd_xfer_handle xfer)
3199 {
3200 }
3201
3202 static void
3203 ehci_device_isoc_close(usbd_pipe_handle pipe)
3204 {
3205 }
3206
3207 static void
3208 ehci_device_isoc_done(usbd_xfer_handle xfer)
3209 {
3210 }
DragonFly BSD