sys/platform/pc64/amd64/initcpu.c

   1 /*-
   2  * Copyright (c) KATO Takenori, 1997, 1998.
   3  * Copyright (c) 2008 The DragonFly Project.
   4  *
   5  * All rights reserved.  Unpublished rights reserved under the copyright
   6  * laws of Japan.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer as
  14  *    the first lines of this file unmodified.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $DragonFly: src/sys/platform/pc64/amd64/initcpu.c,v 1.1 2008/08/29 17:07:10 dillon Exp $
  31  */
  32
  33 #include "opt_cpu.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/systm.h>
  38 #include <sys/sysctl.h>
  39
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43 #include <machine/smp.h>
  44
  45 #include <vm/vm.h>
  46 #include <vm/pmap.h>
  47
  48 static int      hw_instruction_sse;
  49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  50     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  51
  52 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  53 u_int   cpu_feature;            /* Feature flags */
  54 u_int   cpu_feature2;           /* Feature flags */
  55 u_int   amd_feature;            /* AMD feature flags */
  56 u_int   amd_feature2;           /* AMD feature flags */
  57 u_int   cpu_high;               /* Highest arg to CPUID */
  58 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  59 u_int   cpu_id;                 /* Stepping ID */
  60 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
  61 u_int   cpu_procinfo2;          /* Multicore info */
  62 char    cpu_vendor[20];         /* CPU Origin code */
  63 u_int   cpu_vendor_id;          /* CPU vendor ID */
  64 u_int   cpu_fxsr;               /* SSE enabled */
  65 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
  66
  67 /*
  68  * Initialize CPU control registers
  69  */
  70 void
  71 initializecpu(void)
  72 {
  73         uint64_t msr;
  74
  75         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  76                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
  77                 cpu_fxsr = hw_instruction_sse = 1;
  78         }
  79         if ((amd_feature & AMDID_NX) != 0) {
  80                 msr = rdmsr(MSR_EFER) | EFER_NXE;
  81                 wrmsr(MSR_EFER, msr);
  82 #if JG
  83                 pg_nx = PG_NX;
  84 #endif
  85         }
  86 }