sys/dev/sound/pci/maestro_reg.h

   1 /*-
   2  * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  *      maestro_reg.h,v 1.13 2001/11/11 18:29:46 taku Exp
  27  * $FreeBSD: src/sys/dev/sound/pci/maestro_reg.h,v 1.3 2004/11/10 04:29:09 julian Exp $
  28  * $DragonFly: src/sys/dev/sound/pci/maestro_reg.h,v 1.3 2007/01/04 21:47:02 corecode Exp $
  29  */
  30
  31 #ifndef MAESTRO_REG_H_INCLUDED
  32 #define MAESTRO_REG_H_INCLUDED
  33
  34 /* -----------------------------
  35  * PCI config registers
  36  */
  37
  38 /* Legacy emulation */
  39 #define CONF_LEGACY     0x40
  40
  41 #define LEGACY_DISABLED 0x8000
  42
  43 /* Chip configurations */
  44 #define CONF_MAESTRO    0x50
  45 #define MAESTRO_PMC             0x08000000
  46 #define MAESTRO_SPDIF           0x01000000
  47 #define MAESTRO_HWVOL           0x00800000
  48 #define MAESTRO_CHIBUS          0x00100000
  49 #define MAESTRO_POSTEDWRITE     0x00000080
  50 #define MAESTRO_DMA_PCITIMING   0x00000040
  51 #define MAESTRO_SWAP_LR         0x00000020
  52
  53 /* ACPI configurations */
  54 #define CONF_ACPI_STOPCLOCK     0x54
  55 #define ACPI_PART_2ndC_CLOCK    15
  56 #define ACPI_PART_CODEC_CLOCK   14
  57 #define ACPI_PART_978           13 /* Docking station or something */
  58 #define ACPI_PART_SPDIF         12
  59 #define ACPI_PART_GLUE          11 /* What? */
  60 #define ACPI_PART_DAA           10
  61 #define ACPI_PART_PCI_IF        9
  62 #define ACPI_PART_HW_VOL        8
  63 #define ACPI_PART_GPIO          7
  64 #define ACPI_PART_ASSP          6
  65 #define ACPI_PART_SB            5
  66 #define ACPI_PART_FM            4
  67 #define ACPI_PART_RINGBUS       3
  68 #define ACPI_PART_MIDI          2
  69 #define ACPI_PART_GAME_PORT     1
  70 #define ACPI_PART_WP            0
  71
  72 /* Power management */
  73 #define CONF_PM_PTR     0x34    /* BYTE R */
  74 #define PM_CID          0       /* BYTE R */
  75 #define PPMI_CID        1
  76 #define PM_CTRL         4       /* BYTE RW */
  77 #define PPMI_D0         0       /* Full power */
  78 #define PPMI_D1         1       /* Medium power */
  79 #define PPMI_D2         2       /* Low power */
  80 #define PPMI_D3         3       /* Turned off */
  81
  82
  83 /* -----------------------------
  84  * I/O ports
  85  */
  86
  87 /* Direct Sound Processor (aka WP) */
  88 #define PORT_DSP_DATA   0x00    /* WORD RW */
  89 #define PORT_DSP_INDEX  0x02    /* WORD RW */
  90 #define PORT_INT_STAT   0x04    /* WORD RW */
  91 #define PORT_SAMPLE_CNT 0x06    /* WORD RO */
  92
  93 /* WaveCache */
  94 #define PORT_WAVCACHE_INDEX     0x10    /* WORD RW */
  95 #define PORT_WAVCACHE_DATA      0x12    /* WORD RW */
  96 #define WAVCACHE_PCMBAR         0x1fc
  97 #define WAVCACHE_WTBAR          0x1f0
  98 #define WAVCACHE_BASEADDR_SHIFT 12
  99
 100 #define WAVCACHE_CHCTL_ADDRTAG_MASK     0xfff8
 101 #define WAVCACHE_CHCTL_U8               0x0004
 102 #define WAVCACHE_CHCTL_STEREO           0x0002
 103 #define WAVCACHE_CHCTL_DECREMENTAL      0x0001
 104
 105 #define PORT_WAVCACHE_CTRL      0x14    /* WORD RW */
 106 #define WAVCACHE_EXTRA_CH_ENABLED       0x0200
 107 #define WAVCACHE_ENABLED                0x0100
 108 #define WAVCACHE_CH_60_ENABLED          0x0080
 109 #define WAVCACHE_WTSIZE_MASK    0x0060
 110 #define WAVCACHE_WTSIZE_1MB     0x0000
 111 #define WAVCACHE_WTSIZE_2MB     0x0020
 112 #define WAVCACHE_WTSIZE_4MB     0x0040
 113 #define WAVCACHE_WTSIZE_8MB     0x0060
 114 #define WAVCACHE_SGC_MASK               0x000c
 115 #define WAVCACHE_SGC_DISABLED           0x0000
 116 #define WAVCACHE_SGC_40_47              0x0004
 117 #define WAVCACHE_SGC_32_47              0x0008
 118 #define WAVCACHE_TESTMODE               0x0001
 119
 120 /* Host Interruption */
 121 #define PORT_HOSTINT_CTRL       0x18    /* WORD RW */
 122 #define HOSTINT_CTRL_SOFT_RESET         0x8000
 123 #define HOSTINT_CTRL_DSOUND_RESET       0x4000
 124 #define HOSTINT_CTRL_HW_VOL_TO_PME      0x0400
 125 #define HOSTINT_CTRL_CLKRUN_ENABLED     0x0100
 126 #define HOSTINT_CTRL_HWVOL_ENABLED      0x0040
 127 #define HOSTINT_CTRL_ASSP_INT_ENABLED   0x0010
 128 #define HOSTINT_CTRL_ISDN_INT_ENABLED   0x0008
 129 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004
 130 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002
 131 #define HOSTINT_CTRL_SB_INT_ENABLED     0x0001
 132
 133 #define PORT_HOSTINT_STAT       0x1a    /* BYTE RW */
 134 #define HOSTINT_STAT_HWVOL      0x40
 135 #define HOSTINT_STAT_ASSP       0x10
 136 #define HOSTINT_STAT_ISDN       0x08
 137 #define HOSTINT_STAT_DSOUND     0x04
 138 #define HOSTINT_STAT_MPU401     0x02
 139 #define HOSTINT_STAT_SB         0x01
 140
 141 /* Hardware volume */
 142 #define PORT_HWVOL_CTRL         0x1b    /* BYTE RW */
 143 #define HWVOL_CTRL_SPLIT_SHADOW 0x01
 144
 145 #define PORT_HWVOL_VOICE_SHADOW 0x1c    /* BYTE RW */
 146 #define PORT_HWVOL_VOICE        0x1d    /* BYTE RW */
 147 #define PORT_HWVOL_MASTER_SHADOW 0x1e   /* BYTE RW */
 148 #define PORT_HWVOL_MASTER       0x1f    /* BYTE RW */
 149 #define HWVOL_NOP               0x88
 150 #define HWVOL_MUTE              0x11
 151 #define HWVOL_UP                0xaa
 152 #define HWVOL_DOWN              0x66
 153
 154 /* CODEC */
 155 #define PORT_CODEC_CMD  0x30    /* BYTE W */
 156 #define CODEC_CMD_READ  0x80
 157 #define CODEC_CMD_WRITE 0x00
 158 #define CODEC_CMD_ADDR_MASK     0x7f
 159
 160 #define PORT_CODEC_STAT 0x30    /* BYTE R */
 161 #define CODEC_STAT_MASK 0x01
 162 #define CODEC_STAT_RW_DONE      0x00
 163 #define CODEC_STAT_PROGLESS     0x01
 164
 165 #define PORT_CODEC_REG  0x32    /* WORD RW */
 166
 167 /* Ring bus control */
 168 #define PORT_RINGBUS_CTRL       0x34    /* DWORD RW */
 169 #define RINGBUS_CTRL_I2S_ENABLED        0x80000000
 170 #define RINGBUS_CTRL_RINGBUS_ENABLED    0x20000000
 171 #define RINGBUS_CTRL_ACLINK_ENABLED     0x10000000
 172 #define RINGBUS_CTRL_AC97_SWRESET       0x08000000
 173
 174 #define RINGBUS_SRC_MIC         20
 175 #define RINGBUS_SRC_I2S         16
 176 #define RINGBUS_SRC_ADC         12
 177 #define RINGBUS_SRC_MODEM       8
 178 #define RINGBUS_SRC_DSOUND      4
 179 #define RINGBUS_SRC_ASSP        0
 180
 181 #define RINGBUS_DEST_MONORAL    000
 182 #define RINGBUS_DEST_STEREO     010
 183 #define RINGBUS_DEST_NONE       0
 184 #define RINGBUS_DEST_DAC        1
 185 #define RINGBUS_DEST_MODEM_IN   2
 186 #define RINGBUS_DEST_RESERVED3  3
 187 #define RINGBUS_DEST_DSOUND_IN  4
 188 #define RINGBUS_DEST_ASSP_IN    5
 189
 190 /* Ring bus control B */
 191 #define PORT_RINGBUS_CTRL_B     0x38    /* BYTE RW */
 192 #define RINGBUS_CTRL_SSPE               0x40
 193 #define RINGBUS_CTRL_2ndCODEC           0x20
 194 #define RINGBUS_CTRL_SPDIF              0x10
 195 #define RINGBUS_CTRL_ITB_DISABLE        0x08
 196 #define RINGBUS_CTRL_CODEC_ID_MASK      0x03
 197 #define RINGBUS_CTRL_CODEC_ID_AC98      2
 198
 199 /* General Purpose I/O */
 200 #define PORT_GPIO_DATA  0x60    /* WORD RW */
 201 #define PORT_GPIO_MASK  0x64    /* WORD RW */
 202 #define PORT_GPIO_DIR   0x68    /* WORD RW */
 203
 204 /* Application Specific Signal Processor */
 205 #define PORT_ASSP_MEM_INDEX     0x80    /* DWORD RW */
 206 #define PORT_ASSP_MEM_DATA      0x84    /* WORD RW */
 207 #define PORT_ASSP_CTRL_A        0xa2    /* BYTE RW */
 208 #define PORT_ASSP_CTRL_B        0xa4    /* BYTE RW */
 209 #define PORT_ASSP_CTRL_C        0xa6    /* BYTE RW */
 210 #define PORT_ASSP_HOST_WR_INDEX 0xa8    /* BYTE W */
 211 #define PORT_ASSP_HOST_WR_DATA  0xaa    /* BYTE RW */
 212 #define PORT_ASSP_INT_STAT      0xac    /* BYTE RW */
 213
 214
 215 /* -----------------------------
 216  * Wave Processor Indexed Data Registers.
 217  */
 218
 219 #define WPREG_DATA_PORT         0
 220 #define WPREG_CRAM_PTR          1
 221 #define WPREG_CRAM_DATA         2
 222 #define WPREG_WAVE_DATA         3
 223 #define WPREG_WAVE_PTR_LOW      4
 224 #define WPREG_WAVE_PTR_HIGH     5
 225
 226 #define WPREG_TIMER_FREQ        6
 227 #define WP_TIMER_FREQ_PRESCALE_MASK     0x00e0  /* actual - 9 */
 228 #define WP_TIMER_FREQ_PRESCALE_SHIFT    5
 229 #define WP_TIMER_FREQ_DIVIDE_MASK       0x001f
 230 #define WP_TIMER_FREQ_DIVIDE_SHIFT      0
 231
 232 #define WPREG_WAVE_ROMRAM       7
 233 #define WP_WAVE_VIRTUAL_ENABLED 0x0400
 234 #define WP_WAVE_8BITRAM_ENABLED 0x0200
 235 #define WP_WAVE_DRAM_ENABLED    0x0100
 236 #define WP_WAVE_RAMSPLIT_MASK   0x00ff
 237 #define WP_WAVE_RAMSPLIT_SHIFT  0
 238
 239 #define WPREG_BASE              12
 240 #define WP_PARAOUT_BASE_MASK    0xf000
 241 #define WP_PARAOUT_BASE_SHIFT   12
 242 #define WP_PARAIN_BASE_MASK     0x0f00
 243 #define WP_PARAIN_BASE_SHIFT    8
 244 #define WP_SERIAL0_BASE_MASK    0x00f0
 245 #define WP_SERIAL0_BASE_SHIFT   4
 246 #define WP_SERIAL1_BASE_MASK    0x000f
 247 #define WP_SERIAL1_BASE_SHIFT   0
 248
 249 #define WPREG_TIMER_ENABLE      17
 250 #define WPREG_TIMER_START       23
 251
 252
 253 /* -----------------------------
 254  * Audio Processing Unit.
 255  */
 256 #define APUREG_APUTYPE  0
 257 #define APU_DMA_ENABLED 0x4000
 258 #define APU_INT_ON_LOOP 0x2000
 259 #define APU_ENDCURVE    0x1000
 260 #define APU_APUTYPE_MASK        0x00f0
 261 #define APU_FILTERTYPE_MASK     0x000c
 262 #define APU_FILTERQ_MASK        0x0003
 263
 264 /* APU types */
 265 #define APU_APUTYPE_SHIFT       4
 266
 267 #define APUTYPE_INACTIVE        0
 268 #define APUTYPE_16BITLINEAR     1
 269 #define APUTYPE_16BITSTEREO     2
 270 #define APUTYPE_8BITLINEAR      3
 271 #define APUTYPE_8BITSTEREO      4
 272 #define APUTYPE_8BITDIFF        5
 273 #define APUTYPE_DIGITALDELAY    6
 274 #define APUTYPE_DUALTAP_READER  7
 275 #define APUTYPE_CORRELATOR      8
 276 #define APUTYPE_INPUTMIXER      9
 277 #define APUTYPE_WAVETABLE       10
 278 #define APUTYPE_RATECONV        11
 279 #define APUTYPE_16BITPINGPONG   12
 280 /* APU type 13 through 15 are reserved. */
 281
 282 /* Filter types */
 283 #define APU_FILTERTYPE_SHIFT    2
 284
 285 #define FILTERTYPE_2POLE_LOPASS         0
 286 #define FILTERTYPE_2POLE_BANDPASS       1
 287 #define FILTERTYPE_2POLE_HIPASS         2
 288 #define FILTERTYPE_1POLE_LOPASS         3
 289 #define FILTERTYPE_1POLE_HIPASS         4
 290 #define FILTERTYPE_PASSTHROUGH          5
 291
 292 /* Filter Q */
 293 #define APU_FILTERQ_SHIFT       0
 294
 295 #define FILTERQ_LESSQ   0
 296 #define FILTERQ_MOREQ   3
 297
 298 /* APU register 2 */
 299 #define APUREG_FREQ_LOBYTE      2
 300 #define APU_FREQ_LOBYTE_MASK    0xff00
 301 #define APU_plus6dB             0x0010
 302
 303 /* APU register 3 */
 304 #define APUREG_FREQ_HIWORD      3
 305 #define APU_FREQ_HIWORD_MASK    0x0fff
 306
 307 /* Frequency */
 308 #define APU_FREQ_LOBYTE_SHIFT   8
 309 #define APU_FREQ_HIWORD_SHIFT   0
 310 #define FREQ_Hz2DIV(freq)       (((u_int64_t)(freq) << 16) / 48000)
 311
 312 /* APU register 4 */
 313 #define APUREG_WAVESPACE        4
 314 #define APU_64KPAGE_MASK        0xff00
 315
 316 /* 64KW (==128KB) Page */
 317 #define APU_64KPAGE_SHIFT       8
 318
 319 /* Wave Processor Wavespace Address */
 320 #define WPWA_MAX                ((1 << 22) - 1)
 321 #define WPWA_STEREO             (1 << 23)
 322 #define WPWA_USE_SYSMEM         (1 << 22)
 323
 324 #define WPWA_WTBAR_SHIFT(wtsz)  WPWA_WTBAR_SHIFT_##wtsz
 325 #define WPWA_WTBAR_SHIFT_1      15
 326 #define WPWA_WTBAR_SHIFT_2      16
 327 #define WPWA_WTBAR_SHIFT_4      17
 328 #define WPWA_WTBAR_SHIFT_8      18
 329
 330 #define WPWA_PCMBAR_SHIFT       20
 331
 332 /* APU register 5 - 7 */
 333 #define APUREG_CURPTR   5
 334 #define APUREG_ENDPTR   6
 335 #define APUREG_LOOPLEN  7
 336
 337 /* APU register 8 */
 338 #define APUREG_EFFECT_GAIN      8
 339
 340 /* Effect gain? */
 341 #define APUREG_EFFECT_GAIN_MASK 0x00ff
 342
 343 /* APU register 9 */
 344 #define APUREG_AMPLITUDE        9
 345 #define APU_AMPLITUDE_NOW_MASK  0xff00
 346 #define APU_AMPLITUDE_DEST_MASK 0x00ff
 347
 348 /* Amplitude now? */
 349 #define APU_AMPLITUDE_NOW_SHIFT 8
 350
 351 /* APU register 10 */
 352 #define APUREG_POSITION 10
 353 #define APU_RADIUS_MASK 0x00c0
 354 #define APU_PAN_MASK    0x003f
 355
 356 /* Radius control. */
 357 #define APU_RADIUS_SHIFT        6
 358 #define RADIUS_CENTERCIRCLE     0
 359 #define RADIUS_MIDDLE           1
 360 #define RADIUS_OUTSIDE          2
 361
 362 /* Polar pan. */
 363 #define APU_PAN_SHIFT   0
 364 #define PAN_RIGHT       0x00
 365 #define PAN_FRONT       0x08
 366 #define PAN_LEFT        0x10
 367
 368 /* Source routing. */
 369 #define APUREG_ROUTING  11
 370 #define APU_INVERT_POLARITY_B   0x8000
 371 #define APU_DATASRC_B_MASK      0x7f00
 372 #define APU_INVERT_POLARITY_A   0x0080
 373 #define APU_DATASRC_A_MASK      0x007f
 374
 375 #define APU_DATASRC_A_SHIFT     0
 376 #define APU_DATASRC_B_SHIFT     8
 377
 378
 379 /* -----------------------------
 380  * Limits.
 381  */
 382 #define WPWA_MAXADDR    ((1 << 23) - 1)
 383 #define MAESTRO_MAXADDR ((1 << 28) - 1)
 384
 385 #endif  /* MAESTRO_REG_H_INCLUDED */